Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a stack structure disposed on the substrate, and a plurality of dummy memory string structures. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The dummy memory string structures are disposed in a staircase region of the semiconductor device and pass through the stack structure along the first direction, wherein the staircase region includes a body portion, and the body portion includes a first region and a second region adjacent to each other. In the first region, a number of the conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, a number of the conductive layers corresponding to the dummy memory string structures is greater than 10. In a top view, an area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second region in a same unit area.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, and particularly to a three-dimensional semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Recently, as the demand for more superior memory devices has gradually increased, various three-dimensional (3D) memory devices, such as a three-dimensional NAND (3D NAND) memory device, a three-dimensional NOR memory device (3D NOR), or a three-dimensional AND memory device (3D AND), have been provided.

[0003] Generally, a three-dimensional memory device includes a substrate and a stack structure disposed on the substrate. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked. Also, the three-dimensional memory device includes an array region and a staircase region adjacent to the array region. Memory string structures and dummy memory string structures can be respectively formed in the array region and the staircase region by the same process. The memory string structures and the dummy memory string structures respectively include epitaxial growth layers extending upward from the substrate.

[0004] However, in the current three-dimensional memory device, it is often found that the epitaxial growth layers of the dummy memory string structures in some regions of the staircase region grow poorly (e.g., the epitaxial growth layers are skewed or have insufficient height), which can cause short circuits, resulting in electrical problems (e.g., leakage current). SUMMARY

[0005] The present application relates to a semiconductor device. A body portion of a staircase region of the semiconductor device includes a first region and a second region. In the first region, a number of conductive layers corresponding to dummy memory string structures is between 1 and 10. In the second region, a number of conductive layers corresponding to the dummy memory string structures is greater than 10. Since an area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second region (i.e., an area of first openings for forming the dummy memory string structures in the first region is greater than an area of first openings for forming the dummy memory string structures in the second region) in a same unit area in a top view, an effect of exhausting etching gas in the first region is better than an effect of exhausting etching gas in the second region during formation of the dummy memory string structures including epitaxial growth layers, which can reduce adverse effects of the etching gas on the epitaxial growth layers in the first region. Therefore, compared to a comparative example in which an area of the dummy memory string structures in the first region is not greater than an area of the dummy memory string structures in the second region, the epitaxial growth layers of the dummy memory string structures in the first region of the present application can have better growth, which can prevent the epitaxial growth layers from being skewed or having insufficient height, thereby avoiding problems of short circuits and leakage current.

[0006] According to one aspect of the present application, a semiconductor device is provided. The semiconductor device includes a substrate, a stack structure disposed on the substrate, and a plurality of dummy memory string structures. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The dummy memory string structures are disposed in a staircase region of the semiconductor device, and pass through the stack structure along the first direction, wherein the staircase region includes a body portion, and the body portion includes a first region and a second region adjacent to each other. In the first region, a number of the conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, the number of the conductive layers corresponding to the dummy memory string structures is greater than 10. In a top view, an area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second region in a same unit area.

[0007] According to another aspect of the present application, a method of manufacturing a semiconductor device is provided. The method of manufacturing the semiconductor device includes the following steps. First, a substrate and a stack structure disposed on the substrate are provided. Thereafter, a plurality of first openings are formed in a staircase region of the semiconductor device. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The first openings pass through the stack structure along the first direction, wherein the staircase region includes a body portion, and the body portion includes a first region and a second region adjacent to each other. In the first region, a number of the conductive layers corresponding to the first openings is between 1 and 10; in the second region, the number of the conductive layers corresponding to the first openings is greater than 10. In a top view, an area of the first openings in the first region is greater than an area of the first openings in the second region in a same unit area.

[0008] For a better understanding of the present application, including its various aspects, reference should be made to the following detailed description and accompanying drawings in which: BRIEF DESCRIPTION OF DRAWINGS

[0009] Figures 1A-2B A flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present application is shown;

[0010] Figure 3A A partial top view of a semiconductor device according to a comparative example is shown;

[0011] Figure 3B A cross-sectional view of the A-A' line of Figure 3A is shown;

[0012] Figure 4A A partial top view of a semiconductor device according to an embodiment of the present application is shown;

[0013] Figure 4B A cross-sectional view of the A-A' line of Figure 4A is shown;

[0014] Figure 5 A graph illustrating a formation height of an epitaxial growth layer of a virtual memory string structure of a semiconductor device according to an embodiment of the present application and a semiconductor device of a comparative example;

[0015] Figure 6A A scan result of an abnormal epitaxial growth layer of a virtual memory string structure of a semiconductor device of a comparative example is illustrated;

[0016] Figure 6B A scan result of an abnormal epitaxial growth layer of a virtual memory string structure of a semiconductor device according to an embodiment of the present application is illustrated;

[0017] Figure 7 A partial plan view of a semiconductor device according to another embodiment of the present application is illustrated;

[0018] Figure 8A A partial plan view of a semiconductor device according to still another embodiment of the present application is illustrated;

[0019] Figure 8B A cross-sectional view of an A-A' line of Figure 8A is illustrated;

[0020] Figure 9A A scan result of an abnormal epitaxial growth layer of a virtual memory string structure of a semiconductor device of a comparative example is illustrated;

[0021] Figure 9B A scan result of an abnormal epitaxial growth layer of a virtual memory string structure of a semiconductor device according to an embodiment of the present application is illustrated;

[0022] Figure 9C A scan result of an abnormal epitaxial growth layer of a virtual memory string structure of a semiconductor device according to another embodiment of the present application is illustrated; and

[0023] Figure 10 A partial plan view of a semiconductor device according to still another embodiment of the present application is illustrated.

[0024]

List of Symbols

[0025] 100, 100A, 100P, 200, 300: semiconductor device

[0026] 110: substrate

[0027] 110a: upper surface

[0028] 112: insulating layer

[0029] 114: conductive layer

[0030] 116: memory string structure

[0031] 116h: Array opening

[0032] 118, 118p, 218, 318, 418: Virtual memory serial structure

[0033] 118h, 118hp, 218h, 318h, 418h: First opening

[0034] 120: Contact Structure

[0035] 120': Pre-defined position of contact structure

[0036] 1161, 1181: Extensional growth layer

[0037] A, A', B, B': Endpoints of the section line

[0038] AR: Array Area

[0039] AS: Stepped Area

[0040] AS1: Main body part

[0041] AS1a: Zone 1

[0042] AS1b: Second Zone

[0043] AS2: Virtual Department

[0044] C1~C5, Ca1, Cb1, Ca2, Cb2, Ca3, Cb3, Ca4, Cb4: Center point

[0045] R1, R2: Row

[0046] S1: Layered structure

[0047] UA: Unit area Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0049] In the following detailed description, various specific details are provided for ease of explanation to provide an overall understanding of embodiments of the invention. However, it should be understood that one or more embodiments can be implemented without these specific details. In other instances, known structures and elements are illustrated schematically for the purpose of simplifying the drawings.

[0050] Figures 1A-2B A flowchart illustrating a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention is shown. Wherein, Figure 1A and Figure 2A A top view illustrating the manufacturing process of a semiconductor device 100 according to an embodiment of the present invention.Figure 1B Draw Figure 1A Cross-sectional view of AA' and BB' connections. Figure 2B Draw Figure 2A Cross-sectional view of AA' and BB' connections.

[0051] Please refer to the following at the same time Figure 1A and Figure 1B A substrate 110 and a stacked structure S1 disposed on the substrate 110 are provided. The stacked structure S1 is disposed on the upper surface 110a of the substrate 110, for example, along a first direction (e.g., the Z direction). The stacked structure S1 includes a plurality of insulating layers 112 and a plurality of conductive layers 114 alternately stacked along the first direction (e.g., the Z direction). Next, the conductive layers 114 are trimmed by conventional memory process steps so that the edge portions of the conductive layers 114 have a stepped structure to form a semiconductor device 100 including an array region AR and a stepped region AS. Subsequently, a plurality of array openings 116h and a plurality of first openings 118h are formed in the array region AR and the stepped region AS by the same process (e.g., an etching process). The array openings 116h and the first openings 118h pass through the stacked structure S1 along the first direction (e.g., the Z direction) and expose the substrate 110.

[0052] The stepped region AS includes a body portion AS1 electrically connected to the array region AR and a dummy portion AS2 not electrically connected to the array region AR. In the plan view, the first openings 118h are staggered with the contact structure predetermined positions 120' of the body portion AS1. Also, the body portion AS1 of the stepped region AS includes an adjacent first region AS1a and a second region AS1b. Since the conductive layers 114 in the body portion AS1 of the stepped region AS are in a stepped structure, the number of the conductive layers 114 corresponding to the first openings 118h differs in different regions. In the first region AS1a, the number of the conductive layers 114 corresponding to the first openings 118h is between 1 and 10, i.e., the first region AS1a is a region where the first openings 118h pass through 1-10 layers of the conductive layers 114 from the bottom (the layer closest to the substrate 110). In the second region AS1b, the number of the conductive layers 114 corresponding to the first openings 118h is greater than 10, i.e., the second region AS1b is a region where the first openings 118h pass through more than 10 layers of the conductive layers 114 from the bottom (the layer closest to the substrate 110). For example, in the first region AS1a, when the number of the conductive layers 114 corresponding to the first openings 118h is 10, the 10th layer of the conductive layers 114 from the bottom is filled with insulating material and does not have a conductive layer; when the number of the conductive layers 114 corresponding to the first openings 118h is 5, the 5th layer of the conductive layers 114 from the bottom is filled with insulating material and does not have a conductive layer, and so on. In the second region AS1b, when the number of the conductive layers 114 corresponding to the first openings 118h is 11, the 11th layer of the conductive layers 114 from the bottom is filled with insulating material and does not have a conductive layer; when the number of the conductive layers 114 corresponding to the first openings 118h is 15, the 15th layer of the conductive layers 114 from the bottom is filled with insulating material and does not have a conductive layer, and so on. Therefore, when it is stated that "the number of the conductive layers 114 corresponding to the first openings 118h in the first region AS1a is between 1 and 10", it means that the first openings 118h in the first region AS1a exist in an environment where the number of the conductive layers 114 from the bottom is between 1 and 10; when it is stated that "the number of the conductive layers 114 corresponding to the first openings 118h in the second region AS1b is greater than 10", it means that the first openings 118h in the second region AS1b exist in an environment where the number of the conductive layers 114 from the bottom is greater than 10; and the first openings 118h in the first region AS1a and the first openings 118h in the second region AS1b can have the same depth.

[0053] The pattern formed by the first openings 118h of the first area AS1a is different from the pattern formed by the first openings 118h of the second area AS1b as viewed from the top view. In detail, the area of the first openings 118h of the first area AS1a is greater than the area of the first openings 118h of the second area AS1b in a same unit area. According to the present embodiment, the number of the first openings 118h of the first area AS1a is greater than the number of the first openings 118h of the second area AS1b in a same unit area, and the area of each of the first openings 118h of the first area AS1a is equal to the area of each of the first openings 118h of the second area AS1b as viewed from the top view. For example, the number of the first openings 118h of the first area AS1a is twice the number of the first openings 118h of the second area AS1b in a same unit area, but the present application is not limited thereto. In other embodiments, the number of the first openings 118h of the first area AS1a can be three times or more than three times the number of the first openings 118h of the second area AS1b in a same unit area, and the area of each of the first openings 118h of the first area AS1a can be different from the area of each of the first openings 118h of the second area AS1b as viewed from the top view, for example, the area of each of the first openings 118h of the first area AS1a can be greater than the area of each of the first openings 118h of the second area AS1b as viewed from the top view.

[0054] Figure 1B Only eight conductive layers 114 are exemplarily shown, but the present application is not limited thereto, and the stack structure S1 can include more than eight conductive layers 114, which can be adjusted according to requirements. In an embodiment, the stack structure S1 can include sixty conductive layers 114.

[0055] In some embodiments, the substrate 110 can be a silicon substrate or other suitable substrate. The insulating layers 112 can be formed of an oxide, for example, silicon dioxide (SiO2). The conductive layers 114 can be formed of a conductive material, for example, tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped poly-silicon, or other suitable material. The insulating layers 112 and the conductive layers 114 can be formed by deposition, respectively. For example, the deposition for forming the insulating layers 112 can be plasma enhanced chemical vapor deposition (PECVD), for example, using reaction gases silane (SiH4) and nitrous oxide (N2O). When the insulating layers 112 formed by the plasma enhanced chemical vapor deposition are silicon dioxide, the reaction formula is as follows:

[0056] SiH4+ 2N2O→ SiO2+ 2N2+ 2H2(1)

[0057] In some embodiments, the gases (e.g., nitrogen and hydrogen) generated in equation (1) can be trapped in the substrate 110.

[0058] In some embodiments, the array openings 116h and the first openings 118h can be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 110 can be over-etched such that the bottoms of the array openings 116h and the first openings 118h are lower than the upper surface 110a of the substrate 110. However, the etching process can react with the gases trapped in the substrate 110 to produce ammonia (NH3) as a byproduct. The ammonia (NH3) can be detrimental to the formation of the epitaxial growth layers 1161 and 1181 (shown in Figure 2B ), respectively. In particular, the substrate 110 in the first area AS1a can trap a higher concentration of ammonia than the substrate 110 in the second area AS1b.

[0059] According to the present embodiment, since the first openings 118h in the first area AS1a have a larger area than the first openings 118h in the second area AS1b in the same unit area, the first area AS1a has more paths (through the first openings 118h) to vent the etching gases (e.g., ammonia) than the second area AS1b. As a result, the effect of venting the etching gases (e.g., ammonia) in the first area AS1a is better than the effect of venting the etching gases in the second area AS1b, and the epitaxial growth layer 1161 (shown in Figure 2B ) in the first area AS1a can be less affected by the etching gases.

[0060] Thereafter, referring to Figure 2A and Figure 2B , respectively, the memory string structures 116 and the dummy memory string structures 118 are formed in the array openings 116h and the first openings 118h, respectively, wherein each of the memory string structures 116 and each of the dummy memory string structures 118 includes an epitaxial growth layer 1161 and 1181, respectively, extending from the substrate 110 along a first direction (e.g., the Z direction). The epitaxial growth layers 1161 and 1181 are, for example, epitaxial growth layers of silicon. Then, the contact structures 120 are formed at the contact structure predetermined locations 120' in the body portion AS1. The contact structures 120 are disposed in the body portion AS1 of the stepped portion AS, and the contact structures 120 in the body portion AS1 are electrically connected to the corresponding conductive layers 114, respectively. The dummy memory string structures 118 in the dummy portion AS2 are used to support the structure of the semiconductor device 100, and are not electrically connected to other devices or elements.

[0061] According to an embodiment of the present application, the area of the virtual memory string structure 118 of the first area AS1a is greater than the area of the virtual memory string structure 118 of the second area AS1b in a same unit area in a top view. Also, the number of the virtual memory string structure 118 of the first area AS1a can be greater than the number of the virtual memory string structure 118 of the second area AS1b (e.g., 2 times) in a same unit area.

[0062] In some embodiments, the memory string structure 116 and the virtual memory string structure 118 comprise the same structure and material. For example, in addition to the epitaxial growth layers 1161 and 1181, the memory string structure 116 and the virtual memory string structure 118 further comprise a storage layer, a channel layer, and an insulating pillar (not shown). In some embodiments, the memory string structure 116 and the virtual memory string structure 118 can have different sizes.

[0063] In some embodiments, the memory string structure 116, the array opening 116h, the virtual memory string structure 118, the first opening 118h, and the contact structure 120 have a rectangular cross section, but the present application is not limited thereto, and in other embodiments, the memory string structure 116, the array opening 116h, the virtual memory string structure 118, the first opening 118h, and the contact structure 120 can have a circular, elliptical, or other suitable geometric shape.

[0064] In some embodiments, the bottommost conductive layer 114 (i.e., the conductive layer 114 closest to the substrate 110) of the conductive layers 114 can serve as a ground select line; the conductive layers 114 of the middle portion of the stack structure S1 can serve as word lines; and the topmost conductive layer 114 (i.e., the conductive layer 114 farthest from the substrate 110) can serve as a string select line.

[0065] Since the area of the dummy memory string structure 118 of the first area AS1a is greater than the area of the dummy memory string structure 118 of the second area AS1b (i.e. the area of the first opening 118h of the dummy memory string structure 118 of the first area AS1a is greater than the area of the first opening 118h of the dummy memory string structure 118 of the second area AS1b) in the same unit area of the top view, the effect of exhausting the etching gas of the first area AS1a is better than the effect of exhausting the etching gas of the second area AS1b during the formation of the dummy memory string structures 116 and 118 including the epitaxial growth layers 1161 and 1181, so that the epitaxial growth layer 1181 of the first area AS1a can be less affected by the etching gas. Therefore, compared with the comparative example in which the area of the dummy memory string structure of the first area is not greater than the area of the dummy memory string structure of the second area, the epitaxial growth layer 1181 of the dummy memory string structure 118 of the first area AS1a of the present application can have a better growth condition, so that the epitaxial growth layer 1181 can be prevented from being skewed or having a low height, thereby avoiding the problems of short circuit and leakage current (e.g. short circuit between the poor growth epitaxial growth layer and the ground select line).

[0066] In the present embodiment, even in the first area AS1a, the height of the epitaxial growth layer 1181 can be greater than the height of the top surface of the conductive layer 114 of the first layer of the conductive layers 114 most adjacent to the substrate 110.

[0067] Figure 3A A partial top view of a semiconductor device 100P according to a comparative example is shown. Figure 3B A partial top view of a semiconductor device 100A according to an embodiment of the present application is shown. Figure 3A A cross-sectional view along the A-A' line of Figure 4A A partial top view of a semiconductor device 100A according to an embodiment of the present application is shown. Figure 4B A partial top view of a semiconductor device 100A according to an embodiment of the present application is shown. Figure 4A A cross-sectional view along the A-A' line of

[0068] The semiconductor device 100P of the comparative example and the semiconductor device 100A of the present application differ in the pattern of the first opening 118hp (or the dummy memory string structure 118p) in the first area AS1a, and other structures are the same or similar. That is, the first opening 118hp (or the dummy memory string structure 118p) has the same pattern in the first area AS1a and the second area AS1b (as shown in Figure 3AThe first openings 118h (or the dummy memory string structures 118) have different patterns in the first area ASla and the second area ASlb (as shown in FIG. 1C). More specifically, the first openings 118h (or the dummy memory string structures 118) in the first area ASla have a pattern of two first openings 118h (or the dummy memory string structures 118) in a row (as shown in FIG. 1C). In contrast, the first openings 118h (or the dummy memory string structures 118) in the second area ASlb have a pattern of one first opening 118h (or the dummy memory string structure 118) in a row (as shown in FIG. 1C). Figure 4A More specifically, the first openings 118hp (or the dummy memory string structures 118p) in the first area ASla have a pattern of two first openings 118hp (or the dummy memory string structures 118p) in a row (as shown in FIG. 1C). In contrast, the first openings 118hp (or the dummy memory string structures 118p) in the second area ASlb have a pattern of one first opening 118hp (or the dummy memory string structure 118p) in a row (as shown in FIG. 1C). Figure 3A In other words, the first openings 118hp (or the dummy memory string structures 118p) in the first area ASla have an area of two first openings 118hp (or the dummy memory string structures 118p) in a row (1 / 2*4=2) under the same unit area UA. The first openings 118hp (or the dummy memory string structures 118p) in the second area ASlb also have an area of two first openings 118hp (or the dummy memory string structures 118p) in a row (1 / 2*4=2) under the same unit area UA. Figure 4A In other words, the first openings 118h (or the dummy memory string structures 118) in the first area ASla have an area of four first openings 118h (or the dummy memory string structures 118) in a row under the same unit area UA. The first openings 118h (or the dummy memory string structures 118) in the second area ASlb have an area of two first openings 118h (or the dummy memory string structures 118) in a row (1 / 2*4=2) under the same unit area UA. Figure 3A In other words, the first openings 118hp (or the dummy memory string structures 118p) in the first area ASla have an area of two first openings 118hp (or the dummy memory string structures 118p) in a row (1 / 2*4=2) under the same unit area UA. The first openings 118hp (or the dummy memory string structures 118p) in the second area ASlb also have an area of two first openings 118hp (or the dummy memory string structures 118p) in a row (1 / 2*4=2) under the same unit area UA. Figure 4A In other words, the first openings 118h (or the dummy memory string structures 118) in the first area ASla have an area of four first openings 118h (or the dummy memory string structures 118) in a row under the same unit area UA. The first openings 118h (or the dummy memory string structures 118) in the second area ASlb have an area of two first openings 118h (or the dummy memory string structures 118) in a row (1 / 2*4=2) under the same unit area UA.

[0069] According to some embodiments of the present application, the number of the first openings 118h (or the dummy memory string structures 118) in the first area AS1a is greater than the number of the first openings 118h (or the dummy memory string structures 118) in the second area AS1b, under the same unit area UA. For example, in the first area AS1a and the second area AS1b of the semiconductor device 100P, the plurality of first openings 118hp (or the dummy memory string structures 118p) are arranged in a row (e.g., a row R1 of the first openings 118hp (or the dummy memory string structures 118p)) along the third direction (e.g., the Y direction) and arranged in a plurality of rows along the second direction (e.g., the X direction), and one row of the first openings 118hp (or the dummy memory string structures 118p) arranged along the third direction (e.g., the Y direction) is disposed between the adjacent two rows of the contact structure predetermined positions 120' arranged along the third direction (e.g., the Y direction). In the semiconductor device 100, the plurality of first openings 118h (or the dummy memory string structures 118) are arranged in a row (e.g., a row R2 of the first openings 118h (or the dummy memory string structures 118)) along the third direction (e.g., the Y direction) and arranged in a plurality of rows along the second direction (e.g., the X direction). In the first area AS1a, two rows of the first openings 118h (or the dummy memory string structures 118) arranged along the third direction (e.g., the Y direction) are disposed between the adjacent two rows of the contact structure predetermined positions 120' arranged along the third direction (e.g., the Y direction). In the second area AS1b, one row of the first openings 118h (or the dummy memory string structures 118) arranged along the third direction (e.g., the Y direction) is disposed between the adjacent two rows of the contact structure predetermined positions 120' arranged along the third direction (e.g., the Y direction). In this embodiment, the number of the first openings 118h (or the dummy memory string structures 118) in the first area AS1a is twice the number of the first openings 118h (or the dummy memory string structures 118) in the second area AS1b, under the same unit area UA, but the present application is not limited thereto.

[0070] In this embodiment, the first openings 118h (or the dummy memory string structures 118) are disposed on the substrate 110 along the second direction (e.g., the X direction), which is perpendicular to the first direction. In the second direction, the center point Ca1 of the first opening 118h (or the dummy memory string structure 118) disposed in the first area AS1a is aligned with the center point Cb1 of the first opening 118h (or the dummy memory string structure 118) disposed in the second area AS1b.

[0071] According to some embodiments of the present application, when the area ratio of the total area of the first opening 118h (or the dummy memory string structure 118) to the total area of the step region AS is equal to or greater than 8% in a plan view, the gas that adversely affects the growth of the epitaxial layer can be effectively released, so that the epitaxial layer 1181 in the first region AS1a of the semiconductor device 100A of the present application can still have a good growth condition. For example, in the semiconductor device 100P of the comparative example, the area ratio of the total area of the first opening 118hp (or the dummy memory string structure 118p) to the total area of the step region AS1 is equal to 5.44% in a plan view. In the semiconductor device 100A of an embodiment of the present application, the area ratio of the total area of the first opening 118h (or the dummy memory string structure 118) to the total area of the step region AS is equal to 8.99% in a plan view.

[0072] Figure 5 A graph showing the formation height of the epitaxial layer of the dummy memory string structure of the semiconductor device 100A according to an embodiment of the present application and the semiconductor device 100P of the comparative example is shown.

[0073] Figure 5 are the results of measuring the epitaxial layer of the dummy memory string structure at the corresponding position in the semiconductor device 100A and the semiconductor device 100P, respectively. The height of the epitaxial layer is defined as the vertical height between the top surface 110a of the substrate 110 and the top surface of the epitaxial layer, for example. The X coordinate represents the number of the dummy memory string structure, wherein S1-S9 represent the number of the dummy memory string structure in the first region AS1a of the body portion AS1, and D0-D10 represent the number of the dummy memory string structure in the dummy portion AS2.

[0074] Generally, when the height of the epitaxial layer is equal to or greater than 800 angstroms , a good electrical effect can be achieved. As can be seen from the results Figure 5 , in the first region AS1a of the semiconductor device 100P, the height of the epitaxial layer of at least the dummy memory string structures numbered S5 and S1 is less than 800 angstroms. In the first region AS1a of the semiconductor device 100A according to an embodiment of the present application, the height of the epitaxial layer 1181 of all the dummy memory string structures 118 is greater than 800 angstroms.

[0075] Figure 6A A scanning result of the abnormal epitaxial layer of the dummy memory string structure of the semiconductor device 100P of the comparative example is shown. Figure 6B A scanning result of the abnormal epitaxial layer of the dummy memory string structure of the semiconductor device 100A according to an embodiment of the present application is shown.

[0076] Please refer toFigure 6A and Figure 6B If the height of the epitaxial growth layer of the virtual memory serial structure is less than 200 angstroms, it is marked with a black dot as an abnormal epitaxial growth layer of the virtual memory serial structure. Figure 6A The comparative example shows an epitaxial growth layer in the semiconductor device 100P that has some anomalous virtual memory serial structures; Figure 6B The semiconductor device 100A shown in one embodiment of the present invention does not have an epitaxial growth layer of an unusual virtual memory serial structure.

[0077] Depend on Figures 5-6B The results show that, compared to the semiconductor device 100P of the comparative example, since the area of ​​the first opening 118h (or virtual memory serial structure 118) of the first region AS1a of the semiconductor device 100A of the present invention is larger than the area of ​​the first opening 118h (or virtual memory serial structure 118) of the second region AS1b (under the same unit area UA), the gas in the substrate 110 that is unfavorable to the growth of the epitaxial growth layer can be removed more effectively. Even the epitaxial growth layer 1181 of the virtual memory serial structure 118 of the first region AS1a can have better growth, thereby avoiding the above-mentioned problems of short circuit and leakage current.

[0078] Figure 7 A partial top view of a semiconductor device 200 according to another embodiment of the present invention is shown.

[0079] Please refer to Figure 7 In a unit area UA, the area of ​​the first opening 218h (or virtual memory serial structure 218) of the first region AS1a is larger than the area of ​​the first opening 218h (or virtual memory serial structure 218) of the second region AS1b. Semiconductor device 200 is similar to semiconductor device 100A, except that the pattern of the first opening 218h (or virtual memory serial structure 218) of the first region AS1a (e.g., Figure 7 The pattern shown is different from the first opening 118h (or the virtual memory serial structure 118) of the first region AS1a (as shown). Figure 4A (As shown). Furthermore, the first opening 218h (or the virtual memory serial structure 218) is disposed on the substrate 110 along a second direction (e.g., the X direction) and a third direction (e.g., the Y direction), the first direction, the second direction, and the third direction being, for example, perpendicular to each other. In the second direction, the center point Ca2 of the first opening 218h (or the virtual memory serial structure 218) disposed in the first region AS1a is offset from the center point Cb2 of the first opening 218h (or the virtual memory serial structure 218) disposed in the second region AS1b.

[0080] In the semiconductor devices 100A and 200, the center points Cal and Ca2 of the first openings 118h and 218h (or the dummy memory string structures 118 and 218) of the first regions ASla are aligned with each other in the second direction. However, the present application is not limited thereto, and in other embodiments, the center points Cal and Ca2 of the first openings 118h and 218h (or the dummy memory string structures 118 and 218) of the first regions ASla of two adjacent rows can be staggered with each other in the second direction.

[0081] The number and arrangement of the first openings 118h and 218h (or the dummy memory string structures 118 and 218) of the present application can be adjusted arbitrarily, as long as the area of the first openings 118h and 218h (or the dummy memory string structures 118 and 218) of the first regions ASla is greater than the area of the first openings 118h and 218h (or the dummy memory string structures 118 and 218) of the second regions ASlb in a same unit area UA.

[0082] Figure 8A Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application. Figure 8B Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application. Figure 8A Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application.

[0083] Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application. Figure 8A Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application. Figure 8B Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application. Figure 8A Fig. 4 shows a partial top view of a semiconductor device 300 according to another embodiment of the present application. Figure 4AFurther, the diameter D1 of the first opening 318h (or the dummy memory string structure 318) of the first area AS1a is greater than the diameter D2 of the first opening 318h (or the dummy memory string structure 318) of the second area AS1b. In an embodiment, the diameter D1 of the first opening 318h (or the dummy memory string structure 318) of the first area AS1a is greater than the diameter D2 of the first opening 318h (or the dummy memory string structure 318) of the second area AS1b by more than 10%. For example, when the diameter D2 of the first opening 318h (or the dummy memory string structure 318) of the second area AS1b is 80 nm, the diameter D1 of the first opening 318h (or the dummy memory string structure 318) of the first area AS1a can be any value greater than 88 nm, such as 90 nm or 100 nm.

[0084] In some embodiments, the first openings 318h (or the dummy memory string structures 318) are disposed along a second direction (e.g., the X direction) and a third direction (e.g., the Y direction) on the substrate 110, and the first direction, the second direction, and the third direction can be perpendicular to each other. In the second direction, the center point Ca3 of the first opening 318h (or the dummy memory string structure 318) disposed in the first area AS1a is aligned with the center point Cb3 of the first opening 318h (or the dummy memory string structure 318) disposed in the second area AS1b.

[0085] Figure 9A A scanning result of the epitaxial growth layer of the abnormal dummy memory string structure of the semiconductor device 100P of the comparative example is shown. Figure 9B A scanning result of the epitaxial growth layer of the abnormal dummy memory string structure of the semiconductor device 300 according to an embodiment of the present application is shown. Figure 9C A scanning result of the epitaxial growth layer of the abnormal dummy memory string structure of the semiconductor device 300 according to another embodiment of the present application is shown.

[0086] In Figure 9A In the comparative example shown, the diameter of the first opening 118hp of the first area AS1a is 80 nm. In Figure 9B In an embodiment of the semiconductor device 300, the diameter of the first opening 318h of the first area AS1a is 90 nm. In Figure 9C In another embodiment of the semiconductor device 300, the diameter of the first opening 318h of the first area AS1a is 100 nm.

[0087] Please refer to Figures 9A-9C If the height of the epitaxial growth layer of the dummy memory string structure is less than 200 angstroms, the epitaxial growth layer of the abnormal dummy memory string structure is marked with a black dot. Figure 9AThe epitaxial growth layer of the semiconductor device 100P of the comparative example has some abnormal virtual memory string structures. Figure 9B and Figure 9C The semiconductor device 300 of some embodiments of the present application does not have abnormal virtual memory string structures.

[0088] Figure 10 A partial top view of a semiconductor device 400 according to another embodiment of the present application is shown.

[0089] Please refer to Figure 10 In a same unit area UA, the area of the first openings 418h (or the virtual memory string structures 418) of the first region AS1a is greater than the area of the first openings 418h (or the virtual memory string structures 418) of the second region AS1b. The semiconductor device 400 is similar to the semiconductor device 300, except that the pattern of the first openings 418h (or the virtual memory string structures 418) of the first region AS1a (as shown in FIG. 4) is different from the pattern of the first openings 318h (or the virtual memory string structures 318) of the first region AS1a (as shown in FIG. 3). Figure 10 Figure 8A Further, the center points Ca4 of the first openings 418h (or the virtual memory string structures 418) of the first region AS1a are staggered with the center points Cb4 of the first openings 418h (or the virtual memory string structures 418) of the second region AS1b in the second direction (e.g., the X direction) and the third direction (e.g., the Y direction).

[0090] The number and arrangement of the first openings 318h and 418h (or the virtual memory string structures 318 and 418) of the present application can be adjusted arbitrarily, as long as the area of the first openings 318h and 418h (or the virtual memory string structures 318 and 418) of the first region AS1a is greater than the area of the first openings 318h and 418h (or the virtual memory string structures 318 and 418) of the second region AS1b in a same unit area UA.

[0091] ​According to some embodiments of the present application, in a same unit area UA, only the area of the first openings 118h (or the virtual memory string structures 118) of the first region AS1a needs to be increased (for example, by increasing the number or diameter of the first openings 118h of the first region AS1a) to achieve the effect of preventing the epitaxial growth layer from being skewed or insufficient in height, and the areas of the first openings 118h (or the virtual memory string structures 118) of the first region AS1a and the second region AS1b do not need to be increased at the same time, so the cost can be greatly saved.

[0092] The present application provides a semiconductor device and a manufacturing method thereof. According to an embodiment, the semiconductor device includes a substrate, a stack structure disposed on the substrate, and a plurality of virtual memory string structures. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The virtual memory string structures are disposed in a staircase region of the semiconductor device and pass through the stack structure along the first direction, wherein the staircase region includes a body portion, and the body portion includes a first region and a second region adjacent to each other. In the first region, the number of the conductive layers corresponding to the virtual memory string structures is between 1 and 10; in the second region, the number of the conductive layers corresponding to the virtual memory string structures is greater than 10. In a same unit area, the area of the virtual memory string structures in the first region is greater than the area of the virtual memory string structures in the second region.

[0093] Compared with a comparative example in which the area of the virtual memory string structures in the first region is not greater than the area of the virtual memory string structures in the second region (in a same unit area), since the area of the virtual memory string structures in the first region of the semiconductor device of the present application is greater than the area of the virtual memory string structures in the second region (in a same unit area), the gas of the epitaxial growth layer of the virtual memory string structures in the first region of the present application can be more effectively released, so that the epitaxial growth layer of the virtual memory string structures in the first region of the present application can have a better growth condition, and can prevent the epitaxial growth layer from being skewed or insufficient in height, thereby avoiding the electrical problems such as short circuit and leakage current.

[0094] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application, and it should be understood that the above-described specific embodiments are only specific embodiments of the present application and are not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, comprising: a substrate and a stack structure disposed on the substrate, the stack structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; and a plurality of dummy memory string structures disposed in a stepped region of the semiconductor device and passing through the stack structure along the first direction, wherein the stepped region includes a body portion, and the body portion includes a first region and a second region adjacent to each other, in the first region, a number of the conductive layers corresponding to the dummy memory string structures is between 1 and 10, in the second region, the number of the conductive layers corresponding to the dummy memory string structures is greater than 10, wherein in a plan view, an area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second region in a same unit area, and wherein a distance between the dummy memory string structures in the first region is less than a distance between the dummy memory string structures in the second region.

2. The semiconductor device of claim 1, wherein a number of the dummy memory string structures in the first region is greater than a number of the dummy memory string structures in the second region in the same unit area.

3. The semiconductor device of claim 2, wherein the dummy memory string structures are disposed on the substrate along a second direction perpendicular to the first direction, in the second direction, center points of the dummy memory string structures disposed in the first region are aligned with center points of the dummy memory string structures disposed in the second region.

4. The semiconductor device of claim 2, wherein the dummy memory string structures are disposed on the substrate along a second direction perpendicular to the first direction, in the second direction, center points of the dummy memory string structures disposed in the first region are staggered with center points of the dummy memory string structures disposed in the second region.

5. The semiconductor device of claim 1, wherein a diameter of each of the dummy memory string structures in the first region is greater than a diameter of each of the dummy memory string structures in the second region.

6. The semiconductor device of claim 5, wherein the diameter of each of the dummy memory string structures in the first region is more than 10% greater than the diameter of each of the dummy memory string structures in the second region.

7. The semiconductor device of claim 5, wherein the dummy memory string structures are disposed on the substrate along a second direction perpendicular to the first direction, in the second direction, center points of the dummy memory string structures disposed in the first region are aligned with center points of the dummy memory string structures disposed in the second region.

8. The semiconductor device of claim 5, wherein the dummy memory string structures are disposed on the substrate along a second direction perpendicular to the first direction, in the second direction, center points of the dummy memory string structures disposed in the first region are staggered with center points of the dummy memory string structures disposed in the second region. In the second direction, the center points of the virtual memory string structures disposed in the first region are staggered with the center points of the virtual memory string structures disposed in the second region.

9. The semiconductor device according to claim 1, wherein an area ratio of a total area of the virtual memory string structures to a total area of the staircase region is equal to or greater than 8% in a top view.

10. A method for manufacturing a semiconductor device, comprising: providing a substrate and a stack structure disposed on the substrate, the stack structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; and forming a plurality of first openings in a staircase region of the semiconductor device, the first openings passing through the stack structure along the first direction, wherein the staircase region includes a body portion, and the body portion includes a first region and a second region adjacent to each other, in the first region, a number of the conductive layers corresponding to the first openings is between 1 and 10; in the second region, a number of the conductive layers corresponding to the first openings is greater than 10, wherein in a top view, an area of the openings in the first region is greater than an area of the first openings in the second region in a same unit area; wherein a distance between the virtual memory string structures in the first region is less than a distance between the virtual memory string structures in the second region.

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