Semiconductor package with sidewall plating

Abstract

Disclosed herein is a technique for forming a dual flat no-lead semiconductor package. The technique begins with a package assembly comprising a plurality of unsingulated packages. The semiconductor package assembly includes a leadframe assembly having a die coupled thereto. A molded encapsulation covers at least some portion of the die and exposes a plurality of leads. A first cutting step exposes the sidewalls of the leads of the leadframe. A plating step deposits a plating layer on the exposed leads. A second cutting step cuts through the molded encapsulation aligned with the step-cut sidewalls. A third cutting step, perpendicular to the step-cut, is formed through the leadframe and molded encapsulation to separate the die into individual packages.

Description

Background Art

[0001] Flat “no-leads” or “leadless” semiconductor packages electrically and physically couple an integrated circuit die (or “chip”) to a printed circuit board (“PCB”) via flat leads and without vias extending through the printed circuit board (“PCB”). It should be noted that although these packages are referred to as “no-leads” or “leadless” packages, the term “leads” in this disclosure is used to refer to the flat contact pads present on the flat no-lead packages. These packages have no “leads,” meaning that no leads extend over or beyond the perimeter of the package. Flat no-lead packages can be categorized as quad flat no-lead (“QFN”) packages, which have leads on all four sides of the package, and dual flat no-lead (“DFN”) packages, which have leads on two opposing sides. Within these packages, one or more integrated circuit dies are encapsulated in a non-conductive molding material. A conductive lead frame, typically made of a metal such as copper, is electrically coupled to the internal components of the package (such as the die) and exposes leads externally that can be electrically coupled to the PCB. Improvements to flat no-lead packages are continually being made.

[0002] Leadless packages offer several advantages over packages with leads that extend beyond the package perimeter. They can have a lower profile than other types of packages. They can also take up less space than traditional packages with leads that extend beyond the package perimeter, resulting in a smaller "footprint" on a printed circuit board. They can also offer better thermal performance than packages with leads that extend beyond the package perimeter.

[0003] As it relates to QFN and DFN semiconductor packages, one problem within the industry is the inspection of the solder connections of the package leads. In order to ensure proper solder connections of QFN and DFN semiconductor packages, it is necessary to inspect the connections. These inspections can be performed, for example, by X-rays, or by automated optical inspection (AOI). Automated optical inspection (AOI) systems are used to inspect defects in, for example, semiconductor devices and printed circuit boards (PCBs). QFN and DFN semiconductor packages can allow for AOI that is less expensive than X-ray inspection if the leads are oriented in such a way that a portion of the side or "flank" of the lead can be wetted by solder (for example, by allowing the solder to wick onto the side or sidewall of the exposed lead).

[0004] Therefore, there is a need for an efficient method of manufacturing DFN semiconductor packages that provides wettable flanks, thereby allowing AOI to confirm proper solder connections. Summary of the Invention

[0005] In one aspect of the present invention, a method for manufacturing a semiconductor package having step-cut wettable flanks is provided. The method includes forming a first series of parallel cuts through a plating bar of a package assembly and partially through a molded encapsulation of the package assembly, wherein the package assembly includes a plurality of die packages organized in rows, each die package having an integrated circuit die and a plurality of leads encapsulated in a molded encapsulation, wherein the die packages are electrically coupled together via the plating bar, and wherein within each die package, the die pads are electrically coupled to opposing plating bars via one or both of tie bonds and wire bonds. The method also includes electroplating exposed surfaces of the leads. The method also includes forming a second series of parallel cuts aligned with the first series of parallel cuts, the second series of parallel cuts extending completely through the molded encapsulation to form the step-cut wettable flanks. The method also includes forming a third series of parallel cuts perpendicular to the first and second series of parallel cuts, the third series of parallel cuts being formed completely through the molded encapsulation and the leadframe.

[0006] In another aspect of the present invention, a dual flat no-lead ("DFN") semiconductor package is provided that is manufactured by a method for manufacturing a semiconductor package with step-cut wettable flanks. The method includes forming a first series of parallel cuts through a plating bar of a package assembly and partially through a molded encapsulation of the package assembly, wherein the package assembly includes a plurality of die packages organized in rows, each die package having an integrated circuit die and a plurality of leads encapsulated in a molded encapsulation, wherein the die packages are electrically coupled together via the plating bar, and wherein within each die package, the die pads are electrically coupled to opposing plating bars via one or both of tie bonds and wire bonds. The method also includes electroplating exposed surfaces of the leads. The method also includes forming a second series of parallel cuts aligned with the first series of parallel cuts, the second series of parallel cuts extending completely through the molded encapsulation to form the step-cut wettable flanks. The method also includes forming a third series of parallel cuts perpendicular to the first series of parallel cuts and the second series of parallel cuts, the third series of parallel cuts being formed completely through the molded encapsulation and the leadframe.

[0007] In another aspect of the present invention, a dual flat no-lead ("DFN") semiconductor package is provided. The DFN semiconductor package includes a molded encapsulation. The DFN semiconductor package also includes a lead frame at least partially disposed within the molded encapsulation, wherein the lead frame has an integrated circuit die disposed on a die pad of the lead frame, the lead frame further having one of tie bars or wire bonds extending from the die pad to an edge of the molded encapsulation. The DFN semiconductor package also includes a pair of opposed step-cut wettable flanks on opposite sides of the package that expose sidewalls of leads of the lead frame to be electrolytically plated. The electrolytically plated sidewalls are configured to receive solder for attachment to, for example, a printed circuit board ("PCB"). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more detailed understanding may be gained from the following description given by way of example in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a flow chart of an illustrative method for forming a package assembly according to one example;

[0010] Figure 1B is a flow chart of an illustrative method for forming a DFN semiconductor package according to one example;

[0011] Figure 2A shows a first set of cutouts formed in a package assembly according to one example;

[0012] Figure 2B shows electroplating applied to wettable flanks of a package assembly according to one example;

[0013] Figure 2C A second set of cuts is shown, according to one example, aligned with the step-cut wettable flanks and formed completely through the molding;

[0014] Figure 2D A third set of cuts is shown, perpendicular to the first and second sets of cuts, to separate the dies, according to one example;

[0015] Figure 2E shows a singulated die with wettable flanks according to one example;

[0016] Figure 3A is shown according to an example Figure 2A a cross-sectional view of the first series of cuts;

[0017] Figure 3B is shown according to an example Figure 2C a cross-sectional view of the second series of cuts;

[0018] Figure 4Ashows a top orthogonal view of a singulated die with wettable flanks according to one example;

[0019] Figure 4B shows a transparent top orthogonal view of a singulated die with wettable flanks according to one example;

[0020] Figure 4C shows a bottom orthogonal view of a singulated die with wettable flanks according to one example;

[0021] Figure 4D shows a transparent bottom orthogonal view of singulated dies with wettable flanks according to one example; and

[0022] Figure 5 An electrolytic plating technique according to one example is shown. DETAILED DESCRIPTION

[0023] Certain terms are used in the following description for convenience only and are not limiting. The words "right," "left," "top," and "bottom" indicate directions in the accompanying drawings to which reference is made. Unless expressly stated otherwise, the words "a" and "an" used in the claims and corresponding parts of the specification are defined to include one or more of the referred-to items. This terminology includes the words specifically mentioned above, their derivatives, and words of similar meanings. The phrase "at least one" followed by a list of two or more items (such as "A, B, or C") means any individual one of A, B, or C and any combination thereof.

[0024] The description provided herein is intended to enable those skilled in the art to make and use the described embodiments. However, various modifications, equivalents, variations, combinations, and substitutes will be apparent to those skilled in the art. Any and all such modifications, variations, equivalents, combinations, and substitutes are intended to fall within the spirit and scope of the present invention as defined by the claims.

[0025] Disclosed herein is a technique for forming wettable flanks on DFN semiconductor packages. The technique begins with a package assembly comprising multiple unsingulated packages. The package assembly includes a leadframe assembly having a die and other internal package components (e.g., wire bonds) coupled thereto. The die and other components form distinct regions of the unsingulated package. The die and other components are encapsulated within a non-conductive mold encapsulation material (also referred to as a "mold," "molding," "encapsulation," "encapsulation material," or other similar terms herein). The non-conductive mold encapsulation material covers most of the package components but may leave exposed certain electrical contact pads (referred to herein as "leads") and thermal contact pads (referred to herein as "die pads"). The leadframe provides a continuous electrical connection between one end of the package assembly and between the various exposed leads and die pads of the package. Elements such as wire bonds or tie bars may assist in forming the electrical connections. This electrical connection is used to allow current flow during the electroplating process. At the boundaries of the areas defining the different packaged die are plating bars, which are portions of the lead frame assembly that electrically connect the different die packages before the die packages are singulated.

[0026] A cutting device (such as a saw, water jet cutting device, laser cutting device, or plasma cutting device) forms a stepped cut through the lead frame and partially but not completely through the molded part at a certain depth to expose certain side walls of the leads. At least some portions of these exposed side walls are then electrolytically plated. In addition, the bottom surface of the leads is electrolytically plated, and the bottom surfaces of certain exposed die pads or contact pads may be electrolytically plated. Within each die package, the die pads are coupled to left and right plating bars via tie bars or wire bonds to allow current to flow for electrolytic plating. Subsequently, the cutting device forms a cut completely through the molded part in the same direction and position as the first cut to separate the rows of die packages. A third set of cuts is formed perpendicular to the first and second sets of cuts to separate the die. The exposed edges of the third set of cuts are not plated. Thus, the finished semiconductor package can be formed as a DFN semiconductor package.

[0027] Figure 1Ais a flow chart of an illustrative method 100 for forming a package assembly according to one aspect of the present invention. Method 100 begins at step 102, where one or more dies are deposited onto a leadframe assembly. The leadframe assembly includes multiple package leadframes integrated into a single component or unit. The leadframe assembly may include one or more fiducial marks, which are machine-detectable markings that allow the machine to align itself for cutting. The leadframe assembly may be made of any metal alloy. Die packages are typically formed in an array of die packages and then cut ("singulated") into individual die packages. To form the array, individual leadframe assemblies are cut from a leadframe material such as a copper sheet. The leadframe assembly has multiple leadframe sections corresponding to individual packages integrated therein. In step 102, one or more integrated circuit dies are deposited onto the leadframe assembly. In step 104, other components such as wire bonds, conductive clips (elements within the package that couple the die to one or more leads), or other components are deposited to form the package. In step 106, a molded encapsulation is deposited around the leadframe and other package components. The molded encapsulant provides a physical and electrical barrier for the packaged components.At the conclusion of method 100, the package assembly includes a plurality of unsingulated packaged dies with the package components (eg, dies, leadframes, and components coupling the dies to the leadframes) encapsulated within the molding material.

[0028] Figure 1B is a flow chart of an illustrative method 100 for forming a DFN semiconductor package according to one aspect of the present invention. Figures 2A-2E discuss Figure 1B Method 150, Figures 2A-2E 1 shows the stages of the package assembly 200 as the method 150 proceeds. The method 150 begins with the package assembly 200 (e.g. Figure 2A ), the package assembly 200 includes a lead frame assembly 205 having an integrated circuit die disposed thereon and attached thereto. The die is at least partially surrounded by an encapsulation material 202. The continuous lead frame assembly 205 includes Figure 2A 1 and 12. The package is shown in FIG. 1 , which is a perspective view of a package comprising a plurality of plated bars 203, a die pad 206 (or "pad"), and package edge leads 204 that are fully electrically coupled together. The leads 204 are formed of a conductive material and are configured to receive electroplating (as described in further detail herein) to serve as solderable contact points of the package to be connected to a printed circuit board. A non-conductive mold encapsulant material 202 surrounds the lead frame assembly 205. The package is a dual flat no-lead ("DFN") package in that the package has two opposing wettable lead sides 207 that include the plurality of leads 204 for external electrical coupling and two opposing non-wettable sides 209 that do not include leads.

[0029] The package assembly 200 includes an array of uncut (or "bonded" or "unsingulated") packages 210. The packages include circuit elements such as integrated circuit dies, conductive elements such as wire bonds, and Figures 2A-2E 200, except for tie bars 215, 217, and 219 which are not exposed on the bottom surface of the package, as these figures only show the bottom surface of the package assembly 200 (except for tie bars 215, 217, and 219 which are not exposed on the bottom surface of the package, as these elements are inside the molded encapsulation 202, but are shown for clarity). Figures 2A-2E ). More specifically, it should be understood that in the package assembly 200 shown, the molded encapsulant 202 has been deposited around the lead frame 204 and other components, so that what is seen is the portion of the molded encapsulant 202 and the lead frame 205 exposed through the molded encapsulant 202. The particular package construction shown and described in this specification is an example, and the details of the construction should not be considered limiting. For example, each package 210 is shown as having a die pad 206, a gate lead 213, and a source lead 211. Thus, in the package 210, the die thermally coupled to the die pad 206 is electrically coupled to the leads 204, as well as the gate lead 213 and the source lead 211 via conductive elements (such as wire bonds) inside the package 210. Although a particular number and configuration of leads 204 are shown, the technology of the present disclosure is applicable to packages 210 having any configuration of leads 204 and / or die pads 206. For example, in some packages, the gate lead and / or source lead may not be present. The leads can be present in any configuration. Furthermore, any number of dies can be present within a package, each connected to leads in a different configuration.

[0030] The plating bars 203 are portions of the leadframe assembly 205 that do not ultimately form the leadframes of the individual die packages 210 after the die packages 210 are singulated. In other words, the plating bars 203 provide structural integrity and conductivity across the die packages 210 for electroplating.

[0031] At step 152, a cutting device performs a first step cut completely through the lead frame 205 and partially through the molded encapsulation 202. The cut is made adjacent to the wettable lead side 207 of the package 210 so as to expose the sidewalls of the leads 204 for plating. The cutting device can be, for example, a saw with a physical blade, a laser cutter, a plasma cutter, or a water jet cutter, or any other acceptable cutting technique known to those skilled in the art. These cuts may be referred to herein as a first series of parallel cuts. Cutting as Figure 2AAs shown. The width of the blade (or other cutting element) used is sufficient to cut the edges of the leads 204 of two adjacent die packages 210. In addition, the cut is formed completely through the lead frame 205 (specifically, through the horizontal plating strip 203) but not completely through the corresponding molded encapsulation, which allows the package assembly 200 to be processed as a single integrated or connected unit through subsequent steps. The cutting of step 152 forms sidewalls 220 at portions of the leads 204.

[0032] In step 154, an electrolytic plating process is performed using an electrolytic plating device to plate the lead frame assembly 205. The lead frame is typically made of a material such as copper. A layer of metal (e.g., tin or a tin alloy) is plated on the surface of the copper to prevent oxidation and provide a wettable surface for soldering. In a typical electrolytic plating device, the lead frame is immersed in a tin solution and electrically coupled to the negative electrode of the electrolytic plating device. The positive electrode is coupled to the plating material, which is also immersed in the solution. An electric current is applied to the lead frame, which causes the plating material to be deposited on the surface of the lead frame, so that the leads 204 and the die pad 206 are plated with the plating material. In the electrolytic plating technology used in the technology described herein, plating materials other than tin (such as gold, palladium, or silver) can be used. The incision formed in step 152 exposes the wettable sidewalls 220 of the leads 204, so that the leads 204 are plated with the plating material. The cuts formed in step 152 electrically decouple the leadframe rows, but within each row, electrical continuity exists from left to right as oriented in the figure. More specifically, within each package 210, current flows from the left plating bar 203 through each component to be plated in package 210 to the right plating bar 203, and then through the shared plating bar 203 to the next package 210. Each individual component to be plated in each package 210 is thus electrically coupled to both the left and right plating bars 203. Specifically, the die pad 206 is coupled to the left plating bar 203 via a tie bar 215. A tie bar is a portion of the leadframe that provides electrical conductivity and / or structural continuity between components in the die package 210 and the plating bar 203 or other components external to the die package 210. In some examples, the tie bar is typically thinner than other conductive components that are part of the leadframe 205 and extend beyond the die package 210, and the tie bar typically does not extend to the bottom surface of the die package 210. The die pad 206 is also electrically coupled to a number of leads 204. The die pad 206 is also coupled to the right plated bar 203 via tie bars 217. The source lead 211 and the gate lead 213 are both coupled to the right plated bar 203 via tie bars 219. Any of the source and gate lead tie bars 219, as well as the tie bars 217 coupling the die pad 206 to the right plated bar 203, can be replaced with other conductive elements, such as wire bonds, to achieve the purpose of coupling the die pad 206, the gate lead 213, or the source lead 211 to the right plated bar 203. Wire bonds differ from tie bars in that wire bonds are not part of the lead frame, but are deposited or coupled between portions or components of the lead frame, such as between the die pad and the leads, to provide an electrical connection.

[0033] At step 156, the cutting device forms a second set of parallel cuts aligned with the first set of parallel cuts. Figure 2CAs shown, the width of the second set of parallel cuts is smaller than the width of the first set of cuts formed in step 152. These cuts form the step-cut wettable flanks of the die and completely separate the molded package into different rows. The step-cut wettable flanks are step-cut sides that expose the sidewalls of the leads for applying solder so that they can be inspected, for example, by AOI. The two widths of the step cuts are Figure 2C Shown in FIG. 1 are width 1 ( W1 ) and width 2 ( W2 ), where W1 is greater than W2 .

[0034] At step 158, the sawing equipment forms a third set of parallel cuts perpendicular to the first and second sets of parallel cuts. The third set of parallel cuts are aligned to cut through the plating strips 203 to separate the dies 210. The third set of parallel cuts are formed deep enough to completely cut through the lead frame 205 and the molded encapsulation 202. Figure 2E A singulated package 210 is shown having wettable flanks.

[0035] Figures 3A-3B Details are shown in relation to steps 152 and 156. In both figures a cutting machine 301 is shown. Figure 3A As shown in step 152 and as Figure 2A An example of a step cut shown partially completely through the leadframe and partially through the molding. Figure 3A The cutouts shown in FIG. 2 are formed at a first thickness configured to expose sidewalls of the leads 204 of the package 210 . Figure 3A The cuts shown in are made with a saw blade having a thickness marked “Z1”, but any technically feasible means for making the cuts may be used, such as a laser cutter, plasma cutter or water jet cutter, or any other acceptable cutting technique known to those skilled in the art.

[0036] Figure 3B An example of a second step cut is shown that completely passes through the cuts made in steps 152 and 154. Figure 2A The lead 204 has plating material 310 deposited thereon via electrolytic plating to form step-cut wettable flanks 312 .

[0037] Figures 4A-4D Different views of the singulated die package 210 are shown, showing the Figure 1B The step cuts formed by the method 150 may wet the flanks. Figure 4A and Figure 4B An orthogonal view is shown showing the top and side of the package 210; Figure 4C and Figure 4D An orthogonal view is shown, illustrating the bottom and sides of the package 210 .

[0038] Reference together Figures 4A-4D The depicted package 210 includes a molded encapsulation 202 and has step-cut wettable flanks 312 with a molded flank 312 having a molded flank 312 having a molded flank 312 according to Figure 1B 2. Electrolytic plating is formed on two opposing sides of the leads 204 using the techniques described in

[15] . Step-cut wettable flanks 312 include the portion of the die package 210 where the step cuts of steps 152 and 156 were performed, and also include the electrolytically plated leads 204. The edges of the portions of the tie bars 215, 217, and 219 that are electrically coupled to the lead frame 205 inside the molded encapsulation 202 are exposed in the non-plated side of the package 210. Figure 4C and Figure 4D The bottom surfaces of the leads 204 and die pad 206 are shown, and are electrolytically plated as described elsewhere herein.

[0039] Internally, the package 210 shown includes a die 402. The die 402 is mounted on and thermally coupled to the die pad 206, which is part of the lead frame 205. Wire bonds couple the die 404 to the leads 204 of the lead frame 205. A source lead 211 and a gate lead 213 are coupled to the die 402 via the wire bonds 404. In addition, the source lead 211 is coupled to a tie bar 219, which is not plated and does not play a role in the finished package, but is used to maintain electrical continuity between the die and the package as described with respect to FIG. Figure 1B and Figures 2A-2E The purpose of the plating is as described above. Gate lead 213 is coupled to tie bar 219, which is also not plated and serves a similar function to tie bar 219 for source lead 211. Die pad 206 is coupled to tie bar 217, which also does not serve any purpose in the finished package and is not plated, but is used during the plating process to establish a complete electrical connection across different die packages. Tie bar 215 is present on the opposite side and is coupled to die pad 206. Tie bar 215 serves a similar purpose to the other tie bars and is not plated.

[0040] Figure 5 An illustrative electrolytic plating technique is shown. This technique can be used, for example, as part of step 104 (e.g., Figure 2B According to this technology, in the electroplating equipment 500, the package component 200 ( Figure 5 205) is placed in solution 502. The negative terminal of power supply 504 is electrically coupled to lead frame 205, and the positive terminal of power supply 504 is coupled to plating material 506. When power supply 504 applies current, plating material 508 is deposited on the exposed surface of lead frame 205.

[0041] It should be understood that the foregoing is presented as an illustration only and not as a limitation. It is expected that various substitutions and modifications may be made to the described embodiments without departing from the spirit and scope of the invention. Having described the invention in such detail, it should be understood and will be apparent to those skilled in the art that many physical changes may be made without changing the inventive concepts and principles embodied therein, only a few of which are illustrated in the detailed description of the invention. It should also be understood that many embodiments are possible that incorporate only a portion of the preferred embodiments, and with respect to these portions, these embodiments do not change the inventive concepts and principles embodied therein. Therefore, the embodiments of the present invention and optional configurations are considered in all respects to be exemplary and / or illustrative and not restrictive, and the scope of the invention is specified by the appended claims rather than the foregoing description, and therefore, all alternative embodiments and changes to the embodiments that fall within the equivalent meaning and scope of the claims are also included therein.

Claims

1. A method for manufacturing a semiconductor package, the method comprising: A lead frame assembly is provided, the lead frame assembly comprising: a plurality of plated bars, the plurality of plated bars comprising a first group of plated bars spaced apart from each other and extending in a first direction, and a second group of plated bars spaced apart from each other and extending in a second direction perpendicular to the first direction; and a plurality of die packages organized in rows, wherein each die package has an integrated circuit die, each die package of the plurality of die packages having a bottom surface, a first side and an opposite second side, a third side and an opposite fourth side, each of the plurality of die packages is positioned between a plating bar in the first group of plating bars adjacent to the first side of the die package and an opposite plating bar in the first group of plating bars adjacent to the second side of the die package, attached to and electrically coupled to the plating bar and the opposite plating bar, and each of the plurality of die packages is positioned between a plating bar in the second group of plating bars adjacent to the third side of the die package and an opposite plating bar in the second group of plating bars adjacent to the fourth side of the die package, attached to and electrically coupled to the plating bar and the opposite plating bar; Each die package of the plurality of die packages comprises: a die pad electrically coupled to a respective one of the first set of plating bars adjacent to a first side of the die package via a single first tie bar and to a respective opposite one of the first set of plating bars adjacent to a second side of the die package via a single second tie bar; a plurality of leads, each of the plurality of leads having a sidewall and a bottom surface, at least some of the plurality of leads extending from and electrically coupled to the die pad, at least one lead of the plurality of leads being spaced apart from the die pad and electrically coupled to a corresponding plating strip of the first set of plating strips adjacent to a second side of the die package via a single third tie bar; encapsulating at least some portions of the lead frame assembly with a mold encapsulant while exposing bottom surfaces of the plurality of leads and a bottom surface of the die pad, the lead frame assembly and mold encapsulant forming a package assembly; forming a first series of parallel cuts completely through the second set of plated bars of the package assembly and partially through a molded encapsulation of the package assembly to create exposed portions of surfaces of sidewalls of the plurality of leads; electroplating at least some of the exposed portions of the surfaces of the sidewalls of the plurality of leads; forming a second series of parallel cuts aligned with the first series of parallel cuts, the second series of parallel cuts extending completely through the molded encapsulation, the second series of parallel cuts having a width less than the width of the first series of parallel cuts, thereby forming a step-cut wettable side; and A third series of parallel cuts is formed completely through the mold encapsulation and the first set of plated strips, perpendicular to the first series of parallel cuts and the second series of parallel cuts.

2. The method according to claim 1, wherein: A first group of the plurality of leads is positioned adjacent a third side of a corresponding one of the plurality of die packages, and wherein a second group of the plurality of leads is positioned adjacent a fourth side of a corresponding one of the plurality of die packages.

3. The method according to claim 2, wherein: The side walls of the first group of leads are aligned with each other along facing surfaces of corresponding plating strips in the second group of plating strips adjacent to the third side of the corresponding tube core package, and wherein the side walls of the second group of leads are aligned with each other along facing surfaces of corresponding plating strips in the second group of plating strips adjacent to the fourth side of the corresponding tube core package.

4. The method according to claim 1, wherein: The at least one of the plurality of leads that is spaced apart from the die pad comprises a gate lead.

5. The method according to claim 4, wherein: At least one of the plurality of leads includes a source lead spaced apart from the die pad and the gate lead and electrically coupled to a same respective plating bar as the gate lead via a single fourth tie bar.

6. The method according to claim 5, in, The second tie bar extends between the gate lead and the source lead.

7. The method according to claim 1, further comprising: The exposed bottom surface of the die pad is electroplated, and the exposed bottom surfaces of the plurality of leads are electroplated.

8. The method according to claim 1, wherein The first side of each die package of the plurality of die packages and the second side of each die package of the plurality of die packages are not electrolytically plated.

9. The method according to claim 1, wherein The width of the first tie rod is greater than the width of the second tie rod.

10. A method for manufacturing a semiconductor package, the method comprising: providing a die package, the die package comprising a die pad and a plurality of leads, the die pad and the leads having bottom surfaces, each of the leads having sidewalls, wherein at least some of the leads extend from and are electrically coupled to the die pad, and wherein at least one lead of the plurality of leads is spaced apart from the die pad; providing a plurality of plating bars surrounding, attached to, and electrically coupled to the die package, the plurality of plating bars including a first group of plating bars spaced apart from one another and extending in a first direction, and a second group of plating bars spaced apart from one another and extending in a second direction, the second direction being perpendicular to the first direction; electrically coupling the first side of the die pad to a plating bar of a first group of plating bars in the plurality of plating bars via a single first tie bar; electrically coupling an opposite second side of the die pad to a different one of a first set of the plurality of plating bars via a single second tie bar; electrically coupling the at least one of the plurality of leads spaced apart from the die pad to one of a first group of the plurality of plating bars via a single third tie bar; encapsulating at least some portions of the die package and at least some portions of the plurality of plated bars with a mold encapsulant while exposing bottom surfaces of the plurality of leads and a bottom surface of the die pad; forming a first series of parallel cuts through a second set of the plurality of plated bars and partially through the mold encapsulation to create exposed portions of surfaces of sidewalls of the plurality of leads; electroplating at least some of the exposed portions of the surfaces of the sidewalls of the plurality of leads; forming a second series of parallel cuts aligned with the first series of parallel cuts, the second series of parallel cuts extending completely through the molded encapsulation, the second series of parallel cuts having a width less than the width of the first series of parallel cuts, thereby forming a step-cut wettable side; and A third series of parallel cuts is formed, the third series of parallel cuts being perpendicular to the first series of parallel cuts and the second series of parallel cuts, the third series of parallel cuts being formed completely through the mold encapsulation and a first set of the plurality of plated strips.

11. The method according to claim 10, wherein: The at least one of the plurality of leads that is spaced apart from the die pad comprises a gate lead.

12. The method according to claim 11, wherein: At least one of the plurality of leads includes a source lead spaced apart from the die pad and the gate lead and electrically coupled to a same respective plating bar as the gate lead via a single fourth tie bar.

13. The method according to claim 12, wherein: The second tie bar extends between the gate lead and the source lead.

14. The method according to claim 10, wherein: The first side of the die package and the second side of the die package are not electrolytically plated.

15. The method according to claim 10, wherein The width of the first tie rod is greater than the width of the second tie rod.

16. The method according to claim 10, wherein A first set of leads in the plurality of leads is positioned adjacent to one of the second set of plated bars, and wherein an opposing second set of leads in the plurality of leads is positioned adjacent to a different one of the second set of plated bars.

17. The method according to claim 16, wherein: The sidewalls of the first set of leads are aligned with each other along facing surfaces of respective ones of the second set of plated strips, and wherein the sidewalls of the second set of leads are aligned with each other along facing surfaces of respective ones of the second set of plated strips.

18. The method according to claim 10, wherein The leads include copper and the electroplating plates the leads with tin.

19. A dual flat no-lead ("DFN") semiconductor package made according to the method of claim 10.

Images