Electronic device flip chip package with exposed clips

Abstract

A packaged electronic device (100) includes a multilayer substrate (106) including a first side (103), a first layer (110) having a first plurality of conductive structures (112, 114, 116) along the first side (103), and a second layer (120) having a second plurality of conductive structures (122, 124, 126); a semiconductor die (101) soldered to a first set of conductive structures (112, 114); a conductive clip (108) directly connected to one of the conductive structures (116, 136) of the first layer (110) and directly connected to a second side (105) of the semiconductor die (101); and a package structure (140) surrounding a portion of the conductive clip (108) and the semiconductor die (101).

Description

Background Technology

[0001] Electronic circuits are susceptible to efficiency and operational performance degradation caused by parasitic inductance, especially at higher operating frequencies. High-frequency devices also experience reduced efficiency at elevated operating temperatures. The thermal limitations of conventional device packages, which rely solely on bottom-side cooling via a printed circuit board (PCB), prevent device size reduction and inhibit increases in power density. Furthermore, grounding the back side of a semiconductor die containing one or more power circuit switching transistors enhances the electrical performance of switching circuits. Current packaging solutions using wire-bonded dies and leadframes suffer from high parasitic inductance and cannot provide top-side cooling or back-side die grounding. Capped embedded die packages feature an inverted die or flip chip with a cap on the top side for heat dissipation but do not provide a top-side ground connection. Other flip-chip approaches do not achieve a ground connection to the back side of the die. Other packages with direct copper plating on embedded dies with a redistribution layer (RDL) are expensive. Summary of the Invention

[0002] A packaged electronic device is described, comprising a conductive clip attached to a multilayer substrate and an inverted die, and a package structure surrounding a portion of the conductive clip and the semiconductor die. The described example provides a cost-effective electronic device packaging solution with good die heat dissipation and electrical performance. The described example packaged electronic device includes a multilayer substrate having a first layer with a first conductive structure and a second layer with a second conductive structure. The example device also includes a semiconductor die having electronic components. The die includes conductive features electrically connected to terminals of the electronic components and directly connected to corresponding conductive structures of the first layer. The example device also includes a conductive clip directly connected to a conductive structure of the first conductive structure of the first layer. The conductive clip is directly connected to one side of the semiconductor die. The example device also includes a package structure surrounding a portion of the conductive clip and the semiconductor die.

[0003] In some examples, the multilayer substrate includes a third layer or multiple intermediate layers with conductive vias between a first layer and a second layer, the conductive vias individually connecting some conductive structures in the first conductive structure to some conductive structures in the second conductive structure. The third layer also includes an insulating structure that separates the vias from each other. In one example, the multilayer substrate is a laminated structure, wherein the insulating structure comprises a laminated stacked material. In another example, the multilayer substrate is a ceramic or insulating metal substrate (IMS), wherein the insulating structure comprises a ceramic material. In one example, the package structure includes a molding material surrounding a portion of a conductive clip and a semiconductor die. In one example, the molding material separates at least some conductive structures in the first conductive structure from each other in the first layer and separates at least some conductive structures in the second conductive structure from each other in the second layer. In one example, the conductive clip is soldered to a conductive structure in the first conductive structure of the first layer, and the conductive clip is soldered or epoxy-bonded to the semiconductor die. In one example, the device also includes a second semiconductor die having a second conductive feature directly connected to a corresponding conductive structure in the conductive structure of the first layer.

[0004] A method for manufacturing an electronic device is described. The method includes soldering a conductive feature of a first side of a semiconductor die to a first set of conductive structures of a first layer of a multilayer substrate, and attaching a conductive clip to the multilayer substrate and the semiconductor die. In one example, attaching the conductive clip includes soldering a first portion of the conductive clip to another conductive structure of the first side of the first layer, and attaching a second portion of the conductive clip to a second side of the semiconductor die. In one example, the second portion of the conductive clip is soldered to the second side of the semiconductor die. In another example, the second portion of the conductive clip is bonded to the second side of the semiconductor die with epoxy resin. The method also includes enclosing a portion of the conductive clip and the semiconductor die within a package structure. In one example, the method further includes soldering a second semiconductor die to a second set of conductive structures before attaching the conductive clip to the multilayer substrate and the semiconductor die. Attached Figure Description

[0005] Figure 1 This is a cross-sectional side view of a flip-chip packaged electronic device having a multilayer laminated substrate including a multilayer laminated structure and an exposed clip.

[0006] Figure 2 It is along Figure 1 The top view of the packaged electronic device is taken from line 2-2.

[0007] Figure 3 It is along Figure 1 The top view of the packaged electronic device is taken from line 3-3.

[0008] Figure 4 It is along Figure 1 The bottom view of the packaged electronic device is taken from line 4-4.

[0009] Figure 5 This is a flowchart of a method for manufacturing packaged electronic devices.

[0010] Figures 6-12 It is based on Figure 5 The method is being manufactured Figures 1-4 A cross-sectional side view of a packaged electronic device.

[0011] Figure 13 This is a cross-sectional side view of another example of a flip-chip packaged electronic device with a multilayer ceramic or insulating metal substrate and exposed clips. Detailed Implementation

[0012] In the accompanying drawings, the same reference numerals always refer to the same elements, and various features are not necessarily drawn to scale. In the following discussion and claims, the terms "comprising," "including," "having," "containing," "with," or variations thereof are intended to be included in a manner similar to the term "comprising," and therefore should be interpreted as meaning "including, but not limited to...". Furthermore, the terms "coupled" or "coupled" are intended to include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intermediate devices and connectors.

[0013] Figures 1-4 An electronic device 100 with an example package having a first semiconductor die 101 and a second semiconductor die 102 is shown. Although the example device 100 includes multiple semiconductor dies 101 and 102, other examples may include a single semiconductor die or more than two semiconductor dies. In the example shown, both semiconductor dies include a lower first surface 103 having a conductive feature 104 that is flip-chip bonded to a conductive structure of a multilayer substrate 106. The example conductive feature 104 extends outward (e.g., downward) from the lower first side 103 of the semiconductor dies 101 and 102. Any suitable conductive feature 104 that can be soldered or otherwise directly attached to a copper pad or other conductive structure of the multilayer substrate 106 can be used. In one example, the conductive feature 104 of the dies 101 and 102 is a solder bump. In another example, the conductive feature 104 is a copper pillar.

[0014] In one example, dies 101 and 102 are manufactured to have one or more electronic components (e.g., transistors, resistors, capacitors, diodes, etc.), as combined below. Figure 7Further discussion. In one example, the first die 101 includes a power transistor, such as a high electron mobility transistor (HEMT), for example, a silicon carbide (SiC) transistor or a gallium nitride (GaN) transistor. Example dies 101 and 102 also include one or more metallization layers, wherein the upper side 103 has copper pillars, solder bumps, or other conductive features 104 extending outward from the upper side 103. At least some of the conductive features 104 are electrically connected via one or more metallization layers to terminals of one or more electronic components within dies 101 and 102. In this example, dies 101 and 102 are inverted or “flip-chip” to allow the conductive features 104 of the first side 103 to be soldered down onto a conductive structure of a multilayer substrate 106 using a flip-chip attachment process. Figure 1 In this configuration, the inverted positioning of dies 101 and 102 positions the second side 105 of the die upwards (e.g., along the positive Z direction). The flip-chip process directly attaches dies 101 and 102 to a first side (e.g., the upper side) 107 of the multilayer substrate 106. The direct electrical connection of the conductive feature 104 to the conductive structure of the multilayer substrate 106 advantageously mitigates or avoids parasitic inductance associated with wire bonding or other interconnect technologies.

[0015] Device 100 also includes a conductive clip 108. Clip 108 can be any suitable conductive material, such as aluminum, copper, etc. The conductive clip 108 is directly connected to one or more conductive structures on a first side 107 of the multilayer substrate 106. In one example, the lower first portion of clip 108 is directly soldered to one or more conductive structures on the first side 107 of the multilayer substrate 106. Furthermore, the conductive clip 108 is directly connected to a second side 105 of the first semiconductor die 101. In one example, the upper second portion of conductive clip 108 is directly soldered to a conductive feature on the second side 105 of the first semiconductor die 101. In another example, the second portion of conductive clip 108 is bonded to a portion of the second side 105 of the first semiconductor die 101 with epoxy resin. In one embodiment, the conductive clip 108 is soldered to a grounded conductive structure on the first side 107 of the multilayer substrate 106, such as a ground connection.

[0016] Also refer to Figures 2-4 , Figure 2 Show along Figure 1 The top view of the packaged electronic device 100 is taken from line 2-2. Figure 1 and Figure 2 The conductive clip 108 extends over and separates from a portion of the second semiconductor die 102. In this example, the clip 108 provides a grounded shield to protect the first semiconductor die 101 and / or the second semiconductor die 102 from electromagnetic interference (EMI) during operation of the device 100, whether soldered or epoxy-bonded to the second side 105 of the first semiconductor die 101. Figure 1 In the example, the conductive clip 108 includes an upper first side 109 exposed to the outside of the packaged electronic device 100. The clip 108 also facilitates heat dissipation from the attached first semiconductor die 101. In use, a heat sink (not shown) may be soldered, epoxy-bonded, or otherwise attached to the exposed first side 109 of the conductive clip 108 to further facilitate heat dissipation.

[0017] Figure 1 The example multilayer substrate 106 is a multilayer laminated substrate structure. In another embodiment (e.g., below) Figure 13 The multilayer substrate 106 is a ceramic substrate or an insulating metal substrate (IMS). For example... Figure 1 As shown, the multilayer laminated substrate 106 includes a first layer 110 at a first side (e.g., the top side) 107 and a second layer 120 at the bottom. The multilayer substrate 106 facilitates signal routing and interconnect locations that are impossible or impractical for leadframes. Figure 1 The example also includes an intermediate third layer 130. The first layer 110 includes a plurality of first conductive structures 112, 114, and 116 that extend through the first layer 110 to a first side 107 of the multilayer substrate 106. The conductive structures 112, 114, and 116 are laterally separated from each other (e.g., along...). Figure 1 (in the X direction). In addition, conductive structures 112, 114 and 116 are separated from each other by a first insulating structure 118.

[0018] exist Figure 1 In one example, the first conductive structure 112 is soldered to the first conductive feature 104 of the semiconductor die 101. In another example, the first semiconductor die 101 includes transistor components (e.g., below). Figure 7 In the example, the first conductive feature 104 of the semiconductor die 101 is electrically connected to the drain terminal of the transistor (in the transistor 701), and the second semiconductor die 102 includes a transistor driver circuit (not shown). Figure 1 (marked as "D" in the original text). The second conductive structure 114 of the first layer 110 is soldered to the second conductive feature 104 of the semiconductor die 101, and the third conductive structure 116 is soldered to the first portion of the conductive clip 108. Figure 1 In the example, the second conductive feature 104 of the semiconductor die 101 is electrically connected to the source terminal of the transistor (in Figure 1 (marked as "S" in the middle). In one example, the driver circuit die 102 connects the source terminal of the transistor die 101 to the circuit ground node or other reference voltage node, and the corresponding ground conductive feature 104 of the second die 102 is soldered to the third conductive structure 116.

[0019] In the illustrated example, the first portion of the conductive clip 108 is directly soldered to a third conductive structure 116 on a first side 107 of the multilayer substrate 106. In this way, the conductive clip 108 is directly electrically connected to the circuit ground and provides grounding shielding for dies 101 and 102. Furthermore, in one example, the first semiconductor die 101 includes an upper body contact on a second side (e.g., the upper side) 105. Figure 1 Not shown in the image below. Figure 7 (as shown in the diagram), and the body contacts are soldered to the second portion of the conductive clip 108. In this embodiment, the conductive clip 108 provides a solder-direct electrical ground connection to the body of the semiconductor die 101.

[0020] Figure 3 It is a top view of a cross section taken along line 3-3 passing through the first layer 110, and Figure 4 It shows along Figure 1 Line 4-4 shows a bottom view of a feature of the second layer (e.g., bottom layer) 120 of a packaged electronic device. The second layer 120 includes a second plurality of conductive structures 122, 124, 126, and 128. The conductive structures 122, 124, 126, and 128 extend through the second layer 120 of the multilayer substrate 106. The second plurality of conductive structures includes a fourth conductive structure 122, a fifth conductive structure 124, and a sixth conductive structure 126. The fourth conductive structure 122 is electrically connected to a first conductive structure 112 of the first layer 110 through a third layer 130 of the multilayer substrate 106. The fifth conductive structure 124 is electrically connected to a third conductive structure 116 through the third layer 130. The illustrated example second layer 120 also includes a sixth conductive structure 126. The sixth conductive structure 126 is electrically connected to the third conductive structure 116 through the third layer 130.

[0021] The third layer 130 includes conductive vias 132, 134, and 136 extending between the first layer 110 and the second layer 120. The vias 132, 134, and 136 can be any suitable conductive material, such as aluminum, copper, etc. The third layer 130 also includes an insulating structure 138 separating at least some of the conductive vias 132, 134, and / or 136 from each other. Figures 1-4 In the laminated substrate example, the insulating structure 138 of the third layer 130 comprises a laminated stacked material 138. In the illustrated example, the insulating structures 118, 128, and 138 of the multilayer substrate 106 are all composed of laminated stacked materials. In one example, the stacked material begins as a sheet that is pressed or otherwise mounted into the gaps between the conductive structures or vias of the respective layers 110, 120, and 130. This technique is known as dry film lamination. In one example, the insulating structures 118, 128, and 138, as well as the stacked material sheet comprising them, are organic materials or include organic materials.

[0022] The packaged electronic device 100 also includes a package structure 140. The package structure 140 can be any suitable package material used to surround all or part of the components of the device 100, such as molded plastic material, ceramic material, etc. The package material includes a first side (e.g., a top side) 141. Figure 1 In the example, a first side 109 of the conductive clip 108 extends vertically beyond a first side 141 of the encapsulation material 140, thereby allowing heat dissipation from the clip 108 and / or allowing an external heat sink (not shown) to be attached to the device 100. The encapsulated electronic device 100 also includes a second side (e.g., a bottom side) 142, wherein Figure 1 Exposed portions of the second plurality of conductive structures 122, 124, and 126 are shown. In use, the exposed conductive structures 122, 124, and 126 on the second side 142 of the packaged electronic device 100 are soldered to a host PCB (not shown) to provide electrical connections from the circuitry of the host PCB to the circuitry formed by the semiconductor dies 101, 102 and the multilayer substrate 106.

[0023] The conductive vias 132, 134, and 136 of the third layer 130 connect some of the conductive structures 112, 114, and 116 of the first layer 110 to some of the conductive structures 122, 124, and 126 of the second layer 120 individually. Figure 1 In this example, the first via 132 directly connects the transistor drain of the first semiconductor die 101 to the fourth conductive structure 122 of the second layer 120 via the first conductive structure 112 of the first layer 110. In this example, the fourth conductive structure 122 provides a drain connection at the bottom side 142 of the packaged electronic device 100, which can be soldered to a PCB (not shown). The second via 134 of the third layer 130 electrically connects a ground node from the third conductive structure 116 to the fifth conductive structure 124 of the second layer 120. Furthermore, the third via 136 of the third layer 130 electrically connects a ground node from the third conductive structure 116 to a sixth conductive structure 126. Conductive structures 124 and 126 provide a ground connection or source connection at the bottom side 142 of the device 100, which can be soldered to a user PCB.

[0024] Figure 1 The cross-sectional side view of device 100 in the middle is along Figures 2-4 Line 1-1 is cut off in the diagram, and not all features of the example multilayer substrate 106 are shown. Figure 3 An example top cross-sectional view of the first layer 110 is shown, which includes a first conductive structure 112 (labeled "D"), a portion of which extends to the lateral edge of the first layer 110. An example second conductive structure 114 of the first layer 110 is wider on the left than on the right, to connect the first semiconductor die 101 and the second semiconductor die 102 (…). Figure 1The first layer 110 also includes a conductive structure 300 (labeled "G") that provides a gate control signal interconnect between the driver circuit die 102 and the gate terminals of the transistors in the first semiconductor die 101. In this example, the transistor gate terminals are connected via corresponding conductive features (not shown) of the first semiconductor die 101 soldered to the top surface of the conductive structure 300. In this example, the second semiconductor die 102 includes a gate control signal output terminal having a corresponding conductive feature (not shown) soldered to a second end of the conductive structure 300. The conductive structure 300 allows the driver die 102 to provide gate control signals to operate the transistors of the first semiconductor die 101. Figure 3 A third conductive structure 116 is also shown to provide a grounding node connection for the conductive clip 108. Furthermore, the first layer 110 includes another conductive structure 302 to facilitate connection to other circuitry within the driver die 102, and to route signals to or from other circuitry within the driver die 102.

[0025] Figure 4 A bottom view of the second layer 120 of the packaged electronic device 100 is shown. The second layer 120 includes a fourth conductive structure 122 that provides a drain connection at the bottom side 142 of the packaged electronic device 100. The bottom side of the second layer 120 also includes a fifth conductive structure 124 (e.g., a ground node connection) and a sixth conductive structure 126 (e.g., another ground node connection). Figure 4 The example of the second layer 120 also includes an exposed portion of another conductive structure 400.

[0026] The example packaged electronic device 100 advantageously combines a multilayer substrate 106 with one or more flip-chip bonded dies 101 and 102 and conductive clips 108 to address various thermal and electrical drawbacks of previous package configurations. Various features of the example device 100 can be used in conjunction with GaN, SiC, or other HEMT transistor circuits to combine the advantages associated with high power density and low cost to improve high-frequency operation. In some embodiments, device 100 facilitates the packaging of the flip-chip GaN die 101 and driver circuitry 102 without the parasitic inductance previously associated with bonding wires.

[0027] The described device 100 also provides an exposed conductive clip 108 attached to the back side of die 101 to improve heat dissipation through top-side cooling, and a ground clip attached to the back side 105 of the first die 101 for good electrical performance. This represents a significant improvement over other solutions that do not achieve a ground connection to the back side of the die in flip-chip packaging. Device 100 also offers a significant cost advantage compared to embedded die packaging solutions with redistribution layer features. Furthermore, the use of a multilayer substrate 106 advantageously facilitates complex interconnect routing capabilities compared to leadframe technology. In addition, the example multilayer laminate structure 106 promotes low electrical parasitics to further improve high-frequency circuit applications. Furthermore, the example device 100, combined with the ground back-side connection, provides good heat dissipation, which is not possible using a covered CCC package. As described below... Figure 13 As discussed further, the multilayer substrate 106 can be implemented using various different structures, including multilayer laminated substrates (e.g., Figures 1-4 ), ceramic substrates or insulating metal substrates (e.g., IMS, Figure 13 ).

[0028] Now for reference Figures 5-12 , Figure 5 An example method 500 for manufacturing packaged electronic devices is shown. In one example, method 500 can be used to manufacture the aforementioned... Figures 1-4 Example packaged electronic device 100. Method 500 can be used to manufacture other packaged electronic devices, such as those described below. Figure 13 The example device described. The method 500 is described below with reference to the manufacture of the example device 100. Figures 6-12 This shows a packaged electronic device 100 being manufactured according to method 500.

[0029] Example method 500 includes wafer fabrication at 502 and forming solder bumps or copper pillars on the top of the wafer at 504. Figure 6 An example is shown in which process 604 is performed to manufacture a wafer 600 including a plurality of through-hole die regions, each through-hole die region having one or more corresponding solder bumps or copper pillar conductive features 104 extending outward from a first side 601 of the wafer 600. The example wafer 600 also includes a back side 602.

[0030] Method 500 also includes in Figure 5 The die at position 506 is separated or split. It can be separated using any suitable sawing, laser cutting, etching, or other separation process (not shown). Figure 6 The die 600 in the middle is separated into multiple semiconductor dies (e.g., Figure 1 The first die 101 in the process. Figure 7 A portion of example first die 100 is shown, which is related to Figure 6The wafer 600 is separated and undergoes process 700, which forms conductive features 104 (e.g., copper pillars or solder bumps) on the first side 103 of the separated die 101.

[0031] Figure 7 The example first die 101 includes a transistor component 701 formed on and / or in a semiconductor substrate 702 (e.g., silicon, gallium nitride, silicon carbide, silicon-on-insulator (SOI), etc.). While the example first die 101 includes a single transistor component 701, other embodiments include integrated circuits having multiple electronic components formed in the die 101. In this example, the processed die 101 includes multiple conductive features 104 individually electrically connected to corresponding terminals (source “S”, drain “D”, gate “G”, and back gate contact) of the transistor component 701. The conductive features 104 are aluminum, copper, soldering materials, or materials suitable for subsequent soldering to a multilayer substrate 106 (e.g., ...). Figure 1 Other conductive materials in the corresponding conductive structures of the first layer 110 ) conductive structures 112 and 114.

[0032] Example die 101 also includes an isolation structure 703 disposed on a selected portion of the upper surface or side surface of substrate 702. In some examples, the isolation structure 703 may be a shallow trench isolation (STI) feature or a field oxide (FOX) structure. Example die 101 also includes a multilayer metallization structure disposed above substrate 702. The metallization structure includes a first dielectric structure layer 704 formed on substrate 702, and multilayer upper metallization structures 706, 710. In one example, the first dielectric structure layer 704 is a front metallization (PMD) layer disposed on the upper surface of transistor 701 and substrate 702. In one example, the first dielectric structure layer 704 includes silicon dioxide (SiO2) deposited on transistor 701, substrate 702, and isolation structure 703.

[0033] The metallization structure includes tungsten plugs or contacts 705 extending from the various terminals of transistor 701 through PMD layer 704, and dielectric layers 706 and 710 above them, referred to herein as interlayer or interlevel dielectric (ILD) layers. Different numbers of layers may be used in different embodiments. In one example, the first ILD layer 706 and the final ILD layer 710 are formed of silicon dioxide (SiO2) or other suitable dielectric materials. In some embodiments, the layers of the multilayer overmount metallization structure are formed in two stages, including an intrametallic dielectric (IMD, not shown) sublayer and an ILD sublayer above the IMD sublayer. The individual IMD sublayers and ILD sublayers may be formed of any suitable one or more dielectric materials, such as SiO2-based dielectric materials.

[0034] The first ILD layer 706 and the upper ILD layer 710 include conductive metallized interconnect structures 708 and 712 (such as aluminum) formed on the top surface of the lower layer, and vias 709 (such as tungsten), thereby providing electrical connections from the metallized features 708, 712 of the individual layers to the upper metallized layers. A substrate 702, electronic components 701, a first dielectric structure layer 704, and upper metallized structures 706, 710 form a die 101 having an upper side or upper surface 103. The top metallized layer 710 includes example conductive features 714, such as the uppermost aluminum via. The conductive features 714 include a side or surface at the upper side 103 of the die 101 at the top of the uppermost metallized layer 710. Any number of conductive features 714 can be provided. One or more conductive features 714 are electrically coupled to a transistor 701 through the metallized structure of the die 101.

[0035] In one example, the upper ILD dielectric layer 710 is covered by one or more passivation layers 716 (e.g., protective outer coating (PO) and / or passivation layers) (e.g., silicon nitride (SiN), silicon oxynitride (SiO2)). x N y The passivation layer 716 is covered with either silicon dioxide (SiO2). In one example, one or more passivation layers 716 include one or more openings that expose a portion of the conductive feature 714 to allow the feature 714 to be electrically connected to a corresponding contact or conductive feature 104. The conductive feature 104 extends outward from the first side (e.g., the upper side) 103 of the metallized structure (e.g., along...). Figure 7 The negative "Z" direction extends upwards. In one example, the conductive feature 104 includes a conductive seed layer, such as copper, extending outwards from the upper side 103 of the metallized structure. In one example, the conductive feature 104 includes a conductive pillar. In another example, the conductive feature 104 is a solder bump. Figure 7 The example die 101 also includes a bottom conductive feature 718 formed on a second side 105 of the die 101. Figure 1 (Not shown in the image).

[0036] Method 500 Figure 5 Continue at point 508 to fabricate or provide a multilayer substrate (e.g., on top of). Figure 1 106 in the example). In one example, the multilayer substrate 106 is a laminated substrate (e.g., Figures 1-4 In another example, the multilayer substrate is fabricated at 508 as a ceramic substrate or an insulating metal substrate (e.g., below). Figure 13 ). Figure 8 An example is shown where a lamination process 800 is performed, which produces the above-mentioned bond. Figures 1-4 The multilayer laminated substrate 106 shown and described.

[0037] Method 500 Figure 5 Continue at point 510, attaching one or more dies to the multilayer substrate. Figure 9 An example is shown in which a flip-chip die attachment bonding process 900 is performed, which bonds conductive features 104 on a first side 103 of a semiconductor die 101 to a first set of conductive structures 112, 114, and 116 of a first layer 110 of an example multilayer laminate substrate 106. In this example, the first die 101 and the second die 102 are simultaneously or separately inverted and positioned on a first side 107 of the multilayer laminate substrate 106, and a heating device 100 causes solder material on the solder bumps 104 to reflow in order to form solder bonds with the conductive structures 112, 114, and 116.

[0038] exist Figure 5 At position 512, the method also includes attaching a conductive clip to a multilayer substrate and a semiconductor die. Figure 10 An example is shown in which an attachment process 1000 is performed, which bonds the lower first portion of the conductive clip 108 to the third conductive structure 116. In one example, the attachment process 1000 also bonds the upper second portion of the conductive clip 108 to the second side 105 of the first semiconductor die 101 (e.g., to...). Figure 7 (Bottom conductive feature 718). In this example, the conductive clip 108 is soldered to the second side 105 of the first semiconductor die 101, providing an electrical connection via the conductive clip 108 to the ground node at the conductive structure 116. In another example, the clip attachment process 1000 adhesively bonds a second portion of the conductive clip to the second side 105 of the first semiconductor die 101 with epoxy resin. In both examples, the clip acts as a ground shield to protect the circuitry of the first semiconductor die 101 and the second semiconductor die 102. Furthermore, attaching the clip 108 to the second side 105 of the first semiconductor die 101 provides a thermal path for heat dissipation from the die 101. As previously mentioned, the end user can attach a heat sink to the top side 109 of the conductive clip 108 to further enhance heat dissipation.

[0039] exist Figure 5 At position 514, method 500 further includes enclosing a portion of conductive clip 108 and semiconductor dies 101 and 102 within a package structure. Figure 11 An example is shown in which a molding process 1100 is performed, which surrounds the upper structure of device 100 in a plastic molding material 140. In this example, the molding process 1100 initially provides an upper surface or top surface 141 of the molded package structure 140 located above the top side 109 of the conductive clip 108.

[0040] exist Figure 5At position 516, example method 500 also includes a portion of the exposed clip 108. Figure 12 An example is shown in which a material removal process 1200 is performed to remove a portion of the top surface of the molded package structure 140 to expose the upper part of the top side 109 of the conductive clip 108.

[0041] In another possible example, a ceramic package structure (not shown) may be used to surround all or part of the semiconductor dies 101, 102 and at least a portion of the conductive clip 108.

[0042] Figure 13 Another example packaged electronic device 1300 is shown, comprising a flip-chip package having a multilayer ceramic or insulating metal substrate 1306 and exposed clips. As described above, device 1300 includes a first semiconductor die 101 and a second semiconductor die 102, and a conductive clip 108. In this example, the multilayer substrate 1306 includes a first side 107, a second side 142, a first layer 1310, a second layer 1320, and a third layer 1330. The first layer 1310 includes a plurality of first conductive structures 1312, 1314, and 1316 extending through the first layer 1310 to the first side 107, and the second layer 1320 includes a plurality of second conductive structures 1322, 1324, and 1326 extending through the second layer 1320 to the second side 142. The third layer 1330 includes conductive vias 1332, 1334, and 1336 extending through the third layer 1330 between the first layer 1310 and the second layer 1320. The third layer 1300 also includes an insulating structure 1338 that separates the vias 1332, 1334, and 1336 from each other. In this example, the insulating structure 1338 comprises a ceramic material 1338.

[0043] In one example, the conductive structures 1312, 1314, and 1316 of the first layer 1300 are created as a direct-bonded copper (DBC) substrate, and the ceramic insulator structure 1338 of the third layer 1300 is a dielectric material, wherein vias 1332, 1334, and 1336 provide electrical interconnections between the first layer 1310 and the second layer 1320. Furthermore, in this example, the package structure 140 includes a molding material surrounding the upper portion of the conductive clip 108 and the semiconductor die 101. In this example, the molding material 140 also separates at least some of the first plurality of conductive structures 1312, 1314, and / or 1316 from each other within the first layer 1310. Furthermore, Figure 13 The molding material 140 in the packaged electronic device 1300 separates at least some of the second plurality of conductive structures 1322, 1324 and 1326 in the second layer 1320 at the bottom of the packaged electronic device 1300.

[0044] The described packaging solution promotes good thermal and electrical performance through a simple and low-cost implementation that allows for complex signal routing beyond the capabilities of leadframe designs. Exposed clips facilitate heat dissipation to the surrounding environment or attached heatsinks and allow connection to ground or other reference voltages. Multilayer substrates avoid the parasitic inductance problems of wire-bonded packages without the additional cost and complexity of embedded die packages. Furthermore, multilayer substrates enable more complex routing than leadframes. Example applications include power circuits with HEMT devices (e.g., GaN or SiC transistors) and multiple dies can be accommodated within a single package.

[0045] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. A packaged electronic device, comprising: A substrate comprising: a first side, a second side, a first plurality of conductive structures exposed from the first side, and a second plurality of conductive structures exposed from the second side; A first semiconductor die includes a first conductive feature exposed from a first side of the first semiconductor die and attached to a first conductive structure in the plurality of conductive structures. The second semiconductor die includes a second conductive feature exposed from a first side of the second semiconductor die and attached to a second conductive structure in the plurality of conductive structures. A conductive clip having a first portion electrically attached to a grounded conductive structure in one of the plurality of conductive structures, and a second portion attached to a second side of the first semiconductor die, the conductive clip extending over and physically separated from the second side of the second semiconductor die; and A packaging structure that surrounds the first semiconductor die, the second semiconductor die, and the first portion of the conductive clip. The substrate includes: A first layer having a first side serving as the first side of the substrate, and having the first plurality of conductive structures; and The second layer has a first side that serves as the second side of the substrate, and has the second plurality of conductive structures.

2. The packaged electronic device according to claim 1, The first plurality of conductive structures include: The first conductive structure is attached to the first conductive feature of the first semiconductor die. The second conductive structure is attached to the second conductive feature of the second semiconductor die and to the third conductive feature of the first semiconductor die, and The grounding conductive structure is attached to the fourth conductive feature of the second semiconductor die and to the first portion of the conductive clip.

3. The packaged electronic device according to claim 1, The first semiconductor die includes electronic components, and the first conductive feature is electrically connected to the terminals of the electronic components.

4. The packaged electronic device according to claim 3, The first semiconductor die is a transistor; The first conductive feature of the first semiconductor die is electrically connected to one of the source and drain terminals of the transistor; and The third conductive feature of the first semiconductor die is electrically connected to another of the source terminal and the drain terminal of the transistor.

5. The packaged electronic device according to claim 1, wherein the second plurality of conductive structures comprises: A fourth conductive structure, which is electrically connected in the substrate to the first conductive structure, and A fifth conductive structure, which is electrically connected to the ground conductive structure in the substrate.

6. The packaged electronic device of claim 5, wherein the second plurality of conductive structures further comprises a sixth conductive structure electrically connected in the substrate to the ground conductive structure.

7. The packaged electronic device of claim 6, wherein the substrate further comprises a third layer disposed between the first layer and the second layer, the third layer comprising: Conductive vias extend between the first layer and the second layer but do not penetrate, to individually connect some conductive structures in the first plurality of conductive structures to some conductive structures in the second plurality of conductive structures, and An insulating structure that separates at least some of the conductive vias from each other.

8. The packaged electronic device of claim 7, wherein the insulating structure of the third layer comprises a laminated material.

9. The packaged electronic device according to claim 7 or claim 8, wherein the insulating structure of the third layer comprises a ceramic material.

10. The packaged electronic device according to claim 1, The encapsulation structure includes a molding material that surrounds the first semiconductor die, the second semiconductor die, and the first portion of the conductive clip.

11. The packaged electronic device of claim 1, wherein the first portion of the conductive clip is soldered to the ground conductive structure in the first plurality of conductive structures, and wherein the second portion of the conductive clip is soldered or epoxy-bonded to the second side of the first semiconductor die.

12. The packaged electronic device according to claim 1, The encapsulation structure includes a molding material that surrounds the first portion of the conductive clip and the semiconductor die. The molding material of the encapsulation structure separates at least some of the conductive structures of the first plurality of conductive structures from each other in the first layer; and The molding material of the encapsulation structure separates at least some of the conductive structures in the second layer of the plurality of conductive structures.

13. The packaged electronic device of claim 1, wherein at least a portion of the conductive clip is exposed from the package structure.

14. The packaged electronic device of claim 1, wherein the second semiconductor die is located horizontally between the first portion of the conductive clip and the first semiconductor die.

15. An electronic device, comprising: A substrate comprising: a first plurality of conductive structures exposed from a first side of the substrate, and a second plurality of conductive structures exposed from a second side of the substrate; A first semiconductor die includes: electronic components and a first conductive feature electrically connected to the electronic components and exposed from a first side of the first semiconductor die, the first conductive feature being attached to a first conductive structure in the plurality of conductive structures; A second semiconductor die includes a second conductive feature exposed from a first side of the second semiconductor die and attached to a second conductive structure in the plurality of conductive structures; and A conductive clip having a first portion electrically attached to a grounded conductive structure among the first plurality of conductive structures, and a second portion attached to a second side of the first semiconductor die, the conductive clip extending over and physically separated from the second side of the second semiconductor die. The substrate includes: The first layer has a first side that serves as the first side of the substrate, and has the first plurality of conductive structures; The second layer has a first side that serves as the second side of the substrate, and has the second plurality of conductive structures.

16. The electronic device of claim 15, wherein the substrate comprises: A third layer, disposed between the first layer and the second layer, the third layer comprising: conductive vias extending between the first layer and the second layer to individually connect some of the first plurality of conductive structures to some of the second plurality of conductive structures; and an insulating structure separating at least some of the conductive vias from each other, wherein the insulating structure comprises a laminated stacked material.

17. The electronic device of claim 16, wherein the insulating structure of the third layer comprises a ceramic material.

18. A method for manufacturing an electronic device, the method comprising: A first conductive feature on a first side of a first semiconductor die is attached to a first conductive structure in the first layer of a multilayer substrate. The second conductive feature on the first side of the second semiconductor die is attached to the second conductive structure in the first layer of the multilayer substrate; Attaching a conductive clip to the multilayer substrate and the first semiconductor die includes: Electrically attaching the first portion of the conductive clip to the grounded conductive structure in the first layer of the multilayer substrate, and The second portion of the conductive clip is attached to the second side of the first semiconductor die, wherein the conductive clip extends over and is physically separated from the second side of the second semiconductor die; as well as The first semiconductor die, the second semiconductor die, and the first portion of the conductive clip are enclosed in a package structure.

19. The method of claim 18, further comprising: The first semiconductor die, the second semiconductor die, and the first portion of the conductive clip are encapsulated in a packaging structure using molding material; as well as At least two of the first conductive structure, the second conductive structure, and the grounded conductive structure are separated using the molding material.

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