Inductor device wiring architecture, integrated circuits and communication equipment

Abstract

The embodiment of the present application discloses an inductor device wiring architecture, including an inductor device and multiple virtual metals located below the inductor device. The multiple virtual metals are arranged in a multi-layer metal layer, each metal layer in the multi-layer metal layer corresponds to a portion of the virtual metals of the multiple virtual metals, and in the direction away from the inductor device, the arrangement area of ​​the virtual metals corresponding to at least two metal layers in the multi-layer metal layer increases. The above-mentioned inductor device wiring architecture can reduce the adverse effects on the performance of the inductor device and improve the product yield. The embodiment of the present application also discloses an integrated circuit and a communication device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an inductor device wiring architecture, an integrated circuit and a communication device. Background Art

[0002] With the rapid development of wireless communication technology, radio frequency integrated circuit (RFIC) has become increasingly important. RFIC can be an integrated circuit that works in the frequency range of 300 megahertz (MHz) to 300 gigahertz (GHz). With the arrival of the latest 5th generation mobile communication, the frequency of the signal will be greatly increased, which will bring people a faster communication experience, but also bring greater challenges and opportunities to RFIC.

[0003] Integrated circuits connect multiple layers of electronic components through metal wires to form a complete logic circuit. Based on the chemical mechanical polishing (CMP) process, the molding quality of each layer of metal wire in the integrated circuit is closely related to the metal arrangement area of ​​the bottom metal layer of the metal wire. If the metal arrangement area of ​​the bottom metal layer of the metal wire is insufficient, the yield of the metal wire is poor, which is easy to cause a short circuit.

[0004] To solve this problem, a common practice is to add dummy metal to the bottom metal of the metal wire to increase the metal layout area. However, when the metal wire is used as an inductor, the dummy metal under the inductor will affect the performance of the inductor, resulting in poor performance of the inductor. Summary of the invention

[0005] The embodiments of the present application provide an inductor device wiring architecture, an integrated circuit, and a communication device. The inductor device wiring architecture can reduce adverse effects on the performance of the inductor device and improve product yield.

[0006] In a first aspect, an embodiment of the present application provides an inductor device wiring architecture. The inductor device wiring architecture can be applied to an integrated circuit. The inductor device wiring architecture includes an inductor device and a plurality of virtual metals located below the inductor device. The plurality of virtual metals are arranged in a multi-layer metal layer, each metal layer in the multi-layer metal layer corresponds to a portion of the virtual metals of the plurality of virtual metals, and in a direction away from the inductor device, the arrangement area of ​​the virtual metal corresponding to at least two metal layers in the multi-layer metal layer increases. That is, the arrangement area of ​​the virtual metal corresponding to at least two metal layers located below the inductor device increases.

[0007] In this embodiment, in the direction away from the inductor, the arrangement area of ​​the virtual metal corresponding to at least two metal layers of the multi-layer metal layer below the inductor increases. At this time, the arrangement area of ​​the virtual metal corresponding to the metal layer close to the inductor is smaller, and the arrangement area of ​​the virtual metal corresponding to the metal layer far from the inductor is larger. That is, when the multiple virtual metals located below the inductor are arranged, they are as far away from the inductor as possible, the virtual metal in the area close to the inductor is less, and the virtual metal in the area far from the inductor is more, thereby reducing the adverse effect of the virtual metal on the performance of the inductor, or even not affecting the performance of the inductor. In addition, each metal layer below the inductor has a relatively sufficient metal arrangement area, which can meet the processing requirements of chemical mechanical polishing, thereby improving the processing quality, so that the product yield of the inductor wiring architecture and the integrated circuit using the inductor wiring architecture is higher.

[0008] In an optional embodiment, the space below the inductor device includes the space of the wiring area of ​​the inductor device projected along the vertical direction of the metal layer where the inductor device is located. The wiring area of ​​the inductor device at least includes the area surrounded by the outer edge of the outermost ring of the inductor device.

[0009] In an optional embodiment, the plurality of virtual metals are arranged in a stair-like shape, that is, in the plurality of metal layers below the inductor, the virtual metal corresponding to the metal layer below extends out relative to the virtual metal corresponding to the metal layer above to form a stair-like shape.

[0010] In this embodiment, since the multiple virtual metals under the inductor device are arranged in a stepped manner, the multiple virtual metals can effectively improve the metal arrangement under the inductor device, so that the inductor device can obtain higher manufacturing accuracy during the chemical mechanical polishing process, and the product yield of the inductor device wiring architecture and the integrated circuit using the inductor device wiring architecture is higher, and the multiple virtual metals can be arranged in an area away from the inductor device instead of in an area close to the inductor device as much as possible, thereby reducing the adverse effects of the virtual metal on the performance of the inductor device, so that the performance of the inductor device is better.

[0011] The inductor device wiring architecture may further include a plurality of virtual metals arranged in the same layer as the inductor device. Some of the virtual metals arranged in the same layer as the inductor device may be arranged in a stepped manner together with a plurality of virtual metals located below the inductor device. In this case, the virtual metals arranged in the same layer as the inductor device have less influence on the performance of the inductor device, the processing quality of the inductor device is higher, and the product yield of the inductor device wiring architecture is higher.

[0012] In an optional embodiment, in the multi-layer metal layer, the arrangement area of ​​the virtual metal corresponding to at least three metal layers arranged adjacent to each other increases in the direction away from the inductor. In this case, the multiple virtual metals under the inductor present a continuous step shape, which is conducive to further improving the processing quality of the wiring architecture of the inductor, and the multiple virtual metals have less impact on the performance of the inductor.

[0013] In an optional embodiment, the arrangement area of ​​the virtual metal corresponding to the i-th metal layer below the inductor device is equal to the arrangement area of ​​the virtual metal corresponding to the i-1-th metal layer, and the i-th metal layer is located on the side of the i-1-th metal layer away from the inductor device, and i is an integer and is greater than or equal to 2.

[0014] In this embodiment, when the wiring structure of the inductor device satisfies the arrangement rule from comb to dense, the bottom of the inductor device includes two metal layers with the same arrangement area of ​​the corresponding virtual metals, so that the arrangement flexibility of the multiple virtual metals in the wiring structure of the inductor device is higher and the arrangement method is more diversified.

[0015] Among them, the inductor device wiring architecture may include a group of two metal layers with the same arrangement area of ​​corresponding virtual metals, or may include more than two groups (including this number) of two metal layers with the same arrangement area of ​​corresponding virtual metals. The inductor device wiring architecture may also include more than three (including this number) metal layers with the same arrangement area of ​​corresponding virtual metals.

[0016] In an optional embodiment, the multiple virtual metals corresponding to the i-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the i-th interval; the multiple virtual metals corresponding to the i-1-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the i-1-th interval; the i-1-th interval is smaller than the i-th interval. At this time, although the metal arrangement area of ​​the i-th metal layer does not increase, the arrangement range of the multiple virtual metals corresponding to the i-th metal layer is larger and the arrangement is more uniform, so the processing quality of the metal layer can be effectively improved, so that the product yield of the inductor device wiring architecture is higher.

[0017] In an optional embodiment, the arrangement area of ​​the virtual metal corresponding to the j-th metal layer below the inductor device is smaller than the arrangement area of ​​the virtual metal corresponding to the j-1-th metal layer, and the j-th metal layer is located on the side of the j-1-th metal layer away from the inductor device, and j is an integer and is greater than or equal to 2.

[0018] In this embodiment, when the wiring structure of the inductor device satisfies the arrangement rule from comb to dense, the bottom of the inductor device includes two metal layers with inverted arrangement areas corresponding to the virtual metals, so that the arrangement flexibility of the multiple virtual metals in the wiring structure of the inductor device is higher and the arrangement method is more diversified.

[0019] The wiring structure of the inductor device may include a group of two metal layers with inverted arrangement areas corresponding to the virtual metal, or more than two groups (including this number) of two metal layers with inverted arrangement areas corresponding to the virtual metal. The wiring structure of the inductor device may also include more than three (including this number) metal layers with inverted arrangement areas corresponding to the virtual metal.

[0020] In an optional embodiment, the multiple virtual metals corresponding to the j-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the j-th interval; the multiple virtual metals corresponding to the j-1-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the j-1-th interval; the j-1-th interval is smaller than the j-th interval. In this case, the multiple virtual metals corresponding to the j-th metal layer with a smaller metal arrangement area have a larger arrangement range and a more uniform arrangement, which can effectively improve the processing quality of the metal layer, so that the product yield of the inductor device wiring architecture is higher.

[0021] In an optional embodiment, under the inductor device, the number of virtual metals corresponding to each metal layer (the metal layer in the multiple metal layers) is multiple, and the virtual metals corresponding to each metal layer are arranged crosswise with the virtual metals corresponding to the adjacent metal layer. In this case, the arrangement of the multiple virtual metals under the inductor device is relatively regular, which is conducive to reducing the design cost and production cost of the wiring architecture of the inductor device.

[0022] In an optional embodiment, under the inductor device, the number of the virtual metals in each metal layer (the metal layer in the multiple metal layers) is multiple, and the virtual metals corresponding to each metal layer are aligned with the virtual metals corresponding to the adjacent metal layer. In this case, the arrangement of the multiple virtual metals under the inductor device is relatively regular, which is conducive to reducing the design cost and production cost of the wiring architecture of the inductor device.

[0023] In an optional embodiment, below the inductor device, the number of virtual metals corresponding to each metal layer (the metal layers in the multiple metal layers) is multiple, and the virtual metals corresponding to one or more metal layers are cross-arranged with the virtual metals corresponding to the adjacent metal layers, and the virtual metals corresponding to one or more metal layers are aligned with the virtual metals corresponding to the adjacent metal layers.

[0024] At this time, part of the virtual metals under the inductor of the inductor wiring structure are aligned and part of the virtual metals are cross-arranged, which enriches the arrangement of the multiple virtual metals and makes the arrangement of the inductor wiring structure more diversified.

[0025] In an optional embodiment, the inductor device is an inductor with two ports or a transformer with four ports. The inductor with two ports includes but is not limited to a spiral inductor, a differential inductor, etc. In the present application, the inductor device can have a variety of implementation structures, and the inductor device wiring architecture has a wider range of applications.

[0026] In an optional embodiment, the inductor device is arranged in the same metal layer; or, the inductor device includes an upper inductor and a lower inductor, and the upper inductor and the lower inductor are arranged in two adjacent metal layers. The upper inductor and the lower inductor can be connected by a conductive material, so that the inductor device can be used as a multi-layer metal series inductor. In the present application, the inductor device can have a variety of implementation structures, and the wiring architecture of the inductor device has a wider range of applications.

[0027] In a second aspect, the present application also provides an integrated circuit, comprising any of the above-mentioned inductor device wiring architectures. Since the inductor device wiring architecture has low cost and little adverse effect on the performance of the inductor device, the integrated circuit has low cost and good performance.

[0028] In a third aspect, an embodiment of the present application further provides a communication device, comprising the above-mentioned integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0030] Figure 2 yes Figure 1 A top view of the inductor device wiring architecture in the first embodiment;

[0031] Figure 3 yes Figure 2 A schematic cross-sectional view of a portion of the structure of the wiring architecture of the inductor device shown taken along line AA;

[0032] Figure 4 yes Figure 1 A top view of the inductor device wiring architecture in the second embodiment;

[0033] Figure 5 yes Figure 4 A schematic cross-sectional view of a portion of the structure of the wiring architecture of the inductor device shown taken along line BB;

[0034] Figure 6 yes Figure 1 The schematic diagram of a part of the structure of the inductor device wiring architecture in the third embodiment;

[0035] Figure 7 yes Figure 1 A schematic diagram of a portion of the structure of the inductor device wiring architecture in the fourth embodiment;

[0036] Figure 8 yes Figure 1 The schematic diagram of the structure of the inductor device wiring architecture in the fifth embodiment;

[0037] Fig. 9 yes Figure 1 The schematic diagram of a part of the structure of the inductor device wiring structure in the sixth embodiment;

[0038] Fig.10 yes Figure 1 The schematic diagram of the structure of the inductor device wiring architecture in the seventh embodiment;

[0039] Fig.11 yes Figure 1 The schematic diagram of the structure of the inductor wiring architecture in the eighth embodiment;

[0040] Fig.12 yes Figure 1 A partial structural diagram of the inductor device wiring architecture in the ninth embodiment;

[0041] Fig.13 yes Figure 1 A schematic diagram of a part of the structure of the inductor device wiring architecture in the tenth embodiment;

[0042] Fig.14 yes Figure 1 An implementation structure of the inductor device of the inductor device wiring architecture shown;

[0043] Fig.15 yes Figure 1 Another implementation structure of the inductor device of the inductor device wiring architecture shown;

[0044] Fig.16 yes Figure 1 Another implementation structure of the inductor device of the inductor device wiring architecture shown;

[0045] Fig.17 yes Figure 1 Another implementation structure of the inductor device of the inductor device wiring architecture shown;

[0046] Fig.18 yes Figure 1 Another implementation structure of the inductor device of the inductor device wiring architecture shown;

[0047] Fig.19 yes Figure 1 Another implementation structure of the inductor device of the inductor device wiring architecture shown. DETAILED DESCRIPTION

[0048] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0049] The embodiment of the present application provides a communication device. The communication device may be a wireless fidelity (Wi-Fi) device, a Bluetooth device, an infrared device, a global positioning system (GPS) device, a near-field communication (NFC) device, a mobile communication device, a router, an optoelectronic device, a base station, a microwave device, etc.

[0050] The communication device includes an integrated circuit (IC). For example, the communication device includes a high frequency integrated circuit (HFIC). The high frequency integrated circuit is an integrated circuit having an operating frequency greater than 100 megahertz (MHz). For example, the high frequency integrated circuit may be a radio frequency integrated circuit (RFIC). The RF integrated circuit may operate in the range of 300 megahertz to 300 gigahertz (GHz) to implement specific radio frequency functions.

[0051] In one embodiment, the integrated circuit includes an inductor device wiring architecture. The inductor device wiring architecture includes an inductor device. The inductor device is one of the most important devices of an integrated circuit. It is connected with resistors, capacitors, metal-oxide-semiconductor field-effect transistors (MOSFET), bipolar junction transistors (BJT), diodes and other devices through a special circuit structure to form an integrated circuit. The integrated circuit has functions such as control, calculation, and memory.

[0052] The integrated circuit may include one or more circuit modules. The circuit module may include, but is not limited to, one or more of a voltage controlled oscillator module (VCO), a low-noise amplifier module (LNA), a mixer module (mixer), a trans-impedance amplifier module (TIA), a variable gain amplifier module (VGA), or a driver module (driver). Inductors are widely used in these circuit modules.

[0053] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of an integrated circuit 100 provided in an embodiment of the present application.

[0054] In one embodiment, the integrated circuit 100 includes a substrate 110 and a plurality of metal layers 120 and a plurality of insulating layers 130 formed on the substrate 110. At least one insulating layer 130 is disposed between any two adjacent metal layers 120. The substrate 110 may be made of silicon material, glass material or ceramic material. The material of the metal layer 120 may include one or more of copper, aluminum, silver, nickel, gold, titanium, indium, tungsten or alloys thereof. The material of the insulating layer 130 may include one or more of an electrically insulating polymer, an electrically insulating ceramic or a dielectric material.

[0055] The metal layer 120 is a patterned metal layer. The patterned metal layer can be formed in a variety of ways, for example:

[0056] In one embodiment, the patterned metal layer Preparation method The method comprises: first, forming a groove on an insulating substrate according to the layout of a patterned metal layer. Then, depositing metal on the insulating substrate so that the metal material fills the groove and overflows outside the groove. Then, removing the metal material overflowing outside the groove by chemical-mechanical polishing (CMP). At this time, the metal material remaining in the groove together forms a patterned metal layer.

[0057] In another embodiment, the patterned metal layer Preparation method The process includes: first depositing a metal film, then depositing a photoresist on the metal film, then performing exposure, development (photolithography) and etching (etching) through a mask to pattern the metal film, and finally planarizing the patterned metal film to form a patterned metal layer. The planarization process usually uses chemical mechanical polishing.

[0058] Therefore, in the forming step of the patterned metal layer, chemical mechanical polishing is usually required in the last step. The completion of the chemical mechanical polishing usually depends on the metal arrangement area of ​​the metal layer to be processed and the metal arrangement area of ​​the underlying metal layer of the metal layer to be processed. If the metal arrangement area is insufficient, it is easy to cause under-polishing, resulting in a low product yield of the patterned metal layer.

[0059] In one embodiment, the integrated circuit 100 includes an inductor device wiring structure 10. The inductor device wiring structure 10 is a part of the integrated circuit 100. The inductor device wiring structure 10 includes a portion of a metal layer 120 and a portion of an insulating layer 130. The inductor device wiring structure 10 is formed synchronously with other parts of the integrated circuit 100 during the preparation process of the integrated circuit 100. The specific number of layers of the inductor device wiring structure 10 can be less than or equal to the number of layers of the integrated circuit 100.

[0060] In one embodiment, the inductor device wiring architecture 10 includes an inductor device and a plurality of dummy metals located below the inductor device. The inductor device wiring architecture 10 may be stacked with multiple metal layers. The metal layer of the inductor device wiring architecture 10 is a portion of the corresponding metal layer 120, and the metal layer of the inductor device wiring architecture 10 is also a patterned metal layer. The inductor device is arranged on the top metal layer of the inductor device wiring architecture 10. The multiple dummy metals below the inductor device are arranged in the multi-layer metal layers below the inductor device. Each metal layer in the multi-layer metal layers below the inductor device corresponds to a portion of the dummy metals in the multiple dummy metals located below the inductor device. In the direction away from the inductor device, the arrangement area of ​​the dummy metal corresponding to at least two metal layers of the multi-layer metal layers below the inductor device increases. At this time, the arrangement area of ​​the dummy metal corresponding to the metal layer close to the inductor device is smaller, and the arrangement area of ​​the dummy metal corresponding to the metal layer away from the inductor device is larger. That is, when arranging the multiple virtual metals under the inductor, they are kept away from the inductor as much as possible, with less virtual metals in the area close to the inductor and more virtual metals in the area far from the inductor, thereby reducing the adverse effects of virtual metals on the performance of the inductor or even not affecting the performance of the inductor. In addition, each metal layer under the inductor has a relatively sufficient metal arrangement area, which can meet the processing requirements of chemical mechanical polishing, thereby improving the processing quality, so that the inductor wiring architecture 10 and the integrated circuit using the inductor wiring architecture 10 have a higher product yield.

[0061] The following is an introduction through specific embodiments.

[0062] Please also read Figure 2 and Figure 3 , Figure 2 yes Figure 1 The top view of the inductor device wiring structure 10 in the first embodiment is shown. Figure 3 yes Figure 2 The schematic cross-sectional view of a portion of the structure of the inductor device wiring architecture 10 is shown along the AA line. Figure 3 The structure in Figure 3 The number of virtual metals 3 in each metal layer 2 is slightly reduced, but the overall arrangement rule remains unchanged.

[0063] The inductor device wiring structure 10 includes an inductor device 1 and a plurality of dummy metals 3 located below the inductor device 1. In the present application, "below" is only a reference to the direction of the attached drawings. Therefore, the directional terms used are for the purpose of explaining and understanding the present application, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present application. For example, in conjunction with reference to Figure 1 and Figure 3 In the integrated circuit 100, the inductor device 1 may be arranged on the top metal layer 120 of the integrated circuit 100. The lower part of the inductor device 1 refers to the space on the side of the inductor device 1 facing the substrate 110 of the integrated circuit 100. That is, the structure or component located below the inductor device 1 is located between the inductor device 1 and the substrate 110.

[0064] The area below the inductor device 1 includes the wiring area of ​​the inductor device 1 (such as Figure 2 In other words, the space below the inductor 1 includes: the space where the wiring area of ​​the inductor 1 is projected along the vertical direction of the plane where the inductor 1 is located. The wiring area of ​​the inductor 1 covers the entire inductor 1. The wiring area of ​​the inductor 1 at least includes: the area surrounded by the outer edge of the outermost ring of the inductor 1. In actual use, the aforementioned "vertical direction" is not limited to a strict direction that forms an angle of 90° with the plane where the inductor 1 is located, but can also be a direction close to 90°. The multiple virtual metals 3 below the inductor 1 are located in the space below the inductor 1.

[0065] The inductor device wiring architecture 10 includes a plurality of stacked metal layers 2. The metal layer 2 is a portion of the metal layer 120 of the corresponding integrated circuit 100. A plurality of dummy metals 3 below the inductor device 1 are arranged in the multi-layer metal layer 2 below the inductor device 1. Each metal layer 2 in the multi-layer metal layer 2 below the inductor device 1 includes a corresponding plurality of dummy metals 3 to increase the metal arrangement area of ​​the metal layer 2. The multi-layer metal layer 2 below the inductor device 1 is the bottom structure of the inductor device 1.

[0066] In this embodiment, the plurality of virtual metals 3 corresponding to the metal layer 2 below the inductor 1 are arranged at intervals from each other. In other embodiments, two or more virtual metals 3 may also be combined into a continuous virtual metal with a larger area. Figure 2 In the illustrated embodiment, a plurality of disconnected dummy metals 3 are merged into one continuous dummy metal.

[0067] The virtual metals 3 in two adjacent metal layers 2 may be connected via the conductive material in the via hole, or may have no connection with each other.

[0068] In this embodiment, the inductor 1 is located in the first metal layer 21. Since the inductor 1 is located in the first metal layer 21, it can be processed into a larger thickness, thereby reducing resistance and improving the quality factor Q. The inductor 1 has a second metal layer 22 to a fifth metal layer 25 below. The second metal layer 22 to the fifth metal layer 25 are the bottom structure of the inductor 1. The multiple virtual metals 3 below the inductor 1 are arranged in the second metal layer 22, the third metal layer 23, the fourth metal layer 24 and the fifth metal layer 25.

[0069] The inductor device wiring structure 10 further includes a plurality of virtual metals 3 arranged in the metal layer 2 where the inductor device 1 is located. For example, in this embodiment, the first metal layer 21 further includes a plurality of virtual metals 3, and the plurality of virtual metals 3 are arranged around the inductor device 1 and away from the inductor device 1. When the inductor device 1 surrounds a middle space with a larger area, the middle space may also be arranged with virtual metals 3.

[0070] Wherein, in the direction away from the inductor 1 (such as Figure 3In the Z direction, the arrangement area of ​​the virtual metal corresponding to at least two metal layers 2 located below the inductor 1 increases. The arrangement area of ​​the virtual metal corresponding to the metal layer 2 is the total arrangement area of ​​the virtual metal 3 in the metal layer 2 and located below the inductor 1. The metal layer 2 with a larger arrangement area of ​​the virtual metal 3 has a larger metal arrangement ratio. At this time, the multiple virtual metals 3 located below the inductor 1 are arranged less in the area close to the inductor 1, and are arranged more in the area far away from the inductor 1, thereby reducing the adverse effect on the performance of the inductor 1. Furthermore, since the arrangement area of ​​the virtual metal 3 corresponding to the metal layer 2 below the inductor device 1 is in an increasing area, the metal layer 2 below the inductor device 1 generally presents an increasing trend of the arrangement area corresponding to the virtual metal 3 (i.e., generally presents a trend of being sparse at the top and dense at the bottom), so each metal layer 2 of the inductor device wiring structure 10 has a relatively sufficient metal arrangement area, which can meet the processing requirements of chemical mechanical polishing, so that the first metal layer 21 has good flatness, the metal residue of the inductor device 1 is very small, and the processing quality is high, thereby reducing the risk of short circuit in the circuit, so that the product yield of the inductor device wiring structure 10 and the integrated circuit 100 using the inductor device wiring structure 10 is high. In short, the inductor device wiring structure 10 can increase the metal arrangement area of ​​each metal layer 2 while reducing the adverse effects of the virtual metal 3 on the inductor device performance of the inductor device 1, thereby improving the product yield.

[0071] The plurality of virtual metals 3 located below the inductor 1 are arranged in a stair-like manner. That is, in the multi-layer metal layers 2 located below the inductor 1, the virtual metals 3 corresponding to the metal layers 2 located below extend relative to the virtual metals 3 corresponding to the metal layers 2 located above to form a stair-like shape. Figure 3 In the figure, the virtual metal 3 corresponding to the third metal layer 23 extends out relative to the virtual metal 3 corresponding to the second metal layer 22 to form a step shape.

[0072] Figure 2 In the inductor device wiring structure 10, different patterns are filled into the virtual metals 3 located in different metal layers 2 to distinguish them. Among them, the inductor device 1 and the virtual metal 3 of the first metal layer 21 are filled with black patterns, the virtual metal 3 of the second metal layer 22 is filled with inclined lines, and the virtual metal 3 of the third metal layer 23 is not filled with patterns (i.e., white background). In this embodiment, the virtual metals 3 in the multiple metal layers 2 are aligned, and the virtual metals 3 of the bottom structure will be blocked by the virtual metals 3 of the top structure. For example, part of the virtual metal 3 in the second metal layer 22 is blocked by the virtual metal 3 in the first metal layer 21. Part of the virtual metal 3 in the second metal layer 22 extends relative to the virtual metal 3 in the first metal layer 21, and the relatively extended part of the virtual metal 3 is exposed.

[0073] In the present embodiment, since the multiple virtual metals 3 located below the inductor device 1 are arranged in a stepped manner, the multiple virtual metals 3 can effectively improve the metal arrangement below the inductor device 1, so that the inductor device 1 obtains a higher manufacturing accuracy during the chemical mechanical polishing process, and the product yield of the inductor device wiring architecture 10 and the integrated circuit 100 using the inductor device wiring architecture 10 is higher, and the multiple virtual metals 3 located below the inductor device 1 can be arranged in an area away from the inductor device 1 instead of being arranged in an area close to the inductor device 1 as much as possible, thereby reducing the adverse effects of the virtual metals 3 on the inductor device performance of the inductor device 1, so that the performance of the inductor device 1 is better.

[0074] Part of the virtual metal 3 arranged on the metal layer 2 where the inductor 1 is located and the virtual metal 3 arranged below the inductor 1 can also be arranged in a stepped manner. Figure 3 In the figure, the virtual metal 3 corresponding to the second metal layer 22 extends out relative to the virtual metal 3 corresponding to the first metal layer 21 to form a step shape.

[0075] For example:

[0076] like Figure 3 As shown, the plurality of virtual metals 3 of the first metal layer 21 are partially arranged around the inductor 1 and partially arranged in the middle space surrounded by the inductor 1. A spacing S1 is formed between the virtual metal 3 closest to the inductor 1 among the virtual metals 3 located in the middle space of the inductor 1 and the inductor 1. A spacing S2 is formed between two adjacent virtual metals 3 located in the middle space of the inductor 1. S1 is greater than S2. At this time, the virtual metal 3 of the first metal layer 21 has little effect on the performance of the inductor 1, and the inductor performance of the inductor 1 is better. Similarly, the spacing between the virtual metal 3 located on the periphery of the inductor 1 and the inductor 1 is greater than the spacing between the two adjacent virtual metals 3 located on the periphery of the inductor 1.

[0077] In this embodiment, the plurality of virtual metals 3 of the first metal layer 21 may be arranged at equal intervals or at unequal intervals, and this application does not make a strict limitation thereto. In this application, the “interval” between two adjacent virtual metals 3 refers to the interval between two virtual metals 3 located on the same side of the inductor 1.

[0078] In this embodiment, the dummy metal 3 of the first metal layer 21 is arranged roughly in an array (dummy metal 3 is not arranged in some areas of the array), and the spacing between two adjacent dummy metals 3 is roughly equal. In other embodiments, the dummy metal 3 of the first metal layer 21 can also have other arrangements, such as roughly diffuse annular arrangement, or scattered random arrangement, etc.

[0079] The plurality of virtual metals 3 corresponding to the second metal layer 22 are as far away from the inductor 1 as possible. For example, the second metal layer 22 arranges the virtual metal 3 obliquely below a certain section of the wiring of the inductor 1 to increase the metal arrangement area of ​​the second metal layer 22 as much as possible, thereby improving the product yield of the inductor wiring architecture 10, and having little effect on the performance of the inductor 1. In the second metal layer 22, the spacing S4 between two virtual metals 3 in the space directly below a certain section of the wiring close to the inductor 1 is greater than or equal to the gap S5 between two adjacent virtual metals 3.

[0080] In this embodiment, part of the virtual metal 3 corresponding to the second metal layer 22 extends relative to the virtual metal 3 of the first metal layer 21, and multiple virtual metals 3 near the inductor 1 in the first metal layer 21 and the second metal layer 22 are arranged roughly in a stepped shape.

[0081] In this embodiment, the structure and size design of the virtual metal 3 of the second metal layer 22 can refer to the virtual metal 3 of the first metal layer 21. For example, S5 is equal to S2. In other embodiments, the structure and size of the virtual metal 3 of the second metal layer 22 can be designed to be different from the virtual metal of the first metal layer 21.

[0082] Among them, S1 can be in the range of 1 micron (μm) to 15 microns. S1 can be set according to the range of the electromagnetic field generated by the inductor 1. S2 can be in the range of 0.1 micron to 10 microns. The width of a certain section of the wiring of the inductor 1 is W1. W1 can be in the range of 1 micron to 20 microns. The width of the virtual metal 3 is W2. W2 can be in the range of 0.1 micron to 10 microns. In the thickness direction (i.e., Z direction) of the inductor wiring structure 10, the thickness of the virtual metal 3 is T1. T1 can be in the range of 0.1 micron to 4 microns. Among them, the virtual metal 3 can be made of copper or aluminum. The inductor 1 can be made of copper or aluminum. The material of the inductor 1 is the same as the material of the virtual metal 3 of the first metal layer 21.

[0083] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 is larger than the arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22. Part of the virtual metal 3 corresponding to the third metal layer 23 extends out relative to the virtual metal 3 corresponding to the second metal layer 22. In this embodiment, the multiple virtual metals 3 in the first metal layer 21, the second metal layer 22 and the third metal layer 23 are arranged in a stepped manner.

[0084] Among them, one of the virtual metals 3 in the third metal layer 23 is located directly below a certain section of the wiring of the inductor device 1, and the spacing between the virtual metal 3 and the section of the wiring of the inductor device 1 is S3. Among them, S3 can be in the range of 1 micron to 15 microns. S3 can be designed according to the electromagnetic field range of the inductor device 1.

[0085] The structure and size of the virtual metal 3 of the third metal layer 23 can be designed with reference to the virtual metal 3 of the first metal layer 21. In other embodiments, the structure and size of the virtual metal 3 of the third metal layer 23 can also be designed to be different from the virtual metal of the first metal layer 21.

[0086] In this embodiment, the inductor device wiring architecture 10 further includes a multi-layer dielectric layer 4. The dielectric layer 4 is a part of the corresponding insulating layer 130. A dielectric layer 4 is disposed between two adjacent metal layers 2. When a gap is formed between the dummy metals 3 in the metal layers 2, an insulating material is filled in the gap to form an insulating portion, and the insulating portion is connected to the dielectric layer 4.

[0087] The thickness of each dielectric layer 4 of the inductor device wiring structure 10 may be the same. Figure 3 As shown, the thickness of the dielectric layer 4 is T2, which may be in the range of 0.1 micrometer to 4 micrometers.

[0088] like Figure 2 and Figure 3 As shown, in this embodiment, the multiple virtual metals 3 below the inductor device 1 are mainly arranged in a stepped manner. In other embodiments, the multiple virtual metals 3 below the inductor device 1 may also be arranged in other ways while meeting processing requirements and performance requirements.

[0089] like Figure 2 and Figure 3 As shown, in this embodiment, the multiple dummy metals 3 below the inductor device 1 have substantially the same shape and size. In other embodiments, the multiple dummy metals 3 below the inductor device 1 may also have different shapes and sizes. Similarly, the multiple dummy metals 3 disposed on the same layer as the inductor device 1 may have substantially the same shape and size as the multiple dummy metals 3 below the inductor device 1, or may be different.

[0090] like Figure 2 As shown, in this embodiment, the multiple virtual metals 3 below the inductor 1 are in a square shape. In other embodiments, the multiple virtual metals 3 below the inductor 1 may also be in a strip, triangle, circle, ellipse, polygon, special shape, etc. This application does not strictly limit the shape and size of the virtual metal 3.

[0091] In one embodiment, the wiring structure 10 of the inductor device further includes a polycrystalline silicon layer (not shown) located below the multi-layer metal layer 2. The polycrystalline silicon layer includes a plurality of polycrystalline silicons, which are used as the gate of the PN junction (a P-type semiconductor and an N-type semiconductor are made on the same semiconductor substrate, and a space charge region is formed at their interface, which is called a PN junction) of the integrated circuit 100. The arrangement of the plurality of polycrystalline silicons also needs to meet the processing requirements of chemical mechanical polishing to flatten the multi-layer metal layer 2. The arrangement rules of the plurality of polycrystalline silicons refer to the arrangement rules of the aforementioned plurality of virtual metals 3. For example, when the distance between the polycrystalline silicon layer and the inductor device 1 is relatively close, the polycrystalline silicon in the polycrystalline silicon layer is arranged in a trend away from the inductor device 1. Specifically, the arrangement area of ​​the polycrystalline silicon in the polycrystalline silicon layer and the arrangement area of ​​the virtual metal 3 corresponding to the metal layer 2 located below the inductor device 1 increase in the direction away from the inductor device 1. The plurality of polycrystalline silicons can be arranged in a stepped manner together with the plurality of virtual metals 3 located below the inductor device 1.

[0092] Further, in the present application, the plurality of virtual metals 3 under the inductor device 1 of the inductor device wiring structure 10 may be arranged in a variety of ways when satisfying: presenting an arrangement rule from comb to dense in the direction away from the inductor device 1, for example:

[0093] In one arrangement, under the inductor 1, the number of virtual metals 3 corresponding to each metal layer 2 is multiple, and the virtual metals 3 corresponding to each metal layer 2 are arranged crosswise with the virtual metals 3 corresponding to the adjacent metal layer 2. In other words, the virtual metals 3 under the inductor 1 and the virtual metals 3 above or below it are roughly staggered. At this time, the arrangement of the multiple virtual metals 3 under the inductor 1 is relatively regular, which is conducive to reducing design costs and production costs.

[0094] In another arrangement, under the inductor 1, the number of virtual metals 3 corresponding to each metal layer 2 is multiple, and the virtual metals 3 corresponding to each metal layer 2 are aligned with the virtual metals 3 corresponding to the adjacent metal layer 2. In other words, the virtual metals 3 under the inductor 1 and the virtual metals 3 above or below it are roughly in a positional relationship facing each other. At this time, the arrangement of the multiple virtual metals 3 under the inductor 1 is relatively regular, which is conducive to reducing design costs and production costs.

[0095] In another arrangement, under the inductor 1, the number of virtual metals 3 corresponding to each metal layer 2 is multiple, and the virtual metals 3 corresponding to one or more metal layers 2 are arranged crosswise with the virtual metals 3 corresponding to the adjacent metal layers 2, and the virtual metals 3 corresponding to one or more metal layers 2 are arranged in alignment with the virtual metals 3 corresponding to the adjacent metal layers 2. In this case, part of the virtual metals 3 under the inductor 1 of the inductor wiring structure 10 are arranged in alignment, and part of the virtual metals 3 are arranged crosswise, which enriches the arrangement of the virtual metals 3 and makes the arrangement of the inductor wiring structure 10 more diversified.

[0096] Specific:

[0097] exist Figure 2 and Figure 3 In the first embodiment shown, under the inductor device 1, the virtual metal 3 corresponding to each metal layer 2 is aligned with the virtual metal 3 corresponding to the adjacent metal layer 2. For example, the virtual metals 3 corresponding to the second metal layer 22 to the fifth metal layer 25 are aligned. In one embodiment, the multiple virtual metals 3 under the inductor device 1 have the same size, and the spacing between two adjacent virtual metals 3 corresponding to each metal layer 2 is equal, for example, S5=S2.

[0098] Please also read Figure 4 and Figure 5 , Figure 4 yes Figure 1 The top view of the inductor device wiring structure 10 in the second embodiment is shown. Figure 5 yes Figure 4 The schematic cross-sectional view of a portion of the structure of the inductor device wiring architecture 10 is cut along line BB. Figure 5 The structure in Figure 5 The number of virtual metals 3 in each metal layer 2 is slightly reduced, but the overall arrangement rule remains unchanged. Most of the technical contents in this embodiment that are the same as those in the previous embodiment are not repeated.

[0099] In the second embodiment, under the inductor device 1, the virtual metal 3 corresponding to each metal layer 2 is arranged crosswise with the virtual metal 3 corresponding to the adjacent metal layer 2. At this time, the layer structure under the inductor device 1 has a more uniform metal arrangement area, which is conducive to improving the processing accuracy of the inductor device 1, so that the product yield of the inductor device wiring architecture 10 is higher.

[0100] In this embodiment, the inductor device wiring structure 10 includes a first metal layer 21, a second metal layer 22, a third metal layer 23, a fourth metal layer 24 and a fifth metal layer 25. The virtual metals 3 corresponding to the second metal layer 22, the third metal layer 23, the fourth metal layer 24 and the fifth metal layer 25 under the inductor device 1 are arranged crosswise. Part of the virtual metals 3 of the first metal layer 21 where the inductor device 1 is located are arranged crosswise with the virtual metals 3 corresponding to the metal layers (22 / 23 / 24 / 25) under the inductor device 1.

[0101] See also Figure 6 , Figure 6 yes Figure 1 The schematic diagram of a part of the structure of the inductor device wiring structure 10 in the third embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiment will not be repeated.

[0102] In the third embodiment, the inductor device wiring structure 10 includes a first metal layer 21 where the inductor device 1 is located and multiple metal layers (a second metal layer 22 to a ninth metal layer 29) located below the inductor device 1. In the direction Z away from the inductor device 1, the arrangement areas of the virtual metals 3 corresponding to the second metal layer 22 to the sixth metal layer 26 increase gradually.

[0103] Below the inductor 1, the virtual metal 3 corresponding to one or more metal layers 2 is arranged crosswise with the virtual metal 3 corresponding to the adjacent metal layer 2, and the virtual metal 3 corresponding to one or more metal layers 2 is arranged in alignment with the virtual metal 3 corresponding to the adjacent metal layer 2. For example, the virtual metal 3 corresponding to the second metal layer 22, the virtual metal 3 corresponding to the third metal layer 23, and the virtual metal 3 corresponding to the fourth metal layer 24 are arranged in alignment. In the fourth metal layer 24, the fifth metal layer 25, the sixth metal layer 26, the seventh metal layer 27, the eighth metal layer 28, and the ninth metal layer 29, the virtual metal 3 corresponding to two adjacent metal layers 2 is arranged crosswise. At this time, the arrangement of the multiple virtual metals 3 located below the inductor 1 in the inductor wiring architecture 10 is more diversified.

[0104] Part of the virtual metal 3 of the first metal layer 21 is arranged crosswise with the virtual metal 3 corresponding to the second metal layer 22. In other embodiments, part of the virtual metal 3 of the first metal layer 21 is arranged aligned with the virtual metal 3 corresponding to the second metal layer 22. The present application does not strictly limit the arrangement of the virtual metal 3 of the multi-layer metal layer 2 of the inductor device wiring architecture 10.

[0105] Furthermore, in the present application, there are multiple implementations for the relationship between the arrangement areas of the virtual metal 3 corresponding to the multi-layer metal layers 2 below the inductor 1, for example:

[0106] In one embodiment, among the multiple metal layers 2 below the inductor 1, the arrangement areas of the virtual metals 3 corresponding to at least three metal layers 2 disposed adjacent to each other increase in a direction Z away from the inductor 1. At this time, the multiple virtual metals 3 below the inductor 1 are in a continuous step shape, which is conducive to further improving the processing quality of the inductor wiring structure 10, and the multiple virtual metals 3 below the inductor 1 have less impact on the performance of the inductor 1.

[0107] In another embodiment, the arrangement area of ​​the virtual metal 3 corresponding to the i-th metal layer below the inductor 1 is equal to the arrangement area of ​​the virtual metal 3 corresponding to the i-1th metal layer. The i-th metal layer is located on the side of the i-1th metal layer away from the inductor 1, that is, the i-th metal layer is located below the i-1th metal layer. i is an integer and is greater than or equal to 2.

[0108] In this embodiment, when the inductor device wiring structure 10 satisfies the arrangement rule of generally being from comb to dense, the lower part of the inductor device 1 includes two metal layers 2 with the same arrangement area corresponding to the virtual metal 3, so that the arrangement flexibility of the multiple virtual metals 3 located below the inductor device 1 in the inductor device wiring structure 10 is higher and the arrangement method is more diversified. Among them, there may be a group of two metal layers 2 with the same arrangement area corresponding to the virtual metal 3 in the inductor device wiring structure 10, or there may be more than two groups (including this number) of two metal layers 2 with the same arrangement area corresponding to the virtual metal 3. There may also be more than three (including this number) metal layers 2 with the same arrangement area corresponding to the virtual metal 3 in the inductor device wiring structure 10.

[0109] Among them, the multiple virtual metals 3 corresponding to the i-th metal layer are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the i-th spacing; the multiple virtual metals 3 corresponding to the i-1th metal layer are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the i-1th spacing; the i-1th spacing is less than or equal to the i-th spacing. When the i-1th spacing is less than the i-th spacing, although the arrangement area of ​​the virtual metal 3 corresponding to the i-th metal layer does not increase, the arrangement range of the multiple virtual metals 3 of the i-th metal layer is larger and the arrangement is more uniform, so it can effectively improve the processing quality of the metal layer 2, so that the product yield of the inductor device wiring architecture 10 is higher. Of course, in other embodiments, the arrangement method and arrangement spacing of the multiple virtual metals 3 corresponding to the i-th metal layer and the i-1th metal layer may also be different from the above scheme, and set according to needs.

[0110] In another embodiment, the arrangement area of ​​the virtual metal 3 corresponding to the j-th metal layer below the inductor 1 is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the j-1-th metal layer. The j-th metal layer is located on the side of the j-1-th metal layer away from the inductor 1, that is, the j-th metal layer is located below the j-1-th metal layer. j is an integer and is greater than or equal to 2.

[0111] In this embodiment, when the inductor device wiring structure 10 satisfies the arrangement rule of generally being from comb to dense, the lower part of the inductor device 1 includes two metal layers 2 with inverted arrangement areas corresponding to the virtual metal 3, so that the arrangement flexibility of the multiple virtual metals 3 located below the inductor device 1 in the inductor device wiring structure 10 is higher and the arrangement method is more diversified. Among them, there may be a group of two metal layers 2 with inverted arrangement areas corresponding to the virtual metal 3 in the inductor device wiring structure 10, or there may be more than two groups (including this number) of two metal layers 2 with inverted arrangement areas corresponding to the virtual metal 3. There may also be more than three (including this number) metal layers 2 with inverted arrangement areas corresponding to the virtual metal 3 in the inductor device wiring structure 10.

[0112] Among them, the multiple virtual metals 3 corresponding to the j-th metal layer are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the j-th spacing; the multiple virtual metals 3 corresponding to the j-1-th metal layer are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the j-1-th spacing; the j-1-th spacing is less than or equal to the j-th spacing. When the j-1-th spacing is less than the j-th spacing, the multiple virtual metals 3 corresponding to the j-th metal layer with a smaller arrangement area of ​​the corresponding virtual metal 3 have a larger arrangement range and a more uniform arrangement, which can effectively improve the processing quality of the metal layer 2, so that the product yield of the inductor device wiring architecture 10 is higher. Of course, in other embodiments, the arrangement method and arrangement spacing of the multiple virtual metals 3 corresponding to the j-th metal layer and the j-1-th metal layer may also be different from the above scheme, and are set according to needs.

[0113] In other words, when the arrangement areas of the virtual metal 3 corresponding to at least two metal layers 2 in the multi-layer metal layers 2 below the inductor device 1 increase in the direction away from the inductor device 1, the arrangement areas of the virtual metal 3 corresponding to one or more metal layers 2 may be the same as or decrease in the arrangement areas of the virtual metal 3 corresponding to the adjacent metal layers 2 (in the direction Z away from the inductor device 1). In this case, the inductor device wiring architecture 10 can also obtain a higher product yield.

[0114] The above three implementations can be used independently or in combination.

[0115] For example:

[0116] See also Figure 3In the first embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement areas of the virtual metals 3 corresponding to the second metal layer 22 and the third metal layer 23 below the inductor 1 increase in a direction away from the inductor 1.

[0117] The arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer under the inductor 1). The arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer under the inductor 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor 1). That is, the arrangement area of ​​the virtual metal 3 corresponding to the i-th metal layer under the inductor 1 is equal to the arrangement area of ​​the virtual metal 3 corresponding to the i-1th metal layer, and the i-th metal layer is located on the side of the i-1th metal layer away from the inductor 1, and i is an integer greater than or equal to 2.

[0118] The plurality of virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor device 1) are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the third spacing. The plurality of virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor device 1) are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the second spacing. The second spacing is equal to the third spacing. The plurality of virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor device 1) are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals 3 is the fourth spacing. The fourth spacing is equal to the third spacing.

[0119] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1), the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor 1), and the arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor 1) are equal. That is, there are more than three (including this number) metal layers 2 with the same arrangement area of ​​the corresponding virtual metal 3 below the inductor 1.

[0120] See also Figure 5In the second embodiment, the inductor 1 is arranged on the first metal layer 21. The second metal layer 22, the third metal layer 23 and the fourth metal layer 24 below the inductor 1 are arranged adjacent to each other, and the arrangement areas of the virtual metals 3 corresponding to the second metal layer 22, the third metal layer 23 and the fourth metal layer 24 increase in the direction Z away from the inductor 1. That is, among the multiple metal layers 2 below the inductor 1, the arrangement areas of the virtual metals 3 corresponding to at least three metal layers 2 arranged adjacent to each other increase in the direction Z away from the inductor 1.

[0121] The arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer under the inductor device 1) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor device 1). The multiple virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the fourth interval. The multiple virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the third interval. The third interval is equal to the fourth interval.

[0122] See also Figure 6 In the third embodiment, the inductor 1 is arranged on the first metal layer 21. The second metal layer 22, the third metal layer 23, the fourth metal layer 24, the fifth metal layer 25 and the sixth metal layer 26 below the inductor 1 are arranged adjacently, and the arrangement areas of the virtual metals 3 corresponding to the second metal layer 22 to the sixth metal layer 26 increase in the direction away from the inductor 1.

[0123] The sixth metal layer 26 (i.e., the fifth metal layer below the inductor device 1), the seventh metal layer 27 (i.e., the sixth metal layer below the inductor device 1), the eighth metal layer 28 (i.e., the seventh metal layer below the inductor device 1), and the ninth metal layer 29 (i.e., the eighth metal layer below the inductor device 1) have the same arrangement area of ​​the virtual metal 3. At this time, there are more than three (including this number) metal layers 2 with the same arrangement area of ​​the corresponding virtual metal 3 below the inductor device 1.

[0124] In the sixth metal layer 26 (i.e., the fifth metal layer below the inductor device 1), the seventh metal layer 27 (i.e., the sixth metal layer below the inductor device 1), the eighth metal layer 28 (i.e., the seventh metal layer below the inductor device 1), and the ninth metal layer 29 (i.e., the eighth metal layer below the inductor device 1), the number of virtual metals 3 corresponding to each metal layer 2 is multiple, and the arrangement spacing between two adjacent virtual metals 3 in different metal layers 2 is equal. In other embodiments, the arrangement spacing between two adjacent virtual metals 3 in different metal layers 2 may also be unequal.

[0125] See also Figure 7 , Figure 7 yes Figure 1 The schematic diagram of the structure of the inductor device wiring structure 10 in the fourth embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiment will not be repeated.

[0126] In the fourth embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement areas of the dummy metals 3 corresponding to the third metal layer 23 and the fourth metal layer 24 below the inductor 1 increase gradually in the direction Z away from the inductor 1.

[0127] The second metal layer 22 and the fourth metal layer 24 are arranged at intervals, and the arrangement areas of the virtual metals 3 corresponding to the second metal layer 22 and the fourth metal layer 24 increase gradually in the direction Z away from the inductor device 1 .

[0128] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer under the inductor 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22 (i.e., the first metal layer under the inductor 1). The arrangement area of ​​the virtual metal 3 of the fifth metal layer 25 (i.e., corresponding to the fourth metal layer under the inductor 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor 1). At this time, the inductor 1 may include two or more groups of two metal layers 2 with equal arrangement areas of the corresponding virtual metal 3.

[0129] The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is the second spacing S7. The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1) is the first spacing S6. The first spacing S6 is equal to the second spacing S7.

[0130] The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor 1) is the fourth spacing. The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor 1) is the third spacing. The third spacing is equal to the fourth spacing. The third spacing may be equal to or different from the second spacing.

[0131] See also Figure 8 , Figure 8 yes Figure 1 The schematic diagram of the structure of the inductor device wiring structure 10 in the fifth embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiments are not repeated here.

[0132] In the fifth embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement areas of the dummy metals 3 corresponding to the third metal layer 23 and the fourth metal layer 24 below the inductor 1 increase gradually in the direction Z away from the inductor 1.

[0133] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1). The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is the second spacing S7. The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1) is the first spacing S6. The first spacing S6 is smaller than the second spacing S7.

[0134] The arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer under the inductor device 1) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor device 1). The multiple virtual metals 3 in the multiple virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the fourth interval. The multiple virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the third interval. The third interval is equal to the fourth interval.

[0135] See also Fig. 9 , Fig. 9 yes Figure 1 The schematic diagram of a part of the structure of the inductor device wiring structure 10 in the sixth embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiments are not repeated here.

[0136] In the sixth embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement areas of the virtual metal 3 corresponding to the second metal layer 22 and the third metal layer 23 below the inductor 1 increase gradually in the direction away from the inductor 1. The arrangement areas of the virtual metal 3 corresponding to the fourth metal layer 24, the fifth metal layer 25 and the sixth metal layer 26 increase gradually in the direction away from the inductor 1.

[0137] The arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor device 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor device 1). The arrangement areas of the virtual metal 3 corresponding to the sixth metal layer 26 (i.e., the fifth metal layer below the inductor device 1), the seventh metal layer 27 (i.e., the sixth metal layer below the inductor device 1), the eighth metal layer 28 (i.e., the seventh metal layer below the inductor device 1) and the ninth metal layer 29 (i.e., the eighth metal layer below the inductor device 1) are equal.

[0138] See also Fig.10 , Fig.10 yes Figure 1 The structure diagram of the inductor device wiring structure 10 in the seventh embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiments are not repeated here.

[0139] In the seventh embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement area of ​​the dummy metal 3 corresponding to the third metal layer 23 and the fourth metal layer 24 below the inductor 1 increases gradually in the direction away from the inductor 1.

[0140] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1). The arrangement spacing between two adjacent virtual metals 3 among the multiple virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is the second spacing S7. The arrangement spacing between two adjacent virtual metals 3 among the multiple virtual metals 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1) is the first spacing S6. The first spacing S6 is equal to the second spacing S7.

[0141] The arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor device 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor device 1). The arrangement spacing between two adjacent virtual metals 3 among the multiple virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor device 1) is equal to the arrangement spacing between two adjacent virtual metals 3 among the multiple virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor device 1).

[0142] See also Fig.11 , Fig.11 yes Figure 1 The schematic diagram of the structure of the inductor device wiring structure 10 in the eighth embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiments are not repeated here.

[0143] In the eighth embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement area of ​​the dummy metal 3 corresponding to the third metal layer 23 and the fourth metal layer 24 below the inductor 1 increases gradually in the direction away from the inductor 1.

[0144] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (ie, the second metal layer below the inductor 1 ) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22 (ie, the first metal layer below the inductor 1 ).

[0145] The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is the second spacing S7. The arrangement spacing between two adjacent virtual metals 3 in the plurality of virtual metals 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1) is the first spacing S6. The first spacing S6 is smaller than the second spacing S7.

[0146] The arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (ie, the fourth metal layer below the inductor 1 ) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (ie, the third metal layer below the inductor 1 ).

[0147] The arrangement spacing between two adjacent virtual metals 3 among the multiple virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor device 1) is equal to the arrangement spacing between two adjacent virtual metals 3 among the multiple virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor device 1).

[0148] See also Fig.12 , Fig.12 yes Figure 1The schematic diagram of a part of the structure of the inductor device wiring structure 10 in the ninth embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiments are not repeated here.

[0149] In the ninth embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement areas of the third metal layer 23 and the fourth metal layer 24 below the inductor 1 corresponding to the virtual metal 3 increase in a direction away from the inductor 1. The arrangement areas of the fifth metal layer 25 and the sixth metal layer 26 corresponding to the virtual metal 3 increase in a direction away from the inductor 1.

[0150] The arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1). The arrangement area of ​​the virtual metal 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor 1) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor 1).

[0151] The multiple virtual metals 3 in the multiple virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the second interval. The multiple virtual metals 3 corresponding to the third metal layer 23 (i.e., the second metal layer below the inductor 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the first interval. The first interval is equal to the second interval.

[0152] The plurality of virtual metals 3 corresponding to the fifth metal layer 25 (i.e., the fourth metal layer below the inductor 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the fourth interval. The plurality of virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the third interval. The third interval is equal to the fourth interval.

[0153] The arrangement areas of the virtual metals 3 corresponding to the sixth metal layer 26 (i.e., the fifth metal layer below the inductor device 1), the seventh metal layer 27 (i.e., the sixth metal layer below the inductor device 1), the eighth metal layer 28 (i.e., the seventh metal layer below the inductor device 1) and the ninth metal layer 29 (i.e., the eighth metal layer below the inductor device 1) are equal.

[0154] See also Fig.13 , Fig.13 yes Figure 1 The schematic diagram of a part of the structure of the inductor device wiring structure 10 in the tenth embodiment is shown. Most of the technical contents in this embodiment that are the same as those in the previous embodiments are not repeated here.

[0155] In the tenth embodiment, the inductor 1 is arranged on the first metal layer 21. The arrangement areas of the virtual metals 3 corresponding to the second metal layer 22 and the third metal layer 23 below the inductor 1 increase gradually in the direction away from the inductor 1. The fourth metal layer 24, the fifth metal layer 25 and the sixth metal layer 26 are arranged adjacent to each other, and the arrangement areas of the virtual metals 3 corresponding to them increase gradually in the direction away from the inductor 1.

[0156] The arrangement area of ​​the virtual metal 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1) is equal to the arrangement area of ​​the virtual metal 3 corresponding to the first metal layer 21 (i.e., the metal layer where the inductor 1 is located). The arrangement spacing between two adjacent virtual metals among the multiple virtual metals 3 corresponding to the second metal layer 22 (i.e., the first metal layer below the inductor 1) is greater than the arrangement spacing between two adjacent virtual metals among the multiple virtual metals 3 corresponding to the first metal layer 21 (i.e., the metal layer where the inductor 1 is located).

[0157] The arrangement area of ​​the virtual metal 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor 1) is smaller than the arrangement area of ​​the virtual metal 3 corresponding to the third metal layer 24 (i.e., the second metal layer below the inductor 1). The multiple virtual metals 3 corresponding to the fourth metal layer 24 (i.e., the third metal layer below the inductor 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the third interval. The multiple virtual metals 3 corresponding to the third metal layer 24 (i.e., the second metal layer below the inductor 1) are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the second interval. The second interval is smaller than the third interval.

[0158] The arrangement areas of the virtual metals 3 corresponding to the sixth metal layer 26 (i.e., the fifth metal layer under the inductor 1), the seventh metal layer 27 (i.e., the sixth metal layer under the inductor 1), the eighth metal layer 28 (i.e., the seventh metal layer under the inductor 1), and the ninth metal layer 29 (i.e., the eighth metal layer under the inductor 1) are equal. In the present application, the arrangement relationship of the multiple virtual metals 3 under the inductor 1 is schematically described in the first to tenth embodiments, and does not form a strict limitation on the arrangement relationship of the multiple virtual metals 3 under the inductor 1 (e.g., the arrangement spacing relationship in a single metal layer 2, and the arrangement spacing between multiple metal layers 2). For example, in the first to tenth embodiments, the multiple virtual metals 3 in the metal layer 2 under the inductor 1 can also be randomly arranged, or in other arrangement patterns.

[0159] Furthermore, in the present application, the inductor device 1 may have a variety of implementation structures. For example, the inductor device 1 may be an inductor with two ports or a transformer with four ports. The inductor device 1 may be arranged in the same metal layer; or, the inductor device 1 may include an upper inductor and a lower inductor, and the upper inductor and the lower inductor are arranged in two adjacent metal layers.

[0160] In an implementation structure, such as Figure 2 As shown, the inductor device 1 in the inductor device wiring architecture 10 is an inductor with two ports.

[0161] See also Fig.14 , Fig.14 yes Figure 1 An implementation structure of the inductor device 1 of the inductor device wiring architecture 10 is shown. Fig.14 A top view of a metal layer where the inductor 1 of the inductor wiring structure 10 is located is shown.

[0162] In another implementation structure, the inductor device 1 in the inductor device wiring architecture 10 is a spiral inductor with two ports. The spiral inductor is arranged in the same metal layer. The two ports 11 of the spiral inductor form a 180° angle. The main structure of the spiral inductor is arranged in the same metal layer. The metal layer where the inductor device 1 is located also includes a plurality of virtual metals 3. Some of the virtual metals 3 are arranged around the periphery of the spiral inductor. Some of the virtual metals 3 are arranged in the middle space surrounded by the spiral inductor. Fig.14 In FIG. 1 , the wiring area of ​​the inductor device 1 is indicated by a dotted frame around the inductor device 1 .

[0163] See also Fig.15 , Fig.15 yes Figure 1 Another implementation structure of the inductor device 1 of the inductor device wiring architecture 10 is shown. Fig.15 A top view of a metal layer where the inductor 1 of the inductor wiring structure 10 is located is shown.

[0164] In another implementation structure, the inductor device 1 in the inductor device wiring architecture 10 is a spiral inductor with two ports. The two ports 11 of the spiral inductor form a 90° angle. The main structure of the spiral inductor is arranged in the same metal layer. The metal layer where the inductor device 1 is located also includes a plurality of virtual metals 3. Part of the virtual metals 3 are arranged around the outer periphery of the spiral inductor. Part of the virtual metals 3 are arranged in the middle space surrounded by the spiral inductor. Fig.15 In FIG. 1 , the wiring area of ​​the inductor device 1 is indicated by a dotted frame around the inductor device 1 .

[0165] See also Fig.16 , Fig.16 yes Figure 1Another implementation structure of the inductor device 1 of the inductor device wiring architecture 10 is shown. Fig.16 A top view of a metal layer where the inductor 1 of the inductor wiring structure 10 is located is shown.

[0166] In another implementation structure, the inductor device 1 in the inductor device wiring architecture 10 is a differential inductor with two ports. The main structure of the differential inductor is arranged in the same metal layer. The metal layer where the inductor device 1 is located also includes a plurality of virtual metals 3. Part of the virtual metals 3 are arranged around the periphery of the differential inductor. Part of the virtual metals 3 are arranged in the middle space surrounded by the differential inductor. Fig.16 In FIG. 1 , the wiring area of ​​the inductor device 1 is indicated by a dotted frame around the inductor device 1 .

[0167] See also Fig.17 , Fig.17 yes Figure 1 Another implementation structure of the inductor device 1 of the inductor device wiring architecture 10 is shown. Fig.17 A top view of a metal layer where the inductor 1 of the inductor wiring structure 10 is located is shown.

[0168] In another implementation structure, the inductor device 1 in the inductor device wiring architecture 10 is a square inductor with two ports. The main structure of the square inductor is arranged in the same metal layer. The metal layer where the inductor device 1 is located also includes a plurality of virtual metals 3. Some of the virtual metals 3 are arranged around the periphery of the square inductor. Some of the virtual metals 3 are arranged in the middle space surrounded by the square inductor. Fig.17 In FIG. 1 , the wiring area of ​​the inductor device 1 is indicated by a dotted frame around the inductor device 1 .

[0169] In this implementation structure, the square inductor is a differential inductor. In other implementation structures, the square inductor may also be other inductors. In other implementation structures, the inductor may also be inductors of other shapes, such as circular, polygonal, etc., which is not strictly limited in this application.

[0170] See also Fig.18 , Fig.18 yes Figure 1 Another implementation structure of the inductor device 1 of the inductor device wiring architecture 10 is shown. Fig.18 A top view of a metal layer where the inductor 1 of the inductor wiring structure 10 is located is shown.

[0171] In another implementation structure, the inductor 1 in the inductor wiring architecture 10 is a transformer with four ports. The transformer includes two coils wound around each other. Each coil has two ports 11. The main structure of the transformer is arranged in the same metal layer. The metal layer where the inductor 1 is located also includes multiple virtual metals 3. Some of the virtual metals 3 are arranged around the outer periphery of the transformer. Some of the virtual metals 3 are arranged in the middle space surrounded by the transformer. Fig.18 In FIG. 1 , the wiring area of ​​the inductor device 1 is indicated by a dotted frame around the inductor device 1 .

[0172] See also Fig.19 , Fig.19 yes Figure 1 Another implementation structure of the inductor device 1 of the inductor device wiring architecture 10 is shown. Fig.19 A schematic diagram of the three-dimensional structure of the inductor device 1 is shown.

[0173] In another implementation structure, the inductor device 1 may include an upper inductor 12 and a lower inductor 13. The upper inductor 12 and the lower inductor 13 are arranged in two adjacent metal layers. The upper inductor 12 and the lower inductor 13 may be connected through a conductive material 14 in a via, so that the inductor device 1 is used as a multi-layer metal serial inductor.

[0174] In the present implementation structure, the wiring area of ​​the inductor device 1 includes an area surrounded by the outer edge of the outermost loop of the upper inductor 12 and an area surrounded by the outer edge of the outermost loop of the lower inductor 13 .

[0175] It can be understood that the various implementation structures of the aforementioned inductor device 1 are all applied to the inductor device wiring architecture 10 shown in the aforementioned first embodiment to the tenth embodiment.

[0176] In the present application, the inductor 1 in the inductor wiring architecture 10 can also be replaced with other transmission wires to form a transmission wire wiring architecture. The transmission wire can be used to transmit signals with a frequency greater than 100 MHz. For example, the transmission wire can be a key signal line for transmitting radio frequency signals.

[0177] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An inductor device wiring architecture, It is characterized in that include: An inductor device and a plurality of virtual metals located below the inductor device; Among them, the multiple virtual metals are arranged in a multi-layer metal layer, and the multiple virtual metals are arranged in a stepped manner. In the multi-layer metal layer, the arrangement area of ​​the virtual metals corresponding to at least three metal layers arranged adjacent to each other increases in the direction away from the inductor device.

2. The inductor device wiring architecture according to claim 1, It is characterized in that The arrangement area of ​​the virtual metal corresponding to the i-th metal layer below the inductor is equal to the arrangement area of ​​the virtual metal corresponding to the i-1-th metal layer, and the i-th metal layer is located on the side of the i-1-th metal layer away from the inductor, and i is an integer and is greater than or equal to 2.

3. The inductor device wiring architecture according to claim 2, It is characterized in that The plurality of virtual metals corresponding to the i-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the i-th interval; The multiple virtual metals corresponding to the i-1th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the i-1th interval; the i-1th interval is smaller than the i-th interval.

4. The inductor device wiring architecture according to any one of claims 1 to 3, It is characterized in that The arrangement area of ​​the virtual metal corresponding to the jth metal layer below the inductor device is smaller than the arrangement area of ​​the virtual metal corresponding to the j-1th metal layer, and the jth metal layer is located on the side of the j-1th metal layer away from the inductor device, where j is an integer and is greater than or equal to 2.

5. The inductor device wiring architecture according to claim 4, It is characterized in that The multiple virtual metals corresponding to the j-th metal layer are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals is the j-th spacing; the multiple virtual metals corresponding to the j-1-th metal layer are arranged at equal intervals, and the arrangement spacing between two adjacent virtual metals is the j-1-th spacing; the j-1-th spacing is smaller than the j-th spacing.

6. The inductor device wiring architecture according to claim 1, It is characterized in that Below the inductor device, the number of virtual metals corresponding to each metal layer is multiple, and the virtual metals corresponding to each metal layer are arranged crosswise with the virtual metals corresponding to the adjacent metal layer.

7. The inductor device wiring architecture according to claim 1, It is characterized in that Below the inductor device, each metal layer has a plurality of virtual metals, and the virtual metals corresponding to each metal layer are aligned with the virtual metals corresponding to the adjacent metal layer.

8. The inductor device wiring architecture according to claim 1, It is characterized in that Below the inductor device, the number of virtual metals corresponding to each metal layer is multiple, and the virtual metals corresponding to one or more metal layers are cross-arranged with the virtual metals corresponding to the adjacent metal layers, and the virtual metals corresponding to one or more metal layers are aligned with the virtual metals corresponding to the adjacent metal layers.

9. The inductor device wiring architecture according to claim 1, It is characterized in that The inductor device is an inductor with two ports or a transformer with four ports.

10. The inductor device wiring structure according to claim 1, It is characterized in that The inductor device is arranged in the same metal layer; or, the inductor device includes an upper inductor and a lower inductor, and the upper inductor and the lower inductor are arranged in two adjacent metal layers.

11. An integrated circuit, It is characterized in that The invention comprises the inductor device wiring structure according to any one of claims 1 to 10.

12. A communication device, It is characterized in that Comprising the integrated circuit of claim 11.

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