Display device

Abstract

A display device can include scan lines extending in a first direction, storage lines parallel to the scan lines, first data lines disposed on the scan lines and the storage lines, the first data lines extending in a second direction intersecting the first direction, second data lines parallel to the first data lines, a transistor including a control electrode protruding from the scan line, a source electrode protruding from the first data line, and a drain electrode spaced apart from the source electrode and including a drain electrode extension portion, and a pixel electrode disposed between the first data line and the second data line and connected to the drain electrode extension portion. The storage line or the scan line can include a first extension portion between the second data line and the drain electrode extension portion in a plan view.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a display device. More particularly, embodiments relate to a liquid crystal display device. BACKGROUND

[0002] With the development of multimedia, the importance of display devices is increasing. Accordingly, various types of display devices, such as liquid crystal display (LCD) devices or organic light emitting display (OLED) devices, etc., are used.

[0003] Among display devices, a liquid crystal display device is one of the most widely used flat panel display devices. A liquid crystal display device can include two display substrates on which electric field generating electrodes are respectively formed, and a liquid crystal layer interposed between the two display substrates. The liquid crystal display device can display an image by applying a voltage to the electric field generating electrodes to generate an electric field in the liquid crystal layer, determining the orientation of liquid crystal molecules of the liquid crystal layer, and controlling the polarization of incident light. SUMMARY

[0004] Embodiments provide a display device that reduces a capacitance deviation between a data line and a pixel.

[0005] A display device according to an embodiment can include a scan line, a storage line, a first data line, a second data line, a transistor, and a pixel electrode. The scan line extends in a first direction. The storage line is parallel to the scan line. The first data line is disposed on the scan line and the storage line, the first data line extending in a second direction that intersects the first direction. The second data line is parallel to the first data line. The transistor includes a control electrode protruding from the scan line, a source electrode protruding from the first data line, and a drain electrode spaced apart from the source electrode and including a drain electrode extension. The pixel electrode is disposed between the first data line and the second data line and connected to the drain electrode extension. A first extension is between the second data line and the drain electrode extension in a plan view.

[0006] In an embodiment, a gap between the drain electrode extension and the second data line can be smaller than a gap between the drain electrode extension and the first data line.

[0007] In an embodiment, the first extension can extend in the second direction.

[0008] In an embodiment, the storage line can include the first extension.

[0009] In an embodiment, the scan line can include the first extension.

[0010] In an embodiment, the display device can further include a shield electrode disposed on the same layer as the pixel electrode, the shield electrode overlapping the first data line and the second data line.

[0011] In an embodiment, the shield electrode can include a second extension portion between the second data line and the drain electrode extension portion in the plan view.

[0012] In an embodiment, the second extension portion can extend in the first direction.

[0013] In an embodiment, the second extension portion can at least partially overlap the first extension portion.

[0014] In an embodiment, the storage line can be disposed on the same layer as the scan line.

[0015] In an embodiment, the storage line can include a storage electrode overlapping the drain electrode extension portion.

[0016] In an embodiment, an area of the storage electrode can be less than an area of the drain electrode extension portion.

[0017] A display device according to an embodiment can include a first pixel, a second pixel, a scan line, a storage line, a first data line, and a second data line. The first pixel includes a transistor and a pixel electrode connected to the transistor. The second pixel is adjacent to the first pixel in a first direction. The scan line extends in the first direction, the scan line being configured to provide a scan signal to the first pixel and the second pixel. The storage line is parallel to the scan line, the storage line being configured to provide a storage voltage to the first pixel and the second pixel. The first data line is disposed on the scan line and the storage line, the first data line extending in a second direction intersecting the first direction and being configured to provide a first data signal to the first pixel. The second data line is parallel to the first data line, the second data line being configured to provide a second data signal to the second pixel. A first extension portion is between the second data line and a pixel electrode connection portion connecting the transistor and the pixel electrode in a plan view.

[0018] In an embodiment, a gap between the pixel electrode connection portion and the second data line can be less than a gap between the pixel electrode connection portion and the first data line.

[0019] In an embodiment, the first extension portion can extend in the second direction.

[0020] In an embodiment, the storage line can include the first extension portion.

[0021] In an embodiment, the scan line can include the first extension portion.

[0022] In an embodiment, the display device can further include a shield electrode disposed on the same layer as the pixel electrode, the shield electrode overlapping the first data line and the second data line.

[0023] In an embodiment, the shield electrode can include a second extension portion between the second data line and the pixel electrode connection portion in the plan view.

[0024] In an embodiment, the second extension portion can extend in the first direction.

[0025] In the display device according to an embodiment, a first extension portion protruding between the second data line and the drain electrode extension portion of the pixel can be formed in the storage line or the scan line, so that the first extension portion can shield between the second data line and the drain electrode extension portion of the pixel. Accordingly, a capacitance deviation between the first data line and the second data line and the pixel can be reduced, and an image quality of the display device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 FIG. 1 is a block diagram illustrating a display device according to an embodiment.

[0028] Figure 2 FIG. 2 is an equivalent circuit diagram illustrating a first pixel and a second pixel in the display device of FIG. 1. Figure 1

[0029] Figure 3 FIG. 3 is a layout diagram illustrating the first pixel in the display device of FIG. 1. Figure 1

[0030] Figure 4 FIG. 4 is a view illustrating a gate pattern included in the first pixel in the display device of FIG. 1. Figure 3

[0031] Figure 5 FIG. 5 is a view illustrating a data pattern included in the first pixel in the display device of FIG. 1. Figure 3

[0032] Figure 6 FIG. 6 is a view illustrating a transparent conductive pattern included in the first pixel in the display device of FIG. 1. Figure 3

[0033] Figure 7 FIG. 7 is a view illustrating a first extension portion of a scan line included in the display device of FIG. 1.​​​​​Figure 3 is a cross-sectional view taken along the line I-I' in FIG. 1.

[0034] Figure 8 is a layout view illustrating a first pixel of a display device according to an embodiment.

[0035] Figure 9 is a view illustrating a transparent conductive pattern included in a first pixel in Figure 8

[0036] Figure 10 is a layout view illustrating a first pixel of a display device according to an embodiment.

[0037] Figure 11 is a view illustrating a gate pattern included in a first pixel in Figure 10

[0038] Figure 12 is a layout view illustrating a first pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, a display device according to an embodiment will be described in detail with reference to the accompanying drawings.

[0040] Hereinafter, a display device according to an embodiment will be described with reference to Figures 1 to 7

[0041] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0042] Referring to Figure 1 , a display device according to an embodiment can include a display unit 110, a scan driver 120, a data driver 130, and a timing controller 140.

[0043] The display unit 110 can display an image. A plurality of pixels including a first pixel PX1 and a second pixel PX2 can be disposed in the display unit 110. The plurality of pixels can be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1.

[0044] Each pixel can be electrically connected to one of scan lines SL and one of data lines DL. The scan lines SL can extend in the first direction DR1. The data lines DL can extend in the second direction DR2, for example, as shown in Figure 1 The first direction DR1 can be a bidirectional direction along a row direction, and the second direction DR2 can be a bidirectional direction along a column direction, for example, as shown in

[0045] ​​​The scan driver 120 can generate a scan signal SS based on a first control signal CONT1 provided from the timing controller 140. The scan driver 120 can provide the scan signal SS to a pixel disposed in the display unit 110 through a scan line SL. In an embodiment, the scan driver 120 can include a transistor. In an embodiment, the scan driver 120 can be an integrated circuit.

[0046] The data driver 130 can receive a second control signal CONT2 and image data DATA from the timing controller 140. The data driver 130 can generate a data signal DS based on the second control signal CONT2 and the image data DATA. The data driver 130 can provide the data signal DS to a pixel disposed in the display unit 110 through a data line DL. In an embodiment, the data driver 130 can include a shift register, a latch, or a digital-to-analog converter, etc.

[0047] The timing controller 140 can receive an image signal RGB and a control signal CS from the outside. The timing controller 140 can process the image signal RGB and the control signal CS to conform to an operating condition of the display unit 110, and can generate the image data DATA, the first control signal CONT1, and the second control signal CONT2.

[0048] The image signal RGB can include grayscale data provided to the display unit 110. The control signal CS can include a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, or a similar signal. The horizontal synchronization signal can indicate a time taken to display one pixel row of the display unit 110. The vertical synchronization signal can indicate a time taken to display one frame of an image. The main clock signal can be a signal used as a reference for generating signals by synchronizing the timing controller 140 with the scan driver 120 and the data driver 130.

[0049] Figure 2 is an equivalent circuit diagram illustrating Figure 1 a first pixel PX1 and a second pixel PX2 in FIG.

[0050] Referring to Figure 2 , the display apparatus can include a first pixel PX1 and a second pixel PX2. The second pixel PX2 can be adjacent to the first pixel PX1 in a first direction DR1. Accordingly, the first pixel PX1 and the second pixel PX2 can be included in one pixel row.

[0051] The first pixel PX1 and the second pixel PX2 can receive different data signals from different data lines. For example, the first pixel PX1 can receive a first data signal DS1 from a first data line DL1, and the second pixel PX2 can receive a second data signal DS2 different from the first data signal DS1 from a second data line DL2 arranged spaced apart from the first data line DL1 in a first direction DR1.

[0052] The first pixel PX1 and the second pixel PX2 can receive a scan signal from the same scan line. For example, the first pixel PX1 and the second pixel PX2 can receive a scan signal SS from a scan line SL.

[0053] Each of the first pixel PX1 and the second pixel PX2 can include a transistor, a liquid crystal capacitor, and a storage capacitor. For example, the first pixel PX1 can include a first transistor TR1, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1, and the second pixel PX2 can include a second transistor TR2, a second liquid crystal capacitor Clc2, and a second storage capacitor Cst2. Hereinafter, both the first pixel PX1 and the second pixel PX2 will be described in more detail based on the first pixel PX1.

[0054] The first transistor TR1 can include a control electrode, a source electrode, and a drain electrode. The control electrode of the first transistor TR1 can be connected to the scan line SL. The source electrode of the first transistor TR1 can be connected to the first data line DL1, and the drain electrode of the first transistor TR1 can be connected to the first node N1. The first transistor TR1 can perform a switching operation based on the scan signal SS provided from the scan line SL, and can provide the first data signal DS1 provided from the first data line DL1 to the first node N1.

[0055] The first liquid crystal capacitor Clc1 can be formed between the first node N1 and a common electrode CM of the Figure 7 The first storage capacitor Cst1 can be formed between the first node N1 and a storage line RL of the Figure 3

[0056] Hereinafter, the driving of the display apparatus according to an embodiment will be described based on the first pixel PX1 and the second pixel PX2.

[0057] ​The first transistor TR1 can perform a switching operation based on the scan signal SS, and the second transistor TR2 can perform a switching operation based on the scan signal SS. Accordingly, the first transistor TR1 and the second transistor TR2 can perform the same switching operation. However, because the first transistor TR1 is connected to the first data line DL1 and the second transistor TR2 is connected to the second data line DL2, different data signals can be provided to the first node N1 and the second node N2.

[0058] Figure 3 is a layout view illustrating a first pixel PX1 included in a display panel 1000. Figure 1 Figure 4 is a view illustrating a gate pattern included in the first pixel PX1 in Figure 3 Figure 5 is a view illustrating a data pattern included in the first pixel PX1 in Figure 3 Figure 6 is a view illustrating a transparent conductive pattern included in the first pixel PX1 in Figure 3 Figure 7 is a cross-sectional view taken along a line I-I' in Figure 3 In the following, for convenience of description, both the first pixel PX1 and the second pixel PX2 will be described based on the first pixel PX1.

[0059] Referring to Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 , the display device can include a first display substrate 200, a second display substrate 300, and a liquid crystal layer 400.

[0060] The first display substrate 200 and the second display substrate 300 can be disposed to face each other. The liquid crystal layer 400 can be interposed between the first display substrate 200 and the second display substrate 300. The liquid crystal layer 400 can include liquid crystal molecules 410. In an embodiment, the first display substrate 200 and the second display substrate 300 can be bonded by a sealing member.

[0061] The first display substrate 200 can include a first substrate 210, a gate pattern GP, a gate insulating layer 220, a data pattern DP, a first passivation layer 250, a color filter CF, an organic insulating layer 260, a second passivation layer 270, and a transparent conductive pattern TP.

[0062] In an embodiment, the first substrate 210 can be a transparent insulating substrate. The transparent insulating substrate can include glass, quartz, or a light-transmissive plastic, etc. In an embodiment, the first substrate 210 can be a flexible substrate, or can be a structure in which various films are stacked.

[0063] ​​​​The gate pattern GP can be disposed on the first substrate 210. The gate pattern GP can include a scan line SL, a control electrode CE, a storage line RL, and a storage electrode RE.

[0064] The scan line SL can extend in the first direction DR1. The control electrode CE can protrude from the scan line SL. In an embodiment, the control electrode CE can protrude from the scan line SL in the second direction DR2.

[0065] The storage line RL can be parallel to the scan line SL. The storage line RL can be disposed on the same layer as the scan line SL. In an embodiment, the storage line RL can be disposed to surround at least a portion of the pixel electrode PE. For example, the storage line RL can include a first portion R1 surrounding a left portion of the pixel electrode PE and a second portion R2 surrounding a right portion of the pixel electrode PE.

[0066] The storage line RL can overlap at least a portion of the pixel electrode PE. Because the storage line RL overlaps the pixel electrode PE, a first storage capacitor Cst1 in the pixel electrode PE can be formed by the storage line RL and the pixel electrode PE. Figure 2

[0067] The storage electrode RE can protrude from the storage line RL. In an embodiment, the storage electrode RE can protrude from the storage line RL in the second direction DR2. The storage electrode RE can overlap at least a portion of the drain electrode extension portion OEP described below. Because the storage electrode RE overlaps the drain electrode extension portion OEP, a first storage capacitor Cst1 in the pixel electrode PE can be formed by the storage electrode RE and the drain electrode extension portion OEP. Figure 2

[0068] In an embodiment, an area of the storage electrode RE can be smaller than an area of the drain electrode extension portion OEP. Because the area of the storage electrode RE is smaller than the area of the drain electrode extension portion OEP, the storage electrode RE can be disposed inside the drain electrode extension portion OEP in a plan view, despite a tolerance occurring in a process of forming the data pattern DP on the gate pattern GP. Accordingly, a capacitance of the first storage capacitor Cst1 in the pixel electrode PE formed by the storage electrode RE and the drain electrode extension portion OEP can be constant. Figure 2

[0069] ​​​The gate pattern GP can be formed as a single layer including one of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W), a double layer including two of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W), or a triple layer including three of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W). The scan lines SL, the control electrodes CE, the storage lines RL, and the storage electrodes RE included in the gate pattern GP can be formed substantially simultaneously through the same photomask.

[0070] The gate insulating layer 220 can be provided on the gate pattern GP. In an embodiment, the gate insulating layer 220 can be formed of silicon nitride, silicon oxide, or the like. The gate insulating layer 220 can have a multi-layer structure including at least two layers having different physical properties.

[0071] The data pattern DP can be provided on the gate insulating layer 220. The data pattern DP can include the first data line DL1, the second data line DL2, the source electrode IE, the drain electrode OE, and the semiconductor layer 230. The channel region CH of the first transistor TR1 can be formed in the semiconductor layer 230 located between the source electrode IE and the drain electrode OE.

[0072] The semiconductor layer 230 can be provided on the gate insulating layer 220. In an embodiment, the semiconductor layer 230 can be formed of amorphous silicon, polysilicon, or the like. In an embodiment, the semiconductor layer 230 can be formed of an oxide semiconductor. When the semiconductor layer 230 is formed of an oxide semiconductor, the semiconductor layer 230 can be formed of one of oxide semiconductors including IGZO, ZnO, ZnO2, CdO, SrO, SrO2, CaO, CaO2, MgO, MgO2, InO, In2O, GaO, Ga2O, Ga2O3, SnO, SnO2, GeO, GeO2, PbO, Pb2O3, Pb3O4, TiO, TiO2, Ti2O3, and Ti3O5.

[0073] In an embodiment, the data pattern DP can further include an ohmic contact layer 240. The ohmic contact layer 240 can be provided on the semiconductor layer 230. The ohmic contact layer 240 can be formed of a material such as n+hydrogenated amorphous silicon doped with a high concentration of an n-type impurity such as phosphorus, or can be formed of a silicide. However, when the semiconductor layer 230 is formed of an oxide semiconductor, the ohmic contact layer 240 can be omitted. Hereinafter, it will be described in the present specification that the data pattern DP includes the ohmic contact layer 240.

[0074] The first data line DL1, the second data line DL2, the source electrode IE, and the drain electrode OE can be disposed on the gate insulating layer 220 and the ohmic contact layer 240. The source electrode IE can protrude from the first data line DL1, and at least a portion of the source electrode IE can overlap the control electrode CE. The drain electrode OE can be spaced apart from the source electrode IE, and at least a portion of the drain electrode OE can overlap the control electrode CE. The drain electrode OE can include a drain electrode extension portion OEP. The drain electrode extension portion OEP can overlap the storage electrode RE and the pixel electrode PE.

[0075] Figure 3 and Figure 5 It is shown that the source electrode IE has a "U" shape in a plan view, and the drain electrode OE is surrounded by the source electrode IE, however, the control electrode CE, the source electrode IE, the drain electrode OE, and the channel region CH can form the first transistor TR1.

[0076] In a plan view, the drain electrode extension portion OEP can be positioned in a first direction DR1 from the first transistor TR1. The first transistor TR1 can be positioned adjacent to the first data line DL1 in a plan view, and the drain electrode extension portion OEP can be positioned adjacent to the second data line DL2 in a plan view.

[0077] The data pattern DP can be formed as a single layer including one of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W), a double layer including two of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W), or a triple layer including three of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W). The first data line DL1, the second data line DL2, the source electrode IE, the drain electrode OE, the semiconductor layer 230, and the ohmic contact layer 240 included in the data pattern DP can be formed substantially simultaneously through the same photomask.

[0078] The first passivation layer 250 can be disposed on the data pattern DP. The first passivation layer 250 can include an opening portion that exposes at least a portion of the drain electrode extension portion OEP. In an embodiment, the first passivation layer 250 can be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or the like. The first passivation layer 250 can prevent pigments of the color filter CF from flowing into the channel region CH.

[0079] The color filter CF can be disposed on the first passivation layer 250. The color filter CF can include an opening portion that overlaps the opening portion of the first passivation layer 250 and exposes at least a portion of the drain electrode extension portion OEP.

[0080] Light passing through the color filter CF can display one of primary colors such as red, green, blue, and the like. However, the light can also display any one of cyan, magenta, yellow, and white. In an embodiment, the color filter CF can be formed of a material displaying a different color for each of the pixels (e.g., the first pixel PX1 and the second pixel PX2) adjacent in the first direction DR1, and can be formed of a material displaying the same color for each of the pixels adjacent in the second direction DR2. However, in an embodiment, the color filter CF can be formed of a material displaying a different color for each of the pixels adjacent regardless of the direction. Figure 7 The color filter CF is shown to be disposed in the first display substrate 200, however, in another embodiment, the color filter CF can be disposed in the second display substrate 300.

[0081] The organic insulating layer 260 can be disposed on the first passivation layer 250 and the color filter CF. The organic insulating layer 260 can include an opening portion overlapping the opening portion of the first passivation layer 250 and exposing at least a portion of the drain electrode extension portion OEP. The organic insulating layer 260 can include an organic material having excellent planarization characteristics and photosensitivity. The organic insulating layer 260 can be omitted.

[0082] The second passivation layer 270 can be disposed on the organic insulating layer 260. The second passivation layer 270 can include an opening portion overlapping the opening portion of the first passivation layer 250 and exposing at least a portion of the drain electrode extension portion OEP. In an embodiment, the second passivation layer 270 can be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or the like. The second passivation layer 270 can be omitted.

[0083] The opening portion of the first passivation layer 250, the opening portion of the color filter CF, the opening portion of the organic insulating layer 260, and the opening portion of the second passivation layer 270 can form a contact hole CNT.

[0084] The transparent conductive pattern TP can be disposed on the second passivation layer 270. The transparent conductive pattern TP can include a transparent conductive material. In an embodiment, the transparent conductive material can include polycrystalline, single-crystalline, or amorphous indium tin oxide (ITO).

[0085] The transparent conductive pattern TP can include a pixel electrode PE and a shield electrode SE. The pixel electrode PE and the shield electrode SE can be disposed on the same layer and can be physically and electrically insulated from each other.

[0086] The shield electrode SE can have a shape extending mainly in the second direction DR2. The shield electrode SE can include a horizontal stem extending in the first direction DR1 and a vertical stem extending from the horizontal stem in the second direction DR2. In an embodiment, the horizontal stem of the shield electrode SE can at least partially overlap the scan line SL. The vertical stem of the shield electrode SE can at least partially overlap the first data line DL1 and the second data line DL2. Further, as shown in Figure 4 and Figure 6 the vertical stem of the shield electrode SE can at least partially overlap the first portion R1 and the second portion R2 of the storage line RL. In an embodiment, the voltage level of the voltage supplied to the shield electrode SE can be substantially the same as the voltage level of the common voltage Vcom supplied to the common electrode CM in Figure 2 In an embodiment, the common voltage Vcom can be directly supplied to the shield electrode SE.

[0087] The pixel electrode PE can directly contact the drain electrode extension portion OEP exposed through the contact hole CNT. In this case, in a plan view, the portion at which the first transistor TR1 and the pixel electrode PE are connected through the contact hole CNT can be defined as a pixel electrode connection portion CP. Further, the pixel electrode PE can overlap the common electrode CM. Accordingly, Figure 2 the first liquid crystal capacitor Clcl in

[0088] The pixel electrode PE can include a first stem portion PEal, a second stem portion PEa2, an edge stem portion PEa3, and a connection stem portion PEa4. The first stem portion PEal extends in the first direction DR1. The second stem portion PEa2 intersects the first stem portion PEal and extends in the second direction DR2. The edge stem portion PEa3 is physically connected to the first stem portion PEal and the second stem portion PEa2, and is physically connected to an end portion of each of the branch portions PEbl to Peb4 described below. The connection stem portion PEa4 is physically spaced apart from the first stem portion PEal, the second stem portion PEa2, and the edge stem portion PEa3, and includes a connection portion PEC.

[0089] The connection portion PEC can be defined as a portion overlapping the contact hole CNT. Accordingly, the connection portion PEC of the pixel electrode PE can be directly connected to the drain electrode extension portion OEP exposed through the contact hole CNT.

[0090] The pixel electrode PE can include a first branch portion PEbl, a second branch portion PEb2, a third branch portion PEb3, and a fourth branch portion PEb4 extending from the first stem portion PEal and the second stem portion PEa2.

[0091] The first branch portion PEb1 can extend from the first trunk portion PEa1 and the second trunk portion PEa2 in a third direction DR3 and can be physically connected to the edge trunk portion PEa3. The second branch portion PEb2 can extend from the first trunk portion PEa1 and the second trunk portion PEa2 in a fourth direction DR4 and can be physically connected to the edge trunk portion PEa3. The third branch portion PEb3 can extend from the first trunk portion PEa1 and the second trunk portion PEa2 in a fifth direction DR5. A first portion of the third branch portion PEb3 can be physically connected to the edge trunk portion PEa3 and a second portion of the third branch portion PEb3 can be physically connected to the connection trunk portion PEa4. The fourth branch portion PEb4 can extend from the first trunk portion PEa1 and the second trunk portion PEa2 in a sixth direction DR6. A first portion of the fourth branch portion PEb4 can be physically connected to the edge trunk portion PEa3 and a second portion of the fourth branch portion PEb4 can not be physically connected to the edge trunk portion PEa3.

[0092] The trunk portions PEa1 to PEa4 and the branch portions PEb1 to PEb4 of the pixel electrode PE can be electrically connected. Accordingly, the trunk portions PEa1 to PEa4 and the branch portions PEb1 to PEb4 can have the same electric potential.

[0093] Based on the first trunk portion PEa1 and the second trunk portion PEa2, the pixel electrode PE can include four domain regions. A first domain region DM1 can be defined as a region positioned in the third direction DR3 from a crossing point between the first trunk portion PEa1 and the second trunk portion PEa2. A second domain region DM2 can be defined as a region positioned in the fourth direction DR4 from the crossing point between the first trunk portion PEa1 and the second trunk portion PEa2. A third domain region DM3 can be defined as a region positioned in the fifth direction DR5 from the crossing point between the first trunk portion PEa1 and the second trunk portion PEa2. A fourth domain region DM4 can be defined as a region positioned in the sixth direction DR6 from the crossing point between the first trunk portion PEa1 and the second trunk portion PEa2.

[0094] The first domain region DM1 can include the first branch portion PEb1. The second domain region DM2 can include the second branch portion PEb2. The third domain region DM3 can include the third branch portion PEb3. The fourth domain region DM4 can include the fourth branch portion PEb4.

[0095] In an embodiment, the areas of the first domain region DM1 and the second domain region DM2 can be substantially the same, and the areas of the third domain region DM3 and the fourth domain region DM4 can be substantially the same. However, in an embodiment, the areas of the respective domain regions can be different from each other. For example, the area of ​​the first domain region DM1 can be larger than the area of ​​the second domain region DM2.

[0096] When an electric field is formed in the liquid crystal layer 400, the liquid crystal molecules 410 disposed in the first domain region DM1 can be oriented in the third direction DR3 or the fifth direction DR5. When an electric field is formed in the liquid crystal layer 400, the liquid crystal molecules 410 disposed in the second domain region DM2 can be oriented in the fourth direction DR4 or the sixth direction DR6. When an electric field is formed in the liquid crystal layer 400, the liquid crystal molecules 410 disposed in the third domain region DM3 can be oriented in the fifth direction DR5 or the third direction DR3. When an electric field is formed in the liquid crystal layer 400, the liquid crystal molecules 410 disposed in the fourth domain region DM4 can be oriented in the sixth direction DR6 or the fourth direction DR4. In this embodiment, the orientation directions of the liquid crystal molecules 410 can be different from each other in the domain regions DM1 to DM4. In this case, the display device can provide a screen with a relatively wide viewing angle.

[0097] A first alignment layer can be formed on the transparent conductive pattern TP. The first alignment layer can induce the initial alignment of the liquid crystal molecules 410 in the liquid crystal layer 400.

[0098] As described above, the drain electrode extension portion OEP can be configured to be adjacent to the second data line DL2. In this case, as... Figure 5 As shown, the gap G2 between the drain electrode extension OEP and the second data line DL2 can be smaller than the gap G1 between the drain electrode extension OEP and the first data line DL1. In other words, the gap between the pixel electrode connection portion CP and the second data line DL2 can be smaller than the gap between the pixel electrode connection portion CP and the first data line DL1. When the gap G2 between the drain electrode extension OEP and the second data line DL2 is smaller than the gap G1 between the drain electrode extension OEP and the first data line DL1, the capacitance between the first pixel PX1 and the second data line DL2 may be greater than the capacitance between the first pixel PX1 and the first data line DL1. Therefore, the capacitance deviation between the first pixel PX1 and the data lines DL1 and DL2 may be relatively large, and the image quality of the display device may be reduced due to the capacitance deviation.

[0099] like Figure 3 and Figure 4As shown in FIG. 1, to reduce the capacitance deviation between the first pixel PX1 and the data lines DL1 and DL2, the storage line RL can include a first extension portion EP1 that protrudes in a plan view to be located between the second data line DL2 and the drain electrode extension portion OEP. In other words, the first extension portion EP1 can protrude in a plan view to be located between the second data line DL2 and the pixel electrode connection portion CP.

[0100] In an embodiment, the first extension portion EP1 can extend in the second direction DR2. In a plan view, the first extension portion EP1 can extend from the storage line RL toward the scan line SL between the second data line DL2 and the drain electrode extension portion OEP.

[0101] In a plan view, the first extension portion EP1 can be disposed between the second data line DL2 and the drain electrode extension portion OEP. The storage voltage Vst in the storage line RL can be provided to the first extension portion EP1, so that the first extension portion EP1 can be shielded between the second data line DL2 and the drain electrode extension portion OEP. Accordingly, the capacitance between the first pixel PX1 and the second data line DL2 can be reduced, and the capacitance deviation between the first pixel PX1 and the data lines DL1 and DL2 can be reduced. Figure 2

[0102] The second display substrate 300 can include a second substrate 310, a black matrix BM, a planarization layer 320, and a common electrode CM.

[0103] The second substrate 310 can be disposed opposite the first substrate 210. The second substrate 310 can be a transparent insulating substrate. In an embodiment, the second substrate 310 can be formed of the same material as the first substrate 210.

[0104] The black matrix BM can be disposed on the second substrate 310. The black matrix BM can be disposed in the first direction DR1 in a passive area. The passive area is a boundary between adjacent pixels in the second direction DR2, and the branch portions PEb1 to PEb4 of the pixel electrode PE can not be disposed in the passive area. The black matrix BM can extend in the first direction DR1 and can overlap the scan line SL.

[0105] The black matrix BM can prevent light from being transmitted through the passive area. In an embodiment, the black matrix BM can be formed of a photosensitive material, an organic material, or a metallic material, etc. For example, the photosensitive material can include a binder resin, a polymerizable monomer, a polymerizable oligomer, a pigment, or a dispersant, etc. Further, the metallic material can include chromium (Cr), etc.

[0106] ​The black matrix BM extending in the second direction DR2 can not be disposed between the pixels adjacent in the first direction DR1, for example, between the first pixel PX1 and the second pixel PX2. The liquid crystal alignment can be adjusted by adjusting the space between the pixels adjacent in the first direction DR1 so that light can not pass between the pixels adjacent in the first direction DR1 without the black matrix BM. In addition, the liquid crystal alignment can be adjusted using the shield electrode SE so that light can not pass.

[0107] A planarization layer 320 can be disposed on the black matrix BM. The planarization layer 320 can provide a planarized surface to the common electrode CM. In an embodiment, the planarization layer 320 can be formed of an organic material or an inorganic material.

[0108] A common electrode CM can be disposed on the planarization layer 320. At least a portion of the common electrode CM can overlap the pixel electrode PE. In an embodiment, the common electrode CM can be formed of a transparent conductive material such as ITO, IZO, or the like, or a reflective metal such as aluminum (Al), silver (Ag), chromium (Cr), an alloy thereof, or the like.

[0109] A second alignment layer can be disposed on the common electrode CM. The second alignment layer can induce an initial alignment of the liquid crystal molecules 410 in the liquid crystal layer 400. In an embodiment, the second alignment layer can be formed of substantially the same material as the first alignment layer.

[0110] The liquid crystal layer 400 can include liquid crystal molecules 410. In an embodiment, the liquid crystal molecules 410 can have a negative dielectric anisotropy and can be vertically aligned in an initial alignment state. The liquid crystal molecules 410 can have a predetermined pre-tilt angle in the initial alignment state. The initial alignment of the liquid crystal molecules 410 can be induced by the first alignment layer and the second alignment layer. When an electric field is formed between the first display substrate 200 and the second display substrate 300, the liquid crystal molecules 410 can tilt or rotate in a certain direction, thereby changing a polarization state of light passing through the liquid crystal layer 400.

[0111] Hereinafter, a display apparatus according to an embodiment will be described with reference to Figure 8 and Figure 9 The display apparatus according to an embodiment can be substantially the same as or similar to the display apparatus described with reference to Figure 8 and Figure 9 The display apparatus according to an embodiment can be substantially the same as or similar to the display apparatus described with reference to Figures 1 to 7 The description of the repeated elements will be omitted.

[0112] Figure 8 is a layout view illustrating a first pixel of a display apparatus according to an embodiment. Figure 9 is a layout view illustrating a second pixel of a display apparatus according to an embodiment. Figure 8a view of a transparent conductive pattern in the first pixel.

[0113] Referring to Figure 8 and Figure 9 , the shield electrode SE of the display device according to the embodiment can include a second extension portion EP2 which protrudes in a plan view to be located between the second data line DL2 and the drain electrode extension portion OEP. In other words, the second extension portion EP2 can protrude in a plan view to be located between the second data line DL2 and the pixel electrode connection portion CP.

[0114] In the embodiment, the second extension portion EP2 can extend in the first direction DR1. In a plan view, the second extension portion EP2 can extend from a first portion of the shield electrode SE which overlaps the second data line DL2 toward a second portion of the shield electrode SE which overlaps the first data line DL1.

[0115] In the embodiment, the second extension portion EP2 can at least partially overlap the first extension portion EP1. Since the insulating layer is disposed between the storage line RL and the shield electrode SE, the second extension portion EP2 which protrudes from the shield electrode SE can be insulated from and at least partially overlap the first extension portion EP1 which protrudes from the storage line RL.

[0116] In a plan view, the second extension portion EP2 can be disposed between the second data line DL2 and the drain electrode extension portion OEP. The common voltage Vcom in Figure 2 may be provided to the second extension portion EP2 so that the second extension portion EP2 can shield together with the first extension portion EP1 between the second data line DL2 and the drain electrode extension portion OEP. Accordingly, a capacitance between the first pixel PX1 and the second data line DL2 can be further reduced, and a capacitance deviation between the first pixel PX1 and the data lines DL1 and DL2 can be reduced.

[0117] Hereinafter, a display device according to an embodiment will be described with reference to Figure 10 and Figure 11 . The display device described with reference to Figure 10 and Figure 11 may be substantially the same as or similar to the display device described with reference to Figures 1 to 7 . Accordingly, a description of overlapping elements will be omitted.

[0118] Figure 10 is a layout view illustrating a first pixel of a display device according to an embodiment. Figure 11 is a view illustrating a gate pattern in the first pixel included in Figure 10 .

[0119] Referring toFigure 10 and Figure 11 The scan line SL of the display device according to the embodiment can include a first extension portion EP1 that protrudes to be located between the second data line DL2 and the drain electrode extension portion OEP in a plan view. In other words, the first extension portion EP1 can protrude to be located between the second data line DL2 and the pixel electrode connection portion CP in a plan view.

[0120] In an embodiment, the first extension portion EP1 can extend in the second direction DR2. The first extension portion EP1 can extend from the scan line SL toward the storage line RL between the second data line DL2 and the drain electrode extension portion OEP in a plan view. Accordingly, the first extension portion EP1 can shield between the second data line DL2 and the drain electrode extension portion OEP. Accordingly, a capacitance between the first pixel PX1 and the second data line DL2 can be further reduced, and a capacitance deviation between the first pixel PX1 and the data lines DL1 and DL2 can be reduced.

[0121] Hereinafter, a display device according to an embodiment will be described with reference to Figure 12 The display device described with reference to Figure 12 may be substantially the same as or similar to the display device described with reference to Figure 10 and Figure 11 Accordingly, a description of overlapping elements will be omitted.

[0122] Figure 12 is a layout view illustrating a first pixel of a display device according to an embodiment.

[0123] The shielding electrode SE of the display device according to the embodiment can include a second extension portion EP2 that protrudes to be located between the second data line DL2 and the drain electrode extension portion OEP in a plan view, with reference to Figure 12 In other words, the second extension portion EP2 can protrude to be located between the second data line DL2 and the pixel electrode connection portion CP in a plan view. In an embodiment, the second extension portion EP2 can extend in the first direction DR1.

[0124] In an embodiment, the second extension part EP2 can at least partially overlap the first extension part EP1. Because the insulating layer is disposed between the scan line SL and the shield electrode SE, the second extension part EP2 protruding from the shield electrode SE can be insulated from and at least partially overlap the first extension part EP1 protruding from the scan line SL. Accordingly, the second extension part EP2 can shield together with the first extension part EP1 between the second data line DL2 and the drain electrode extension part OEP. Accordingly, a capacitance between the first pixel PX1 and the second data line DL2 can be further reduced, and a capacitance deviation between the first pixel PX1 and the data lines DL1 and DL2 can be reduced.

[0125] The display device according to an embodiment can be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet computer, a PMP, a PDA, or an MP3 player, etc.

[0126] Although the display device according to an embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is an example, and modifications and changes can be made by those skilled in the art without departing from the technical spirit described in the appended claims.

Claims

1. A display device, wherein, The display device includes: a scan line extending in a first direction; a storage line parallel to the scan line; a first data line provided on the scan line and the storage line, the first data line extending in a second direction intersecting the first direction; a second data line parallel to the first data line; a transistor including a control electrode protruding from the scan line, a source electrode protruding from the first data line, and a drain electrode spaced apart from the source electrode and including a drain electrode extension; a pixel electrode provided between the first data line and the second data line and connected to the drain electrode extension; and a first extension between the second data line and the drain electrode extension in a plan view, wherein the first extension does not overlap any conductive configuration included in the display device in the plan view.

2. The display device according to claim 1, wherein A gap between the drain electrode extension and the second data line is smaller than a gap between the drain electrode extension and the first data line.

3. The display device according to claim 1, wherein The first extension extends in the second direction.

4. The display device according to claim 1, wherein The storage line includes the first extension.

5. The display device according to claim 1, wherein The scan line includes the first extension.

6. The display device according to claim 1, wherein The display device further includes: a shield electrode provided on the same layer as the pixel electrode, the shield electrode overlapping the first data line and the second data line.

7. The display device according to claim 1, wherein The storage line is provided on the same layer as the scan line.

8. The display device according to claim 1, wherein The storage line includes a storage electrode overlapping the drain electrode extension.

9. The display device of claim 8, wherein, An area of the storage electrode is smaller than an area of the drain electrode extension.

10. A display device, wherein, The display device includes: a first pixel including a transistor and a pixel electrode connected to the transistor; a second pixel adjacent to the first pixel in a first direction; a scan line extending in the first direction, the scan line configured to provide a scan signal to the first pixel and the second pixel; a storage line parallel to the scan line, the storage line configured to provide a storage voltage to the first pixel and the second pixel; a first data line provided on the scan line and the storage line, the first data line extending in a second direction intersecting the first direction and configured to provide a first data signal to the first pixel; a second data line parallel to the first data line, the second data line configured to provide a second data signal to the second pixel; and a first extension between the second data line and a pixel electrode connection portion connecting the transistor and the pixel electrode in a plan view, wherein the first extension does not overlap any conductive configuration included in the display device in the plan view.

11. The display device of claim 10, wherein, A gap between the pixel electrode connection portion and the second data line is smaller than a gap between the pixel electrode connection portion and the first data line.

12. The display device of claim 10, wherein, The first extension portion extends in the second direction.

13. The display device of claim 10, wherein, The storage line includes the first extension portion.

14. The display device of claim 10, wherein, The scan line includes the first extension portion.

15. The display device of claim 10, wherein, The display device further includes: A shield electrode disposed on the same layer as the pixel electrode, the shield electrode overlapping the first data line and the second data line.

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