A stacked chip

Abstract

The present invention provides a stacked chip, comprising: a first programmable gate array component, the first programmable gate array component including a first interface module, the first interface module being embedded within the first programmable gate array component and including a first bond lead-out region; and a first memory array component provided with a second bond lead-out region. The first bond lead-out region and the second bond lead-out region are bonded together to connect interconnect signals on the first programmable gate array component and the first memory array component, thereby achieving high bandwidth and low power consumption for memory access.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a stacked chip. Background Art

[0002] With the rapid growth of application computing scale, the bandwidth and energy consumption overhead of storage access have become important factors limiting the development of scalable computing circuits. Summary of the Invention

[0003] The present invention provides a stacked chip capable of achieving high bandwidth and low power consumption for storage access.

[0004] To solve the above technical problems, the present invention provides a technical solution: providing a stacked chip, comprising: a first programmable gate array component, the first programmable gate array component including a first interface module, the first interface module being embedded in the first programmable gate array component, the first interface module including a first bonding lead-out area; a first storage array component, provided with a second bonding lead-out area; the first bonding lead-out area and the second bonding lead-out area are bonded and connected to connect the interconnection signals on the first programmable gate array component and the first storage array component together.

[0005] The first programmable gate array component includes multiple functional modules, the number of the first interface module is at least one, the first interface module is located between the multiple functional modules, and is connected to the functional modules through the interface routing unit.

[0006] The interior of the functional module is strip-shaped, and the first interface module is arranged extending along the strip-shaped functional module layout.

[0007] The functional module is connected to the interface routing unit through an internal metal layer, and the first interface module is interconnected with the interface routing unit through the internal metal layer.

[0008] The first programmable gate array component includes a programmable routing network, a plurality of functional modules are interconnected with the programmable routing network through an internal metal layer, and are connected to the interface routing unit through the programmable routing network.

[0009] The stacked chip further includes: a physical layer, which is used to implement level conversion between the first programmable gate array component and the second storage array component; the physical layer is arranged on the first interface module.

[0010] Among them, the functional modules include: any one or more of the programmable logic block LAB (Logic Array Block) / CLB (Configurable Logic Block), the storage block BRAM (Block Random Access Memory, BRAM), the multiplication unit DSP (Digital Signal Processor) and the multiplication and accumulation unit MAC (Multiply Accumulate) in any combination.

[0011] Among them, the functional module also includes: a combination of dedicated integrated circuit array units, which are solidified hardware circuits used to complete fixed computing targets.

[0012] The storage block is connected to the programmable logic block through a storage routing unit.

[0013] The first programmable gate array component includes a field programmable gate array (FPGA) or an embedded field programmable gate array (eFPGA).

[0014] Among them, the stacked chip also includes: a storage control unit, which is arranged on the first interface module; or, the storage control unit is arranged at a position of the first programmable gate array component close to the first interface; or, the storage control unit is arranged on the first storage array component; the storage control unit controls the first programmable gate array component to perform storage access to the first storage array component.

[0015] Among them, the stacked chip also includes: a second storage array component, the second storage array component is arranged on the side of the first programmable gate array component away from the first storage array component; the second storage array component is provided with a third bonding lead-out area; the first interface module includes a fourth bonding lead-out area, and the first programmable gate array component and the second storage array component are bonded and connected through the third bonding lead-out area and the fourth bonding lead-out area.

[0016] Among them, the stacked chip also includes: a second storage array component, the second storage array component is arranged on a side of the first storage array component away from the first programmable gate array component; the second storage array component is provided with a third four-bonding lead-out area; the first storage array component includes a fourth bonding lead-out area, and the first storage array component and the second storage array component are bonded and connected through the fourth bonding lead-out area and the third bonding lead-out area.

[0017] The stacked chip further includes: a storage control unit, which is arranged on the first interface module; the storage control unit controls the first programmable gate array component to access the first storage array component and the second storage array component.

[0018] Among them, the first programmable gate array component also includes: a programmable logic unit, connected to the storage control unit, and the programmable logic unit leads to a logic signal; the storage control unit selectively controls the first programmable gate array component to access the first storage array component based on the logic signal, or controls the first programmable gate array component to access the second storage array component.

[0019] Among them, the stacked chip also includes: a first storage control unit, which is arranged on the first interface module; a second storage control unit, which is arranged on the first interface module; the first storage control unit controls the first programmable gate array component to access the first storage array component, and the second storage control unit controls the first programmable gate array component to access the second storage array component.

[0020] Among them, the first programmable gate array component also includes: a programmable logic unit, connected to the first storage control unit and the second storage control unit, and the programmable logic unit leads to a logic signal; the first storage control unit controls the first programmable gate array component to access the first storage array component based on the logic signal, and the second storage control unit simultaneously controls the first programmable gate array component to access the second storage array component based on the logic signal.

[0021] The beneficial effects of the present invention are different from those of the prior art. The stacked chip of the present invention connects the interconnection signals on the first programmable gate array component and the first storage array component through the first bonding lead-out area and the second bonding lead-out area, and the first interface module of the first bonding lead-out area is embedded in the first programmable gate array component, thereby realizing a three-dimensional heterogeneous integrated structure and achieving the purpose of high bandwidth and low power consumption of storage access. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0023] Figure 1 This is a schematic structural diagram of a first embodiment of a stacked chip according to the present invention;

[0024] Figure 2 Schematic diagram of the planar structure of the first programmable gate array component of the present invention;

[0025] Figure 3 for Figure 1 A schematic diagram of a storage access structure of the first programmable gate array component to the first storage array component;

[0026] Figure 4 This is a schematic structural diagram of a second embodiment of the stacked chip of the present invention;

[0027] Figure 5 for Figure 4 A schematic structural diagram of the shared storage access of the first programmable gate array component and the second programmable gate array component to the first storage array component;

[0028] Figure 6 for Figure 4 A schematic diagram of a structure in which the first programmable gate array component and the second programmable gate array component independently access the first storage array component;

[0029] Figure 7 Schematic diagram of the structure of a third embodiment of the stacked chip of the present invention;

[0030] Figure 8 for Figure 7 A schematic diagram of a structure in which the first programmable gate array component accesses the shared storage of the first storage array component and the second storage array component;

[0031] Figure 9 for Figure 7 A schematic diagram of a structure in which the first programmable gate array component independently accesses the first storage array component and the second storage array component;

[0032] Figure 10 Schematic diagram of the structure of a fourth embodiment of the stacked chip of the present invention;

[0033] Figure 11 for Figure 10 A schematic diagram of a structure in which the first programmable gate array component accesses the shared storage of the first storage array component and the second storage array component;

[0034] Figure 12 for Figure 10 A schematic diagram of a structure in which the first programmable gate array component independently accesses the first storage array component and the second storage array component;

[0035] Figure 13 A schematic diagram of the structure of a programmable routing network and a programmable logic block;

[0036] Figure 14 Schematic diagram of the three-dimensional heterogeneous integration structure between functional components 210, 220, and 230. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] The terms "first", "second" and "third" in the present invention are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second" and "third" may explicitly or implicitly include at least one of such features. In the description of the present invention, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0039] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0040] See Figure 1 , which is a structural diagram of the first embodiment of the stacked chip of the present invention. Specifically, the stacked chip includes a first programmable gate array component 1 and a first storage array component 2. In the present application, the first programmable gate array component 1 and the first storage array component 2 are hybrid bonded and integrated by means of three-dimensional heterogeneous integration. Three-dimensional heterogeneous integration is to directly interconnect the internal metal layers of two chip components across the chip. The physical and electrical parameters follow the characteristics of the semiconductor process technology. The interconnection density and speed of three-dimensional heterogeneous integration are greatly improved compared with the interconnection achieved through input and output (I / O) interfaces and / or I / O circuits. The internal interconnection of the stacked chip is thus able to achieve high bandwidth and low power consumption of the stacked chip.

[0041] In one embodiment, the first storage array component 2 may be a DRAM (Dynamic Random Access Memory). In another embodiment, the first storage array component 2 may also be an SRAM (static Random Access Memory). Of course, considering the iterative development of technology, the first storage array component 2 may also be other types of memory or a combination of SRAM and other types of memory, such as flash memory (Flash), resistive RAM (RRAM or ReRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), oxide resistive RAM (OxRAM), bridge RAM (CBRAM), phase change RAM (PCM), spin transfer torque RAM (STT-MRAM), and electrically erasable programmable program memory (EEPROM), etc., without specific limitation. The above memories have their own characteristics and advantages, and may require a storage controller as a storage access interface. The storage controller is used to implement functions such as physical interface, data reading and writing, data buffering, data prefetching, data refresh, and data block remapping, without specific limitation.

[0042] Specifically, such as Figure 1 As shown, the first programmable gate array component 1 includes a first interface module 11, and the first interface module 11 is embedded in the first programmable gate array component 1. Specifically, the first interface module 11 includes a first bonding lead-out area 111. The first storage array component 2 is provided with a second bonding lead-out area 21. The first bonding lead-out area 111 and the second bonding lead-out area 21 are bonded together through a three-dimensional heterogeneous integration bonding structure, thereby realizing the three-dimensional heterogeneous integration of the first programmable gate array component 1 and the first storage array component 2, and thereby realizing a high-bandwidth, low-power programmable static storage and computing integrated structure of stacked chips. The three-dimensional heterogeneous integration bonding can greatly improve the interconnection density between the first programmable gate array component 1 and the first interface module 11, and can further improve the interconnection density between the first programmable gate array component 1 and the first storage array component 2, reduce the interconnection distribution parameters, improve the interconnection bandwidth and reduce the interconnection power consumption.

[0043] Specifically, the first programmable gate array component 1 includes multiple functional modules 13, a first interface module 11 is located between the multiple functional modules 13, and an interface routing unit 137 is provided on the side of the first interface module 11 close to the functional modules 13. The interface routing unit 137 connects the functional modules 13 with the first interface module 11. Specifically, the functional modules 13 are connected to the interface routing unit 137 via an internal metal layer, and the first interface module 11 is connected to the interface routing unit 137 via an internal metal layer. In one specific embodiment, the number of first interface modules 11 is one. In another embodiment, the number of first interface modules 11 is at least two, and at least two first interface modules 11 are interspersed between the multiple functional modules 13 and connected to the functional modules 13 via the interface routing unit 137. Figure 1 In the illustrated embodiment, only one first interface module 11 is shown. In other embodiments, there may be multiple first interface modules 11 . The present application is not limited thereto and the configuration is specific according to the requirements.

[0044] In one embodiment, if Figure 2 As shown, Figure 2 The figure is a schematic diagram of the planar structure of the first programmable gate array component 1. The functional module 13 includes a programmable logic block (Logic Array Block, LAB / Configurable Logic Block, CLB) 133, a memory block (Block Random Access Memory, BRAM) 134, a multiplication unit (Digital Signal Processor) 135, and a multiplication and accumulation unit (Multiply Accumulate, MAC) 138. It should be noted that the multiplication unit 135 is not a digital signal processor chip, but an embedded programmable multiplication unit. In a specific embodiment, the functional module 13 can be configured as required and is not limited to this application.

[0045] In this embodiment, the first bonding lead-out area 111 is the three-dimensional heterogeneous integrated interconnection resource in the first programmable gate array component 1. The first programmable gate array component 1 is directly bonded to the second bonding lead-out area 21 of the first storage array component 2 through the first bonding lead-out area 111, realizing direct interconnection of metal layers with high density and low distribution parameters, realizing storage access, avoiding the use of the first programmable gate array component 1 to be interconnected with the first storage array component 2 through the IO interface and IO interface circuit, thereby achieving the purpose of high bandwidth and low power consumption, and having the advantages of high density and low distribution parameters.

[0046] In one embodiment, the first programmable gate array component 1 further includes: a programmable routing network. Multiple functional modules 13 are interconnected with the programmable routing network through internal metal layers, and are connected to the interface routing unit 137 through the programmable routing network. Specifically, the programmable routing network is used to establish interconnection and data exchange of all resources within the first programmable gate array component 1 using the internal metal layers of the first programmable gate array component 1 in a programmable manner. The functional modules 13 establish a wide range of reconfigurable high-bandwidth data interconnections between modules and between modules and storage devices through the programmable routing network. Figure 2 As shown, the programmable routing network is connected to the storage routing unit 136, and the storage block BRAM 134 is interconnected with the storage routing unit 136 and connected to the programmable storage routing network, enabling all functional modules 13 in the first programmable gate array component 1 to access the storage of all storage block BRAMs 134 through the storage routing unit 136 (existing technology). The programmable routing network is connected to the interface routing unit 137, and the first storage array component 2 is interconnected with the interface routing unit 137 through the first interface module 11 and connected to the programmable storage routing network, enabling all functional modules 13 in the first programmable gate array component 1 to access the storage of all storage arrays on the first storage array component 2 through the interface routing unit 137.

[0047] Specifically, all functional modules 13 on the first programmable gate array assembly 1 are connected to the interface routing unit 137 via a programmable routing network. The interface routing unit 137 is connected to the three-dimensional heterogeneous integrated bonding structure corresponding to the first interface module 11, thereby establishing storage access from the functional modules 13 to all storage arrays on the first storage array assembly 2. Because the programmable routing network is widely distributed on the first programmable gate array assembly 1 and supports programmable features, functional modules 13, whether close to or far from the first interface module 11, can establish high-density intra-chip metal layer interconnections with the interface routing unit 137 through the programmable routing network. The first interface module 11 achieves high-density, low-distribution parameter, cross-chip metal layer direct interconnection with the first storage array assembly 2 via the first bond lead-out region 111 and the second bond lead-out region 21. This avoids the shortcomings of low interconnection density, low interconnection speed, and high interconnection power consumption associated with IO interfaces and IO interface circuits, thereby establishing high-bandwidth and low-power storage access from all functional modules 13 to all storage arrays on the first storage array assembly 2.

[0048] It is understandable that the BRAM memory blocks on the programmable gate array component are connected to the programmable routing network through the storage routing unit, providing high-bandwidth storage resources for the functional modules. However, due to the area constraints of the programmable gate array component, the capacity of the BRAM memory blocks is usually between tens of thousands and millions of memory cells, which cannot meet the needs of conventional applications. In the prior art, large-capacity storage resources are expanded outside the programmable gate array component through the IO of the programmable gate array component and the external memory, and the BRAM memory blocks inside the programmable gate array component are usually used as a cache for external large-capacity storage resources. Due to the interconnection technology for expanding large-capacity storage resources outside the programmable gate array component, the external storage access bandwidth is much lower than the internal one, and the storage access power consumption is greater. Compared with the prior art, the present application has two advantages that overcome the above-mentioned shortcomings: similar to the interconnection and storage access structure between the functional module and the storage block BRAM, the interface routing unit 137 and the first interface module 11 are designed, and all functional modules 13 can establish high-density metal layer interconnection within the chip with the interface routing unit 137 through the programmable routing network, and all functional modules 13 can further be interconnected with the first interface module 11 through the interface routing unit 137. Since the first interface module 11 is connected to the first storage array component 2 through a three-dimensional heterogeneous integration, that is, in fact, in the present application, the first programmable gate array component 1 and the first storage array component 2 establish high-density metal layer interconnection between chips through three-dimensional heterogeneous integration, and the physical and electrical parameters of the interconnection follow the characteristics of the semiconductor process technology, inheriting the high-density and high-speed bandwidth advantages and low power consumption advantages of the interconnection between the storage block BRAM 134 and the functional module 13 through the storage routing unit 136 within the chip of the first programmable gate array component 1, and almost infinitely expanding the storage capacity. Figure 2 As shown in FIG1 , the programmable logic blocks LAB / CLB 133, memory blocks BRAM 134, multiplication units DSP 135, multiplication and accumulation units MAC 138, etc. in the functional module 13 are all arranged in a stripe pattern, and the storage routing unit 136 is arranged in a stripe pattern. The programmable logic blocks LAB / CLB 133, memory blocks BRAM 134, multiplication units DSP 135, multiplication and accumulation units MAC 138, storage routing unit 136, etc. are arranged in the first programmable gate array component 1 as required, as shown in FIG1 . Figure 2The strip-shaped arbitrarily repeated combination is used, and programmable interconnection is established through a programmable routing network. The specific combination method is not limited by this application. In this embodiment, the first interface module 11 is configured to match the shape of the functional module 13 and is also arranged in a strip-shaped layout to be embedded between the functional modules 13. The first interface module 11 is extended and expanded in capacity along the functional module 13 in the strip-shaped length direction based on the size of the functional module 13. In a specific embodiment, the interface routing unit 137 is configured to match the shape of the functional module 13 and is also arranged in a strip-shaped layout to be embedded between the functional modules 13. The interface routing unit 137 is extended in the strip-shaped length direction based on the size of the functional module 13 to support the capacity expansion of the first interface module 11; thereby, a large-capacity storage access interconnection can be formed between the functional module 13 and the first storage array component 2. The interconnection density is much greater than the interconnection with the external large-capacity memory through the internal IO circuit of the FPGA and / or the external IO interface, thereby realizing high-bandwidth and low-power storage access of the stacked chip.

[0049] The stacked chip of this embodiment is designed with an interface routing unit 137, which can significantly increase the bit width of the bus. The interface routing unit 137 is directly connected to the three-dimensional heterogeneous integrated bonding structure and is connected to the first storage array component 2 through the three-dimensional heterogeneous integrated interconnect structure, thereby enabling access to a large-capacity storage array.

[0050] In this embodiment, a first interface module 11 is provided on the first programmable gate array component 1 to implement storage access with the first storage array component 2. This is different from the conventional method in which the first programmable gate array component 1 is connected to a large-capacity external memory through an internal IO circuit and an external IO interface. The stacked chips in this embodiment can save IO resources of the first programmable gate array component 1, provide an external storage interconnection density far higher than that through IO, improve storage access bandwidth, and reduce storage access power consumption.

[0051] In one embodiment, a global bus, such as a NOC AXIAHB, may be provided on the first programmable gate array assembly 1 to enable cross-region memory access for programmable logic on the first programmable gate array assembly 1. Specifically, the global bus may be provided near the first interface module 11, or may be provided at other memory access-related locations, without limitation.

[0052] In one embodiment, if Figure 2As shown, the first programmable gate array assembly 1 may also include an application-specific integrated circuit array unit 139. This unit includes hard-core computation / processing elements (processing elements) implemented using application-specific integrated circuits, such as a multiplication-addition computation array, a multiplication computation array, a systolic processor array, a hash computation array, various encoder arrays, a dedicated layer array for machine learning, a retrieval function array, an image / video processing array, and any combination of these hard-core computation / processing elements, such as CPUs and MCUs. Similar to the layout and interconnection of the functional modules 13 within the first programmable gate array assembly 1, the application-specific integrated circuit array unit 139 is arranged in a stripe pattern within the first programmable gate array assembly 1, embedded between the functional modules 13. Its size and capacity extend along the length of the stripe, expanding with the functional modules 13. It is extensively interconnected on a programmable routing network, serving as a hard-core computation / processing expansion circuit for the functional modules 13. The application-specific integrated circuit array unit 139 has limited or no programmability and is used for computation / processing acceleration for specific needs. Compared to the functional modules 13 with arbitrary programmability, its computation / processing density is significantly higher, significantly increasing the computation / processing density of the stacked chip.

[0053] In one embodiment, when there is a high demand for the dedicated integrated circuit array unit 139 in combination with specific application requirements, the cross-chip expansion of the dedicated integrated circuit array unit 139 is performed in combination with the large-capacity storage cross-chip expansion method of the first storage array component 2 to the first programmable gate array component 1: 1. The dedicated integrated circuit array unit 139 is designed to include hard-core operation / processing units implemented by dedicated integrated circuits, such as a multiplication and addition calculation array, a multiplication calculation array, a systolic processor array, a hash calculation array, a variety of encoder arrays, a dedicated layer array for machine learning, a retrieval function array, an image / video processing array, and one or more arbitrary combinations of hard-core operation / processing units such as CPU and MCU; 2. An operation / processing interface module is designed on the first programmable gate array component 1 to establish high-density cross-chip interconnection with the operation / processing units in the dedicated integrated circuit array unit 139 through three-dimensional heterogeneous integration; 3. An operation / processing interface routing unit is designed on the first programmable gate array component 1 to establish high-density interconnection of the on-chip metal layer between the programmable routing network and the operation / processing interface module. In this way, the functional module 13 on the first programmable gate array component 1 is implemented, and the calculation / processing unit on the integrated circuit array unit 139 is scheduled based on high-density three-dimensional heterogeneous integration. The calculation input and calculation results of the calculation / processing unit are mapped to the large-capacity storage array on the first storage array component 2 through storage access based on high-density three-dimensional heterogeneous integration.

[0054] In one embodiment, the stacked chip further includes a storage control unit 113, which is used to control the storage and access of the first programmable gate array component 1 to the first storage array component 2. Specifically, the storage control unit 113 can be set on the first interface module 11; or near the first interface module 11 on the first programmable gate array component 1; or the storage control unit 113 can be set on the first storage array component 2. The stacked chip of this embodiment can avoid interconnection through physical IO interfaces, thereby saving IO resources, providing an interconnection density far higher than that of IO interfaces, improving storage access bandwidth, and reducing storage access power consumption. It achieves high-density, close-range interconnection from the internal signals of the first programmable gate array component 1 to the first storage array component 2.

[0055] In a preferred embodiment, the storage control unit 113 is located on the first interface module 11. Since the programmable gate array component must access the storage array component through the first interface module 11, this facilitates data flow. In a preferred embodiment, placing the storage control unit 113 on the first programmable gate array component 1 allows for higher density and speed, as the programmable gate array component boasts superior process performance to the storage array component. In a preferred embodiment, placing the storage control unit 113 near the first interface module 11 allows for inheriting the process performance of the programmable gate array component, achieving higher density and speed. This also reduces the area of ​​the interface module 11, reducing the area overhead of the interconnection region for three-dimensional heterogeneous integration. The storage control unit 113 can also be combined with the programmable features of the functional module 13, making some of the functions and / or parameters of the storage control unit 113 programmable. In a preferred embodiment, placing the storage control unit 113 on the storage array component reduces implementation costs and relatively increases the density of the programmable gate array component, as the process for the storage array component is less expensive per unit area than that of the programmable gate array component.

[0056] In one embodiment, the stacked chip further includes a physical layer 114, which is used to implement level conversion of the three-dimensional heterogeneous integrated interconnection between the first programmable gate array component 1 and the first memory array component 2 when the core voltages of the first programmable gate array component 1 and the first memory array component 2 are different. In one embodiment, if Figure 1 As shown, the physical layer 114 can be set on the first interface module 11. In another embodiment, the physical layer 114 can also be designed on the first programmable gate array component 1, usually on or near the first interface module 11, to inherit the process performance of the first programmable gate array component 1 and achieve higher density and speed; the physical layer 114 can be designed on the first storage array component 2, usually on or near the vertical projection area of ​​the first interface module 11, to save the area of ​​the first programmable gate array component 1 and improve the computing / processing density of the first programmable gate array component 1.

[0057] In the present application, the physical and electrical parameters of the cross-chip three-dimensional heterogeneous integrated interconnection between the first programmable gate array component 1 and the first storage array component 2 follow the characteristics of the semiconductor process technology. Compared with traditional PCB or 2.5D packaging, the number of interconnections (storage access bandwidth) between the first programmable gate array component 1 and the first storage array component 2 is increased by 4 to 2 orders of magnitude. Compared with traditional PCB or 2.5D packaging, the first programmable gate array component 1 and the first storage array component 2 are directly interconnected without passing through the IO interface and / or IO circuit, making the interconnection distance closer, the interconnection distribution parameters lower (especially the distributed capacitance of the interconnection line to the reference ground is lower), and the power consumption overhead of storage access is significantly reduced. A near-memory storage access architecture is formed between the first programmable gate array component 1 and the first storage array component 2, enabling the functional module 13 on the first programmable gate array component 1 to access the nearest storage, avoiding the storage access conflict and efficiency reduction of the traditional shared bus; saving the IO overhead used in traditional technology for interconnecting the first programmable gate array component 1 with external large-capacity storage devices.

[0058] In one embodiment of the present application, Figure 3 The following example illustrates a storage control unit disposed on the first interface module. Specifically, the storage control unit H21 is disposed on the first interface module H17. The first storage array assembly 2 includes a storage cell G13. The second lead-out bonding area G14 is disposed on the storage cell G13. The storage control unit H21 is connected to the first lead-out bonding area H19. The first lead-out bonding area H19 is connected to the second lead-out bonding area G14 on the first storage array assembly 2.

[0059] Furthermore, the first programmable gate array component 1 is provided with a programmable logic unit K23, which is connected to the storage control unit H21 via the interface routing unit H22. The programmable logic unit K23 outputs logic signals, and the storage control unit H21 controls the first programmable gate array component 1 to access the first storage array component 2 based on the logic signals.

[0060] In this application, the number and position of the first programmable gate array component 1 and the first storage array component 2 can be set according to requirements, such as Figure 4 As shown, Figure 4 FIG. 1 is a schematic structural diagram of a second embodiment of the stacked chip of the present invention. Figure 1Compared to the first embodiment shown, the stacked chip of this embodiment differs in that it further includes a second programmable gate array component 3. The second programmable gate array component 3 is disposed on a side of the first programmable gate array component 1 away from the first storage array component 2. Specifically, the second programmable gate array component 3 includes a second interface module 31, and the second interface module 31 includes a third bond lead-out region 32. In this embodiment, the first interface module 11 further includes a fourth bond lead-out region 12, and the third bond lead-out region 32 is bonded to the fourth bond lead-out region 12 to bond the second programmable gate array component 3 to the second programmable gate array component 1.

[0061] The stacked chip of this embodiment is provided with two layers of programmable gate array components, namely, a second programmable gate array component 3 and a first programmable gate array component 1, and the second programmable gate array component 3 and the first programmable gate array component 1 are bonded to each other via a third bond lead-out region 32 and a fourth bond lead-out region 12. In this embodiment, the third bond lead-out region 32 is the three-dimensional heterogeneous interconnection resource of the second programmable gate array component 3, that is, the second programmable gate array component 3 is directly connected to the first interface module 11 via the interconnection resource, and then interconnected with the first storage array component 2 via the interconnection resource (first bond lead-out region 111) in the first programmable gate array component 1 to achieve storage access, avoiding the use of the IO interface of the second programmable gate array component 3 to interconnect with the first storage array component 2, thereby achieving the purpose of high bandwidth and low power consumption, and having the advantages of high programmable resource density, low distribution parameter, and fast storage access speed.

[0062] In a stacked chip, adjacent components are interconnected through three-dimensional heterogeneous integration, establishing high-density metal layer interconnections within the chip layer by layer. The components of the stacked chip are designed and packaged in a single stacked chip, eliminating the need for existing I / O circuits, such as driver, external voltage boost (for output), external voltage step-down (for input), tri-state controller, ESD protection, and surge protection circuits. Instead of interconnecting through existing I / O interfaces and / or I / O circuits, high-density metal layer interconnections are directly established across the components. This reduces the use of I / O structures in programmable gate array components, increasing the interconnection density and speed between programmable gate array components and memory array components. Furthermore, because the three-dimensional heterogeneous integration interconnection avoids traditional I / O structures and has shorter interconnection distances, it reduces inter-chip communication power consumption. This in turn increases the integration density of the stacked chip and the interconnection frequency between programmable gate array components and memory array components, while reducing interconnection power consumption. Consequently, the programmable routing network that extensively interconnects programmable resources on the programmable gate array components extends across the chip to the large-capacity memory array on the memory chip, forming extensive interconnections that enable high-bandwidth, programmable access to the large-capacity memory array on the memory chip through the three-dimensional heterogeneous integration. The multi-layer chip combines the large capacity of external memory with the key advantages of large bit width and high bandwidth, similar to the existing PGA components, which interconnect memory blocks through a programmable routing network (BRAM, which has a smaller capacity). This fundamentally overcomes the bottlenecks of I / O number, memory bandwidth, and memory power consumption that currently limit the expansion of large-scale memory using PGA chips.

[0063] Relative to Figure 1 In the first embodiment shown, the stacked chip of this embodiment can further improve computing density, facilitating more complex reconfigurable computing. In combination with the stacked chip of this embodiment, more programmable gate array components can be provided as needed to increase the density of the programmable gate array components in the stacked chip.

[0064] It should be noted that the second programmable gate array component 3 may also be different from the first programmable gate array component 1, and may be provided with different functional modules according to actual needs. For example, in one embodiment, the functional modules of the first programmable gate array component 1 include programmable functional modules, which include but are not limited to any combination of programmable logic blocks LAB / CLB, memory blocks BRAM, multiplication units DSP, and multiplication-accumulation units MAC; the functional modules of the second programmable gate array component 3 may partially or entirely include application-specific integrated circuit array units, which include but are not limited to multiplication-addition calculation arrays, multiplication calculation arrays, systolic processor arrays, hash calculation arrays, various encoder arrays, dedicated layer arrays for machine learning, retrieval function arrays, image / video processing arrays, and any combination of one or more hard-core computing / processing units such as CPUs and MCUs.

[0065] In this embodiment, the first programmable gate array assembly 1 and the second programmable gate array assembly 3 share the same storage control unit 113 to access the same storage unit of the first storage array assembly 2. Specifically, in this embodiment, the storage control unit 113 can be disposed on or near the first interface module 11; the storage control unit 113 can also be disposed on or near the second interface module 31; or the storage control unit 113 can also be disposed on the first storage array assembly 2.

[0066] Specifically, in one embodiment, the first programmable gate array component 1 further includes a first programmable logic unit, which is connected to the storage control unit 113 and outputs a first logic signal. The second programmable gate array component 3 further includes a second programmable logic unit, which is connected to the storage control unit 113 and outputs a second logic signal. The storage control unit 113 selects the first programmable gate array component 1 to access the first storage array component 2 or the second programmable gate array component 3 to access the first storage array component 2 based on the first logic signal and the second logic signal.

[0067] Specifically, such as Figure 5 As shown, the storage control unit H21 is provided on the first interface module H17 as an example for explanation. The first storage array component 2 includes a storage cell G13, a second bond lead-out region G14 is provided on the storage cell G13, and a first bond lead-out region H19 is provided on the first interface module H17, with the first bond lead-out region H19 being bonded to the second bond lead-out region G14. The storage control unit H21 is provided on the first interface module H17, and is connected to the first bond lead-out region H19. The first interface module H17 is also provided with a fourth bond lead-out region H24, which is connected to the storage control unit H21. The second interface module I27 is provided with a third bond lead-out region I28, which is connected to the fourth bond lead-out region H24. Furthermore, in this embodiment, the first programmable gate array component 1 also includes a first programmable logic unit H23, which is connected to the storage control unit H21. The second programmable gate array component 321 also includes a second programmable logic unit 132, and the second programmable logic unit 132 is connected to the third bonding lead-out region 128.

[0068] For example, in one embodiment, when the first programmable gate array component 1 needs to access the first storage array component 2, the first programmable logic unit H23 outputs a first logic signal to the storage control unit H21. At this time, the storage control unit H21 controls the first programmable gate array component 1 to access the storage cell G13 on the first storage array component 2 via the first bond lead-out region H19 and the second bond lead-out region G14 based on the first logic signal. When the second programmable gate array component 3 needs to access the first storage array component 2, the second programmable logic unit I32 outputs a second logic signal to the storage control unit H21. At this time, the storage control unit H21 controls the second programmable gate array component 3 to access the storage cell G13 on the first storage array component 2 via the third bond lead-out region I28 and the fourth bond lead-out region H24 based on the second logic signal. In this way, the storage control unit selects whether the first programmable gate array component 1 accesses the first storage array component 2 or the second programmable gate array component 3 accesses the first storage array component 2 based on the first logic signal and the second logic signal.

[0069] In this embodiment, only one storage control unit H21 is designed. The storage control unit H21 can be located on or near the first interface module H17, on or near the second interface module I27, or on the first storage array assembly 2. The specific details are not limited. The storage units G13 on the first storage array assembly 2 are all connected to the storage control unit H21 through the second bond lead area G14 and the first bond lead area H19. The storage control unit H21 can directly connect to two groups of storage access interfaces (for example, Figure 5 H19, H24), multiple groups of programmable gate array components share storage access to storage unit G13 through this interface.

[0070] In one embodiment, the first programmable logic unit H23 and the second programmable logic unit I32 include any combination of programmable logic blocks, storage blocks, multiplication units, multiplication-accumulation units, and hard-core operation / processing units. The first programmable logic unit H23 outputs a first logic signal, and the second programmable logic unit I32 outputs a second logic signal. Based on the first logic signal and the second logic signal, the storage control unit H21 switches the storage access interface of the storage control unit H21 to the direction of bonding between the first bond lead-out region H19 and the second bond lead-out region G14, or to the direction of bonding between the fourth bond lead-out region H24 and the third bond lead-out region I28. The first programmable logic unit H23 and the second programmable logic unit I32 use the memory in a time-sharing manner, thereby achieving shared memory access.

[0071] It should be noted that, in this embodiment, the third bond-out region I28 is connected to the interface routing unit I30, and the interface routing unit I30 connects the second programmable logic unit I32 to the fourth bond-out region H24.

[0072] In this embodiment, a shared storage control unit H21 is used, which occupies a small area.

[0073] In another embodiment, the first programmable gate array component 1 and the second programmable gate array component 3 each use an independent storage control unit to access different storage cells of the first storage array component 2. Specifically, the stacked chip includes a first storage control unit and a second storage control unit. The first programmable gate array component 1 uses the first storage control unit to access the storage cells of the first storage array component 2, and the second programmable gate array component 3 uses the second storage control unit to access the storage cells of the first storage array component 2.

[0074] In this embodiment, the second storage control unit is disposed on or near the second interface module 31, and the first storage control unit is disposed on or near the first interface module 11. In this embodiment, the first programmable gate array component 1 further includes: a first programmable logic unit, which is connected to the first storage control unit and outputs a first logic signal; the second programmable gate array component 3 further includes: a second programmable logic unit, which is connected to the second storage control unit and outputs a second logic signal.

[0075] In response to the first storage control unit and the second storage control unit both controlling all storage cells of the first storage array component 2, and the first programmable gate array component 1 and the second programmable gate array component 3 simultaneously accessing the same storage cell, the first storage control unit controls the first programmable gate array component 1 to access the storage cell at a first time based on a first logic signal; and the second storage control unit controls the second programmable gate array component 3 to access the storage cell at a second time based on a second logic signal. In response to the first storage control unit and the second storage control unit respectively controlling different storage cells of the first storage array component, the first storage control unit and the second storage control unit simultaneously control the first programmable gate array component 1 and the second programmable gate array component 3 to access different storage cells of the first storage array component 2.

[0076] Specifically, in this embodiment, if the first storage control unit and the second storage control unit both control all storage cells of the first storage array component 2, and if the first programmable gate array component 1 and the second programmable gate array component 3 simultaneously access the same storage cell, the first storage control unit and the second storage control unit respectively control the first programmable gate array component 1 and the second programmable gate array component 3 to access the storage cell. Specifically, the first storage control unit controls the first programmable gate array component 1 to access the storage cell at a first time based on a first logic signal, and the second storage control unit controls the second programmable gate array component 3 to access the storage cell at a second time based on a second logic signal, thereby achieving time-sharing access to the same storage cell by different programmable gate arrays, i.e., eliminating access conflicts.

[0077] Specifically, the first programmable gate array component 1 may include arbitration logic for storage cells that selects access by the first storage control unit or the second storage control unit based on a first logic signal and a second logic signal. When the first storage control unit of the first programmable gate array component 1 and the second storage control unit of the second programmable gate array component 3 simultaneously access the same region of the same storage cell of the first storage array component 2, the arbitration logic for the storage cells in the first programmable gate array component 1 establishes time-sharing access by the first storage control unit of the first programmable gate array component 1 or the second storage control unit of the second programmable gate array component 3 based on the first logic signal and the second logic signal. The arbitration logic for the storage cells in the first programmable gate array component 1 may also be provided on the first storage array component 2 or the second programmable gate array component 3. That is, based on the arbitration logic, the first programmable gate array component 1 and the second programmable gate array component 3 are selected to access the first storage array component 2 in a time-sharing manner.

[0078] In another embodiment, when the first storage control unit and the second storage control unit respectively control different storage units of the first storage array component, the first storage control unit and the second storage control unit simultaneously control the first programmable gate array component 1 and the second programmable gate array component 3 to access different storage units of the first storage array component 2.

[0079] Specifically, when the first storage control unit of the first programmable gate array component 1 and the second storage control unit of the second programmable gate array component 3 respectively access different storage units of the first storage array component 2 at the same time, since each storage control unit is independent, the arbitration logic in the storage unit in the first programmable gate array component 1 can simultaneously establish access of the first storage control unit of the first programmable gate array component 1 and the second storage control unit of the second programmable gate array component 3 to the storage unit of the first storage array component 2 based on the first logic signal and the second logic signal.

[0080] In this embodiment, each logical component has an independent storage access interface, providing the highest memory access bandwidth. While accessing different specific units of the storage array, simultaneous access is possible. Writing to the shared area of ​​the storage array, when the specific units are the same, can result in conflicts, requiring arbitration and time-sharing access. Specifically, when both the first storage control unit and the second storage control unit control all storage units of the first storage array assembly 2, simultaneous access to the same storage unit requires time-sharing access. When the first and second storage control units control different storage units, time-sharing access is not required.

[0081] In this embodiment, the second storage control unit is disposed on or near the second interface module 31, and the first storage control unit is disposed on or near the first interface module 11. In this embodiment, the first storage control unit controls the first programmable gate array component 1 to access some storage cells of the first storage array component 2 based on a first logic signal; the second storage control unit controls the second programmable gate array component 3 to access the remaining storage cells of the first storage array component 2 based on a second logic signal; the storage cells accessed by the second programmable gate array component 1 in the first storage array component 2 do not overlap with the access area of ​​the first programmable gate array component 3. The first programmable logic unit utilizes the first storage control unit, and the second programmable logic unit utilizes the second storage control unit to independently and simultaneously access different storage cells on their respective first storage array components 2.

[0082] In this embodiment, each logic component has an independent storage access interface with the highest memory access bandwidth, and the access is divided into the first storage array component 2 to different programmable logic units using a storage control unit combination; concurrent storage access to different programmable logic units is achieved without reducing storage access efficiency due to arbitration and time-sharing access.

[0083] For details, see Figure 6The first storage array component 2 includes a storage unit G13, wherein the storage unit G13 is provided with two second bond lead-out regions, namely the second bond lead-out region G14 and the second bond lead-out region G12. The second bond lead-out region G14 is connected to the first bond lead-out region H19 on the first interface module H17 located on the first programmable gate array component 1. The first interface module H17 of the first programmable gate array component 1 is provided with a first storage control unit H20, and the first storage control unit H20 is used to control the first programmable gate array component 1 to access the first storage array component 2. Specifically, the first storage control unit H20 is connected to the first bond lead-out region H19. The first programmable gate array component 1 is provided with a first programmable logic unit H23, and the first programmable logic unit H23 is connected to the first storage control unit H20 through the interface routing unit H22. When the first programmable gate array component 1 accesses the first storage array component 2, the first programmable logic unit H23 leads to the first logic signal to the first storage control unit H20. The first storage control unit H20 controls the first programmable gate array component 1 to access part of the storage unit G13 of the first storage array component 2 through the first bonding lead-out area H19 and the second bonding lead-out area G14 based on the first logic signal.

[0084] In addition, the second bond lead-out region G12 is connected to the first bond lead-out region H18 on the first interface module H17, and the first bond lead-out region H18 is connected to the third bond lead-out region I28 on the second programmable gate array component 3. The second programmable gate array component 3 also includes a second programmable logic unit I32, which is connected to the second storage control unit I29 located on the second interface module I27 of the second programmable gate array component 3 via the interface routing unit I31. When the second programmable gate array component 3 accesses the first storage array component 2, the second programmable logic unit I32 outputs a second logic signal to the second storage control unit I29. Based on the second logic signal, the second storage control unit I29 controls the second programmable gate array component 3 to access the remaining storage cells G13 of the first storage array component 2 via the third bond lead-out region I28, the first bond lead-out region H18, and the second bond lead-out region G14.

[0085] pass Figure 6 The connection mode shown enables the first programmable gate array component 1 and the second programmable gate array component 3 to independently access the first storage array component 2. It is understandable that the programmable gate array component can also be 3-layer or 4-layer without specific limitation.

[0086] It should be noted that the first programmable gate array component 1 and the second programmable gate array component 3 of the present application can be an FPGA (field programmable gate array) or an eFPGA (non-volatile field programmable gate array). In a preferred embodiment, the first programmable gate array component 1 and the second programmable gate array component 3 are FPGAs (field programmable gate arrays) or eFPGAs (embedded field programmable gate arrays).

[0087] In the stacked chip of this embodiment, the second programmable gate array component 3 does not access the storage of the first storage array component 2 through the IO interface and / or IO circuit, which makes the interconnection distance closer, the interconnection distribution parameter lower, and the power consumption of storage access significantly reduced. During the chip manufacturing process, the second programmable gate array component 3 and the first programmable gate array component 1 can be produced simultaneously, and the second programmable gate array component 3 can be bonded to the first programmable gate array component 1 and then to the first storage array component 2, which can reduce process complexity and save costs. However, the second programmable gate array component 3 needs to access the storage of the first storage array component 2 through the first interface module 11 and the second interface module 31, which will cause a slight area loss.

[0088] The present application also proposes another embodiment, in which multiple programmable gate array components are used in combination with at least one storage array component. Figure 5 and Figure 6 The method designs reused or independent storage control units to achieve hybrid storage access. In the same stacked chip, the programmable logic units in some areas use Figure 5 The multiplexed storage control unit shown in the figure realizes storage access; the programmable logic unit in some areas uses Figure 6 The independent storage control unit is shown.

[0089] The present application also proposes another embodiment, in which the second programmable gate array component 3 is arranged on a side of the first storage array component 2 away from the first programmable gate array component 1. That is, the first storage array component 2 is arranged between the second programmable gate array component 3 and the first programmable gate array component 1. Among them, the first storage array component 2 includes a fourth bonding lead-out area, and the fourth bonding lead-out area and the third bonding lead-out area constitute a three-dimensional heterogeneous integrated interconnection. In this embodiment, the second programmable gate array component 3 and the first programmable gate array component 1 can both achieve direct interconnection with the first storage array component 2, increase programmable processing density, and facilitate greater storage access bandwidth.

[0090] In this embodiment, the first programmable gate array component 1 only needs to access the storage of the first storage array component 2 through the first interface module 11, and the second programmable gate array component 3 only needs to access the storage of the first storage array component 2 through the second interface module 31. This structure shortens the interconnection distance between the second programmable gate array component 3 and the first storage array component 2, further reducing the power consumption of storage access. However, during the preparation process of stacked chips with this structure, the second programmable gate array component 3 must first be bonded to the first storage array component 2, and then to the first programmable gate array component 1.

[0091] See Figure 7 , is a schematic structural diagram of a third embodiment of the stacked chip of the present invention, which is similar to the above Figure 1 Compared to the first embodiment shown, the stacked chip in this embodiment further comprises a second memory array assembly 4. The second memory array assembly 4 is disposed on a side of the first memory array assembly 2 that is away from the first programmable gate array assembly 1. The second memory array assembly 4 is provided with a third bond lead-out region 41. In this embodiment, the first memory array assembly 2 further comprises a fourth bond lead-out region 12. The third bond lead-out region 41 and the fourth bond lead-out region 12 form a three-dimensional heterogeneous integrated interconnect.

[0092] In this embodiment, integrating more storage array components helps increase storage density and achieve greater storage access bandwidth. In this embodiment, integrating more storage array components helps increase storage density. After multiple storage array components are uniformly manufactured and tested to form a standard product, they are then integrated with logic components, which helps reduce costs.

[0093] In one embodiment, the first programmable gate array component 1 shares the same storage control unit to access the first storage array component 2 and the second storage array component 4. Specifically, when the first programmable gate array component 1 shares the same storage control unit to access the first storage array component 2 and the second storage array component 4, to avoid access conflicts, the storage control unit can selectively select the first programmable gate array component 1 to access the first storage array component 2 or the second storage array component 4 in a time-sharing manner.

[0094] Please refer to 8 for details. In this embodiment, the stacked chip also includes a storage control unit H21, which is provided on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond lead-out areas, namely the first bond lead-out area H19 and the first bond lead-out area H18. The first storage array component 2 is provided with a plurality of storage cells G13, and the storage cells G13 have two second bond lead-out areas, namely the second bond lead-out area G12 and the second bond lead-out area G14. The second storage array component 4 is provided with a plurality of storage cells F01, and the storage cells F01 are provided with a third bond lead-out area I28.

[0095] Specifically, the first lead-out bonding region H18 is connected to the second lead-out bonding region G14. The storage control unit H21 is connected to the first lead-out bonding region H18. Thus, the storage control unit H21 can control the first programmable gate array component 1 to access the first memory array component 2 through the first lead-out bonding region H18 and the second lead-out bonding region G14.

[0096] The first lead-out bond region H19 is connected to the second lead-out bond region G12, and the second lead-out bond region G12 is connected to the third lead-out bond region I28. Thus, the storage control unit H21 can control the first programmable gate array component 1 to access the second memory array component 4 through the first lead-out bond region H19, the second lead-out bond region G12, and the third lead-out bond region I28. It should be noted that the second lead-out bond region G12 is not connected to the memory cell G13.

[0097] In this embodiment, the first programmable gate array component 1 further includes a programmable logic unit K23, which is connected to the storage control unit H21 via the interface routing unit H22. The programmable logic unit K23 outputs logic signals. The storage control unit H21 selectively controls the first programmable gate array component 1 to access the first storage array component 2 or the second storage array component 4 based on the logic signals in a time-sharing manner. Specifically, the storage control unit H21 controls the first programmable gate array component 1 to access the first storage array component 2 at a first time, and controls the first programmable gate array component 1 to access the second storage array component 4 at a second time based on the logic signals.

[0098] In one embodiment, the first programmable gate array component 1 uses two different storage control units to access the first storage array component 2 and the second storage array component 4. Specifically, when the first programmable gate array component 1 uses two different storage control units to access the first storage array component 2 and the second storage array component 4, since there is no access conflict, the storage control units can simultaneously control the first programmable gate array component 1 to access the first storage array component 2 and control the first programmable gate array component 1 to access the second storage array component 4. Specifically, the first storage control unit controls the first programmable gate array component 1 to access the first storage array component 2, and the second storage control unit controls the first programmable gate array component 1 to access the second storage array component 4.

[0099] For details, please see Figure 9 In this embodiment, the stacked chip further includes a first storage control unit H20 and a second storage control unit I29, which are disposed on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond lead-out regions, namely, a first bond lead-out region H19 and a first bond lead-out region H18. A plurality of storage cells G13 are disposed on the first storage array component 2, and the storage cells G13 have two second bond lead-out regions, namely, a second bond lead-out region G12 and a second bond lead-out region G14. A plurality of storage cells F01 are disposed on the second storage array component 4, and a third bond lead-out region I28 is disposed on the storage cells F01.

[0100] In this embodiment, the first storage control unit H20 is connected to the first lead-out bond region H18, which is in turn connected to the second lead-out bond region G14. Thus, the first storage control unit H18 can control the first programmable gate array component 1 to access the first storage array component 2 via the first lead-out bond region H18 and the second lead-out bond region G14.

[0101] Furthermore, the second storage control unit 129 is connected to the first lead-out bond region H19, which is connected to the second lead-out bond region G12, which is connected to the third lead-out bond region 128. Thus, the second storage control unit 129 can control the first programmable gate array component 1 to access the second storage array component 4 via the first lead-out bond region H19, the second lead-out bond region G12, and the third lead-out bond region 128. It should be noted that the second lead-out bond region G12 is not connected to the storage unit G13.

[0102] In this embodiment, the first programmable gate array component 1 further includes a programmable logic unit K23, which is connected to the first storage control unit H20 and the second storage control unit I29. The programmable logic unit K23 outputs logic signals. Specifically, the programmable logic unit K23 is connected to the first storage control unit H20 and the second storage control unit I29 via the interface routing unit H22. In this embodiment, the first storage control unit H20 controls the first programmable gate array component 1 to access the first storage array component 2 based on logic signals, and the second storage control unit I29 controls the first programmable gate array component 1 to access the second storage array component 4 based on logic signals.

[0103] The present application also proposes another embodiment, in which multiple storage array components are used in combination with at least one programmable gate array component. Figure 8 and Figure 9 The method designs reused or independent storage control units to achieve hybrid storage access. In the same stacked chip, the programmable logic units in some areas use Figure 8 The multiplexed storage control unit shown in the figure realizes storage access; the programmable logic unit in some areas uses Figure 9 The independent storage control unit shown implements storage access.

[0104] In another embodiment, if Figure 10 As shown, the second memory array assembly 4 can also be arranged on a side of the first programmable gate array assembly 1 away from the first memory array assembly 2. In this embodiment, the first interface module 11 further includes a fourth bond lead-out region 12, and the third bond lead-out region 41 and the fourth bond lead-out region 12 form a three-dimensional heterogeneous integrated interconnection.

[0105] In this embodiment, integrating more memory array components helps increase storage density. Furthermore, because the first memory array component 2 and the second memory array component 4 are directly connected to the first programmable gate array component 1, the complexity of three-dimensional heterogeneous integration is reduced, the interconnection distance is shortened, the storage access distance is shortened, the distribution parameter is small, and the storage access frequency and power consumption are optimized.

[0106] In one embodiment, the first programmable gate array component 1 shares the same storage control unit to access the first storage array component 2 and the second storage array component 4. Specifically, when the first programmable gate array component 1 shares the same storage control unit to access the first storage array component 2 and the second storage array component 4, to avoid access conflicts, the storage control unit can selectively select the first programmable gate array component 1 to access the first storage array component 2 or the second storage array component 4 in a time-sharing manner.

[0107] Please refer to 11 for details. In this embodiment, the stacked chip also includes a storage control unit H21, which is provided on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond lead-out areas, namely the first bond lead-out area H19 and the first bond lead-out area H18. A plurality of storage cells G13 are provided on the first storage array component 2, and a second bond lead-out area G14 is provided on the storage cell G13. A plurality of storage cells F01 are provided on the second storage array component 4, and a third bond lead-out area I28 is provided on the storage cell F01.

[0108] Specifically, the first lead-out bonding region H18 is connected to the second lead-out bonding region G14. The storage control unit H21 is connected to the first lead-out bonding region H18. Thus, the storage control unit H21 can control the first programmable gate array component 1 to access the first memory array component 2 through the first lead-out bonding region H18 and the second lead-out bonding region G14.

[0109] The storage control unit H21 can control the first programmable gate array component 1 to access the second storage array component 4 through the first bonding lead-out region H19, which is connected to the third bonding lead-out region I28.

[0110] In this embodiment, the first programmable gate array component 1 further includes a programmable logic unit K23, which is connected to the storage control unit H21 via the interface routing unit H22. The programmable logic unit K23 outputs a logic signal. The storage control unit H21 selectively controls the first programmable gate array component 1 to access the first storage array component 2 or the second storage array component 4 based on the logic signal in a time-sharing manner. Specifically, the storage control unit H21 controls the first programmable gate array component 1 to access the first storage array component 2 at a first time, and controls the first programmable gate array component 1 to access the second storage array component 4 at a second time based on the logic signal.

[0111] In one embodiment, the first programmable gate array component 1 uses two different storage control units to access the first storage array component 2 and the second storage array component 4. Specifically, when the first programmable gate array component 1 uses two different storage control units to access the first storage array component 2 and the second storage array component 4, since there is no access conflict, the storage control units can simultaneously control the first programmable gate array component 1 to access the first storage array component 2 and control the first programmable gate array component 1 to access the second storage array component 4. Specifically, the first storage control unit controls the first programmable gate array component 1 to access the first storage array component 2, and the second storage control unit controls the first programmable gate array component 1 to access the second storage array component 4.

[0112] For details, please see Figure 12 In this embodiment, the stacked chip further includes a first storage control unit H20 and a second storage control unit I29, which are disposed on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond lead-out regions, namely, a first bond lead-out region H19 and a first bond lead-out region H18. A plurality of storage cells G13 are disposed on the first storage array assembly 2, and a second bond lead-out region G14 is disposed on the storage cells G13. A plurality of storage cells F01 are disposed on the second storage array assembly 4, and a third bond lead-out region I28 is disposed on the storage cells F01.

[0113] In this embodiment, the first storage control unit H20 is connected to the first lead-out bond region H18, which is in turn connected to the second lead-out bond region G14. Thus, the first storage control unit H18 can control the first programmable gate array component 1 to access the first storage array component 2 via the first lead-out bond region H18 and the second lead-out bond region G14.

[0114] Furthermore, the second storage control unit 129 is connected to the first bond lead-out region H19, which is in turn connected to the third bond lead-out region 128. Thus, the second storage control unit 129 can control the first programmable gate array component 1 to access the second storage array component 4 via the first bond lead-out region H19 and the third bond lead-out region 128.

[0115] In this embodiment, the first programmable gate array component 1 further includes a programmable logic unit K23, which is connected to the first storage control unit H20 and the second storage control unit I29. The programmable logic unit K23 outputs logic signals. Specifically, the programmable logic unit K23 is connected to the first storage control unit H20 and the second storage control unit I29 via the interface routing unit H22. In this embodiment, the first storage control unit H20 controls the first programmable gate array component 1 to access the first storage array component 2 based on logic signals, and the second storage control unit I29 controls the first programmable gate array component 1 to access the second storage array component 4 based on logic signals.

[0116] The present application also proposes another embodiment, in which multiple storage array components are used in combination with at least one programmable gate array component. Figure 11 and Figure 12 The method designs reused or independent storage control units to achieve hybrid storage access. In the same stacked chip, the programmable logic units in some areas use Figure 11 The multiplexed storage control unit shown in the figure realizes storage access; the programmable logic unit in some areas uses Figure 12 The independent storage control unit shown implements storage access.

[0117] In the present application, the storage array component can be a multi-layer chip, which is combined through three-dimensional heterogeneous integration bonding; the dedicated integrated circuit array component can be set up with a multiplication and addition calculation array, a multiplication calculation array, a pulsation processor array, a hash calculation array, a variety of encoder arrays, a dedicated layer array for machine learning, a retrieval function array, an image / video processing array, and one or more arbitrary combinations of hard-core calculation / processing units such as CPU and MCU, which are used in combination with the programming gate array component to improve the processing density of the stacked chip.

[0118] Specifically, the component can be at least one of a die or chip or a wafer, but is not limited thereto and can also be any alternative that can be conceived by those skilled in the art. A wafer refers to a silicon wafer used to manufacture silicon semiconductor circuits, and a chip or die refers to a silicon wafer obtained by dividing the wafer on which the semiconductor circuits are manufactured. For example, the memory array component of the present application can be a memory array die (DRAM die or DRAM chip) or a memory array wafer (DRAM wafer).

[0119] Based on the same inventive concept as the method, an embodiment of the present invention also provides a three-dimensional heterogeneously integrated stacked chip structure. The stacked chip is provided with hierarchical stacked components, which are interconnected through three-dimensional heterogeneous integration. These components can be any of the components mentioned above. When preparing the stacked chip, it is also possible to directly prepare it on a wafer basis and perform three-dimensional heterogeneous integration.

[0120] When preparing stacked chips, it is also possible to prepare part of them in wafer units and perform three-dimensional heterogeneous integration. There are two specific methods: first perform three-dimensional heterogeneous integration on some wafer layers to form an intermediate product, and then iterate the remaining wafer layers and the intermediate product until the preparation is completed; or first perform three-dimensional heterogeneous integration on some wafer layers to form an intermediate product, and then cut the intermediate product into die, and perform die-to-die three-dimensional heterogeneous integration with the die of other components to complete the preparation.

[0121] Specifically, Figure 4 There are two methods for preparing the stacked chip composed of the multi-layer programmable gate array component and at least one layer of storage array component: performing three-dimensional heterogeneous integration of the multi-layer programmable gate array component on a wafer basis to form an intermediate product to improve the interconnection density, and then performing three-dimensional heterogeneous integration of the intermediate product with the intermediate product formed by at least one layer of storage array component to obtain a stacked chip; or performing three-dimensional heterogeneous integration of the multi-layer programmable gate array component on a wafer basis to form an intermediate product, cutting the intermediate product into grains and testing it, and then performing grain-to-grain integration with the cut and tested intermediate product formed by at least one layer of storage array component to obtain a stacked chip. Because the finished product comes from the three-dimensional heterogeneous integration of the cut and tested components, the yield is significantly improved.

[0122] Likewise, Figure 7 There are two methods for preparing the stacked chip composed of the multi-layer storage array component and at least one layer of programmable gate array component: performing three-dimensional heterogeneous integration of the multi-layer storage array component on a wafer basis to form an intermediate product to improve the interconnection density, and then performing three-dimensional heterogeneous integration of the intermediate product with the intermediate product formed by at least one layer of programmable gate array component to obtain a stacked chip; or performing three-dimensional heterogeneous integration of the multi-layer storage array component on a wafer basis to form an intermediate product, cutting the intermediate product into grains and testing it, and then performing grain-to-grain integration with the cut and tested intermediate product formed by at least one layer of programmable gate array component to obtain a stacked chip. Because the finished product comes from the three-dimensional heterogeneous integration of the cut and tested components, the yield is significantly improved.

[0123] The number and order of layers in the stacked chip's programmable gate array and memory array components depend on the application scenario, engineering requirements, and a complex trade-off between production cost and yield, resulting in no single optimal solution. Different target products with varying numbers and orders of layers require diverse manufacturing processes, and significantly different design and reuse requirements for the memory controller.

[0124] In a programmable gate array component, the extensive interconnection of programmable functional blocks with a programmable routing network, see Figure 13 The programmable gate array component is based on the extension of the field-programmable gate array (FPGA / Embedded Field-Programmable Gate Array, eFPGA) technology. The programmable gate array component includes programmable logic blocks 11A and a programmable routing network 11B (interconnect); the programmable logic blocks 11A are interconnected with each other through the routing network 11B and configured as several programmable functional modules, and at least a part of the programmable routing network 11B can be extended to an interface routing unit, and then through three-dimensional heterogeneous integration, a large-capacity storage array is interconnected across levels to form a large-capacity, high-bandwidth, programmable storage access.

[0125] 3D heterogeneous integration is a technology for interconnecting and bonding stacked chips, such as hybrid bonding processes. By utilizing a 3D heterogeneous integration bonding layer fabricated in the back-end-of-line (BEOL) process on top of pre-fabricated chips (such as programmable gate arrays or memory arrays), high-density signal interconnection between chips is achieved, resulting in a stacked chip.

[0126] Specifically Figure 14 Take this as an example. Figure 14In the stacked chip, functional components 210, 220, and 230 are included. Functional components 210, 220, and 230 can be programmable gate array components and / or memory array components. Functional components 210, 220, and 230 each include a top metal layer, an internal metal layer, an active layer, and a substrate. The top metal layer and the internal metal layer are used for signal interconnection within the component; the active layer is used to implement transistors and form module functions; and the substrate is used to protect the module and provide mechanical support. A three-dimensional heterogeneous integration bonding layer is fabricated on the side of functional components 210 and 220 near the top metal layer through a back-end process and interconnected to form a face-to-face interconnect structure. A three-dimensional heterogeneous integration bonding layer is fabricated on the side of functional component 220 near the substrate and on the side of functional component 230 near the top metal layer through a back-end process and interconnected to form a back-to-face (or face-to-back) interconnect structure. Cross-component signal interconnection can be established between functional components 210, 220, and 230 through three-dimensional heterogeneous integration. Whether the core voltages of the functional component 210 , the functional component 220 and the functional component 230 are the same corresponds to two interconnection technologies.

[0127] When the core voltages of the functional component 210 and the functional component 230 are the same, take the example of the functional circuit 1 in the functional component 210 needing to establish cross-component interconnection with the functional circuit 10 in the functional component 230: the lead-out signal of the functional circuit 1 in the internal metal layer in the functional component 210 is connected to the face-to-face three-dimensional heterogeneous integrated bonding structure between the functional component 210 and the functional component 220 through the top metal of the functional component 210, and then interconnected with the top metal of the functional component 220; the interconnection signal is interconnected to the back-to-face three-dimensional heterogeneous integrated bonding structure between the functional component 220 and the functional component 230 through the internal metal layer of the functional component 220 and the through-silicon via (TSV) penetrating the active layer and the thinned substrate of the functional component 220, and then interconnected to the top metal layer of the functional component 230; the interconnection signal passes through the internal metal layer of the functional component 230 to realize cross-component interconnection of the functional circuit 10 in the functional component 230.

[0128] When the core voltages of functional components 210 and 230 differ, for example, functional circuit 2 in a functional component needs to establish a cross-component interconnection with functional circuit 10 in functional component 230: A level shifter circuit 2 is designed in functional component 210, and level shifter circuit 2 and functional circuit 2 are interconnected in functional component 210. Level shifter circuit 2 converts the interconnection signal of functional circuit 2 to match the core voltage of functional component 230, and then uses the aforementioned method to interconnect to functional circuit 20 in functional component 230. Furthermore, level shifter circuit 2 can also be transferred to functional module 230 or functional module 220 through three-dimensional heterogeneous integrated interconnection.

[0129] In the stacked chip provided by this application, the programmable gate array component and the application-specific integrated circuit array component access the memory array component without going through the I / O interface and / or I / O circuit, making the interconnection distance closer and significantly reducing the power consumption of memory access. Furthermore, a high-bandwidth, low-power integrated programmable memory structure is achieved through three-dimensional heterogeneous integrated bonding.

[0130] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A stacked chip, characterized in that: include: a first programmable gate array component, the first programmable gate array component comprising a first interface module, the first interface module being embedded in the first programmable gate array component, the first interface module comprising a first bond lead-out region; The first memory array assembly is provided with a second bonding lead-out area; The first bond lead-out region and the second bond lead-out region are bonded together through a three-dimensional heterogeneous integrated bonding structure to connect interconnection signals on the first programmable gate array component and the first memory array component; Wherein, the first programmable gate array component includes multiple functional modules, The number of the first interface module is at least one. The first interface module is located between the plurality of functional modules and is connected to the functional modules through an interface routing unit.

2. The stacked chip according to claim 1, wherein: The interior of the functional module is strip-shaped, and the first interface module is arranged extending along the strip-shaped functional module.

3. The stacked chip according to claim 1, wherein: The functional module is connected to the interface routing unit through an internal metal layer, and the first interface module is interconnected with the interface routing unit through an internal metal layer.

4. The stacked chip according to claim 3, wherein: The first programmable gate array component includes a programmable routing network, the multiple functional modules are interconnected with the programmable routing network through an internal metal layer, and are connected to the interface routing unit through the programmable routing network.

5. The stacked chip according to claim 1, wherein: The stacked chip further comprises: A physical layer, the physical layer being used to implement level conversion between the first programmable gate array component and the first storage array component; The physical layer is arranged on the first interface module.

6. The stacked chip according to claim 1, wherein: The functional modules include any one or more of a programmable logic block LAB (Logic Array Block) or a CLB (Configurable Logic Block), a storage block BRAM (Block Random Access Memory, BRAM), a multiplication unit DSP (Digital Signal Processor) and a multiplication and accumulation unit MAC (Multiply Accumulate) or any combination thereof.

7. The stacked chip according to claim 6, wherein: The functional modules also include: A combination of application-specific integrated circuit array units, which are fixed hardware circuits used to complete fixed computing goals.

8. The stacked chip according to claim 6, wherein: The memory block is connected to the programmable logic block through a memory routing unit.

9. The stacked chip according to claim 1, wherein: The first programmable gate array component includes a field programmable gate array (FPGA) or an embedded field programmable gate array (eFPGA).

10. The stacked chip according to claim 1, wherein: The stacked chip further comprises: a storage control unit, the storage control unit being provided on the first interface module; or The storage control unit is arranged at a position of the first programmable gate array component close to the first interface; or, The storage control unit is arranged on the first storage array component; The storage control unit controls the first programmable gate array component to perform storage access on the first storage array component.

11. The stacked chip according to claim 1, wherein: The stacked chip further comprises: a second storage array component, the second storage array component being disposed on a side of the first programmable gate array component away from the first storage array component; The second memory array assembly is provided with a third bonding lead-out region; The first interface module includes a fourth bonding lead-out area, and the first programmable gate array component and the second storage array component are bonded and connected via the third bonding lead-out area and the fourth bonding lead-out area.

12. The stacked chip according to claim 1, wherein: The stacked chip further comprises: a second storage array component, the second storage array component being arranged on a side of the first storage array component away from the first programmable gate array component; The second memory array assembly is provided with a third bonding lead-out region; The first memory array component includes a fourth bonding lead-out region, and the first memory array component and the second memory array component are bonded and connected via the fourth bonding lead-out region and the third bonding lead-out region.

13. The stacked chip according to claim 11 or 12, characterized in that: The stacked chip further comprises: a storage control unit, the storage control unit being arranged on the first interface module; The storage control unit controls the first programmable gate array component to access the first storage array component and the second storage array component.

14. The stacked chip according to claim 13, wherein: The first programmable gate array component further includes: A programmable logic unit, connected to the storage control unit, the programmable logic unit leading to a logic signal; The storage control unit selectively controls the first programmable gate array component to access the first storage array component, or controls the first programmable gate array component to access the second storage array component based on the logic signal in a time-sharing manner.

15. The stacked chip according to claim 11 or 12, characterized in that: The stacked chip further comprises: A first storage control unit is provided on the first interface module; a second storage control unit, provided on the first interface module; The first storage control unit controls the first programmable gate array component to access the first storage array component, and the second storage control unit controls the first programmable gate array component to access the second storage array component.

16. The stacked chip according to claim 15, wherein: The first programmable gate array component further includes: a programmable logic unit, connected to the first storage control unit and the second storage control unit, the programmable logic unit leading to a logic signal; The first storage control unit controls the first programmable gate array component to access the first storage array component based on the logic signal, and the second storage control unit controls the first programmable gate array component to access the second storage array component based on the logic signal.

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