Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor device packages and methods of manufacturing the same. The semiconductor device package includes a substrate having a first surface and a second surface opposite the first surface. The semiconductor device package also includes a first electrically conductive layer disposed over the first surface of the substrate and an insulating layer disposed over the first surface of the substrate. The semiconductor device package also includes a magnetically conductive layer disposed between the first electrically conductive layer and the insulating layer. The magnetically conductive layer has a bottom surface facing the first surface of the substrate, a top surface opposite the first surface of the substrate, and a side surface extending between the bottom surface of the magnetically conductive layer and the top surface of the magnetically conductive layer. Another embodiment of the present disclosure relates to a method of manufacturing a semiconductor device package.

Description

Technical Field

[0001] This invention relates to semiconductor device packaging and manufacturing methods thereof, and more specifically, to semiconductor device packaging with magnetic materials. Background Technology

[0002] A transformer contains at least two inductor coils and typically includes magnetic material to increase its inductance. In the prior art, transformers are not formed within a stacked circuit structure of a printed circuit board. Furthermore, the prior art does not combine printed circuit board manufacturing processes with transformer manufacturing processes. Summary of the Invention

[0003] Embodiments of this disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first electrically conductive layer disposed above the first surface of the substrate; and an insulating layer disposed above the first surface of the substrate. The semiconductor device package further includes a magnetically conductive layer disposed between the first electrically conductive layer and the insulating layer. The magnetically conductive layer has a bottom surface facing the first surface of the substrate, a top surface opposite to the first surface of the substrate, and a side surface extending between the bottom surface and the top surface of the magnetically conductive layer.

[0004] Embodiments of this disclosure relate to a method for manufacturing a semiconductor device package. The method includes providing a substrate, forming a patterned metal layer on the substrate, and forming a patterned magnetic material on the substrate to cover the patterned metal layer. Attached Figure Description

[0005] The various embodiments of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the structures are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0006] Figure 1A The diagram shown is a cross-sectional view of a semiconductor device package according to certain embodiments of this invention;

[0007] Figure 1B The diagram shown is a cross-sectional view of a semiconductor device package according to certain embodiments of this invention;

[0008] Figure 2A The image shown is a perspective view of a semiconductor device package according to certain embodiments of this invention;

[0009] Figure 2B The image shown is a perspective view of a semiconductor device package according to certain embodiments of this invention;

[0010] Figure 3 The diagram shown is a perspective view of a semiconductor device package according to certain embodiments of this invention; and

[0011] Figures 4A to 4D The illustration shows one or more stages in a method of manufacturing a semiconductor device package according to certain embodiments of this case.

[0012] Identical or similar components are designated using the same reference numerals in the drawings and detailed description. Several embodiments of this disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0015] This disclosure provides a semiconductor device package and a method for manufacturing the same. Compared to comparative embodiments, the package structure of this disclosure utilizes a circuit layer in a substrate to fabricate an inductor coil, and at least one circuit layer in the substrate is formed with magnetic material by printing on a stencil. This manufacturing method eliminates the need to drill holes in the substrate and fill them with magnetic material. Furthermore, this manufacturing method integrates the substrate and transformer processes, thereby reducing process costs and minimizing component size.

[0016] Reference Figure 1A , Figure 1A The diagram shown is a cross-sectional view of a semiconductor device package 1 according to certain embodiments of the present invention. The semiconductor device package 1 includes a substrate 10, electrically conductive layers (or patterned metal layers) 11c and 12c, magnetically conductive layers 13 and 15, and insulating layers 14 and 16.

[0017] The substrate 10 has a surface (or first surface) 111 and a surface (or second surface) 112 opposite to the surface 111.

[0018] The substrate 10 can be (or contains) a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. For example, such as Figure 1A As shown, the substrate 10 may include a core layer 10d and dielectric layers 11d1, 11d2, 12d1 and 12d2 stacked on the top and bottom sides of the core layer 10d.

[0019] The core layer 10d, dielectric layers 11d1, 11d2, 12d1, and 12d2 may include (but are not limited to) a solder mask, polyimide (PI), polypropylene (PP), ABF substrate (Ajinomoto build-up film, ABF), molding compounds, pre-impregnated composite fibers (e.g., prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), combinations thereof, or other similar materials. Examples of molding compounds may include (but are not limited to) epoxy resin (containing fillers dispersed therein). Examples of prepreg materials may include (but are not limited to) multilayer structures formed by stacking or laminating multiple prepreg materials and / or sheets. Although the figures in this disclosure depict four dielectric layers, the semiconductor device package of the present invention may also have any number of dielectric layers. For example, the semiconductor device package of the present invention may also be used to form a transformer or inductor in a substrate having any number of layers.

[0020] The electrically conductive layer 11c includes an electrically conductive layer 11c1 encapsulated within a dielectric layer 11d2 and an electrically conductive layer 11c2 disposed above the surface 111 of the substrate 10. Specifically, the electrically conductive layer 11c1 is disposed on a surface of the core layer 10d, and the dielectric layer 11d2 covers the electrically conductive layer 11c1. The electrically conductive layer 11c1 is electrically connected to the electrically conductive layer 11c2 through a conductive via 11v. The conductive via 11v extends from the surface 111 through the dielectric layers 11d1 and 11d2 to contact the electrically conductive layer 11c1. The width of the conductive via 11v tapers from the surface 111 toward the core layer 10d.

[0021] In some embodiments, the electrically conductive layer 11c1 forms a spiral inductor. In some embodiments, the spiral inductor formed by the electrically conductive layer 11c1 is generally parallel to a surface of the core layer 10d. In some embodiments, the electrically conductive layer 11c2 forms a spiral inductor. In some embodiments, the spiral inductor formed by the electrically conductive layer 11c2 is generally parallel to surface 111. From a cross-sectional view, the electrically conductive layer 11c2 includes several portions separated from each other or spaced apart by a distance. The distance between each portion is denoted as "S", and each portion may have a width (or linewidth) denoted as "W". In some embodiments, the linewidth W may be between 100 micrometers (μm) and 500 μm. However, the invention is not limited thereto; in some embodiments, the linewidth W may be greater than 500 μm. In some embodiments, the distance S may be between 50 μm and 100 μm. However, the invention is not limited thereto; in some embodiments, the distance S may be greater than 100 μm.

[0022] Each pair of portions of the electrically conductive layer 11c2 forms a cavity with the surface 111, in which the magnetically conductive layer 13 fills or accommodates.

[0023] The electrically conductive layers 11c1 and 11c2, and the conductive pillar 11v may contain (but are not limited to) copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys.

[0024] A magnetic conductive layer 13 is disposed above the surface 111 of the substrate 10 and covers the electrically conductive layer 11c2. The magnetic conductive layer 13 has a surface (or top surface) 131, a surface (or bottom surface) 132, and a surface (or side surface) 133 extending between the surfaces 131 and 132. Surface 132 faces the surface 111 of the substrate 10. Surface 131 faces away from the surface 111 of the substrate 10.

[0025] In some embodiments, the magnetic conductive layer 13 covers a portion of the sidewalls of the electrically conductive layer 11c2 (e.g., covers the sidewalls of a groove). In some embodiments, the magnetic conductive layer 13 has a portion located within a groove defined by an adjacent electrically conductive layer 11c2. In some embodiments, the magnetic conductive layer 13 has a recessed portion located above the groove defined by an adjacent electrically conductive layer 11c2. The magnetic conductive layer 13 is in contact with the electrically conductive layer 11c2. For example, the magnetic conductive layer 13 is in direct contact with the electrically conductive layer 11c2. For example, the magnetic conductive layer 13 is formed directly on top of the electrically conductive layer 11c2. The magnetic conductive layer 13 and the electrically conductive layer 11c2 are in direct contact to form an interface. The interface has a measurable surface roughness. The interface has an uneven surface.

[0026] The magnetic conductive layer 13 may comprise (but is not limited to) magnetic particles, magnetic particle mixtures (e.g., mixtures with binders and solvents), or a magnetic coating layer. The magnetic particles may comprise (but are not limited to) iron oxides (e.g., Fe3O4, γ-Fe2O3), chromium oxides (e.g., CrO2), other metal oxides (e.g., cobalt-iron oxide), or other feasible materials. For example, the magnetic conductive layer 13 may comprise a liquid magnetic material. For example, the magnetic conductive layer 13 may comprise a material that is magnetically permeable but not electrically conductive.

[0027] An insulating layer 14 is disposed above the surface 111 of the substrate 10 and covers the magnetic conductive layer 13. For example, a portion of the insulating layer 14 is located on the surface 111 of the substrate 10, and a portion of the insulating layer 14 is located on the surface 131 of the magnetic conductive layer 13. For example, the magnetic conductive layer 13 is disposed between the insulating layer 14 and the surface 111 of the substrate 10. For example, the insulating layer 14 covers both the surface 131 and the surface 133 of the magnetic conductive layer 13. The surface 132 of the magnetic conductive layer 13 is located above the surface 111 of the substrate 10. The surface 132 of the magnetic conductive layer 13 contacts the surface 111 of the substrate 10.

[0028] The insulating layer 14 has a height (or first height) h1 measured from the surface 111 of the substrate 10 to the farthest point from the surface 111 of the substrate 10. The magnetic conductive layer 13 has a height (or second height) h2 measured from the surface 132 to the surface 131. In some embodiments, height h1 is greater than height h2. In some embodiments, height h2 is less than 60%, 50%, 40%, 30%, or a lower percentage of height h1. In some embodiments, the insulating layer 14 may be formed by a lamination process. Controlling the maximum height of the magnetic conductive layer 13 to within 60% of the maximum height of the insulating layer 14 facilitates the execution of the process, for example, by forming an insulating layer 14 with a generally planar surface, and by helping to prevent the magnetic conductive layer 13 from becoming too thick and deforming during the lamination process.

[0029] In some embodiments, the insulating layer 14 formed by lamination has a generally flat surface. For example, in some embodiments, the insulating layer 14 located on the surface 111 of the substrate 10 has a maximum height h1 and a generally flat surface. In some embodiments, the insulating layer 14 located on the surface 131 of the magnetic conductive layer 13 has a maximum height h3 and a generally planar surface. Because the insulating layer 14 located on the surface 111 of the substrate 10 and the insulating layer 14 located on the surface 131 of the magnetic conductive layer 13 are coplanar as a result of the lamination process, the maximum height h1 will be greater than the maximum height h3.

[0030] The insulating layer 14 has a width WW' measured in a direction perpendicular to height h1. The magnetic conductive layer 13 has a width WW measured in a direction perpendicular to height h2. In some embodiments, the width WW of the magnetic conductive layer 13 is smaller than the width WW' of the insulating layer 14. In some embodiments, the surface 133 of the magnetic conductive layer 13 contacts the insulating layer 14. In some embodiments, the surface 133 (or side surface) of the magnetic conductive layer 13 is covered by the insulating layer 14.

[0031] The insulating layer 14 may have the materials listed above for the core layer and dielectric layer. The insulating layer 14 may have the same or different materials as the core layer and dielectric layer. For example, the insulating layer 14 may include (but is not limited to) solder resist, PI, PP, ABF substrate, molding compound, prepreg composite fiber (e.g., prepreg material), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, combinations thereof, or other similar materials.

[0032] On the other side of the core layer 10d, the electrically conductive layers 12c1 and 12c2, and the conductive pillar 12v may have the same or similar configuration as the electrically conductive layers 11c1 and 11c2, and the conductive pillar 11v. A detailed description of the electrically conductive layers 12c1 and 12c2, and the conductive pillar 12v will not be repeated here. Similarly, the magnetically conductive layer 15 may have the same or similar configuration as the magnetically conductive layer 13, and the insulating layer 16 may have the same or similar configuration as the insulating layer 14.

[0033] Reference Figure 1B , Figure 1B The diagram shown is a cross-sectional view of a semiconductor device package 2 according to certain embodiments of this invention. Figure 1B The semiconductor device package 2 shown Figure 1A Components that are the same as or similar to those in the semiconductor device package 1 shown are identified by the same component symbols, and detailed descriptions of the components will not be repeated.

[0034] The semiconductor device package 2 further includes an electrically conductive layer 21 disposed above the insulating layer 14. In some embodiments, the electrically conductive layer 21 forms a spiral inductor (see reference). Figure 2A The spiral inductance formed by the electrically conductive layer 21 is generally parallel to one surface of the insulating layer 14. In some embodiments, the spiral inductance formed by the electrically conductive layer 21 is generally parallel to the spiral inductance formed by the electrically conductive layer 11c1. In some embodiments, the spiral inductance formed by the electrically conductive layer 21 is generally parallel to the spiral inductance formed by the electrically conductive layer 11c2. The electrically conductive layer 21 is electrically connected to the electrically conductive layer 11c2 through the conductive post 21v. The magnetically conductive layer 22 is disposed above the insulating layer 14 and covers the electrically conductive layer 21. In some embodiments, the magnetically conductive layer 13 and the magnetically conductive layer 22 may be generally parallel to each other. In some embodiments, the conductive post 21v penetrates a portion of the magnetically conductive layer 13 and its side surface contacts the magnetically conductive layer 13, thus connecting to the electrically conductive layer 11c2.

[0035] Figure 1A and Figure 1B The configuration of the wiring (e.g., conductive layers and conductive pillars) and other components shown is merely illustrative and the invention is not limited thereto. The configuration of the wiring and other components (including their quantity and location) may vary depending on requirements and device specifications.

[0036] Reference Figure 2A and 2B , Figure 2A The diagram shown is a perspective view of a semiconductor device package according to certain embodiments of this invention. Figure 2B The diagram shown is a perspective view of a semiconductor device package according to certain embodiments of this invention. In some embodiments, Figure 1A The semiconductor device package 1 shown can be Figure 2A A cross-sectional view along the X-axis or Y-axis. Figure 2A For the sake of simplicity, only the electrically conductive layer and the upper and lower magnetically conductive layers 13 and 15 are drawn in the 3D diagram. Figure 2B 3D diagram and Figure 2A Similarly, for the sake of simplicity, only the electrically conductive layers 11c1, 11c2, 12c1, and 12c2 are drawn.

[0037] like Figure 2A and 2B As shown, the electrically conductive layers 11c1, 11c2, 12c1, and 12c2 are individually formed into helical coils. In some embodiments, the magnetic conductive layers 13 and 15 have a normal direction parallel to the Z-axis, and each turn of each helical coil is substantially parallel to the surface formed by the X and Y axes.

[0038] Reference Figure 3 , Figure 3 The diagram shown is a perspective view of a semiconductor device package 3 according to certain embodiments of the present invention. The semiconductor device package 3 includes electrically conductive layers 31c and 32c, a magnetically conductive layer 33, and an insulating layer 34. Figure 3 The 3D model omits the background for simplicity.

[0039] Electrically conductive layer 31c is electrically connected to electrically conductive layer 32c through conductive post 31v. Electrically conductive layer 31c, conductive post 31v, and electrically conductive layer 32c form a helical coil around magnetic conductive layer 33. For example, electrically conductive layer 31c, conductive post 31v, and electrically conductive layer 32c form a helical coil with magnetic conductive layer 33 as its axis. Compared to Figure 2A and 2B The spiral coil shown (each turn is parallel to the surface formed by the X and Y axes) Figure 3 Each turn of the spiral coil shown is not parallel to the surface formed by the X and Y axes. Furthermore, Figure 2A and 2B Each turn of the spiral coil shown does not wrap around the magnetic conductive layer 13, but is electrically connected through a conductive post (e.g., 21V in Figure 2). Figure 3 Each turn of the spiral coil shown (including the conductive post 31v) surrounds the magnetic conductive layer 33.

[0040] Reference Figures 4A to 4D , Figures 4A to 4D The figures illustrate one or more stages in a method of manufacturing a semiconductor device package according to certain embodiments of this application. At least some of these figures have been simplified to better understand the nature of this disclosure.

[0041] Reference Figure 4AThe manufacturing method includes providing a substrate 10. The substrate 10 has a surface (or a first surface) 111 and a surface (or a second surface) 112 opposite to the surface 111. The substrate 10 has a core layer 10d and dielectric layers 11d1, 11d2, 12d1, and 12d2.

[0042] The manufacturing method includes forming an electrically conductive layer (or patterned metal layer) 11c1 on the core layer 10d, forming conductive pillars 11v, and forming an electrically conductive layer 11c2 on the surface 111 of the substrate 10.

[0043] The conductive pillar 11v can be formed, for example, by forming pores in the dielectric layers 11d1 and 11d2 to expose portions of the electrically conductive layer 11c1 using etching, drilling, or laser drilling techniques; and depositing conductive material in the pores on the exposed portions of the electrically conductive layer 11c1.

[0044] The electrically conductive layer 11c2 can be formed, for example, by coating a photoresist film (or mask) on the surface 111 of the substrate 10, patterning the mask using a lithography technique, depositing conductive material in the patterned mask, and removing the mask. The conductive material can be deposited by sputtering, electroless plating, electroplating, printing, or other suitable processes. The mask can be removed by etching, stripping, or other suitable processes.

[0045] Reference Figure 4B The manufacturing method includes forming a magnetic material on the surface 111 of the substrate 10 to cover the electrically conductive layer 11c2. In some embodiments, the magnetic material may be formed by a stencil printing process, which may form a patterned magnetic material that covers only a portion of the dielectric layers 11d1 and 12d2.

[0046] Reference Figure 4C The magnetic material is pre-cured to form a solid. In some embodiments, the pre-curing method includes heating and / or pressing the magnetic material. For example, the magnetic material is solidified under a certain temperature and / or pressure. The pre-cured magnetic material forms magnetic conductive layers 13 and 15.

[0047] Reference Figure 4DInsulating layers 14 and 16 are formed on magnetic conductive layers 13 and 15. In some embodiments, insulating layers 14 and 16 can be formed by a lamination process. For example, after applying the materials of insulating layers 14 and 16 to magnetic conductive layers 13 and 15, magnetic conductive layers 13 and 15 are fed into a lamination machine (e.g., a hot press), so that the materials of insulating layers 14 and 16 are formed into a semi-molten state and bonded to magnetic conductive layers 13 and 15 under a certain temperature and / or pressure. In some embodiments, the lamination process further includes feeding the hot-pressed magnetic conductive layers 13 and 15 into a cold press to cool the magnetic conductive layers 13 and 15 and prevent them from oxidizing or deforming. In some embodiments, after the lamination process, magnetic conductive layers 13 and 15 can be further processed, such as edge finishing to make the edges smooth and flat. In some embodiments, after the lamination process, excess insulating layer material can overflow from both sides and flow out of the device. In some embodiments, a cleaning operation can be performed to remove excess insulating layer material. In some embodiments, after the lamination process, the upper surfaces of insulating layers 14 and 16 are higher than the upper surfaces of magnetic conductive layers 13 and 15. In some embodiments, the maximum height h2 of magnetic conductive layers 13 and 15 is less than sixty percent (60%) of the maximum height h1 of insulating layers 14 and 16. In some embodiments, controlling the maximum width of magnetic conductive layer 13 to within 60% of the maximum width of insulating layer 14 facilitates the execution of the lamination process.

[0048] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one component or feature as shown in the accompanying drawings and one or more other components or features. In addition to the orientation depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it may be directly connected to or coupled to the other component, or there may be an intermediate component present.

[0049] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm when located along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0050] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0051] Symbol Explanation

[0052] 1. Semiconductor device packaging

[0053] 2 Semiconductor device packaging

[0054] 3. Semiconductor device packaging

[0055] 10 Substrates

[0056] 10d core layer

[0057] 11d1 dielectric layer

[0058] 11d2 dielectric layer

[0059] 12d1 dielectric layer

[0060] 12d2 dielectric layer

[0061] 11c Electrically Conductive Layer

[0062] 11c1 Electrically conductive layer

[0063] 11c2 Electrically Conductive Layer

[0064] 11V Conductive Post

[0065] 12c Electrically Conductive Layer

[0066] 12c1 Electrically conductive layer

[0067] 12c2 Electrically Conductive Layer

[0068] 13 Magnetic Conductive Layer

[0069] 14 Insulation layer

[0070] 15 Magnetic Conductive Layer

[0071] 16 Insulation layer

[0072] 21 Electrically Conductive Layer

[0073] 21V Conductive Post

[0074] 22 Magnetic Conductive Layer

[0075] 31c Electrically Conductive Layer

[0076] 31V Conductive Post

[0077] 32c Electrically Conductive Layer

[0078] 33 Magnetic Conductive Layer

[0079] 34 Insulation layer

[0080] 111 Surface

[0081] 112 Surface

[0082] 131 Surface

[0083] 132 surface

[0084] 133 surface

[0085] h1 height

[0086] h2 height

[0087] S distance

[0088] W line width

[0089] WW width

[0090] WW' width

Claims

1. A semiconductor device package, comprising: The substrate has a core layer, a first dielectric layer disposed on the core layer, and a second dielectric layer disposed on the first dielectric layer; A first electrically conductive layer is disposed above the core layer of the substrate and covered by the first dielectric layer; A second electrically conductive layer is disposed above the substrate and connected to the first electrically conductive layer through a first conductive post, wherein the first conductive post passes through the second dielectric layer and the first dielectric layer; An insulating layer is disposed above the substrate; and A first magnetic conductive layer is disposed between the second electrically conductive layer and the insulating layer; and A second magnetic conductive layer is disposed within the insulating layer and is separated from the first magnetic conductive layer through the insulating layer.

2. The semiconductor device package according to claim 1, further comprising: A third electrically conductive layer is disposed in the second magnetically conductive layer and connected to the second electrically conductive layer through a second conductive post, wherein the second conductive post passes through the insulating layer and the first magnetically conductive layer.

3. The semiconductor device package of claim 2, wherein the first electrically conductive layer is formed in the substrate as a first spiral inductor, the second electrically conductive layer is formed on the substrate as a second spiral inductor, and the third electrically conductive layer is formed on the substrate as a third spiral inductor.

4. The semiconductor device package of claim 1, wherein the shortest distance between the second magnetic conductive layer and the substrate is a first distance, the longest distance between the first magnetic conductive layer and the substrate is a second distance, wherein the second distance is less than 60 percent of the first distance.

5. The semiconductor device package of claim 2, wherein the first conductive post and the second conductive post are offset in a direction substantially perpendicular to the substrate and taper toward the substrate.

6. A method for manufacturing a semiconductor device package, comprising: A substrate is provided having a core layer, a first dielectric layer disposed on the core layer, and a second dielectric layer disposed on the first dielectric layer, wherein the substrate has a first electrically conductive layer disposed above the core layer and covered by the first dielectric layer; A first conductive pillar is formed that passes through the second dielectric layer and the first dielectric layer; A second electrically conductive layer is formed on the substrate, which is connected to the first electrically conductive layer through the first conductive pillar; A first magnetic conductive layer is formed on the substrate to cover the first electrically conductive layer; An insulating layer is formed on the first magnetic conductive layer; A second magnetic conductive layer is formed in the insulating layer, which is separated from the first magnetic conductive layer through the insulating layer.

7. The method for manufacturing a semiconductor device package according to claim 6, further comprising: A second conductive pillar is formed that passes through the insulating layer and the first magnetic conductive layer; A third electrically conductive layer is formed in the second magnetic conductive layer, which is connected to the second electrically conductive layer through the second conductive post.

8. The method of manufacturing a semiconductor device package according to claim 6, wherein forming the first magnetic conductive layer to cover the first electrical conductive layer comprises performing a stencil printing process.

9. The method for manufacturing a semiconductor device package according to claim 6, further comprising: Pre-curing the first magnetic conductive layer; and Without removing the first magnetic conductive layer, the insulating layer is formed directly on the pre-cured first magnetic conductive layer to cover the pre-cured first magnetic conductive layer.

10. The method of manufacturing a semiconductor device package according to claim 9, wherein forming the insulating layer on the pre-cured first magnetic conductive layer includes a lamination process, and after the lamination process, the thickness of the first magnetic conductive layer is less than 60% of the thickness of the insulating layer.

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