Semiconductor structure and method for manufacturing multiple semiconductor structures

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a first hybrid bonding structure, a memory structure and a control circuit structure. The first hybrid bonding structure has a first surface and a second surface. The memory structure contacts the first surface. The control circuit structure is used to control the memory structure. The circuit control structure contacts the second surface. The present disclosure also provides a system-level packaging structure and a method for manufacturing multiple semiconductor structures.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a method for manufacturing a plurality of semiconductor structures, and in particular, the disclosed semiconductor structure has a memory structure integrated with a logic structure through a wafer stacking technology. Background Art

[0002] Based on the prospect of high performance, the realization of system-on-chip (SOC) has been greatly promoted; SOC, as a structure that embeds DRAM array into logic elements, is considered to be a better solution for high-speed transmission of large amounts of data. However, the merger of DRAM and logic elements requires reducing the difference in the process of the two. For example, for SOC, the compatibility of the design rules of logic elements and embedded DRAM is crucial.

[0003] The process of coordinating the compatibility of logic elements and embedded DRAM depends mainly on several different approaches. For example, memory circuits can be integrated into logic elements optimized for high-performance technology, or logic circuits can be integrated into high-density, low-performance DRAM optimized for technology. Each option has advantages and disadvantages. Generally, merging DRAM and logic elements into the same chip can produce huge advantages, but it is not easy to achieve and the integration process is challenging. In other words, since the process of logic elements and DRAM is incompatible in many aspects, it is necessary to propose new methods to solve the problem for the integration of these semiconductor structures. Summary of the invention

[0004] An embodiment of the present invention relates to a semiconductor structure, which includes: a first hybrid bonding structure having a first surface and a second surface; a memory structure contacting the first surface; and a control circuit structure for controlling the memory structure and contacting the second surface.

[0005] An embodiment of the present invention relates to a system-level packaging structure, which includes: a first semiconductor structure having a first critical dimension; a second semiconductor structure stacked with the first semiconductor structure, having a second critical dimension and contacting the first semiconductor structure via a hybrid bonding interface; and a substrate electrically connected to the first semiconductor structure and the second semiconductor structure via a first conductive bump; wherein the first critical dimension is different from the second critical dimension.

[0006] One embodiment of the present invention relates to a method for manufacturing multiple semiconductor structures, which includes: forming a first hybrid bonding layer on a first wafer having multiple first memory structures; forming a second hybrid bonding layer on a second wafer having multiple control circuit structures; bonding the first wafer and the second wafer through a first hybrid bonding step to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer; and monomerizing at least the first wafer, the second wafer, the first hybrid bonding layer and the second hybrid bonding layer to obtain multiple semiconductor structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0009] Figure 1B Describe the definitions of the front side and back side of a semiconductor structure or semiconductor wafer.

[0010] Figure 2 Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0011] Figure 3 Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0012] FIG. 4A to FIG. 4J Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure.

[0013] FIG. 5A to FIG. 5B Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure.

[0014] FIG. 6A to FIG. 6B Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure.

[0015] Figure 7 Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0016] Figure 8 Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0017] FIG. 9A to FIG. 9B Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure.

[0018] Fig.10Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0019] FIG. 11A to FIG. 11B Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure.

[0020] Fig.12 Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0021] FIG. 13A to FIG. 13B Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure.

[0022] Fig.14 Cross-sectional views of some embodiments of semiconductor structures according to the present disclosure are illustrated.

[0023] FIG. 15A to FIG. 15C Cross-sectional views illustrating some embodiments of forming semiconductor structures according to the present disclosure. DETAILED DESCRIPTION

[0024] This application claims priority to U.S. Provisional Patent Application No. 63 / 021,608, filed on May 7, 2020, the entire disclosure of which is incorporated herein by reference in its entirety.

[0025] The following disclosure provides many different embodiments or examples of different components for implementing the target provided. The specific examples of components and configurations are described below to simplify this disclosure. Of course, these are only examples and are not intended to be limiting. For example, a first component in the following description is formed on or above a second component and may include an embodiment in which the first component and the second component are formed as direct contacts, and may also include an embodiment in which additional components may be formed between the first component and the second component so that the first component and the second component may not directly contact. In addition, this disclosure may repeat component symbols and / or letters in each example. This repetition is for the purpose of simplification and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0026] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "down," "above," "up," "on," and the like may be used herein to describe the relationship of one element or component to another element or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted likewise.

[0027] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, which should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Unless clearly indicated by the context, terms such as "first," "second," and "third" when used herein do not imply a sequence or order.

[0028] For example, high bandwidth memory (HBM) is a CPU or GPU memory system that stacks memory dies vertically on top of logic dies. The stacked memory dies are placed on top of the logic die in the form of a distinguishable layer of memory towers, where each two adjacent memory dies are connected by micro-bumps that are laterally surrounded by molding material. Although these HBM stacks are not physically integrated into the CPU or GPU, they are close enough and are quickly connected to the CPU or GPU through an interposer, so the characteristics of HBM are almost indistinguishable from memory integrated into the chip.

[0029] Generally speaking, before stacking memory dies through micro-bumping, these memory dies used in the HBM structure are usually cut and tested, such as known good dies (KGD) obtained through some standard electrical test operations. These KGDs can then be stacked or packaged for high-end applications. Each memory die is bonded by micro-bumping to form a memory stack (which may include control circuit dies), and the memory die is further flip-chip bonded to a silicon interposer to form a chip-on-wafer (CoW) structure. However, micro-bumping operations result in high costs, the process of selecting KGDs reduces production efficiency, and stacking defects caused by micro-bumping operations reduce production yield.

[0030] Therefore, some embodiments of the present disclosure provide a memory structure integrated with a control circuit, which is completed through wafer stacking rather than CoW operation. The control circuit may include one or more logic structures. In other words, the memory structure on the control circuit can be manufactured through a hybrid bonding operation based on wafer stacking (wafer-on-wafer or wafer-to-wafer). The memory stack (which may include the control circuit) can be cut or separated after the hybrid bonding operation is completed. In this way, the production efficiency of forming the memory stack can be greatly improved, and the risk of stacking defects caused by micro-bump operations can be significantly reduced. As for the side where the KGD selection of the memory grain is omitted, the memory block of the memory grain can be tested by providing a control circuit without the need for probe measurement or testing machine. For example, U.S. patent application No. US 16 / 899,166 "Semiconductor device and method for manufacturing the same" is used as a reference for this case.

[0031] Figure 1A A semiconductor structure is shown, which includes a memory structure integrated with a control circuit structure through wafer stacking. In some embodiments, the control circuit structure may include at least one logic structure, for example, a transistor having the minimum line width of the semiconductor structure. As shown in the figure, the semiconductor structure includes a hybrid bonding structure 10, a memory structure 100 and a control circuit structure 200. The hybrid bonding structure 10 includes a first surface 101A and a second surface 201A opposite to the first surface 101A. The hybrid bonding structure 10 is sandwiched between the memory structure 100 and the control circuit structure 200. The hybrid bonding structure 10 is used to integrate the memory structure 100 and the control circuit structure 200. In some embodiments, the memory structure 100 is in contact with the first surface 101A of the hybrid bonding structure 10. The control circuit structure 200 is in contact with the second surface 201A of the hybrid bonding structure 10.

[0032] In some embodiments, the hybrid bonding structure 10 includes a first hybrid bonding layer 101 adjacent to the memory structure 100, and a second hybrid bonding layer 201 adjacent to the control circuit structure 200. The first hybrid bonding layer 101 is formed on the memory structure 100 and is used to bond the second hybrid bonding layer 201. The second hybrid bonding layer 201 is formed on the control circuit structure 200 and is used to bond the first hybrid bonding layer 101. In some embodiments, each of the first hybrid bonding layer 101 and the second hybrid bonding layer includes a plurality of bonding pads surrounded by dielectric materials, examples of which include oxides.

[0033] Hybrid bonding is a method that can connect two substrates or wafers by both metal bonding and oxide bonding, that is, it allows two substrates or wafers to be connected in a "face-to-face", "face-to-back" or "back-to-back" manner. For the purpose of illustration, Figure 1B The definition of the front and back sides of a semiconductor structure or semiconductor wafer is shown. Figure 1A For the memory structure 100 or the control circuit structure 200 shown in the figure or for a wafer, the semiconductor structure may include a semiconductor substrate 83 and a back-end-of-line structure 85, and a front-end-of-line structure 84 is formed on or in the semiconductor substrate 83. According to some embodiments, the surface of the back-end-of-line structure 85 may be the front side 81 of the semiconductor structure 80, and the surface of the semiconductor substrate 83 may be the back side 82 of the semiconductor structure 80. However, this does not constitute a limitation of the present embodiment. The definition of the front side or back side of the semiconductor structure may also be interchanged. In some implementations, the position of the memory structure 100 and the position of the control circuit structure 200 may be vertically aligned through bonding, and the first bonding pads 102 of the first hybrid bonding layer 101 may thus contact the second bonding pads 202 of the second hybrid bonding layer 201; at the same time, the first oxide portions 103 of the first hybrid bonding layer 101 are in contact with the second oxide portions 203 of the second hybrid bonding layer 201. In these embodiments, the first bonding pads 102 of the first hybrid bonding layer 101 and the second bonding pads 202 of the second hybrid bonding layer 201 are distributed in a mirror image.

[0034] In some embodiments, the first bonding pad 102 and the second bonding pad 202 are made of copper (Cu). In some embodiments, the first oxide portion 103 and the second oxide portion 203 are made of a dielectric material such as silicon dioxide (SiO2). In order to strengthen the copper-copper connection, the control of the flatness of the bonding pad surface is an important factor. For example, in some embodiments, the surface of the copper bonding pad can be controlled to be substantially flush with the silicon dioxide portion by performing a chemical mechanical polishing (CMP) operation. In some embodiments, depending on the hybrid bonding operation performed, the silicon dioxide portion can slightly protrude from the copper bonding pad. In the present disclosure, for example, the memory structure 100 and the control circuit structure 200 can be bonded by first contacting the first oxide portion 103 with the second oxide portion 203; the bonding between the aforementioned oxide portions can be through van der Waals forces. Thereafter, an annealing operation can be performed to facilitate the connection between the first bonding pad 102 and the second bonding pad 202.

[0035] In some embodiments, the control circuit structure 200 is a DRAM control logic. In some embodiments, in addition to being used to control the memory structure 100, the control circuit structure 200 can also be further used as a system on chip (SoC) integrated with a GPU or a CPU.

[0036] like Figure 2 As shown, the semiconductor structure disclosed herein may include a system-in-package (SiP) structure. In these embodiments, the system and package structure includes a first semiconductor structure 100', a second semiconductor structure 200' and a substrate 500. The second semiconductor structure 200' is stacked with the first semiconductor structure 100'. The second semiconductor structure 200' is in contact with the first semiconductor structure 100' via a hybrid bonding interface 1201. The substrate 500 is electrically connected to the first semiconductor structure 100' and the second semiconductor structure 200' via a first conductive bump connection 501. The first conductive bump connection 501 may include a plurality of solders, wherein these solders may be surrounded by a suitable bottom filling glue material (not shown in the figure).

[0037] In some embodiments, the first semiconductor structure 100' may include a plurality of memory dies (i.e., memory dies 100A, 100B, 100C, 100D, etc.) stacked on the second semiconductor structure 200'. In some embodiments, at least two memory dies are hybrid bonded via a second hybrid bonding structure 20. In some embodiments, two adjacent memory dies are hybrid bonded via the second hybrid bonding structure 20. The details of the second hybrid bonding structure 20 are the same as the first hybrid bonding structure 10 described above, except that the mirror-distributed bonding pads are formed on adjacent memory dies. In some embodiments, each memory die of the first semiconductor structure 100' may include a DRAM structure having a first critical dimension (i.e., the minimum line width that can be achieved in the structure through a lithography process operation). Similarly, the second semiconductor structure 200' may include at least a logic structure having a second critical dimension (i.e., the minimum line width that can be achieved in the structure through a lithography process operation). Since different technology nodes can be implemented to manufacture the first semiconductor structure 100' and the second semiconductor structure 200', the first critical dimension is different from the second critical dimension. In some embodiments, when the technology node implemented in manufacturing the first semiconductor structure 100' is more advanced, the first critical dimension is smaller than the second critical dimension. In another embodiment, when the technology node implemented in manufacturing the second semiconductor structure 200' is more advanced, the first critical dimension is greater than the second critical dimension. It is worth noting that when the first semiconductor structure 100' and the second semiconductor structure 200' are manufactured by the same technology node, the first critical dimension may be equal to the second critical dimension.

[0038] In the present disclosure, the number of memory dies vertically stacked on the second semiconductor structure 200' through hybrid bonding is customizable. For example, in view of the fact that in a conventional structure, four or eight memory dies are usually stacked on a control circuit or logic die through microbumps, some embodiments of the present disclosure use four memory dies vertically stacked on the second semiconductor structure 200' through hybrid bonding as an example, but in fact, the number of memory dies is not limited to this number or range.

[0039] In some embodiments, the second semiconductor structure 200' is a DRAM control logic. In some embodiments, the second semiconductor structure 200' is Figure 1A The first hybrid bonding structure 10 shown is bonded to the memory die 100A of the first semiconductor structure 100'. In some embodiments, the bonding structure in the first semiconductor structure 100' and the bonding structure between the first semiconductor structure 100' and the second semiconductor structure 200' are different from the bonding structure between the second semiconductor structure 200' and the substrate 500. For example, the first hybrid bonding structure 10 and the second hybrid bonding structure 20 are formed by appropriate hybrid bonding operations, characterized by a hybrid bonding interface 1201; and the first conductive bump connection portion 501 is formed by appropriate micro-bump operations, and multiple solder bumps can be observed.

[0040] In some embodiments, the SiP structure may include a third semiconductor structure 300 electrically connected to the first semiconductor structure 100' and the second semiconductor structure 200' via a second conductive bump connection 401. The second conductive bump connection 401 may include a plurality of solders, wherein the solders may be surrounded by a suitable bottom filler material (not shown in the figure). In some embodiments, the third semiconductor structure 300 has a third critical dimension that is smaller than the first critical dimension of the first semiconductor structure 100'. In some embodiments, the third semiconductor structure 300 is adjacent to a stack formed by the first semiconductor structure 100' and the second semiconductor structure 200'. In some embodiments, the third semiconductor structure 300 is used as a SOC for a GPU or a CPU.

[0041] In some embodiments, the SiP structure may include an interposer 400 between the substrate 500 and the second semiconductor structure 200'. The interposer 400 may be used to support the first semiconductor structure 100', the second semiconductor structure 200', and the third semiconductor structure 300. Figure 2The interposer 400 is electrically connected to the first semiconductor structure 100', the second semiconductor structure 200' and the substrate 500 through the second conductive bump connection 401, the first conductive bump connection 501 and a redistribution layer located between the third semiconductor structure 300 and the second semiconductor structure 200' for laterally transmitting signals. The redistribution layer of the interposer 400 can also allow a higher density I / O near the second semiconductor structure 200' to be reconfigured into a lower density I / O near the substrate 500.

[0042] As mentioned above, hybrid bonding allows two substrates or wafers to be connected in a "face-to-face" or "face-to-back" arrangement. In some embodiments, with different hybrid bonding schemes and many optional sequences in manufacturing the through holes of each memory die and logic die, the stacking of substrates or wafers of memory die and logic die can have different application forms.

[0043] like Figure 3 As shown, in some embodiments, each memory structure and control circuit structure is manufactured by a via-last process. Through the via-last process, through silicon vias (TSVs) are formed after transistors are prepared and wired; in other words, both the front-end-of-line (FEOL) structure and the back-end-of-line (BEOL) structure are formed before operations such as via etching and via filling. In these embodiments, the logic die and the memory die can be stacked in a "face-to-face" arrangement, while the memory die in the memory structure are stacked in a "back-to-back" arrangement (Scheme I). On the other hand, the bonding pads dispersed on the logic die and the bonding pads dispersed on the memory die are distributed in a mirror image. In addition, in the embodiment with the stacking arrangement of Scheme I, the second surface 201A of the hybrid bonding structure 10 shown in FIG. 1 is closer to the back-end-of-line structure of the control circuit structure 200, and farther away from the front-end-of-line structure of the control circuit structure 200.

[0044] like Figure 3 As shown, since the memory chips are from a first wafer 61 (later disclosed in Figure 4A ) is manufactured, each memory chip includes a first front side 61A and a first back side 61B; and the control circuit structure 200 is manufactured from a second wafer 62 (later disclosed in Figure 4A) and has a second front side 62A and a second back side 62B. The first hybrid bonding structure 10 is sandwiched between the control circuit structure 200 and the memory die 100A. In addition, each second hybrid bonding structure 20 is sandwiched between adjacent memory dies, such as the memory dies 100A and 100B. In some embodiments, each second hybrid bonding structure 20 includes two first hybrid bonding layers 101, wherein the bonding pads located in these first hybrid bonding layers 101 are distributed in a mirror image along the hybrid bonding interface 1201.

[0045] For reference FIG. 4A to FIG. 4J To manufacture Figure 3 The semiconductor structure shown. Figure 4A As shown, in some embodiments, the memory structure 100 (i.e., memory die) and the control circuit structure 200 (i.e., logic die) are formed on the first wafer 61 and the second wafer 62 respectively before the hybrid bonding operation. Each of the first wafer 61 and the second wafer 62 may include multiple die regions, and the present disclosure only shows one of the die regions as an example. In some embodiments, a first reserved area 631 may be included within the scope of each memory structure 100. Similarly, a second reserved area 632 may be included within the scope of each control circuit structure 200. The first reserved area 631 and the second reserved area 632 are reserved for subsequent operations to form TSVs there, because the position of the bonding pads may be related to the location of the TSVs. As mentioned above, since the bonding pads in the hybrid bonding layer should be distributed in a mirror image, when designing the layout of each memory structure 100 (i.e., memory die) and the control circuit structure 200 (i.e., logic die), the aforementioned first reserved area 631 and the second reserved area 632 may be pre-planned.

[0046] like Figure 4B As shown, a first TSV 104 and a second TSV 204 may be formed adjacent to the first front side 61A of the first wafer 61 and the second front side 62A of the second wafer 62, respectively. In some embodiments, the first TSV 104 and the second TSV 204 are formed by a through-hole etching operation, and the hole structure of the through-hole is filled with a conductive material by an electroplating operation. Figure 4B In the illustrated operation stage, only one end of the first TSV 104 and the second TSV 204 may be exposed outside the first wafer 61 and the second wafer 62, respectively; however, in a subsequent wafer thinning operation (eg, Figure 4F and Fig. 4I As shown in FIG. 1 , both ends of the first TSV 104 and the second TSV 204 may be exposed outside the first wafer 61 and the second wafer 62 , respectively.

[0047] like Figure 4CAs shown, in some embodiments, after forming the first TSV 104 and the second TSV 204, a first metal layer 105 may be formed on the first front side 61A of the first wafer 61 to connect the first TSV 104 and a top metal 106. Similarly, a second metal layer 205 may be formed on the second front side 62A of the second wafer 62 to connect the second TSV 204 and a top metal 206.

[0048] like Figure 4D As shown, in some embodiments, the first hybrid bonding layer 101 is formed on the first front side 61A of the first wafer 61. Similarly, the second hybrid bonding layer 201 is formed on the first front side 62A of the second wafer 62. In some embodiments, the first hybrid bonding layer 101 includes the above-mentioned Figure 1A The first bonding pad 102 is shown. In some embodiments, the first hybrid bonding layer 101 further includes a plurality of first conductive vias 108 located in a first hybrid bonding portion 107 thereof. In other words, the first hybrid bonding portion 107 may include a metal via structure to connect the first bonding pad 102 and the first metal layer 105. Since the first conductive via 108 may be designed to have a small critical dimension (e.g., a small diameter), in order to increase the product yield, connection defects caused by manufacturing operations may be prevented by forming a plurality of first conductive vias 108 corresponding to the first bonding pad 102. The first TSV 104 may be coupled to one end of the first conductive via 108 through the first metal layer 105, and the first bonding pad 102 may be in contact with the other end of the first conductive via 108. Similarly, in some embodiments, the second hybrid bonding layer 201 further includes a plurality of second conductive vias 208 located in a second hybrid bonding portion 207 thereof. The second TSV 204 may be coupled to one end of the second conductive via 208 through the second metal layer 205, and the second bonding pad 202 may be in contact with the other end of the second conductive via 208. The conductive via in these embodiments may enhance the conductivity between the bonding pad and the TSV.

[0049] In addition, in some embodiments, the first hybrid bonding portion 107 may further include a third bonding pad 102', which is electrically disconnected from the memory structure 100. In other words, the third bonding pad 102' is a dummy bonding pad, which is only used for hybrid bonding and is not coupled to the first metal layer 105. Similarly, the second hybrid bonding portion 207 may further include a fourth bonding pad 202', which is electrically disconnected from the control circuit structure 200. The third bonding pad 102' can be used for hybrid bonding to the fourth bonding pad 202' in a subsequent hybrid bonding operation.

[0050] like Figure 4EAs shown, the first wafer 61 is flipped and stacked on the second wafer 62 through a hybrid bonding operation, wherein the first front side 61A faces the second front side 62A, thereby performing a "face-to-face" stacking between the two. In this stacking, the first bonding pad 102 is in contact with the second bonding pad 202 for hybrid bonding and electrical connection; and the third bonding pad 102' is in contact with the fourth bonding pad 202' and is only used for hybrid bonding. In some embodiments, the first wafer 61 and the second wafer 62 are hybrid bonded under appropriate conditions. In some embodiments, the first TSV 104 and the second TSV 204 are formed in the first reserved area 631 and the second reserved area 632, respectively. After the hybrid bonding operation, it can be observed that the first TSV 104 and the second TSV 204 are located on the same side of the first bonding pad 102 and the second bonding pad 202 in the stacking structure.

[0051] Through the hybrid bonding operation, the first wafer 61 and the second wafer 62 are hybrid bonded, and the first bonding layer 101 on the first wafer 61 is connected to the second bonding layer 201 on the second wafer 62, thereby obtaining a first bonded wafer 64. In some embodiments, the first bonded wafer 64 can be subsequently singulated to obtain a plurality of semiconductor structures, wherein each semiconductor structure includes the aforementioned Figure 1A The memory structure 100 and the control circuit structure 200 are shown. In some other embodiments, and as will be described below, Figures 4F to 4G As mentioned, depending on product requirements and the level of current process technology, other additional wafers identical to the first wafer 61 may be bonded to the first bonded wafer 64, i.e., an additional number of memory dies may be stacked on the logic dies on a wafer-to-wafer packaging basis.

[0052] like Figure 4F As shown, in some embodiments, after bonding the first wafer 61 and the second wafer 62, the first wafer 61 is thinned from the first back side 61B to expose the first TSV 104. The thinning operation can be performed by mechanical polishing, chemical mechanical polishing, wet etching, dry etching, or a combination thereof. In some embodiments, the thickness of the first wafer 61 can be thinned to less than 50 microns.

[0053] like Figure 4G As shown, in some embodiments, another first hybrid bonding layer (eg, a fourth hybrid bonding layer 101B shown in the figure) may be formed on the first bonding wafer 64 and electrically connected to the exposed first TSV 104. Figure 4H As shown, in some embodiments, another first wafer (for example, a third wafer 61C having a third hybrid bonding layer 101C as shown in the figure) can be stacked on the first wafer by hybrid bonding operation. Figure 4GAs for the third wafer 61C, before forming the third hybrid bonding layer 101C on the third wafer 61C, a third TSV 104C may be formed on the third wafer 61C adjacent to the first front side 61A.

[0054] The third hybrid bonding layer 101C and the fourth hybrid bonding layer 101B may be connected by a hybrid bonding operation, and a second bonded wafer 65 may be obtained thereby. The second bonded wafer 65 may be thinned to expose the third TSV 104C for another round of stacking operation. That is, the stacking of memory chips is essentially achieved by repeatedly forming a memory wafer similar to the first wafer 61 having the first hybrid bonding layer 101 thereon, and forming the first hybrid bonding layer 101 again, until a total of four or eight wafers are stacked by multiple hybrid bonding operations. In these embodiments, memory wafers similar to the first wafer 61 are stacked in the same direction, in other words, the memory chips of the memory structure are stacked in a "face-to-back" arrangement.

[0055] like Fig. 4I As shown, in some embodiments, a top first wafer 61' may be omitted as described above. Figure 4F The thinning operation shown is performed because the first hybrid bonding layer does not need to be formed above it. Accordingly, a top first TSV 104' may not be exposed to a top first back side 61B' of the top first wafer 61', and the thickness of a top memory die is greater than the thickness of at least one memory die located between the top memory die and the control circuit structure 200. In some embodiments, after the memory die are stacked by hybrid bonding, the second wafer 62 is thinned from the second back side 62B to expose the second TSV 204. The thinning operation can be performed by mechanical grinding, chemical mechanical grinding, wet etching, dry etching, or a combination thereof. In some embodiments, the thickness of the second wafer 62 can be thinned to less than 50 microns.

[0056] like Figure 4J As shown, after the second wafer 62 is thinned from the second back side 62B, a bottom metal layer 209 can be formed on the second back side 62B to electrically connect to the second TSV 204. Next, a second conductive bump connection 401 can be disposed in contact with the bottom metal layer 209 to electrically connect to the interposer 400.

[0057] Before the control circuit structure 200 and the memory structure 100 are stacked on the interposer 400, the stacked second wafer 62 and the first wafer 61 can be singulated to obtain a plurality of wafers as described above. Figure 3 The semiconductor structure shown. Figure 5AAs shown, in some embodiments, the singulation operation of the bonded wafers (i.e., the first bonded wafer 64 or the second bonded wafer 65) includes performing a laser scribing operation. In some embodiments, a laser 70 may be used to cut at least a portion of the stacked wafers. In some embodiments, the unthinned wafers (e.g., Fig. 4I The top first wafer 61' shown can be used as a bulk substrate, and the scribe line 71 formed by laser scribing can stop in the bulk substrate. In some embodiments, a mechanical dicing operation can be followed by the laser scribing operation; for example, Figure 5B As shown, a mechanical saw 72 is used to cut through the bulk substrate of the top first wafer 61' to completely separate the individual memory stacks.

[0058] In some embodiments, the operation of singulating the first wafer and the second wafer may include performing a plasma etching operation. Fig. 6A As shown, a photoresist layer 73 may be disposed on the side of the wafer stack opposite to the bulk substrate of the top first wafer 61', and an anisotropic plasma etch may form a trench on the stack structure that stops at the bulk substrate. Figure 6B As shown, subsequently, a grinding operation may be performed on the bulk substrate of the top first wafer 61' after the plasma etching operation, so as to completely separate the single memory stack. However, this is not a limitation of the present embodiment. In other embodiments, a grinding operation may be performed on the bulk substrate of the top first wafer 61' first, and then a plasma etching operation may be performed on the stacked second wafer 62 and the first wafer 61 to separate the single memory stack.

[0059] By applying the above-mentioned singulation operation, the first wafer 61, the second wafer 62, the first hybrid bonding structure 10 located between the first wafer 61 and the second wafer 62, and the second hybrid bonding structure 20 located between adjacent first wafers 61 can be completely separated to obtain a plurality of semiconductor structures including the above-mentioned structures. Figure 7 As shown, the memory structure 100 has a first side surface 100C', the first hybrid bonding structure 10 has a second side surface 10C, and the control circuit structure 200 has a third side surface 200C; wherein the first side surface 100C', the second side surface 10C, and the third side surface 200C substantially have the characteristics of a continuous line at a cross-sectional angle. In addition, due to the singulation operation, the continuous line may not be perfectly vertical due to the cutting edge generated by laser scribing or plasma etching, which means that in most cases, a tapered groove may be cut to form, so that the continuous line includes a slope. After the cutting is completed, the tapered groove is transformed into a slope that can be observed at the side surfaces of the memory structure 100, the first hybrid bonding structure 10, and the control circuit structure 200.

[0060] like Figure 8 As shown, in some embodiments, the logic die (i.e., the control circuit structure 200) and the memory die 100A, 100B, 100C, 100D may all be arranged "face to back" (Scheme II). In these embodiments, the reserved area for TSV in the logic die is substantially the same as the reserved area for TSV in the memory die, and as mentioned above, the first TSV 104 and the second TSV 204 are located on the same side of a specific pair of bonding pads. In addition, in the embodiment with the stacking arrangement of Scheme II, the second surface 201A shown in the aforementioned FIG. 1 is closer to the front-end process structure of the control circuit structure 200, and farther away from the back-end process structure of the control circuit structure 200.

[0061] Fig.9A and Fig. 9B Demonstrated preparation Figure 8 The steps of semiconductor structure. Fig.9A and Fig. 9B As shown, the second wafer 62 may be thinned on the second back side 62B to expose the second TSV 204 before forming the second hybrid bonding layer 201 thereon. Thereafter, a bottom metal layer 209 may be formed on the second front side 62A to electrically connect to the exposed second TSV 204. Further, in these embodiments, the second wafer 62 is flipped to form the second hybrid bonding layer 201 on the second back side 62B of the second wafer 62, and the second hybrid bonding layer 201 may then be hybrid bonded with the first hybrid bonding layer 101 on the first front side 61A of the first wafer 61. The hybrid bonding operation mentioned here is the same as the hybrid bonding operation described above and is shown in the aforementioned embodiment. Figure 4E For further information on stacking a plurality of additional wafers identical to the first wafer 61 through hybrid bonding, forming the second conductive bump connection portion 401 and wafer dicing operations, please refer to the aforementioned FIG. 4F to FIG. 4J , which is omitted here for brevity.

[0062] like Fig.10 As shown, in some embodiments, each memory structure and control circuit structure is manufactured through a via-middle process; the via-middle process is also referred to as a via-first process in some embodiments. Through the via-middle process, TSV formation is performed after transistor formation and before back-end operations; that is, operations such as via etching and via filling are performed after the front-end structure is formed but before metallization in the back-end stage.

[0063] In these embodiments, the hybrid bonded logic die and memory die can be arranged in the form of the aforementioned schemes I and II. Fig.10 As shown, the logic die (i.e., the control circuit structure 200) and the memory die 100A are stacked in a "face-to-face" arrangement, while the memory die 100A, 100B, 100C, and 100D in the memory structure are stacked in a "face-to-back" arrangement (Scheme I). Because the second TSV 204 in the control circuit structure 200 is formed by a mid-drilling process or a front-drilling process, it is electrically connected to a bottom of a metallization structure 210 in the control circuit structure 200. In the case where the control circuit structure 200 is stacked on the memory die 100A in a "face-to-face" arrangement, the second hybrid bonding layer 201' formed on the second front side 62A of the second wafer can omit the formation of the second metal layer 205 (as described above). Figure 3 ); instead, Fig.11A and Fig. 11B As shown, the second conductive via 208 may be formed near the second front side 62A of the second wafer and contact the top metal 206 of the metallization structure 210. Similarly, the first hybrid bonding layer 101' formed on the first front side 61A of the first wafer may omit the formation of the first metal layer 105 (as described above). Figure 3 instead, the first conductive via 108 may be formed near the second front side 61A of the first wafer and contact the top metal 106 of the metallization structure.

[0064] like Fig.10 As shown, in contrast to the first hybrid bonding layer 101' and the second hybrid bonding layer 201' formed on the front side of the wafer, the first hybrid bonding layer 101 formed on the first back side 61B of the first wafer and the second back side 62B of the second wafer can still respectively have the first metal layer 105 and the bottom metal layer 209 to connect TSV to the corresponding bonding pads. For further information on stacking a plurality of additional wafers identical to the first wafer through hybrid bonding, forming the second conductive bump connection portion 401 and wafer dicing operations, please refer to the aforementioned FIG. 4F to FIG. 4J , which is omitted here for brevity.

[0065] like Fig.12 As shown, in some embodiments, the logic die (i.e., the control circuit structure 200) and the memory die 100A, 100B, 100C, 100D in the memory structure are all formed by a middle drilling process or a front drilling process, and are stacked in a "face-to-back" arrangement (Scheme II). In these embodiments, due to the "face-to-back" arrangement, Fig.13A and Fig. 13BAs shown, the second hybrid bonding layer 201 can be formed on the second back side 62B of the second wafer 62, and includes the second metal layer 205. The second hybrid bonding layer 201 can be used for hybrid bonding to the first hybrid bonding layer 101' formed on the first front side 61A of the first wafer 61, and the first hybrid bonding layer 101' does not include the first metal layer 105. For further information on stacking more first wafers through hybrid bonding, forming the second conductive bump connection portion 401 and the bottom metal layer 209, and the wafer cutting operation, please refer to the above-mentioned FIG. 4F to FIG. 4J , which is omitted here for brevity.

[0066] In some embodiments, the TSV structure of the logic die can be formed by a backside TSV process. Fig.14 As shown, a backside TSV (BTSV) in the control circuit structure 200 is formed after the control circuit structure 200 and the memory die 100A are stacked in a "face-to-face" arrangement, while the memory die 100A, 100B, 100C, and 100D in the memory structure are stacked in a "face-to-back" arrangement (Scheme I). Fig.15A , Fig. 15B and Fig. 15C In some embodiments, after the control circuit structure 200 and the memory chips 100A, 100B, 100C, 100D are stacked by hybrid bonding (eg, Fig.15A ), the second wafer 62 is then thinned from its second back side 62B (eg Fig. 15B ). In some embodiments, the second wafer 62 is thinned so that the thickness between the first metal layer 2102 (e.g., the bottom metal layer in the figure) and the second back side 62B of the second wafer in the back-end process structure of the second wafer 62 is less than about 10 microns. Subsequently, a through hole etching and a through hole filling operation are performed on the second back side 62B of the second wafer 62 to form a BTSV 211, which is electrically connected to the metallization structure 210. For further details on stacking the first wafer through hybrid bonding, forming the second conductive bump connection portion 401 and the bottom metal layer 209, and the wafer cutting operation, please refer to the aforementioned FIG. 4F to FIG. 4J , which is omitted here for brevity.

[0067] like Fig.10 , Fig.12 and Fig.14 As shown, in some embodiments, the second TSV 204 is substantially a semi-through via, one end of which is in contact with a back-end process structure, such as a back-end process metal line.

[0068] In short, based on the above-mentioned embodiments, the process efficiency of forming a memory stack can be significantly improved, and the risk of stacking defects caused by micro-bump operations is also greatly reduced. In addition, compared with the existing process, the present disclosure uses a large number of bonding pads to connect the memory structure and the control circuit structure, and uses a large number of bonding pads to connect the memory structure, which can also increase the memory access bandwidth of the existing memory system.

[0069] In an exemplary embodiment, the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first hybrid bonding structure, a memory structure and a control circuit structure. The first hybrid bonding structure has a first surface and a second surface. The memory structure contacts the first surface. The control circuit structure is used to control the memory structure, and the control circuit structure contacts the second surface.

[0070] In another exemplary embodiment, the present disclosure provides a system-level packaging structure. The system-level packaging structure includes a first semiconductor structure, a second semiconductor structure and a substrate. The first semiconductor structure has a first critical dimension. The second semiconductor structure is stacked with the first semiconductor structure. The second semiconductor structure has a second critical dimension and is in contact with the first semiconductor structure via a hybrid bonding interface. The substrate is electrically connected to the first semiconductor structure and the second semiconductor structure via a first conductive bump. The first critical dimension is different from the second critical dimension.

[0071] In another exemplary aspect, the present disclosure provides a method for manufacturing a plurality of semiconductor structures, which comprises the following steps: a first hybrid bonding layer is formed on a first wafer having a plurality of first memory structures; a second hybrid bonding layer is formed on a second wafer having a plurality of control circuit structures; the first wafer and the second wafer are bonded via a first hybrid bonding step to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer; and at least the first wafer, the second wafer, the first hybrid bonding layer, and the second hybrid bonding layer are singulated to obtain a plurality of semiconductor structures.

[0072] The foregoing content summarizes the structures of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0073] Explanation of symbols

[0074] 10: First hybrid bonding structure

[0075] 10C: Second side surface

[0076] 20: Second hybrid bonding structure

[0077] 61: First Wafer

[0078] 61': Top first wafer

[0079] 61A: First front

[0080] 61B: First back

[0081] 61B': Top First Back

[0082] 62: Second Wafer

[0083] 62A: Second front

[0084] 62B: Second back

[0085] 64: First Bonded Wafer

[0086] 65: Second bonding wafer

[0087] 70: Laser

[0088] 71: Cutting Road

[0089] 72: Mechanical saw

[0090] 73: Photoresist layer

[0091] 80:Semiconductor structure

[0092] 81: Positive

[0093] 82: Back

[0094] 83:Semiconductor substrate

[0095] 84: Front-end process structure

[0096] 85: Back-end process structure

[0097] 100: Memory structure

[0098] 100': first semiconductor structure

[0099] 100A:Memory chip

[0100] 100B: memory die

[0101] 100C: Memory die

[0102] 100C': first side surface

[0103] 100D: Memory die

[0104] 101: first hybrid bonding layer

[0105] 101': first hybrid bonding layer

[0106] 101A: First surface

[0107] 101B: Fourth hybrid bonding layer

[0108] 101C: Third hybrid bonding layer

[0109] 102: first bonding pad

[0110] 102': third bonding pad

[0111] 103: first oxide portion

[0112] 104: First TSV

[0113] 104': Top 1st TSV

[0114] 104C: Third TSV

[0115] 105: First metal layer

[0116] 106: Top Metal

[0117] 107: first hybrid bonding part

[0118] 108: first conductive via

[0119] 200: Control circuit structure

[0120] 200': second semiconductor structure

[0121] 200C: third side surface

[0122] 201: second hybrid bonding layer

[0123] 201': second hybrid bonding layer

[0124] 201A: Second surface

[0125] 202: Second bonding pad

[0126] 202': fourth bonding pad

[0127] 203: Second oxide part

[0128] 204: Second TSV

[0129] 205: Second metal layer

[0130] 206: Top Metal

[0131] 207: Second hybrid bonding part

[0132] 208: second conductive via

[0133] 209: Bottom metal layer

[0134] 210:Metalized structure

[0135] 2102: First metal layer

[0136] 211:BTSV

[0137] 300: Third semiconductor structure

[0138] 400:Intermediary board

[0139] 401: second conductive bump connection portion

[0140] 500:Substrate

[0141] 501: first conductive bump connection portion

[0142] 631: First reserved area

[0143] 632: Second reserved area

[0144] 1201: Hybrid Bonding Interface

Claims

1. A semiconductor structure comprising: a first hybrid bonding structure having a first surface and a second surface; a DRAM structure contacting the first surface, the DRAM structure comprising a plurality of DRAM memory dies stacked vertically; and a control circuit structure for controlling the plurality of DRAM memory dies of the DRAM structure and contacting the second surface; The second surface is a front-end process structure closer to the control circuit structure and a back-end process structure farther away from the control circuit structure, and The DRAM structure and the control circuit structure are vertically bonded via the first hybrid bonding structure.

2. The semiconductor structure as claimed in claim 1, wherein at least two DRAM dies are hybrid-bonded via a second hybrid bonding structure.

3. The semiconductor structure of claim 2, wherein a thickness of a top DRAM die of the DRAM die is greater than a thickness of one of the DRAM die disposed between the top DRAM die and the control circuit structure.

4. The semiconductor structure of claim 1, wherein the DRAM structure has a first side surface, the first hybrid bonding structure has a second side surface, and the control circuit structure has a third side surface, and the first side surface, the second side surface and the third side surface substantially form a continuous line at a cross-sectional viewing angle.

5. The semiconductor structure of claim 1, wherein the DRAM structure further comprises a first through via, and the control circuit structure further comprises a second through via, and the first hybrid bonding structure comprises: a first hybrid bonding portion having a plurality of first conductive vias and a first bonding pad, wherein the first through-via is coupled to a plurality of first ends of the first conductive vias, and the first bonding pad is in contact with a plurality of second ends of the first conductive vias; and A second hybrid bonding portion has a plurality of second conductive vias and a second bonding pad, wherein the second bonding pad is in contact with the first bonding pad, the second through-hole is coupled to a plurality of first ends of the second conductive vias, and the second bonding pad is in contact with a plurality of second ends of the second conductive vias.

6. The semiconductor structure of claim 5, wherein the first hybrid bonding portion further comprises a third bonding pad, and the second hybrid bonding portion further comprises a fourth bonding pad contacting the third bonding pad, wherein: The third bonding pad and the fourth bonding pad are electrically disconnected from the DRAM structure and the control circuit structure. 7 . The semiconductor structure as claimed in claim 5 , wherein the second through via is a half through via, one end of which contacts a back-end-of-line metal line.

8. A system-level packaging structure, comprising: a first semiconductor structure comprising a DRAM structure having a first critical dimension, wherein the DRAM structure comprises a plurality of DRAM memory dies stacked vertically; a second semiconductor structure stacked with the first semiconductor structure, comprising a control circuit structure for controlling the plurality of DRAM memory dies of the DRAM structure, having a second critical dimension and contacting the first semiconductor structure via a hybrid bonding interface, the second semiconductor structure having a front-end-of-line structure closer to the hybrid bonding interface, and a back-end-of-line structure farther from the hybrid bonding interface; and a substrate electrically connected to the first semiconductor structure and the second semiconductor structure through a first conductive bump; in, The first critical dimension is different from the second critical dimension.

9. The system-in-package structure of claim 8, further comprising: a third semiconductor structure having a second conductive bump electrically connected to the first semiconductor structure and the second semiconductor structure, wherein the third semiconductor structure has a third critical dimension smaller than the first critical dimension; and An intermediate board supports the first semiconductor structure, the second semiconductor structure and the third semiconductor structure and is connected to the substrate.

10. The system-level package structure as described in claim 8 further comprises a first bonding pad located at the hybrid bonding interface, which contacts a second bonding pad at the hybrid bonding interface, wherein the first bonding pad is electrically connected to a first through silicon via of the first semiconductor structure, and the second bonding pad is electrically connected to a second through silicon via of the second semiconductor structure. 11 . The system-in-package structure as claimed in claim 8 , wherein the first critical dimension is smaller than the second critical dimension.

12. A method of manufacturing a plurality of semiconductor structures, the method comprising: forming a first hybrid bonding layer on a first wafer having a plurality of first DRAM structures, each of the plurality of first DRAM structures comprising a first DRAM memory die; forming a second hybrid bonding layer on a second wafer having a plurality of control circuit structures, wherein the plurality of control circuit structures are used to control the plurality of first DRAM structures on the first wafer; Bonding the first wafer to a side of the second wafer closer to each of the plurality of control circuit structure front-end process structures through a first hybrid bonding step, so that a side of the second wafer closer to each of the plurality of control circuit structure back-end process structures is farther away from the first wafer, so as to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer; forming a third hybrid bonding layer on a third wafer having a plurality of second DRAM structures, each of the plurality of second DRAM structures comprising a second DRAM memory die; forming a fourth hybrid bonding layer on the first bonding wafer; Bonding the third wafer and the first bonded wafer through a second hybrid bonding step to connect the third hybrid bonding layer and the fourth hybrid bonding layer, thereby obtaining a second bonded wafer, wherein the plurality of first DRAM memory dies and the plurality of second DRAM memory dies are vertically stacked in the second bonded wafer; and The second bonded wafer is singulated to obtain a plurality of semiconductor structures, each of which includes the vertically stacked first DRAM memory die, the second DRAM memory die, and the control circuit structure for controlling the first DRAM memory die and the second DRAM memory die.

13. The method of claim 12, further comprising: Before forming the first hybrid bonding layer on the first wafer, forming a first through hole adjacent to a front surface of the first wafer, wherein the first hybrid bonding layer is formed on the front surface of the first wafer; Before forming the second hybrid bonding layer on the second wafer, forming a second through hole adjacent to a front surface of the second wafer, wherein the second hybrid bonding layer is formed on the front surface of the second wafer; After bonding the first wafer and the second wafer and before forming the fourth hybrid bonding layer on the first bonded wafer, thinning the first wafer from a back side of the first wafer to expose the first through hole; Before forming the third hybrid bonding layer on the third wafer, forming a third through hole adjacent to a front surface of the third wafer; and The second wafer is thinned from a back side of the second wafer to expose the second through hole.

14. The method of claim 12, further comprising: Before forming the first hybrid bonding layer on the first wafer, forming a first through hole adjacent to a front surface of the first wafer; Before forming the third hybrid bonding layer on the third wafer, forming a second through hole adjacent to a front surface of the third wafer; After bonding the first wafer and the second wafer and before bonding the third wafer and the first bonded wafer, thinning the first wafer from a back side of the first wafer to expose the first through hole; After bonding the third wafer and the first bonded wafer, thinning the first bonded wafer from a back side of the second wafer to form a thinned second wafer; and A third through hole is formed in the thinned second wafer.

15. The method of claim 12, further comprising: Before forming the first hybrid bonding layer on the first wafer, forming a first through hole adjacent to a front surface of the first wafer, wherein the first hybrid bonding layer is formed on the front surface of the first wafer; forming a second through hole adjacent to a front surface of the second wafer; Before forming the second hybrid bonding layer on the second wafer, thinning the second wafer from a back side of the second wafer to expose the second through hole, wherein the second hybrid bonding layer is formed on the back side of the second wafer; and Before forming the third hybrid bonding layer on the third wafer, a third through hole is formed adjacent to a front surface of the third wafer.

16. The method of claim 12, wherein at least the step of singulating the second bonded wafer comprises: performing a laser scribing operation; and A mechanical cutting operation is performed subsequent to the laser scribing operation.

17. The method of claim 12, wherein at least the step of singulating the second bonded wafer comprises: performing a plasma etching operation; and A grinding operation is performed.

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