Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate, a fin-shaped structure having a fin top surface disposed on the substrate, a source / drain (S / D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer having first and second spacer portions disposed between the gate structure and the source / drain region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the source / drain region.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling down increases the complexity of the semiconductor manufacturing process. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, there is provided a semiconductor device, comprising: a substrate; a fin structure having a fin top surface disposed on the substrate; a source / drain (S / D) region disposed on the fin structure; a gate structure disposed on the fin top surface; and a gate spacer having a first spacer portion and a second spacer portion disposed between the gate structure and the source / drain region.

[0004] Wherein, the first spacer portion extends above the top surface of the fin and is disposed along the sidewall of the gate structure, and wherein the second spacer portion extends below the top surface of the fin and is disposed along the sidewall of the source / drain region.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a substrate; a fin structure having a fin top surface disposed on the substrate; a source / drain (S / D) region disposed within the fin structure; a gate structure disposed on the fin top surface; and a gate spacer having a first spacer portion and a second spacer portion disposed between the gate structure and the source / drain region.

[0006] wherein the first spacer portion is a non-tapered structure and extends above the top surface of the fin, and wherein the second spacer portion is a tapered structure and is disposed within the fin structure.

[0007] According to another aspect of an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a fin structure having a fin top surface on a substrate; forming a first polysilicon structure and a second polysilicon structure on the fin top surface; forming a spacer opening in the fin structure and between the first polysilicon structure and the second polysilicon structure; forming a gate spacer; forming a source / drain region between the first polysilicon structure and the second polysilicon structure; and replacing the first polysilicon structure and the second polysilicon structure with a first gate structure and a second gate structure.

[0008] The forming of the gate spacer includes: forming a first spacer portion of the gate spacer along a sidewall of the first polysilicon structure, and forming a second spacer portion of the gate spacer in a spacer opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures.

[0010] Figure 1A An isometric view of a semiconductor device in accordance with some embodiments is shown.

[0011] Figure 1B-Figure 1D A cross-sectional view of a semiconductor device having extended gate spacers is shown in accordance with some embodiments.

[0012] Figure 2 is a flow chart of a method for fabricating a semiconductor device having extended gate spacers according to some embodiments.

[0013] Figure 3-Figure 4 , Figures 5A-12B and Figure 13-Figure 14 Isometric and cross-sectional views of a semiconductor device with extended gate spacers at various stages of its fabrication process are shown in accordance with some embodiments.

[0014] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. Unless otherwise noted, the discussion of elements with the same annotations applies to each other. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular component, structure, or feature, but each embodiment may not necessarily include the particular component, structure, or feature. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular component, structure, or feature is described in conjunction with an embodiment, whether or not explicitly described, it would be within the knowledge of those skilled in the art to implement such component, structure, or feature in conjunction with other embodiments.

[0018] It should be understood that the terms and phrases herein are for the purpose of description rather than limitation, so that those skilled in the relevant art can understand the terms and phrases of this specification based on the teachings of this specification.

[0019] In some embodiments, the terms "about" and "substantially" may mean that the value of a given amount varies within 5% of the value (e.g., values ​​of ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are examples only and are not limiting. The terms "about" and "substantially" may refer to percentages of values ​​interpreted by a person skilled in the relevant art based on the teachings herein.

[0020] The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. The double patterning or multiple patterning processes may combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure.

[0021] The present disclosure provides an example semiconductor device (e.g., finFET) having an extended gate spacer in a gate structure and an example method of forming such a semiconductor device. The extended gate spacer improves the sidewall profile of the epitaxial source / drain (S / D) region and prevents the epitaxial S / D region from extending into the gate structure region during the manufacturing process to avoid electrical short circuits between the epitaxial S / D region and the gate structure.

[0022] In some embodiments, a gate structure is disposed on a fin structure of a semiconductor device, and an epitaxial S / D region is grown in an etched region of the fin structure. The gate structure is separated from the epitaxial source / drain region by an extended gate spacer disposed along the sidewall of the gate structure. In some embodiments, a first spacer portion of the extended gate spacer is disposed on a fin top surface of the fin structure, and a second spacer portion of the extended gate spacer is disposed in the fin structure. The first spacer portion may have a non-tapered structure, and the second spacer portion may have a tapered structure. The first spacer portion may protect the gate structure during subsequent processing of adjacent structures. The second spacer portion may control the etching profile of the source / drain opening formed in the fin structure for growing the epitaxial source / drain region in the source / drain opening. As a result, the second spacer portion controls the sidewall profile of the epitaxial S / D region grown in the S / D opening and prevents the epitaxial S / D region from extending into the gate structure region.

[0023] Figure 1A An isometric view of a semiconductor device 100 having FETs 102A and 102B according to some embodiments is shown. In some embodiments, the FETs 102A and 102B may represent n-type FETs 102A and 102B (NFETs 102A and 102B) or p-type FETs 102A and 102B (PFETs 102A and 102B). Unless otherwise noted, the discussion of FETs 102A and 102B applies to both NFETs 102A and 102B and PFETs 102A and 102B. Figure 1B and Figure 1C Shown along Figure 1A A cross-sectional view of FET 102A taken along line AA. Figure 1D The diagram shows the Figure 1A BB is a cross-sectional view of FET 102B. For simplicity, Figure 1B-Figure 1D A cross-sectional view of a semiconductor device 100 is shown, wherein the semiconductor device 100 has a Figure 1A Unless otherwise noted, the discussion of elements of FETs 102A and 102B having the same annotations applies to each other.

[0024] refer to Figure 1A, the FETs 102A and 102B may include an array of gate structures 112A and 112B disposed on the respective fin structures 106A and 106B, and an array of epitaxial S / D regions 110A and 110B disposed on portions of the respective fin structures 106A and 106B that are not covered by the respective gate structures 112A and 112B. The FETs 102A and 102B may also include gate spacers 114A-114B and 115A-115B (also referred to as extended gate spacers 114A-114B and 115A-115B), a shallow trench isolation (STI) region 116, an etch stop layer (ESL) 117, and an interlayer dielectric (ILD) layer 118. The ILD layer 118 may be disposed on the ESL 117. In some embodiments, the gate spacers 114A- 114B and 115A- 115B, the STI region 116 , the ESL 117 , and the ILD layer 118 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), and silicon germanium oxide.

[0025] FETs 102A and 102B may be formed on substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed on substrate 104. Substrate 104 may be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, substrate 104 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, fin structures 106A-106B may include materials similar to substrate 104 and extend along the X-axis. In some embodiments, fin structures 106A and 106B may have similar dimensions.

[0026] refer to Figure 1B FET 102A may include a gate structure 112A disposed on the fin top surface 106At, an epitaxial S / D region 110A disposed within the fin structure 106A, and a gate structure 112A disposed on the fin top surface 106At. Figure 1B 1 ), and gate spacers 114A and 114B. The gate structure 112A may be a multilayer structure and may have a gate pitch GP1. The gate pitch is defined as the sum of the distance along the X-axis between adjacent gate structures (e.g., gate structure 112A) having equal gate lengths (e.g., gate length GL1) and the gate length of one of the adjacent gate structures. Each gate structure 112A may include an interfacial oxide (IO) layer 120, a high-k (HK) gate dielectric layer 122 disposed on the IO layer 120, a work function metal (WFM) layer 124 disposed on the HK gate dielectric layer 122, and a gate metal fill layer 126 disposed on the WFM layer 124.

[0027] The IO layer 120 may include silicon oxide (SiO2), silicon germanium oxide (SiGeO x ) or germanium oxide (GeO x The HK gate dielectric layer 122 may include (i) a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and (ii) a dielectric material having lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium ( The invention relates to a high-k dielectric material of an oxide of yttrium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), (iii) other suitable high-k dielectric materials, or (iv) combinations thereof. As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (e.g., greater than 3.9).

[0028] For the NFET 102A, the WFM layer 124 may include a metal material having a work function value closer to a conduction band energy than a valence band energy of a material of the fin structure 106A. For example, the WFM layer 124 may include an Al-based or Al-doped metal material having a work function value less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which may be closer to a conduction band energy (e.g., 4.1 eV Si or 3.8 eV SiGe) than a valence band energy (e.g., 5.2 eV Si or 4.8 eV SiGe) of a Si-based or SiGe-based fin structure 106A. In some embodiments, the WFM layer 124 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium (Ti), aluminum-doped titanium nitride (TiN), Al-doped tantalum (Ta), Al-doped tantalum nitride (TaN), other suitable Al-based materials, or combinations thereof.

[0029] For the PFET 102A, the WFM layer 124 may include a metal material having a work function value closer to a valence band edge energy than a conduction band edge energy of the material of the fin structure 106A. For example, the WFM layer 124 may include a substantially Al-free (e.g., Al-free) metal material having a work function value equal to or greater than 4.5 eV (e.g., about 4.5 eV to about 5.5 eV), which may be closer to a conduction band edge energy (e.g., 4.1 eV Si or 3.8 eV SiGe) than a valence band edge energy (e.g., 5.2 eV Si or 4.8 eV SiGe) of a Si-based or SiGe-based fin structure 106A. In some embodiments, the WFM layer 124 may include a substantially Al-free (e.g., Al-free) Ti-based or Ta-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, tantalum copper (Ta-Cu), and combinations thereof.

[0030] The gate metal fill layer 126 may include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. In some embodiments, the gate metal fill layer 126 may include a substantially fluorine-free metal layer (e.g., fluorine-free W). The substantially fluorine-free metal layer may include an amount of fluorine contaminants in ionic, atomic, and / or molecular form less than about 5 atomic percent. In some embodiments, the gate structure 112A may be electrically isolated from an overlying interconnect structure (not shown) by a gate cap layer (not shown), which may include a dielectric nitride layer.

[0031] For NFET 102A, epitaxial S / D region 110A may include epitaxially grown semiconductor material such as Si, and n-type dopants such as phosphorus and other suitable n-type dopants. For PFET 102A, epitaxial S / D region 110A may include epitaxially grown semiconductor material such as Si and SiGe, and p-type dopants such as boron and other suitable p-type dopants.

[0032] In some embodiments, the gate spacers 114A and 114B may include first spacer portions 128A and 130A, and second spacer portions 128B and 130B. The first spacer portions 128A and 130A protect the gate structure 112A during subsequent processing of adjacent structures, such as the ESL 117, the ILD layer 118, and the S / D contact structure (not shown) on the epitaxial S / D region 110A. The second spacer portions 128B and 130B control the S / D openings 1042 ( Fig. 10A 1042) for subsequent growth of the epitaxial S / D region 110A in the S / D opening 1042, which will be described in detail below. As a result, the second spacer portions 128B and 130B control the sidewall profile of the epitaxial S / D region 110A and prevent the epitaxial S / D region 110A from extending into the region of the fin structure 106A below the gate structure 112A. Figure 1B As shown, the epitaxial S / D region 110A has substantially vertical sidewalls along the Z-axis and is separated from the gate structure 112A by distances D1 and D2 due to the second spacer portions 128B and 130B. The distances D1 and D2 may be the distances between adjacent sidewalls of the gate structure 112A and adjacent sidewalls of the portion of the epitaxial S / D region 110A extending below the second spacer portions 128B and 130B. In some embodiments, the distances D1 and D2 may be equal to or different from each other and may be in a range from about 1 nm to about 15 nm. If the distances D1 and D2 are less than about 1 nm, dopants and / or other materials may diffuse from the epitaxial S / D region 110A into the gate structure 112A, which may degrade device performance. On the other hand, if the distances D1 and D2 are greater than 15 nm, the device size and manufacturing costs may increase.

[0033] The first spacer portions 128A and 130A extend above the fin top surface 106At and may have a non-tapered structure. The first spacer portions 128A and 130A may have thicknesses T1 and T2, respectively, which may be equal to or different from each other and may be in the range of about 1 nm to about 10 nm to adequately protect the gate structure 112A without affecting device size and manufacturing cost. In some embodiments, the distances D1 and D2 may be equal to or different from the respective thicknesses T1 and T2.

[0034] The second spacer portions 128B and 130B extend below the fin top surface 106At by distances D3 and D4 that may be equal or different from each other. The second spacer portions 128B and 130B may have a tapered structure in which the first sidewall and the second sidewall face each other. The first sidewalls of the second spacer portions 128B and 130B are adjacent to the epitaxial S / D region 110A and form angles A and B with the fin top surface 106At. The second sidewalls of the second spacer portions 128B and 130B are adjacent to the fin structure 106A and form angles C and D with the fin top surface 106At. Angles A and B are also formed between the sidewalls of the epitaxial S / D region 110A and the fin top surface 106At.

[0035] In order to adequately control the sidewall profile of the epitaxial S / D region 110A without affecting the device size and manufacturing cost, the distances D3 and D4 range from about 1 nm to about 10 nm, and the angles A and B range from about 15 degrees to about 90 degrees. In addition, in order to adequately control the sidewall profile of the epitaxial S / D region 110A, the values ​​of the thicknesses T1 and T2, the distances D3 and D4, and the angles A and B may be limited by the following conditions: (i) the difference between the thicknesses T1 and T2 is between about 10 nm and about -10 nm, (ii) the difference between the distances D3 and D4 is between about 10 nm and about -10 nm, (iii) the difference between the thickness T1 and the distance D3 is between about 10 nm and about -10 nm, (iv) the difference between the thickness T2 and the distance D4 is between about 10 nm and about -10 nm, and (v) the difference between the angles A and B is equal to 0 degrees or between about 0 degrees and about 60 degrees.

[0036] In some embodiments, angles C and D are less than corresponding angles A and B and may be in a range from about 30 degrees to about 60 degrees. In some embodiments, the ratio between angles A and C and the ratio between angles B and D may be about 2:1. In some embodiments, epitaxial S / D region 110A extends a distance H1 below second spacer portions 128B and 130B along the Z-axis and extends a distance H2 above second spacer portions 128B and 130B along the Z-axis. In some embodiments, distance H1 is greater than distances H2, D3, and D4, and distance H2 is less than distances D3 and D4.

[0037] In some embodiments, if the angles A and B are less than about 90 degrees (eg, the angles A and B are between about 60 degrees and about 90 degrees), the second spacer portions 128B and 130B and the epitaxial S / D region 110A may have a shape as shown in FIG. Figure 1C The cross-sectional structure shown is not Figure 1B . In this case, the second spacer portions 128B and 130B extend below the fin top surface 106At by distances D7 and D8, and the distances D7 and D8 are shorter than the distances D3 and D4. In addition, the distances between the adjacent sidewalls of the gate structure 112A and the adjacent sidewalls of the portions of the epitaxial S / D region 110A extending below the second spacer portions 128B and 130B are distances D5 and D6, and the distances D5 and D6 are shorter than the distances D1 and D2 and the thicknesses T1 and T2. Since the etching profile is controlled by the second spacer portions 128B and 130B during the formation of the S / D openings 1042, these portions of the epitaxial S / D region 110A extending below the second spacer portions 128B and 130B can have substantially vertical sidewalls along the Z-axis (refer to Fig. 10AOn the other hand, a portion of the epitaxial S / D region 110A adjacent to the second spacer portions 128B and 130B may have an inclined sidewall, forming angles A and B between the inclined sidewall of the epitaxial S / D region 110A and the fin top surface 106At.

[0038] Similar to distances D3 and D4, the values ​​of distances D7 and D8 can be limited by the following conditions: (i) the difference between distances D7 and D8 is between about 10 nm and about -10 nm, (ii) the difference between thickness T1 and distance D7 is between about 10 nm and about -10 nm, and (iii) the difference between thickness T2 and distance D8 is between about 10 nm and about -10 nm.

[0039] refer to Figure 1D FET 102B may include a gate structure 112B disposed on the fin top surface 106Bt, an epitaxial S / D region 110B disposed within the fin structure 106B ( Figure 1D ), and gate spacers 115A and 115B. Unless otherwise noted, the discussion of gate structure 112A and epitaxial S / D region 110A applies to gate structure 112B and epitaxial S / D region 110B. Each gate structure 112B may include an IO layer 120, a HK gate dielectric layer 122 disposed on the IO layer 120, a WFM layer 124 disposed on the HK gate dielectric layer 122, and a gate metal fill layer 126 disposed on the WFM layer 124. The gate structure 112B may have a gate length GL1 similar to the gate structure 112A and may have a gate pitch GP2 that is approximately 2 times to about 5 times greater than GP1 of the gate structure 112A. Although similar operations may be used (see below), Figure 2 FETs 102A and 102B are formed simultaneously on substrate 104, but due to different gate pitches GP1 and GP2 resulting in different spacings between gate structures 112A and between gate structures 112B, the size of epitaxial S / D region 110B and gate spacers 115A and 115B may be different from the size of epitaxial S / D region 110A and gate spacers 114A and 114B. Due to the larger gate pitch GP2, epitaxial S / D region 110B may be wider along the X-axis than epitaxial S / D region 110A.

[0040] Similar to the gate spacers 114A and 114B, the gate spacers 115A and 115B include first spacer portions 132A and 134A and second spacer portions 132B and 134B. The first spacer portions 132A and 134A protect the gate structure 112B during subsequent processing of adjacent structures, such as the ESL 117, the ILD layer 118, and the S / D contact structure (not shown) on the epitaxial S / D region 110B. The second spacer portions 132B and 134B control the etch profile of the S / D opening (not shown) formed in the fin structure 106B for subsequent growth of the epitaxial S / D region 110B in the S / D opening. As a result, the second spacer portions 132B and 134B control the sidewall profile of the epitaxial S / D region 110B and prevent the epitaxial S / D region 110B from extending into the region of the fin structure 106B below the gate structure 112B. Figure 1D As shown, the epitaxial S / D region 110B has substantially vertical sidewalls along the Z-axis and is separated from the gate structure 112B by distances D9 and D10 due to the second spacer portions 132B and 134B. The distances D9 and D10 may be the distances between adjacent sidewalls of the gate structure 112B and adjacent sidewalls of the portion of the epitaxial S / D region 110B extending under the second spacer portions 132B and 134B. In some embodiments, the distances D9 and D10 may be equal to or different from each other and may be in the range of about 1 nm to about 15 nm, similar to the distances D1 and D2 of the FET 102A.

[0041] The first spacer portions 132A and 134A extend above the fin top surface 106Bt and may have a non-tapered structure. The first spacer portions 132A and 134A may have thicknesses T3 and T4, respectively, which may be equal to or different from each other and may be in a range of about 1 nm to about 10 nm to adequately protect the gate structure 112B without affecting device size and manufacturing cost. In some embodiments, the distances D9 and D10 may be equal to or different from the respective thicknesses T3 and T4. In some embodiments, the thicknesses T3 and T4 may be greater than the corresponding thicknesses T1 and T2 of the first spacer portions 128A and 130A because during the formation of the gate spacers 114A-114B and 115A-115B, a thicker spacer material may be deposited in a wider spacing between the gate structures 112B than in a narrower spacing between the gate structures 112A.

[0042] The second spacer portions 132B and 134B extend below the fin top surface 106Bt by distances D11 and D12, respectively, which may be equal to or different from each other. In some embodiments, the distances D11 and D12 may be shorter than the corresponding distances D3 and D4 of the second spacer portions 128A and 130A. This difference in distance may be due to the spacer openings 740 and 1340 (see, respectively, FIG. 1 ) in which the gate spacers 114A-114B and 115A-115B are formed. Fig. 7A and Fig.13 106B between the gate structures 112A. The spacer openings 1340 formed by etching the fin structure 106B between the gate structures 112B may have a smaller radius of curvature than the spacer openings 740 formed simultaneously in the same operation by etching the fin structure 106A between the gate structures 112A. Due to the smaller radius of curvature of the spacer openings 1340, the distances D11 and D12 that the second spacer portions 132B and 134B extend into the fin structure 106B are shorter than the distances D3 and D4 of the second spacer portions 128B and 130B. The difference in the radius of curvature of the spacer openings 740 and 1340 may be due to the inverse relationship between the width of the etched area and the radius of curvature of the etched area. Since the spacer openings 1340 between the gate structures 112B are wider than the spacer openings 740 between the gate structures 112A, the radius of curvature of the spacer openings 1340 is smaller than the radius of curvature of the spacer openings 740.

[0043] Similar to the second spacer portions 128B and 130B, the second spacer portions 132B and 134B may have a tapered structure in which a first sidewall and a second sidewall face each other. The first sidewalls of the second spacer portions 132B and 134B are adjacent to the epitaxial S / D region 110B and form angles E and F with the fin top surface 106Bt. The second sidewalls of the second spacer portions 132B and 134B are adjacent to the fin structure 106B and form angles G and H with the fin top surface 106Bt. Angles E and F are also formed between the sidewalls of the epitaxial S / D region 110B and the fin top surface 106Bt.

[0044] In order to adequately control the sidewall profile of the epitaxial S / D region 110B without affecting the device size and manufacturing cost, the distances D11 and D12 range from about 1 nm to about 10 nm, and the angles E and F range from about 15 degrees to about 90 degrees. Similar to the second spacer portions 128B and 130B, the values ​​of the thicknesses T3 and T4, the distances D11 and D12, and the angles E and F may be constrained by the following conditions: (i) the difference between the thicknesses T3 and T4 is between about 10 nm and about -10 nm, (ii) the difference between the distances D11 and D12 is between about 10 nm and about -10 nm, (iii) the difference between the thickness T3 and the distance D11 is between about 10 nm and about -10 nm, (iv) the difference between the thickness T4 and the distance D12 is between about 10 nm and about -10 nm, and (v) the difference between the angles E and F is equal to 0 degrees or between about 0 degrees and about 60 degrees. In addition, the values ​​of thicknesses T1 and T4, and the values ​​of distances D3 and D4 and D11 and D12 can be constrained by the following conditions: (i) the difference between thicknesses T3 and T4 and the difference between thicknesses T1 and T2 is between about 10 nm and about -10 nm, and (ii) the difference between distances D11 and D12 and the difference between distances D3 and D4 is between about 10 nm and about -10 nm.

[0045] In some embodiments, angles G and H are less than corresponding angles E and F, and may range from about 30 degrees to about 60 degrees. In some embodiments, the ratio between angles E and G and the ratio between angles F and H may be about 2:1.

[0046] Figure 2 According to some embodiments, a method for manufacturing a Figure 1B 1. For purposes of illustration, reference will be made to a flow chart of an example method 200 for manufacturing a FET 102A in cross section as shown. Figure 3-Figure 4 and Figures 5A-12B An example manufacturing process of FET 102A is shown to describe Figure 2 The operation shown. Figure 3-Figure 4 and Figures 5A-12B According to various embodiments, at various stages of manufacture, Figure 1A 1 and 10. The FET 102A is an isometric view and a cross-sectional view of lines AA and CC. The operations may be performed in a different order, or not performed, depending on the particular application. It should be noted that method 200 may not produce a complete FET 102A. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes may only be briefly described herein. Figure 3-Figure 4 and Figures 5A-12B With the above description Figure 1A-Figure 1CAlthough method 200 describes operations for fabricating FET 102A, similar operations may be performed to fabricate FET 102B on the same substrate 104 concurrently with FET 102A.

[0047] In operation 205, a fin structure is formed on a substrate. Figure 3 As shown, fin structure 106A is formed on substrate 104. The formation of fin structure 106A may include using a photolithography patterning process on substrate 104. Similar operations may be performed simultaneously on substrate 104 to form fin structure 106B. After forming fin structure 106A, STI region 116 may be formed, as shown in FIG. Figure 3 shown.

[0048] refer to Figure 2 In operation 210, a polysilicon structure is formed on the fin structure. Figure 4 and Figures 5A-6B As shown, the polysilicon structure 612 is formed on the fin structure 106A. The formation of the polysilicon structure 612 may include the following sequential operations: (i) Figure 3 A polysilicon layer 412 is deposited on the structure, such as Figure 4 As shown, (ii) a hard mask 435 is deposited on the polysilicon layer 412, as shown in FIG. Figure 4 As shown, (iii) a mask layer 436 is deposited on the hard mask 435, as shown in FIG. Figure 4 As shown, (iv) forming a pattern mask layer 536, as shown Figure 5A As shown, and (v) etching the hard mask 435 and the polysilicon layer 412 through the patterned mask layer 536 to form a polysilicon structure 612 having a gate pitch GP1, as shown Figure 6A-6B Although similar operations may be performed simultaneously on the fin structure 106B to form a similar polysilicon structure 612 on the fin structure 106B, a different mask pattern is used to form the polysilicon structure on the fin structure 106B to achieve the gate pitch GP2 of the FET 102B.

[0049] refer to Figure 2 In operation 215, a gate spacer is formed, wherein a first spacer portion is along a sidewall of the polysilicon structure and a second spacer portion is located within the fin structure. Figures 7A-9B As described, the gate spacers 114A and 114B are formed with first spacer portions 128A and 130A along the sidewalls of the polysilicon structure 612 and second spacer portions 128B and 130B within the fin structure 106A. The formation of the gate spacers 114A and 114B may include sequential operations: (i) forming a spacer opening 740, such as Figure 7A-7B As shown, by passing through the opening 638 ( Fig. 6A ) etching the exposed area of ​​the fin structure 106A, (ii) removing the patterned mask layer 536, and (iii) Figure 7A-7B A spacer material layer 714 is deposited on the structure to form Figure 8A-8B and (iv) etching the spacer material layer 714 to form gate spacers 114A and 114B, such as Figure 9A-9B shown.

[0050] Etching the fin structure 106A through the opening 638 may include using an etching gas, such as sulfur hexafluoride (SF6) and carbon tetrafluoride (CF4) with a gas mixture of chlorine, hydrogen bromide (HBr), and helium, at a pressure in a range from about 10 mtorr to about 200 mtorr, and a bias power in a range from about 100 W to about 800 W. In some embodiments, a ratio of the etching gas SF6 or CF4 to the gas mixture may range from about 1:10 to about 1:25. In some embodiments, if the etching bias power is 100 W, the etching may be performed for a duration of about 300 seconds to about 1200 seconds in a temperature range of about 20° C. to about 60° C. In some embodiments, if the etching bias power is 800 W, the etching may be performed for a duration of about 100 seconds to about 500 seconds in a temperature range of about 20° C. to about 60° C.

[0051] like Fig.13 As shown, a similar etching operation can be simultaneously performed on the exposed area of ​​the fin structure 106B through the opening between the polysilicon structures 612 of the FET 102B to form the spacer opening 1340. Since the spacing between the polysilicon structures 612 of the FET 102B is wider, the curvature radius of the spacer opening 1340 is smaller than the curvature radius of the spacer 740, and the maximum height H5 of the spacer opening 1340 is smaller than the maximum height H4 of the spacer opening 740, as shown in FIG. Fig.14 As shown in the following figure, Fig.9A As compared to the distances D3 and D4 of the second spacer portions 128B and 130B shown, the second spacer portions 132B and 134B are formed into the fin structure 106B at shorter distances D11 and D12, as shown in FIG. Fig.14 As shown. Fig.14 As shown, the gate spacers 115A and 115B may be formed in operations similar to the sequential operations (ii)-(iv) of forming the gate spacers 114A and 114B. Fig.13 in terms of structure.

[0052] refer to Figure 2 In operation 220, an epitaxial S / D region is formed on the fin structure. Figures 10A-11BAs described, an epitaxial S / D region 110A is formed in the fin structure 106A. The formation of the epitaxial S / D region 110A may include the following sequential operations: (i) forming an S / D opening 1042, such as Fig. 10A As shown, and (ii) epitaxially growing semiconductor material in the S / D opening 1042 to form an epitaxial S / D region 110A, as shown Figure 11A-11B The formation of the S / D opening 1042 may include etching the fin structure 106A through the spacer opening 740 and extending the spacer opening 740 to a distance H1 below the second spacer portions 128A and 130B, as shown. Fig. 10A After forming the epitaxial S / D region 110A, the ESL 117 and the ILD layer 118 may be formed. Figure 12A-12B shown.

[0053] refer to Figure 2 In operation 225, the polysilicon structure is replaced by a gate structure. Fig. 12A As shown, the polysilicon structure 612 and the hard mask 435 are replaced by the gate structure 112A. The polysilicon structure 612 and the hard mask 435 are replaced by the gate structure 112A. The replacement of the polysilicon structure 612 and the hard mask 435 by the gate structure 112A may include sequential operations: (i) etching the hard mask 435, (ii) etching the polysilicon structure 612 to form a gate opening (not shown), (iii) forming the IO layer 120 on the fin structure 106A within the gate opening, as shown in FIG. Fig. 12A As shown, (iv) depositing a HK gate dielectric layer 122 on the IO layer 120, (v) depositing a WFM layer 124 on the HK gate dielectric layer 122, (vi) depositing a gate metal filling layer 126 on the WFM layer 124, and (vi) performing a chemical mechanical polishing (CMP) process to substantially make top surfaces of the HK gate dielectric layer 122, the WFM layer 124, and the gate metal filling layer 126 coplanar with a top surface of the ILD layer 118, as shown. Fig. 12A shown.

[0054] The present disclosure provides example semiconductor devices (e.g., FETs 102A and 102B) having extended gate spacers (e.g., gate spacers 114A-114B and 115A-115B) in gate structures (e.g., gate structures 112A and 112B) and example methods (e.g., method 200) of forming such semiconductor devices. The extended gate spacers improve the sidewall profile of epitaxial source / drain (S / D) regions (e.g., epitaxial S / D regions 110A and 110B) and prevent the epitaxial S / D regions from extending into the gate structure region during the manufacturing process to avoid electrical shorting between the epitaxial S / D regions and the gate structure.

[0055] In some embodiments, a gate structure is disposed on a fin structure (e.g., fin structures 106A and 106B) of a semiconductor device and an epitaxial S / D region is grown in an etched region of the fin structure. The gate structure is separated from the epitaxial source / drain region by an extended gate spacer disposed along the sidewall of the gate structure. In some embodiments, a first spacer portion of the extended gate spacer (e.g., first spacer portions 128A-130A and 132A-134A) is disposed on a fin top surface (e.g., fin top surfaces 106At and 106Bt) of the fin structure, and a second spacer portion of the extended gate spacer (e.g., second spacer portions 128B-130B and 132B-134B) is disposed within the fin structure. The first spacer portion may have a non-tapered structure, and the second spacer portion may have a tapered structure. The first spacer portion may protect the gate structure during subsequent processing of adjacent structures. The second spacer portion can control the etching profile of the S / D opening (e.g., S / D opening 1042) formed in the fin structure for growing the epitaxial S / D region in the S / D opening. As a result, the second spacer portion controls the sidewall profile of the epitaxial S / D region grown in the S / D opening and prevents the epitaxial S / D region from extending into the gate structure region.

[0056] In some embodiments, a semiconductor device includes a substrate, a fin structure having a fin top surface disposed on the substrate, a source / drain (S / D) region disposed on the fin structure, a gate structure top surface disposed on the fin, and a gate spacer, wherein a first spacer portion and a second spacer portion are disposed between the gate structure and the source / drain region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the source / drain region.

[0057] In the above semiconductor device, the second spacer portion has a tapered structure.

[0058] In the above semiconductor device, the first spacer portion has a non-tapered structure.

[0059] In the above semiconductor device, a first sidewall of the second spacer portion is adjacent to the fin structure, and a second sidewall of the second spacer portion is adjacent to the source / drain region.

[0060] In the above semiconductor device, the second spacer portion has an inclined sidewall adjacent to the fin structure and a substantially vertical sidewall adjacent to the source / drain region.

[0061] In the above semiconductor device, the second spacer is partially disposed within the fin structure.

[0062] In the above semiconductor device, the second spacer is disposed between the fin structure and the source / drain region.

[0063] In the above semiconductor device, a sidewall of the second spacer portion and a top surface of the fin form an angle ranging from about 15 degrees to about 90 degrees.

[0064] In the above semiconductor device, a first portion of the S / D region is disposed within the fin structure, and a second portion of the S / D region extends above a top surface of the fin, and wherein a sidewall of the first portion is substantially vertical.

[0065] In the above semiconductor device, the first spacer portion is disposed along a portion of the S / D region extending above a top surface of the fin.

[0066] In some embodiments, a semiconductor device includes a substrate, a fin structure having a fin top surface disposed on the substrate, a source / drain (S / D) region disposed within the fin structure, a gate structure top surface disposed on the fin, and a gate spacer, wherein a first spacer portion and a second spacer portion are disposed between the gate structure and the source / drain region. The first spacer portion is a non-tapered structure and extends above the fin top surface. The second spacer portion is a tapered structure and is disposed within the fin structure.

[0067] In the above semiconductor device, the second spacer portion has a first inclined sidewall adjacent to the fin structure and a second inclined sidewall adjacent to the source / drain region.

[0068] In the above-mentioned semiconductor device, a first portion of the source / drain region is adjacent to a second spacer portion, and the first portion of the source / drain region has an inclined sidewall, and wherein a second portion of the S / D region extends below the second spacer portion, and the second portion of the S / D region has a substantially vertical sidewall.

[0069] In the above-mentioned semiconductor device, a first portion of the source / drain region is adjacent to the second spacer portion, and the first portion of the source / drain region has a first width, and wherein a second portion of the S / D region extends below the second spacer portion, and the second portion of the S / D region has a second width greater than the first width.

[0070] In the above semiconductor device, the second spacer portion is disposed between the source / drain region and a portion of the fin structure located below the gate structure.

[0071] In the above semiconductor device, the second spacer is partially disposed along the sidewalls of the source / drain regions but not along the sidewalls of the gate structure.

[0072] In some embodiments, a method includes forming a fin structure having a fin top surface on a substrate, forming first and second polysilicon structures on the fin top surface, forming a spacer opening structure in the fin structure and between the first and second polysilicon structures, forming a gate spacer, forming a source / drain region between the first and second polysilicon structures, replacing the first and second polysilicon structures with the first and second gate structures. Forming the gate spacer includes: forming a first spacer portion of the gate spacer along a sidewall of the first polysilicon structure, and forming a second spacer portion of the gate spacer in the spacer opening.

[0073] In the above method, forming the spacer opening includes etching an exposed region of the fin structure between the first polysilicon structure and the second polysilicon structure.

[0074] In the above method, forming the gate spacer includes depositing a spacer material layer on the first polysilicon structure and the second polysilicon structure and within the spacer opening.

[0075] In the above method, forming the source / drain region includes: etching an exposed region of the fin structure in the spacer opening to form an S / D opening; and epitaxially growing a semiconductor layer in the S / D opening.

[0076] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: substrate; a fin structure having a fin top surface disposed on the substrate; A source / drain region, disposed on the fin structure; A gate structure, disposed on the top surface of the fin, comprising a gate oxide layer and a high-k gate dielectric layer; as well as a gate spacer having a first spacer portion and a second spacer portion disposed between the gate structure and the source / drain region, wherein the first spacer portion extends above the top surface of the fin and contacts the sidewalls of the gate oxide layer and the sidewalls of the high-k gate dielectric layer, wherein the second spacer portion extends below the top surface of the fin and is disposed between the sidewall of the source / drain region and the sidewall of the fin structure facing the source / drain region, wherein the second spacer portion comprises a tapered structure having a first inclined sidewall adjacent to the source / drain region and a second inclined sidewall adjacent to the fin structure, and The entire portion of the source / drain region extending below the second spacer portion has a vertical sidewall.

2. The semiconductor device according to claim 1, wherein The second spacer portion has a triangular cross-sectional profile.

3. The semiconductor device according to claim 1, wherein The first spacer portion includes a rectangular cross-sectional profile and vertical sidewalls in contact with the gate oxide layer and the high-k gate dielectric layer.

4. The semiconductor device according to claim 1, wherein: The second spacer is partially located below a bottom surface of the gate structure.

5. The semiconductor device according to claim 1, wherein The second inclined sidewall extends from an interface between the gate oxide layer and the top surface of the fin to an interface between the fin structure and the source / drain region.

6. The semiconductor device according to claim 1, wherein A bottom edge of a sidewall of the first spacer portion contacts an interface between the gate oxide layer and a top surface of the fin.

7. The semiconductor device according to claim 1, wherein Vertical sidewalls of the first spacer portion and the second spacer portion facing the source / drain regions are aligned with each other along a vertical plane.

8. The semiconductor device according to claim 1, wherein An interface between the vertical sidewalls of the first spacer portion and the inclined sidewalls of the second spacer portion contacts the source / drain region.

9. The semiconductor device according to claim 1, wherein: A first portion of the source / drain region is disposed within the fin structure, and a second portion of the source / drain region extends above a top surface of the fin.

10. The semiconductor device according to claim 1, wherein The first spacer portion is disposed along a portion of the source / drain region extending above a top surface of the fin.

11. A semiconductor device comprising: substrate; a fin structure having a fin top surface disposed on the substrate; A source / drain region, disposed in the fin structure; A gate structure is disposed on the top surface of the fin; as well as a gate spacer having a first spacer portion and a second spacer portion disposed between the gate structure and the source / drain region, wherein the first spacer portion is a non-tapered structure having vertical sidewalls facing the source / drain region and extending above the top surface of the fin, The second spacer portion is a tapered structure and is disposed in the fin structure, wherein the tapered structure has a first inclined sidewall facing the fin structure and a second inclined sidewall facing the source / drain region, wherein an interface between the vertical sidewall and the inclined sidewall contacts an interface between the gate structure and the fin structure, and, The entire portion of the source / drain region extending below the second spacer portion has a vertical sidewall and a bottom surface with a V-shaped cross-sectional profile.

12. The semiconductor device according to claim 11, wherein The first inclined sidewall is adjacent to the fin structure, and the second inclined sidewall is adjacent to the source / drain region.

13. The semiconductor device according to claim 11, wherein A first portion of the source / drain region is adjacent to the second spacer portion, and the first portion of the source / drain region has an inclined sidewall.

14. The semiconductor device according to claim 11, wherein A first portion of the source / drain region is adjacent to the second spacer portion, and the first portion of the source / drain region has a first width, and Wherein, a second portion of the source / drain region extends below the second spacer portion, and the second portion of the source / drain region has a second width greater than the first width.

15. The semiconductor device according to claim 11, wherein The second spacer portion is disposed between the source / drain region and a portion of the fin structure below the gate structure.

16. The semiconductor device according to claim 11, wherein The second spacer is partially disposed along the sidewalls of the source / drain region but not along the sidewalls of the gate structure.

17. A method for manufacturing a semiconductor device, comprising: forming a fin structure having a fin top surface on a substrate; forming a first polysilicon structure and a second polysilicon structure on a top surface of the fin; forming a spacer opening within the fin structure and between the first polysilicon structure and the second polysilicon structure; forming a gate spacer, wherein forming the gate spacer comprises: forming a first spacer portion of the gate spacer along a sidewall of the first polysilicon structure, and forming a second spacer portion of the gate spacer within the spacer opening; forming a source / drain region between the first polysilicon structure and the second polysilicon structure; and replacing the first polysilicon structure and the second polysilicon structure with a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure both include a gate oxide layer and a high-k gate dielectric layer, the first spacer portion contacts a sidewall of the gate oxide layer and a sidewall of the high-k gate dielectric layer, and the second spacer portion is disposed between a sidewall of the source / drain region and a sidewall of the fin structure facing the source / drain region, wherein the second spacer portion comprises a tapered structure having a first inclined sidewall adjacent to the source / drain region and a second inclined sidewall adjacent to the fin structure, The entire portion of the source / drain region extending below the second spacer portion has a vertical sidewall and a bottom surface with a V-shaped cross-sectional profile.

18. The method according to claim 17, wherein: Forming the spacer opening includes etching an exposed region of the fin structure between the first polysilicon structure and the second polysilicon structure.

19. The method according to claim 17, wherein: Forming the gate spacer includes depositing a spacer material layer over the first and second polysilicon structures and within the spacer openings.

20. The method according to claim 17, wherein: Forming the source / drain region includes: etching exposed regions of the fin structure within the spacer openings to form source / drain openings; and A semiconductor layer is epitaxially grown in the source / drain openings.

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