A novel six-phase charge pump circuit structure

Abstract

The present invention discloses a novel six-phase charge pump circuit structure, including a PUMP_REG circuit module. The input end of the PUMP_REG circuit module is provided with a PUMP_STG circuit module, and the input end of the PUMP_STG circuit module is provided with a six-phase non-overlapping clock circuit module. The present invention adopts a six-phase non-overlapping clock circuit, mainly to generate phases that are sequentially misaligned and have the same frequency. The PUMP_STG is controlled by the six-phase non-overlapping clock, so that M1 / M2 / M3 / M4 are not conducting simultaneously and there is no overlapping situation, avoiding mutual influence. The DBBN and DBBP modules are adopted to avoid the conduction and leakage of parasitic diodes. When using CLK1 / CLK2 / CLK3 / CLK4 / CLKA / CLKB, the clocks with sequentially misaligned phases, the same frequency, and a duty cycle of 50% are used to eliminate the VTH voltage drop, avoid the generation of reverse current, improve the pump efficiency, simplify the clock control, increase the dynamic substrate bias, avoid the conduction and leakage of parasitic diodes, and make the main transistors of the PUMP_STG conduct individually, reducing mutual influence.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chips, and more specifically, to a novel six-phase charge pump circuit structure. Background Art

[0002] The commonly used charge pumps are of two-phase or four-phase structures. Commonly used two-phase charge pumps include Dickson CP, Static CTS CP, Dynamic CTS CP, and Pelliconi CP structures. Commonly used four-phase charge pumps include CTS CP type and cross-coupled type.

[0003] The existing charge pump structures have the following deficiencies:

[0004] 1. There is a VTH voltage drop in the pump path, reducing the pump efficiency;

[0005] 2. Reverse current leakage causes the output voltage and output current to decrease, reducing the pump efficiency;

[0006] 3. When the substrate voltage of the NMOS / PMOS transistor is higher / lower than the source or drain voltage, the parasitic diode conducts and leaks current;

[0007] 4. The clock control of the four-phase charge pump is complex;

[0008] 5. In the four-phase charge pump, there will be a situation where two tubes in the input stage or two tubes in the output stage conduct simultaneously, affecting each other and reducing the pump efficiency. Summary of the Invention

[0009] In order to overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides a novel six-phase charge pump circuit structure, which adopts a six-phase non-overlapping clock circuit. Mainly, it generates phases that are sequentially misaligned and have the same frequency. The six-phase non-overlapping clock is used to control PUMP_STG, so that M1 / M2 / M3 / M4 do not conduct simultaneously and there is no overlapping situation, avoiding mutual influence. The DBBN and DBBP modules are adopted to avoid the conduction and leakage of parasitic diodes. When using CLK1 / CLK2 / CLK3 / CLK4 / CLKA / CLKB, the clocks with sequentially misaligned phases, the same frequency, and a duty cycle of 50% are used to eliminate the VTH voltage drop, avoid the generation of reverse current, improve the pump efficiency, simplify the clock control, increase the dynamic substrate bias, avoid the conduction and leakage of parasitic diodes, and make the main transistors of PUMP_STG conduct individually, reducing mutual influence, so as to solve the problems raised in the above background art.

[0010] To achieve the above object, the present invention provides the following technical solutions: It includes a PUMP_REG circuit module. The input end of the PUMP_REG circuit module is provided with a PUMP_STG circuit module, and the input end of the PUMP_STG circuit module is provided with a six-phase non-overlapping clock circuit module.

[0011] In a preferred embodiment, the PUMP_STG circuit module includes an NM1 transistor, an NM2 transistor, a PM1 transistor, and a PM2 transistor. The source ends of the NM1 transistor and the NM2 transistor are both connected to the converted output voltage. The drain end of the NM1 transistor is electrically connected to the drain end of the PM1 transistor, and the drain end of the NM2 transistor is electrically connected to the drain end of the PM2 transistor. The gate end of the NM1 transistor is electrically connected to the gate end of the PM2 transistor, and the gate end of the NM2 transistor is electrically connected to the gate end of the PM1 transistor.

[0012] In a preferred embodiment, the output end of the PM1 transistor is provided with an NM3 transistor, a PM4 transistor, and an NM4 transistor. The output end of the PM2 transistor is provided with a PM6 transistor, an NM6 transistor, and a PM8 transistor. The source end of the NM3 transistor, the drain end of the PM4 transistor, and the source end of the NM4 transistor are all connected to the source end of the PM1 transistor. The drain end of the PM6 transistor, the source end of the NM6 transistor, and the source end of the PM8 transistor are all electrically connected to the source end of the PM2 transistor. The gate end of the PM4 transistor and the gate end of the NM4 transistor are connected. The gate end of the PM6 transistor and the gate end of the NM6 transistor are connected.

[0013] In a preferred embodiment, the output end of the NM3 transistor is provided with a PM3 transistor. The output end of the PM4 transistor is provided with a PM5 transistor. The output end of the NM4 transistor is provided with an NM5 transistor. The drain end of the PM3 transistor is connected to the drain end of the NM3 transistor. The drain end of the PM5 transistor is connected to the source end of the PM4 transistor. The source end of the NM5 transistor is connected to the drain end of the NM4 transistor. The gate end of the PM4 transistor is connected to the gate end of the NM4 transistor. The gate end of the PM5 transistor is connected to the gate end of the NM5 transistor.

[0014] In a preferred embodiment, a PM7 transistor is provided at the output end of the PM6 transistor, an NM7 transistor is provided at the output end of the NM6 transistor, an NM8 transistor is provided at the output end of the PM8 transistor, and the drain end of the PM7 transistor is connected to the source end of the PM6 transistor, the source end of the NM7 transistor is electrically connected to the drain end of the NM6 transistor, the drain end of the NM8 transistor is connected to the drain end of the PM8 transistor, the gate end of the PM6 transistor is connected to the gate end of the NM6 transistor, and the gate end of the PM7 transistor is connected to the gate end of the NM7 transistor.

[0015] In a preferred embodiment, low-voltage domain voltage signals are input to the source end of the PM3 transistor, the source end of the PM5 transistor, the drain end of the NM5 transistor, the source end of the PM7 transistor, the drain end of the NM7 transistor, and the source end of the NM8 transistor.

[0016] In a preferred embodiment, the PUMP_STG circuit module further includes a PM9 transistor, a PM10 transistor, an NM10 transistor, a PM12 transistor, an NM12 transistor, and an NM14 transistor, and the gate end of the PM10 transistor is connected to the gate end of the NM10 transistor, the gate end of the PM12 transistor is connected to the gate end of the NM12 transistor, and the source end of the PM9 transistor, the source end of the PM10 transistor, the drain end of the NM10 transistor, the source end of the PM12 transistor, the drain end of the NM12 transistor, and the source end of the NM14 transistor are all connected to the converted output voltage.

[0017] In a preferred embodiment, an NM9 transistor is provided at the output end of the PM9 transistor, a PM11 transistor is provided at the output end of the PM10 transistor, an NM11 transistor is provided at the output end of the NM10 transistor, a PM13 transistor is provided at the output end of the PM12 transistor, an NM13 transistor is provided at the output end of the NM12 transistor, a PM14 transistor is provided at the output end of the NM14 transistor, the drain end of the PM9 transistor is connected to the drain end of the NM9 transistor, the drain end of the PM10 transistor is connected to the source end of the PM11 transistor, the source end of the NM10 transistor is connected to the drain end of the NM11 transistor, the source end of the NM13 transistor is connected to the drain end of the PM12 transistor, the source end of the NM12 transistor is connected to the drain end of the NM13 transistor, and the drain end of the NM14 transistor is connected to the drain end of the PM14 transistor.

[0018] In a preferred embodiment, a PM15 transistor is provided at the output ends of the NM9 transistor, the PM11 transistor, and the NM11 transistor; a PM16 transistor is provided at the output ends of the PM13 transistor, the NM13 transistor, and the PM14 transistor; the source end of the NM9 transistor, the drain end of the PM11 transistor, and the source end of the NM11 transistor are all connected to the source end of the PM15 transistor; the drain end of the PM13 transistor, the source end of the NM13 transistor, and the source end of the PM14 transistor are all connected to the source end of the PM16 transistor; an NM15 transistor is provided at the output end of the PM15 transistor; an NM16 transistor is provided at the output end of the PM16 transistor; the drain end of the NM15 transistor is connected to the drain end of the PM15 transistor; the drain end of the NM16 transistor is connected to the drain end of the PM16 transistor; the gate end of the PM15 transistor is connected to the gate end of the NM16 transistor; the gate end of the NM15 transistor is connected to the gate end of the PM16 transistor; the source end of the NM15 transistor and the source end of the NM16 transistor both input a low-voltage domain voltage signal.

[0019] In a preferred embodiment, the PUMP_STG circuit module further includes two DBBN modules, two DBBP modules, an M1 transistor, an M2 transistor, an M3 transistor, and an M4 transistor, and the DBBN module is electrically connected to the DBBP module; the drain ends of the M3 transistor and the M4 transistor both input a low-voltage domain voltage signal; the drain end of the M1 transistor and the drain end of the M2 transistor are both connected to the converted output voltage; the two DBBP modules are respectively electrically connected to the M1 transistor and the M2 transistor; the two DBBN modules are respectively electrically connected to the M3 transistor and the M4 transistor; the six-phase non-overlapping clock circuit module includes a GLK1 interface, a GLK2 interface, a GLK3 interface, a GLK4 interface, a GLKA interface, and a GLKB interface.

[0020] The technical effects and advantages of the present invention:

[0021] Six-phase non-overlapping clock circuit mainly generates clocks CLK1 / CLK2 / CLK3 / CLK4 / CLKA / CLKB with sequentially misaligned phases, the same frequency, and a 50% duty cycle. The PUMP_STG circuit, which is the main circuit of the charge pump and also the main circuit of the present invention. The PUMP_REG circuit is used to trim the output of the charge pump, connect the open-loop charge pump into a closed-loop state, and trim the output stable voltage as needed. The six-phase non-overlapping clock is used to control PUMP_STG, so that M1 / M2 / M3 / M4 are not conducting simultaneously and there is no overlap, avoiding mutual influence. The DBBN and DBBP modules are adopted to avoid the conduction and leakage of parasitic diodes. The clocks CLK1 / CLK2 / CLK3 / CLK4 / CLKA / CLKB with sequentially misaligned phases, the same frequency, and a 50% duty cycle are simple and easy to understand;

[0022] 1. Eliminate the VTH voltage drop and improve the pump efficiency;

[0023] 2. Avoid the generation of reverse current and improve the pump efficiency;

[0024] 3. Simplify the clock control;

[0025] 4. Increase the dynamic substrate bias to avoid the conduction and leakage of parasitic diodes;

[0026] 5. Make the main transistors of PUMP_STG conduct individually, reduce mutual influence, and improve the pump efficiency. Description of the Drawings

[0027] Figure 1 It is a schematic structural diagram of the four-stage PUMP_STG series system of the present invention.

[0028] Figure 2 It is a schematic structural diagram of the two-series and two-parallel PUMP_STG system of the present invention.

[0029] Figure 3 It is the circuit schematic diagram of PUMP_STG of the present invention.

[0030] Figure 4 It is the timing diagram of the six-phase non-overlapping clock circuit module of the present invention.

[0031] Reference numerals are: 1. PUMP_REG circuit module; 2. PUMP_STG circuit module; 3. Six-phase non-overlapping clock circuit module. Detailed Embodiment

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] Referring to the accompanying Figures 1-4 drawings, a novel six-phase charge pump circuit structure according to an embodiment of the present invention includes a PUMP_REG circuit module 1. The input end of the PUMP_REG circuit module 1 is provided with a PUMP_STG circuit module 2. The input end of the PUMP_STG circuit module 2 is provided with a six-phase non-overlapping clock circuit module 3. The PUMP_STG circuit module 2 includes an NM1 transistor, an NM2 transistor, a PM1 transistor, and a PM2 transistor. The source ends of the NM1 transistor and the NM2 transistor are both connected to the converted output voltage. The drain end of the NM1 transistor is electrically connected to the drain end of the PM1 transistor. The drain end of the NM2 transistor is electrically connected to the drain end of the PM2 transistor. The gate end of the NM1 transistor is electrically connected to the gate end of the PM2 transistor. The gate end of the NM2 transistor is electrically connected to the gate end of the PM1 transistor. The six-phase non-overlapping clock circuit mainly generates clocks CLK1 / CLK2 / CLK3 / CLK4 / CLKA / CLKB with sequentially misaligned phases, the same frequency, and a duty cycle of 50%. The PUMP_STG circuit is the main circuit of the charge pump and also the main circuit of the present invention. The PUMP_REG circuit is used to trim the output of the charge pump, connect the open-loop charge pump into a closed-loop state, and trim the output stable voltage as needed. The PUMP_STG is controlled by a six-phase non-overlapping clock, so that M1 / M2 / M3 / M4 are not simultaneously turned on and there is no overlap, avoiding mutual influence. The DBBN and DBBP modules are adopted to avoid the conduction and leakage of parasitic diodes. The clocks CLK1 / CLK2 / CLK3 / CLK4 / CLKA / CLKB with sequentially misaligned phases, the same frequency, and a duty cycle of 50% are simple and easy to understand.

[0034] Further, the output terminal of the PM1 transistor is provided with an NM3 transistor, a PM4 transistor, and an NM4 transistor. The output terminal of the PM2 transistor is provided with a PM6 transistor, an NM6 transistor, and a PM8 transistor. The source terminal of the NM3 transistor, the drain terminal of the PM4 transistor, and the source terminal of the NM4 transistor are all connected to the source terminal of the PM1 transistor. The drain terminal of the PM6 transistor, the source terminal of the NM6 transistor, and the source terminal of the PM8 transistor are all electrically connected to the source terminal of the PM2 transistor. The gate terminals of the PM4 transistor and the NM4 transistor are connected. The gate terminals of the PM6 transistor and the NM6 transistor are connected. When t = t0, CLK1 / CLK2 / CLK3 / CLK4 / CLKA are all at low level, and CLKB is at high level. At this time, only the PM4 / PM5, PM6 / PM7, PM10 / PM11, and PM12 / PM13 paths are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT, so M1 / M2 / M3 / M4 are turned off.

[0035] Further, the output terminal of the NM3 transistor is provided with a PM3 transistor. The output terminal of the PM4 transistor is provided with a PM5 transistor. The output terminal of the NM4 transistor is provided with an NM5 transistor. The drain terminal of the PM3 transistor is connected to the drain terminal of the NM3 transistor. The drain terminal of the PM5 transistor is connected to the source terminal of the PM4 transistor. The source terminal of the NM5 transistor is connected to the drain terminal of the NM4 transistor. The gate terminals of the PM4 transistor and the NM4 transistor are connected. The gate terminals of the PM5 transistor and the NM5 transistor are connected. When t = t1, CLK1 / CLK2 / CLK3 / CLK4 / CLKB are all at low level, and CLKA is at high level. At this time, VA rises with CLKA, and VB drops with CLKB. M1 / M2 / M3 / M4 all remain turned off.

[0036] Further, an output terminal of the PM6 transistor is provided with a PM7 transistor, an output terminal of the NM6 transistor is provided with an NM7 transistor, and an output terminal of the PM8 transistor is provided with an NM8 transistor. A drain terminal of the PM7 transistor is connected to a source terminal of the PM6 transistor, a source terminal of the NM7 transistor is electrically connected to a drain terminal of the NM6 transistor, a drain terminal of the NM8 transistor is electrically connected to a drain terminal of the PM8 transistor, a gate terminal of the PM6 transistor is connected to a gate terminal of the NM6 transistor, and a gate terminal of the PM7 transistor is connected to a gate terminal of the NM7 transistor. When t = t2, CLK1 / CLK2 / CLK3 / CLKB are all at a low level, and CLK4 / CLKA are at a high level. At this time, only the NM2 / PM2, NM3 / PM3, PM10 / PM11, and PM12 / PM13 paths are conducting. Therefore, NA = VIN, NB = PA = PB = VOUT. So, M1 / M2 / M3 are turned off, and M4 is turned on. The current flows from VIN to VB until VB = VIN.

[0037] Further, a source terminal of the PM3 transistor, a source terminal of the PM5 transistor, a drain terminal of the NM5 transistor, a source terminal of the PM7 transistor, a drain terminal of the NM7 transistor, and a source terminal of the NM8 transistor all input low-voltage domain voltage signals. The PUMP_STG circuit module 2 further includes a PM9 transistor, a PM10 transistor, an NM10 transistor, a PM12 transistor, an NM12 transistor, and an NM14 transistor. A gate terminal of the PM10 transistor is connected to a gate terminal of the NM10 transistor, a gate terminal of the PM12 transistor is connected to a gate terminal of the NM12 transistor, and a source terminal of the PM9 transistor, a source terminal of the PM10 transistor, a drain terminal of the NM10 transistor, a source terminal of the PM12 transistor, a drain terminal of the NM12 transistor, and a source terminal of the NM14 transistor are all connected to the converted output voltage. When t = t4, CLK1 / CLKB are both at a low level, and CLK2 / CLK3 / CLK4 / CLKA are at a high level. At this time, only the NM4 / NM5, NM6 / NM7, NM14 / PM14, and PM15 / NM15 paths are conducting. Therefore, PA = NA = NB = VIN, PB = VOUT. So, M2 / M3 / M4 are turned off, and M1 is turned on. The current flows from VA to VOUT until VOUT = VA.

[0038] Further, an NM9 transistor is provided at the output end of the PM9 transistor, a PM11 transistor is provided at the output end of the PM10 transistor, an NM11 transistor is provided at the output end of the NM10 transistor, a PM13 transistor is provided at the output end of the PM12 transistor, an NM13 transistor is provided at the output end of the NM12 transistor, and a PM14 transistor is provided at the output end of the NM14 transistor. The drain terminal of the PM9 transistor is connected to the drain terminal of the NM9 transistor, the drain terminal of the PM10 transistor is connected to the source terminal of the PM11 transistor, the source terminal of the NM10 transistor is connected to the drain terminal of the NM11 transistor, the source terminal of the NM13 transistor is connected to the drain terminal of the PM12 transistor, the source terminal of the NM12 transistor is connected to the drain terminal of the NM13 transistor, and the drain terminal of the NM14 transistor is connected to the drain terminal of the PM14 transistor. When t = t5, CLKB is at a low level, and CLK1 / CLK2 / CLK3 / CLK4 / CLKA are at a high level. At this time, only the NM4 / NM5, NM6 / NM7, NM10 / NM11, and NM12 / NM13 paths are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT, so M1 / M2 / M3 / M4 are turned off.

[0039] Further, a PM15 transistor is provided at the output ends of the NM9 transistor, the PM11 transistor, and the NM11 transistor, and a PM16 transistor is provided at the output ends of the PM13 transistor, the NM13 transistor, and the PM14 transistor. The source terminal of the NM9 transistor, the drain terminal of the PM11 transistor, and the source terminal of the NM11 transistor are all connected to the source terminal of the PM15 transistor. The drain terminal of the PM13 transistor, the source terminal of the NM13 transistor, and the source terminal of the PM14 transistor are all connected to the source terminal of the PM16 transistor. An NM15 transistor is provided at the output end of the PM15 transistor, and an NM16 transistor is provided at the output end of the PM16 transistor. The drain terminal of the NM15 transistor is connected to the drain terminal of the PM15 transistor, and the drain terminal of the NM16 transistor is connected to the drain terminal of the PM16 transistor. The gate terminal of the PM15 transistor is connected to the gate terminal of the NM16 transistor, and the gate terminal of the NM15 transistor is connected to the gate terminal of the PM16 transistor. The source terminals of the NM15 transistor and the NM16 transistor both input a low-voltage domain voltage signal. When t = t6, CLKA is at a low level, and CLK1 / CLK2 / CLK3 / CLK4 / CLKB are at a high level. At this time, only the NM4 / NM5, NM6 / NM7, NM10 / NM11, and NM12 / NM13 paths are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT, so M1 / M2 / M3 / M4 are turned off, and VA decreases to VC (VC < VIN) as CLKA drops, while VB rises with CLKB. At this time, VB = VIN + VCLKB.

[0040] Further, the PUMP_STG circuit module 2 further includes two DBBN modules, two DBBP modules, an M1 transistor, an M2 transistor, an M3 transistor, and an M4 transistor. The DBBN module is electrically connected to the DBBP module. The drain terminals of the M3 transistor and the M4 transistor both input low-voltage domain voltage signals. The drain terminals of the M1 transistor and the M2 transistor are both connected to the converted output voltage. The two DBBP modules are respectively electrically connected to the M1 transistor and the M2 transistor. The two DBBN modules are respectively electrically connected to the M3 transistor and the M4 transistor. The six-phase non-overlapping clock circuit module 3 includes a GLK1 interface, a GLK2 interface, a GLK3 interface, a GLK4 interface, a GLKA interface, and a GLKB interface. When t = t7, CLK4 / CLKA is at a low level, and CLK1 / CLK2 / CLK3 / CLKB is at a high level. At this time, only the NM1 / PM1, PM8 / NM8, NM10 / NM11, and NM12 / NM13 paths are conducting. Therefore, NB = VIN, NA = PA = PB = VOUT. So, M1 / M2 / M4 are turned off; M3 is turned on, and the current flows from VIN to VA until VA = VIN. When t = t8, CLK3 / CLK4 / CLKA is at a low level, and CLK1 / CLK2 / CLKB is at a high level. At this time, only the PM4 / PM5, PM6 / PM7, NM10 / NM11, and NM12 / NM13 paths are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT. So, M1 / M2 / M3 / M4 are turned off. When t = t9, CLK1 / CLK3 / CLK4 / CLKA is at a low level, and CLK2 / CLKB is at a high level. At this time, only the PM4 / PM5, PM6 / PM7, PM9 / NM9, and PM16 / NM16 paths are conducting. Therefore, PB = NA = NB = VIN, PA = VOUT. So, M1 / M3 / M4 are turned off; M2 is turned on, and the current flows from VB to VOUT until VOUT = VB.

[0041] Example 1:

[0042] ① When t = t0, CLK1 / CLK2 / CLK3 / CLK4 / CLKA are all at a low level, and CLKB is at a high level. At this time, only the PM4 / PM5, PM6 / PM7, PM10 / PM11, and PM12 / PM13 paths are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT. So, M1 / M2 / M3 / M4 are turned off;

[0043] ② When t = t1, CLK1 / CLK2 / CLK3 / CLK4 / CLKB are all at a low level, and CLKA is at a high level. At this time, VA rises with CLKA, and VB drops with CLKB. M1 / M2 / M3 / M4 all remain turned off;

[0044] ③ When t = t2, CLK1 / CLK2 / CLK3 / CLKB are all at low level, CLK4 / CLKA are at high level. At this time, only the paths of NM2 / PM2, NM3 / PM3, PM10 / PM11, and PM12 / PM13 are conducting. Therefore, NA = VIN, NB = PA = PB = VOUT. So M1 / M2 / M3 are turned off and M4 is turned on. The current flows from VIN to VB until VB = VIN;

[0045] ④ When t = t3, CLK1 / CLK2 / CLKB are all at low level, CLK3 / CLK4 / CLKA are at high level. At this time, only the paths of NM4 / NM5, NM6 / NM7, PM10 / PM11, and PM12 / PM13 are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT. So M1 / M2 / M3 / M4 are turned off;

[0046] ⑤ When t = t4, CLK1 / CLKB are all at low level, CLK2 / CLK3 / CLK4 / CLKA are at high level. At this time, only the paths of NM4 / NM5, NM6 / NM7, NM14 / PM14, and PM15 / NM15 are conducting. Therefore, PA = NA = NB = VIN, PB = VOUT. So M2 / M3 / M4 are turned off and M1 is turned on. The current flows from VA to VOUT until VOUT = VA;

[0047] ⑥ When t = t5, CLKB is at low level, CLK1 / CLK2 / CLK3 / CLK4 / CLKA are at high level. At this time, only the paths of NM4 / NM5, NM6 / NM7, NM10 / NM11, and NM12 / NM13 are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT. So M1 / M2 / M3 / M4 are turned off;

[0048] ⑦ When t = t6, CLKA is at low level, CLK1 / CLK2 / CLK3 / CLK4 / CLKB are at high level. At this time, only the paths of NM4 / NM5, NM6 / NM7, NM10 / NM11, and NM12 / NM13 are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT. So M1 / M2 / M3 / M4 are turned off, and VA decreases with CLKA to VC (VC < VIN), VB increases with CLKB, and at this time VB = VIN + VCLKB;

[0049] ⑧ When t = t7, CLK4 / CLKA is at low level, and CLK1 / CLK2 / CLK3 / CLKB is at high level. At this time, only the paths of NM1 / PM1, PM8 / NM8, NM10 / NM11, and NM12 / NM13 are conducting. Therefore, NB = VIN, NA = PA = PB = VOUT. So, M1 / M2 / M4 are turned off; M3 is turned on, and the current flows from VIN to VA until VA = VIN.

[0050] ⑨ When t = t8, CLK3 / CLK4 / CLKA is at low level, and CLK1 / CLK2 / CLKB is at high level. At this time, only the paths of PM4 / PM5, PM6 / PM7, NM10 / NM11, and NM12 / NM13 are conducting. Therefore, NA = NB = VIN, PA = PB = VOUT. So, M1 / M2 / M3 / M4 are turned off;

[0051] ⑩ When t = t9, CLK1 / CLK3 / CLK4 / CLKA is at low level, and CLK2 / CLKB is at high level. At this time, only the paths of PM4 / PM5, PM6 / PM7, PM9 / NM9, and PM16 / NM16 are conducting. Therefore, PB = NA = NB = VIN, PA = VOUT. So, M1 / M3 / M4 are turned off; M2 is turned on, and the current flows from VB to VOUT until VOUT = VB.

[0052] The working principle time sequence ①②③④⑤⑥⑦⑧⑨⑩ is one CLK cycle. CLKA / CLKB / CLK1 / CLK2 / CLK3 / CLK4 are non - overlapping clocks with the same frequency and different phases. M1 / M2 / M3 / M4 are all individually turned on, and there is no situation of simultaneous conduction. DBBN / DBBP are the dynamic substrate bias circuits of NMOS and PMOS respectively. Using DBBN can make the Bulk of NMOS always connected to the end with a lower voltage. Similarly, using DBBP can make the Bulk of PMOS always connected to the end with a higher voltage.

[0053] Embodiment 2: Figure 1 It is a four - stage PUMP_STG series system structure. This structure is suitable for applications with high - voltage output and low - current driving ability, such as Vcc = 3.3v, pump_out = 13.2v; The number of stages is determined according to needs.

[0054] Embodiment 3: Figure 2 It is a two - series - two - parallel PUMP_STG system structure. This structure is suitable for applications with high - current driving ability. The number of parallel stages is determined according to needs.

[0055] The following points should be noted: First, in the description of this application, it should be noted that unless otherwise specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense, which can be mechanical connection or electrical connection, or the communication inside two components, and can be directly connected. The terms "upper", "lower", "left", "right", etc. are only used to represent the relative position relationship. When the absolute position of the object being described changes, the relative position relationship may change;

[0056] Second, in the drawings of the disclosed embodiments of the present invention, only the structures related to the disclosed embodiments are involved. For other structures, reference can be made to the general design. Without conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

[0057] Finally, the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A novel six-phase charge pump circuit structure, comprising a PUMP_REG circuit module (1), characterized in that: The input end of the PUMP_REG circuit module (1) is provided with a PUMP_STG circuit module (2), and the input end of the PUMP_STG circuit module (2) is provided with a six-phase non-overlapping clock circuit module (3). The PUMP_STG circuit module (2) further includes a PM9 transistor, a PM10 transistor, an NM10 transistor, a PM12 transistor, an NM12 transistor, and an NM14 transistor. The gate terminal of the PM10 transistor is connected to the gate terminal of the NM10 transistor, the gate terminal of the PM12 transistor is connected to the gate terminal of the NM12 transistor, and the source terminals of the PM9 transistor, the PM10 transistor, the drain terminal of the NM10 transistor, the source terminal of the PM12 transistor, the drain terminal of the NM12 transistor, and the source terminal of the NM14 transistor are all connected to the converted output voltage. The output end of the PM9 transistor is provided with an NM9 transistor, the output end of the PM10 transistor is provided with a PM11 transistor, the output end of the NM10 transistor is provided with an NM11 transistor, the output end of the PM12 transistor is provided with a PM13 transistor, the output end of the NM12 transistor is provided with an NM13 transistor, and the output end of the NM14 transistor is provided with a PM14 transistor. The drain terminal of the PM9 transistor is connected to the drain terminal of the NM9 transistor, the drain terminal of the PM10 transistor is connected to the source terminal of the PM11 transistor, the source terminal of the NM10 transistor is connected to the drain terminal of the NM11 transistor, the source terminal of the PM13 transistor is connected to the drain terminal of the PM12 transistor, the source terminal of the NM12 transistor is connected to the drain terminal of the NM13 transistor, and the drain terminal of the NM14 transistor is connected to the drain terminal of the PM14 transistor. The output ends of the NM9 transistor, the PM11 transistor, and the NM11 transistor are provided with a PM15 transistor, and the output ends of the PM13 transistor, the NM13 transistor, and the PM14 transistor are provided with a PM16 transistor. The source terminals of the NM9 transistor, the drain terminal of the PM11 transistor, and the source terminal of the NM11 transistor are all connected to the source terminal of the PM15 transistor. The drain terminal of the PM13 transistor, the source terminal of the NM13 transistor, and the source terminal of the PM14 transistor are all connected to the source terminal of the PM16 transistor. The output end of the PM15 transistor is provided with an NM15 transistor, and the output end of the PM16 transistor is provided with an NM16 transistor. The drain terminal of the NM15 transistor is connected to the drain terminal of the PM15 transistor, the drain terminal of the NM16 transistor is connected to the drain terminal of the PM16 transistor, the gate terminal of the PM15 transistor is connected to the gate terminal of the NM16 transistor, the gate terminal of the NM15 transistor is connected to the gate terminal of the PM16 transistor, and the source terminals of the NM15 transistor and the NM16 transistor both input a low-voltage domain voltage signal. The PUMP_STG circuit module (2) further includes an NM1 transistor, an NM2 transistor, a PM1 transistor, and a PM2 transistor. The source terminals of the NM1 transistor and the NM2 transistor are both connected to the converted output voltage. The drain terminal of the NM1 transistor is electrically connected to the drain terminal of the PM1 transistor, and the drain terminal of the NM2 transistor is electrically connected to the drain terminal of the PM2 transistor. The gate terminal of the NM1 transistor is electrically connected to the gate terminal of the PM2 transistor, and the gate terminal of the NM2 transistor is electrically connected to the gate terminal of the PM1 transistor; The PUMP_STG circuit module (2) further includes two DBBN modules, two DBBP modules, an M1 transistor, an M2 transistor, an M3 transistor, and an M4 transistor. The DBBN module is electrically connected to the DBBP module. The drain terminals of the M3 transistor and the M4 transistor both input low-voltage domain voltage signals. The drain terminals of the M1 transistor and the M2 transistor are both connected to the converted output voltage. The two DBBP modules are respectively electrically connected to the M1 transistor and the M2 transistor. The two DBBN modules are respectively electrically connected to the M3 transistor and the M4 transistor. The six-phase non-overlapping clock circuit module (3) includes a CLK1 interface, a CLK2 interface, a CLK3 interface, a CLK4 interface, a CLKA interface, and a CLKB interface; Among them, the PUMP_REG circuit module (1) adjusts the output of the charge_pump, connects the open-loop charge_pump into a closed-loop state, and adjusts the output stable voltage as needed. The six-phase non-overlapping clock is used to control the PUMP_STG, so that the transistors M1 / M2 / M3 / M4 are not simultaneously turned on and there is no overlap, avoiding mutual influence. The DBBN and DBBP modules are adopted to avoid the conduction and leakage of parasitic diodes. The phases of the CLK1 interface / CLK2 interface / CLK3 interface / CLK4 interface / CLKA interface / CLKB interface are sequentially misaligned, with the same frequency and a duty cycle of 50%.

2. The novel six-phase charge pump circuit structure according to claim 1, characterized in that: The output terminal of the PM1 transistor is provided with an NM3 transistor, a PM4 transistor, and an NM4 transistor. The output terminal of the PM2 transistor is provided with a PM6 transistor, an NM6 transistor, and a PM8 transistor. The source terminal of the NM3 transistor, the drain terminal of the PM4 transistor, and the source terminal of the NM4 transistor are all connected to the source terminal of the PM1 transistor. The drain terminal of the PM6 transistor, the source terminal of the NM6 transistor, and the source terminal of the PM8 transistor are all electrically connected to the source terminal of the PM2 transistor. The gate terminals of the PM4 transistor and the NM4 transistor are connected. The gate terminals of the PM6 transistor and the NM6 transistor are connected.

3. The novel six-phase charge pump circuit structure according to claim 2, characterized in that: The output terminal of the NM3 transistor is provided with a PM3 transistor, the output terminal of the PM4 transistor is provided with a PM5 transistor, the output terminal of the NM4 transistor is provided with an NM5 transistor, and the drain terminal of the PM3 transistor is connected to the drain terminal of the NM3 transistor, the drain terminal of the PM5 transistor is connected to the source terminal of the PM4 transistor, the source terminal of the NM5 transistor is connected to the drain terminal of the NM4 transistor, the gate terminal of the PM4 transistor is connected to the gate terminal of the NM4 transistor, and the gate terminal of the PM5 transistor is connected to the gate terminal of the NM5 transistor.

4. The novel six-phase charge pump circuit structure according to claim 2, characterized in that: The output terminal of the PM6 transistor is provided with a PM7 transistor, the output terminal of the NM6 transistor is provided with an NM7 transistor, the output terminal of the PM8 transistor is provided with an NM8 transistor, and the drain terminal of the PM7 transistor is connected to the source terminal of the PM6 transistor, the source terminal of the NM7 transistor is electrically connected to the drain terminal of the NM6 transistor, the drain terminal of the NM8 transistor is electrically connected to the drain terminal of the PM8 transistor, the gate terminal of the PM6 transistor is connected to the gate terminal of the NM6 transistor, and the gate terminal of the PM7 transistor is connected to the gate terminal of the NM7 transistor.

5. The novel six-phase charge pump circuit structure according to claim 3, characterized in that: The source terminals of the PM3 transistor, the PM5 transistor, the drain terminal of the NM5 transistor, the source terminal of the PM7 transistor, the drain terminal of the NM7 transistor, and the source terminal of the NM8 transistor are all input with low voltage domain voltage signals.

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