Readout circuit

Abstract

The present invention provides a readout circuit. The readout circuit is coupled to a pixel circuit and is used to read out a signal from the pixel circuit. The readout circuit includes a bias circuit. The bias circuit includes a common source and common gate transistor and a bias transistor. The first end of the common source and common gate transistor is coupled to the output end of the bias circuit and the pixel circuit. The second end of the common source and common gate transistor is coupled to the first end of the bias transistor. The second end of the bias transistor is coupled to a negative voltage. The readout circuit of the present invention can effectively read out a signal from a floating diffusion node of a pixel circuit.

Description

Technical Field

[0001] The present invention relates to a circuit, and in particular to a readout circuit. Background Art

[0002] Generally speaking, since the effective voltage range of the floating diffusion node in the pixel circuit of the image sensor is limited by the output voltage swing (OVS) of the readout circuit, the sensing signal provided by the photodiode of the pixel circuit may be truncated, and further cause image distortion. Therefore, regarding how to make the readout circuit have a wider output voltage swing, several embodiments of the solution are provided below. Summary of the invention

[0003] The present invention relates to a readout circuit and is capable of efficiently reading out a signal from a floating diffusion node of a pixel circuit.

[0004] The readout circuit of the present invention is suitable for coupling to a pixel circuit for reading out a signal from the pixel circuit. The readout circuit includes a bias circuit. The bias circuit includes a cascode transistor and a bias transistor. The first end of the cascode transistor is coupled to the output end of the bias circuit and the pixel circuit. The second end of the cascode transistor is coupled to the first end of the bias transistor. The second end of the bias transistor is coupled to a negative voltage.

[0005] Based on the above, according to the readout circuit of the present invention, the readout circuit is coupled to a negative voltage to provide a signal readout function with a high dynamic range effect.

[0006] In order to make the foregoing content more easily understood, several embodiments with drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.

[0008] Figure 1 is a schematic diagram showing a readout circuit and a pixel circuit according to an embodiment of the present invention.

[0009] Figure 2 is a schematic diagram showing a readout circuit and a pixel circuit according to another embodiment of the present invention.

[0010] Figure 3 FIG. 4 is a schematic diagram showing a readout circuit and a pixel circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0011] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0012] It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. In addition, it should be understood that the words and terms used herein are for illustrative purposes and should not be considered as limiting. The use of "including", "comprising" or "having" and variations thereof herein is intended to encompass the items listed thereafter and their equivalents and additional items. Unless otherwise limited, the terms "connected", "coupled" and "set" and variations thereof are used broadly herein and encompass direct connections, direct couplings and direct settings as well as indirect connections, indirect couplings and indirect settings.

[0013] Figure 1 is a schematic diagram showing a readout circuit and a pixel circuit according to an embodiment of the present invention. Figure 1 The readout circuit 100 includes a bias circuit 110. The readout circuit 100 may be integrated into an integrated chip (IC), such as a fingerprint sensor integrated chip. The bias circuit 110 includes a common source common gate transistor M CAS and bias transistor M bias . Cascode transistor M CAS The first end of the common-source common-gate transistor M is coupled to the output end Sout of the bias circuit 110 and the pixel circuit 200. CAS The second end of the bias transistor M bias The first end of the bias transistor M bias The second end is coupled to a negative voltage V MINUS In an embodiment of the present invention, the cascode transistor M CAS The control end receives the control signal C cas , and the cascode transistor M bias The control end receives the control signal C bias . Bias transistor M bias The common source and common gate transistor M is used to provide bias current for the pixel circuit. CAS To clamp the bias transistor M bias The drain voltage of the control signal C cas And control signal C bias can be fixed voltages, and the common source and common gate transistors M CAS With bias transistor M biasIn the embodiment of the present invention, due to the bias transistor M bias The second end is coupled to a negative voltage V MINUS Therefore, the pixel circuit 200 can provide a wider output voltage swing (OVS) through the output terminal Sout.

[0014] In an embodiment of the present invention, the pixel circuit 200 may be used to sense a fingerprint image. In other words, in other embodiments of the present invention, the readout circuit 100 may be applied to a fingerprint sensor. The fingerprint sensor may include a pixel array, and the pixel array includes a plurality of pixel circuits, such as Figure 1 Each column of the pixel array may include a single line (eg, signal line SL) and multiple rows of pixel circuits. Therefore, each single line of the fingerprint sensor is coupled to a readout circuit, such as Figure 1 The readout circuit 100 is provided in the embodiment of the present invention, and one readout circuit is used to read out the signals of the plurality of rows of pixel circuits in a time-sharing manner after the selection transistor of each of the plurality of rows of pixel circuits is turned on in a time-sharing manner.

[0015] In an embodiment of the present invention, the pixel circuit 200 is an active pixel sensor, but the present invention is not limited thereto. The pixel circuit 200 may include a reset transistor M RST , photodiode PD, source follower transistor M SF and select transistor M SEL . Reset transistor M RST , source follower transistor M SF and select transistor M SEL They can be metal-oxide-semiconductor field effect transistors (MOSFETs). RST The first end of the reset transistor M is coupled to the power supply voltage VDD, and the reset transistor M RST The second end of the photodiode PD is coupled to the floating diffusion node FN. The first end of the photodiode PD is coupled to the floating diffusion node FN, and the second end of the photodiode PD is coupled to the bias voltage V bias . Source follower transistor M SF The first end of the source follower transistor M is coupled to the power supply voltage VDD, and the source follower transistor M SF The control terminal of the select transistor M is coupled to the floating diffusion node FN. SEL The first end is coupled to the source follower transistor M SF The second end of the transistor M is selected SEL The second end of the transistor M is coupled to the common-source common-gate transistor M through the signal line SL. CAS The first end and the output end Sout.

[0016] In an embodiment of the present invention, during the sampling period, the reset transistor M RST Turn off and select transistor M SEL The control terminal of the photodiode PD receives the selection signal SEL to be turned on. The photodiode PD generates a photocurrent (dark current) during exposure, thus causing the voltage of the photodiode PD to drop. Therefore, the voltage of the floating diffusion node FN may change accordingly based on the voltage of the photodiode PD, and the selection transistor M SEL The sampling voltage corresponding to the voltage of the floating diffusion node FN is output to the readout circuit 100 through the signal line SL, so that the output terminal Sout outputs the sampling voltage to the related analog front-end circuit in the readout circuit 100. In addition, during the reset period, the reset transistor M RST The control terminal receives the reset signal S RST to be turned on, and the transistor M is selected SEL The control terminal of the photodiode PD receives the selection signal SEL so that it is also turned on. The photodiode PD is reset by the power supply voltage VDD, so the voltage of the photodiode PD is reset at the same time. Therefore, the selection transistor M SEL A background voltage corresponding to the voltage of the floating diffusion node FN is output to the readout circuit 100 through the signal line SL, so that the output terminal Sout outputs the background voltage to the analog front end in the readout circuit 100 .

[0017] In an embodiment of the present invention, the output voltage swing of the output terminal Sout satisfies the following equation (1), where the symbol 2*V OV Represents the bias transistor M bias and cascode transistor M CAS Two overdrive voltages, and the symbol V GS Represents the source follower transistor M SF In addition, the effective voltage range FN of the floating diffusion node FN effective The following equation (2) is satisfied. From equations (1) and (2), it can be seen that if the negative voltage V MINUS becomes lower, then the effective voltage range of the floating diffusion node FN becomes larger. Therefore, the following equation (3) can be derived by deriving equations (1) and (2). Therefore, in the embodiment of the present invention, the negative voltage V MINUS The following equation (3) is satisfied, so that the output terminal Sout can provide a wider output voltage swing accordingly. In addition, considering the common source common gate transistor M CAS and bias transistor M bias After the reliability, the negative voltage V MINUS It can be further designed to satisfy the following equation (4).

[0018] V MINUS +2×V OV ≤S out ≤VDD-V GS .........(1)

[0019] V MINUS +2×V OV +V GS ≤FN effective ≤VDD.........(2)

[0020] V MINUS ≤V bias -2×V Oy -V GS .........(3)

[0021] V MINUS >-2×V Oy .........(4)

[0022] Figure 2 is a schematic diagram showing a readout circuit and a pixel circuit according to another embodiment of the present invention. Figure 2 The readout circuit 300 includes a bias circuit 310 and a correlated double sampling circuit 330. The bias circuit 310 includes a common-source common-gate transistor M CAS and bias transistor M bias . Cascode transistor M CAS The first end of the common-source common-gate transistor M is coupled to the output end Sout of the bias circuit 310 and the pixel circuit 400, and the common-source common-gate transistor M CAS The second end of the bias transistor M bias The first end of the bias transistor M bias The second end is coupled to a negative voltage V MINUS In an embodiment of the present invention, the cascode transistor M CAS The control end receives the control signal C cas , and the cascode transistor M bias The control end receives the control signal C bias The pixel circuit 400 may include a reset transistor M RST , photodiode PD, source follower transistor M SF and select transistor M SEL . Reset transistor M RST The first end of the reset transistor M is coupled to the power supply voltage VDD, and the reset transistor M RST The second end of the photodiode PD is coupled to the floating diffusion node FN. The first end of the photodiode PD is coupled to the floating diffusion node FN, and the second end of the photodiode PD is coupled to the bias voltage V bias . Source follower transistor MSF The first end of the source follower transistor M is coupled to the power supply voltage VDD, and the source follower transistor M SF The control terminal of the select transistor M is coupled to the floating diffusion node FN. SEL The first end is coupled to the source follower transistor M SF The second end of the transistor M is selected SEL The second end of the transistor M is coupled to the common-source common-gate transistor M through the signal line SL. CAS However, it can be obtained from Figure 1 Sufficient teaching content, implementation details and technical features of the bias circuit 310 and the pixel circuit 400 of the embodiment can be found in the relevant description of the embodiment, and therefore they are not described in detail again.

[0023] In the embodiment of the present invention, the correlated double sampling circuit 330 includes a first switch circuit TG SHS , the first capacitor C SHS , the second switch circuit TG SHR and the second capacitor C SHR The first switch circuit TG SHS The first end of the first capacitor C is coupled to the output end Sout of the bias circuit 310. SHS The first end is coupled to the first switch circuit TG SHS The second end of the first capacitor C SHS The second end of the second switch circuit TG is coupled to the ground voltage AGND. SHR The first end of the second capacitor C is coupled to the output end Sout of the bias circuit 310. SHR The first end is coupled to the second switch circuit TG SHR The second end of the second capacitor C SHR The second end of the first capacitor C is coupled to the ground voltage AGND. SHS The second capacitor C is used to receive a sample-and-hold signal (SHS) from the output terminal Sout to store the sampled voltage. SHR The circuit is used to receive a sample-and-hold reset signal (SHR) from the output terminal Sout to store the background voltage.

[0024] In an embodiment of the present invention, the first switch circuit TG SHS and the second switch circuit TG SHR They are transmission gate circuits, but the present invention is not limited thereto. The first switch circuit TG SHSThe first transistor TG1 includes a first transistor TG1 and a second transistor TG2. The first transistor TG1 is a p-type transistor, and the second transistor TG2 is an n-type transistor. A first terminal of the first transistor TG1 is coupled to the output terminal Sout, and a second terminal of the first transistor TG1 is coupled to the first capacitor C SHS The first end of the second transistor TG2 is coupled to the output end Sout and the first end of the first transistor TG1, and the second end of the second transistor TG2 is coupled to the first capacitor C SHS The control terminal of the second transistor TG2 receives the switch signal SHS, and the control terminal of the first transistor TG1 receives the inverted switch signal The second switch circuit TG SHR The first terminal of the third transistor TG3 is coupled to the output terminal Sout, and the second terminal of the third transistor TG3 is coupled to the second capacitor Cout. SHR The first end of the fourth transistor TG4 is coupled to the output end Sout and the first end of the third transistor TG3, and the second end of the fourth transistor TG4 is coupled to the second capacitor C SHR The control terminal of the fourth transistor TG4 receives the switch signal SHR, and the control terminal of the third transistor TG3 receives the inverted switch signal

[0025] In an embodiment of the present invention, during the sampling period, the first switch circuit TG SHS is turned on and the second switch circuit TG SHR is turned off, so that the first capacitor C SHS The sampled voltage is stored. Then, during the reset period, the first switch circuit TG SHS is turned off and the second switch circuit TG SHR is turned on, so that the second capacitor C SHR Therefore, another back-end image processing circuit can read the first capacitor C SHS and the second capacitor C SHR However, it should be considered that the first switch circuit TG SHS and the second switch circuit TG SHRreliability. In the embodiment of the present invention, the first transistor to the fourth transistor TG1 to TG4 are MOSFETs respectively. Specifically, in the embodiment of the present invention, since the base-gate voltage overstress and drain-base voltage leakage of the second transistor TG2 and the fourth transistor TG4 are avoided, in addition to the above equations (3) and (4), the voltage of the output terminal Sout should be higher than or equal to the ground voltage AGND. Therefore, in other embodiments of the present invention, the negative voltage V MINUS For example, it may be designed to be equal to or approximately -0.6 volt (V), so that the output terminal Sout can provide a wider output voltage swing accordingly.

[0026] Figure 3 is a schematic diagram showing a readout circuit and a pixel circuit according to another embodiment of the present invention. Figure 3 The readout circuit 500 includes a bias circuit 510, a switched capacitor amplifier circuit 520, and a correlated double sampling circuit 530. The switched capacitor amplifier circuit 520 is coupled between the bias circuit 510 and the correlated double sampling circuit 530. The bias circuit 510 includes a common source common gate transistor M CAS and bias transistor M bias . Cascode transistor M CAS The first end of the transistor M is coupled to the output end Sout of the bias circuit 510 and the pixel circuit 600, and the common source common gate transistor M CAS The second end is coupled to the bias transistor M bias The first end of the bias transistor M bias The second end is coupled to a negative voltage V MINUS In an embodiment of the present invention, the cascode transistor M CAS The control end receives the control signal C cas , and the cascode transistor M bias The control end receives the control signal C bias The pixel circuit 600 may include a reset transistor M RST , photodiode PD, source follower transistor M SF and select transistor M SEL . Reset transistor M RST The first end of the reset transistor M is coupled to the power supply voltage VDD, and the reset transistor M RST The second end of the photodiode PD is coupled to the floating diffusion node FN. The first end of the photodiode PD is coupled to the floating diffusion node FN, and the second end of the photodiode PD is coupled to the bias voltage V bias . Source follower transistor M SF The first end of the source follower transistor M is coupled to the power supply voltage VDD, and the source follower transistor M SFThe control terminal of the select transistor M is coupled to the floating diffusion node FN. SEL The first end is coupled to the source follower transistor M SF The second end of the transistor M is selected SEL The second end of the transistor M is coupled to the common-source common-gate transistor M through the signal line SL. CAS However, it can be obtained from Figure 1 Sufficient teaching content, implementation details and technical features of the bias circuit 510 and the pixel circuit 600 of the embodiment can be found in the relevant description of the embodiment, and therefore they are not described in detail again.

[0027] In an embodiment of the present invention, the switched capacitor amplifier circuit 520 includes a series capacitor CS, an operational amplifier AP, a compensation capacitor CF, and a third switch circuit TG. rst . A first end of the series capacitor CS is coupled to the output end of the bias circuit 510. An inverting input end (-) of the operational amplifier AP is coupled to a second end of the series capacitor CS, a non-inverting input end (+) of the operational amplifier AP is coupled to a reference voltage Vref, and an output end of the operational amplifier AP is coupled to a correlated double sampling circuit 530. A first end of the compensation capacitor CF is coupled to the inverting input end of the operational amplifier AP, and a second end of the compensation capacitor CF is coupled to the output end of the operational amplifier AP. The third switch circuit TG rst The first end of the third switch circuit TG is coupled to the inverting input terminal of the operational amplifier AP, and the third switch circuit TG rst The second end of is coupled to the output end of the operational amplifier AP. The operational amplifier AP operates under the operating voltage AVDD and the ground voltage AGND.

[0028] In an embodiment of the present invention, the third switch circuit TG rst The invention comprises a fifth transistor TG5 and a sixth transistor TG6. The fifth transistor TG5 is a p-type transistor, and the sixth transistor TG6 is an n-type transistor. The first end of the fifth transistor TG5 is coupled to the inverting input end of the operational amplifier AP, and the second end of the fifth transistor TG5 is coupled to the output end of the operational amplifier AP. The first end of the sixth transistor TG6 is coupled to the inverting input end of the operational amplifier AP and the first end of the fifth transistor TG5, and the second end of the sixth transistor TG6 is coupled to the output end of the operational amplifier AP and the second end of the fifth transistor TG5. The control end of the sixth transistor TG6 receives the switch signal RST_OP, and the control end of the fifth transistor TG5 receives the inverted switch signal RST_OP.

[0029] In the embodiment of the present invention, the correlated double sampling circuit 530 includes a first switch circuit TG SHS , the first capacitor C SHS , the second switch circuit TG SHRand the second capacitor C SHR . The first switch circuit TG SHS The first end of the first capacitor C is coupled to the output end Sout of the bias circuit 510. SHS The first end is coupled to the first switch circuit TG SHS The second end of the first capacitor C SHS The second end of the second switch circuit TG is coupled to the ground voltage AGND. SHR The first end of the second capacitor C is coupled to the output end Sout of the bias circuit 510. SHR The first end is coupled to the second switch circuit TG SHR The second end of the second capacitor C SHR The second end of the first capacitor C is coupled to the ground voltage AGND. SHS The second capacitor C is used to receive a sample and hold signal (SHS) from the output terminal Sout to store the sampled voltage. SHR The output terminal Sout is used to receive a sample and hold reset signal (SHR) to store the background voltage.

[0030] In an embodiment of the present invention, the first switch circuit TG SHS and the second switch circuit TG SHR They are transmission gate circuits, but the present invention is not limited thereto. The first switch circuit TG SHS The first transistor TG1 includes a first transistor TG1 and a second transistor TG2. The first transistor TG1 is a p-type transistor, and the second transistor TG2 is an n-type transistor. A first terminal of the first transistor TG1 is coupled to the output terminal Sout, and a second terminal of the first transistor TG1 is coupled to the first capacitor C SHS The first end of the second transistor TG2 is coupled to the output end Sout and the first end of the first transistor TG1, and the second end of the second transistor TG2 is coupled to the first capacitor C SHS The control terminal of the second transistor TG2 receives the switch signal SHS, and the control terminal of the first transistor TG1 receives the inverted switch signal The second switch circuit TG SHR The first terminal of the third transistor TG3 is coupled to the output terminal Sout, and the second terminal of the third transistor TG3 is coupled to the second capacitor Cout. SHR The first end of the fourth transistor TG4 is coupled to the output end Sout and the first end of the third transistor TG3, and the second end of the fourth transistor TG4 is coupled to the second capacitor C SHRThe control terminal of the fourth transistor TG4 receives the switch signal SHR, and the control terminal of the third transistor TG3 receives the inverted switch signal However, it is available from Figure 2 Sufficient teachings, implementation details and technical features of the correlated double sampling circuit 530 of the embodiment are known from the related description of the embodiment, and therefore they are not described in detail again.

[0031] In an embodiment of the present invention, during the sampling period, the switch signal RST_OP may be the operating voltage AVDD, and the inverted switch signal The operational amplifier AP is operated in a unity-gain state to store the sampled voltage in the series capacitor CS. Then, the switch signal RST_OP is the ground voltage AGND, and the inverted switch signal Therefore, the operational amplifier AP operates in a capacitive feedback state so as to provide the sampled voltage stored in the series capacitor CS to the first capacitor C SHS In addition, during the reset period, the switch signal RST_OP may be the operating voltage AVDD, and the inverted switch signal The operational amplifier AP is thus operated in a unit gain state so as to store the background voltage in the series capacitor CS. Then, the switch signal RST_OP is the ground voltage AGND, and the inverted switch signal Therefore, the operational amplifier AP operates in a capacitive feedback state so as to provide the background voltage stored in the series capacitor CS to the first capacitor C SHR However, since the output terminal Sout is coupled in series to the series capacitor CS, and the operational amplifier AP feeds back the reference voltage Vref, there is no need to further consider the reliability of the second transistor TG2, the fourth transistor TG4, and the sixth transistor TG6. Therefore, in the embodiment of the present invention, the negative voltage V MINUS Satisfying the above equations (3) and (4) enables the output terminal Sout to provide a wider output voltage swing accordingly.

[0032] In summary, by specially designing the negative voltage coupled to the bias circuit, the readout circuit of the present invention can provide a wider output voltage swing. Therefore, the readout circuit of the present invention can provide an effective signal readout function with a high dynamic range effect.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A readout circuit for reading out a signal from a pixel circuit, characterized in that: include: A bias circuit, including a cascode transistor and a bias transistor; A correlated double sampling circuit, coupled to an output terminal of the bias circuit; as well as a switched capacitor amplifier circuit coupled between the output terminal of the bias circuit and the correlated double sampling circuit, wherein a first terminal of the cascode transistor is coupled to the output terminal of the bias circuit and the pixel circuit, a second terminal of the cascode transistor is coupled to a first terminal of the bias transistor, and a second terminal of the bias transistor is coupled to a negative voltage, The switched capacitor amplifier circuit comprises: a series capacitor, wherein a first end of the series capacitor is coupled to the output end of the bias circuit; an operational amplifier, wherein an inverting input terminal of the operational amplifier is coupled to the second end of the series capacitor, a non-inverting input terminal of the operational amplifier is coupled to a reference voltage, and an output terminal of the operational amplifier is coupled to the correlated double sampling circuit; a compensation capacitor, wherein a first end of the compensation capacitor is coupled to the inverting input terminal of the operational amplifier and a second end of the compensation capacitor is coupled to the output terminal of the operational amplifier; and a third switch circuit, wherein a first terminal of the third switch circuit is coupled to the inverting input terminal of the operational amplifier, and a second terminal of the third switch circuit is coupled to the output terminal of the operational amplifier, The pixel circuit comprises: a reset transistor, wherein a first terminal of the reset transistor is coupled to a supply voltage and a second terminal of the reset transistor is coupled to a floating diffusion node; a photodiode, wherein a first terminal of the photodiode is coupled to the floating diffusion node and a second terminal of the photodiode is coupled to a bias voltage; a source follower transistor, wherein a first terminal of the source follower transistor is coupled to the supply voltage and a control terminal of the source follower transistor is coupled to the floating diffusion node; and a select transistor, wherein a first terminal of the select transistor is coupled to a second terminal of the source follower transistor and a second terminal of the select transistor is coupled to the first terminal of the cascode transistor, The negative voltage satisfies the first equation: V MINUS ≤V bias -2×V OV -V GS , where the symbol V MINUS Indicates the negative voltage, symbol V bias represents the bias voltage received by the control terminal of the bias transistor, symbol 2*V OV represents the two overdrive voltages of the bias transistor and the cascode transistor, and the symbol V GS represents the gate-source voltage of the source follower transistor.

2. The readout circuit according to claim 1, characterized in that The pixel circuit is an active pixel sensor.

3. The readout circuit according to claim 1, characterized in that The negative voltage also satisfies the second equation: V MINUS >-2×V OV .

4. The readout circuit according to claim 1, characterized in that: The correlated double sampling circuit comprises: a first switch circuit, wherein a first terminal of the first switch circuit is coupled to the output terminal of the bias circuit; a first capacitor, wherein a first end of the first capacitor is coupled to a second end of the first switch circuit, and a second end of the first capacitor is coupled to a ground voltage; a second switch circuit, wherein a first terminal of the second switch circuit is coupled to the output terminal of the bias circuit; and A second capacitor, wherein a first terminal of the second capacitor is coupled to the second terminal of the second switch circuit, and a second terminal of the second capacitor is coupled to the ground voltage.

5. The readout circuit according to claim 4, characterized in that: The negative voltage is equal to -0.6V.

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