Current measurement device, molecular entity sensing device, method for measuring current, method for sensing molecular entity

Abstract

Methods and apparatus for measuring current are provided. In one arrangement, a first charge amplifier integrates the current to be measured. A processing circuit filters the output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module. A second charge amplifier integrates the current resulting from the filtered output from the first charge amplifier. The apparatus is configured to reset the first charge amplifier at the start of each sensing frame among a plurality of sensing frames. The processing circuit obtains at least a first sample of the output from the first charge amplifier within each sensing frame. Sampling of the first sample alternates between sampling through the first low-pass filter module and sampling through the second low-pass filter module from one sensing frame to the next.

Description

Technical Field

[0001] The present invention relates to the measurement of small electric currents with high sensitivity, specifically but not only in the context of sensing molecular entities, for example by the interaction between a molecular entity and a nanopore sensor. Background Art

[0002] It is known to use nanopore sensors comprising membrane proteins inserted in an amphiphilic membrane to sense molecular entities. The interaction between a molecular entity and a membrane protein can cause a modulation of the properties of an electrical signal that appears across the amphiphilic membrane. For example, the ionic current flowing through a membrane protein that is a protein pore can be modulated by the interaction. By monitoring the electrical signal that appears across the amphiphilic membrane, the modulation of the properties can be detected and thus the molecular entity can be sensed. Based on this principle, a variety of techniques have been proposed, an example of which is disclosed in WO-2008 / 102120.

[0003] Sensing molecular entities using nanopore sensors provides a method for identifying individual molecules and molecular entities. There are a wide range of possible applications, such as sequencing DNA or other nucleic acids; sensing chemical or biological molecules for security and defense; detecting biomarkers for diagnosis; screening ion channels for drug development; and analyzing the interaction between biomolecules without labels.

[0004] For DNA sequencing, the detected current is typically in the range of 20 pA to 100 pA, and in the case of an open pore, the current is in the range of 50 pA to 500 pA. The electronic detection of such currents is challenging. A combination of a multi-channel device and a sensor array can be employed. The device can be implemented using an application-specific integrated circuit (ASIC).

[0005] Sensitive current measurements are also required in other applications. For example, medical X-ray detectors that detect the charge generated by X-ray quanta in direct and indirect conversion materials are known. Such detectors typically also use ASICs, and the minimum charge detection level can be approximately 10,000 electrons, with approximately 1,000 electrons being the RMS noise. The X-ray detector can operate by accumulating charge on a capacitor. For example, the charge can be accumulated over a period of several milliseconds. The accumulated charge can be read out into a charge amplifier within a few microseconds. In this type of configuration, the current level is thus in the nanoampere region. X-ray detectors with thousands of sensing channels are known.

[0006] It is known that the charge levels obtained in nanopore sequencing applications are similar to those obtained in known X-ray detectors. A similar noise level is also required, typically corresponding to a current noise of approximately 2 pA RMS at 10 kHz sampling.

[0007] Figure 1An example current measurement device is shown, which is configured to measure the current flowing through a nanopore. Corresponding arrangements can be provided for medical X-ray detectors or other charge or current measurement devices, adjusted as appropriate.

[0008] The example device includes a charge integration amplifier 102 (which can also be referred to as a charge amplifier) that serves to integrate the charge flowing through the nanopore represented by resistor 101. A 50 pA current will generate a voltage of approximately 50 mV in 100 microseconds, with the component values shown in the figure. After 100 microseconds, the circuit is reset using a switch (not shown) on the integration capacitor (the 100 fF capacitor in Figure 1 ). Figure 2 Schematically shows how the voltage output rises with time during the integration process.

[0009] The inherent noise performance can be analyzed approximately as follows. Figure 3 Shows Figure 1 the main noise sources in the device. Resistor R PORE (with resistance R PORE ) represents the resistance of the nanopore. The noise in the resistor is represented by V NPORE . R PORE will typically be in the range of 3 GOhm to 20 GOhm or higher and will generate white noise V proportional to NPORE , where k B is the Boltzmann constant, and T is the temperature. The amplifier noise source is shown as V NAMP , and for a CMOS integrated amplifier, at 1 Hz, it will typically be about down to a white noise floor at frequencies exceeding 100 kHz An important component is the capacitance of the amphiphilic membrane (which can be a bilayer lipid membrane), which is labeled C BL . C BL is relatively large, for example, typically about 30 pF. Finally, the labeled electrode resistance R ELE and the associated noise V NELE . The value of R ELE can typically be about 4 kOhm.

[0010] Although the nanopore resistance R PORE is very high, it is severely filtered by the capacitance C BL , and its contribution to the overall RMS noise can be negligible except at very low frequencies. The amplifier noise V NAMP and the electrode resistance noise V NELEis a major contribution because it amplifies by the ratio of the amplification capacitance C BL to the capacitance C of the integrating capacitor FB . Typically, this ratio is about 300. The RMS current noise under these conditions is about 5 pA RMS, which is relatively high. The RMS current noise can be reduced by applying known filtering techniques. For example, by applying correlated double sampling (CDS) and low-pass (LP) filtering to the arrangement of Figure 3 , it is possible to reduce the noise level to about 1.4 pA, which is acceptable for many applications, including detecting biomolecules in nanopores. Correlated double sampling acts as a high-pass filter and thus combines as a band-pass filter at the sampling rate (or integration period) of the circuit.

[0011] Known circuit systems, especially sensing circuits or those for implementing the noise reduction techniques discussed above, may undesirably increase power consumption and require additional heat dissipation. This may limit practical applications, especially in cases where a large array of circuit systems is required to provide high throughput and / or in cases where implementation in small and / or battery-powered devices is desired. SUMMARY OF THE INVENTION

[0012] An object of the present invention is to at least partially solve one or more of the problems discussed above.

[0013] According to one aspect, there is provided a current measurement device comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter an output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module; and a second charge amplifier configured to integrate a current derived from the filtered output from the first charge amplifier, wherein: the device is configured to reset the first charge amplifier at the start of each sensing frame among a plurality of sensing frames; the processing circuit is configured to obtain at least a first sample of the output from the first charge amplifier within each sensing frame; and the sampling of the first sample alternates between sampling through the first low-pass filter module and sampling through the second low-pass filter module from one sensing frame to the next.

[0014] The alternation of sampling from one sensing frame to the next avoids the need for a buffer, thus allowing the circuit system to be implemented with fewer amplifiers. This helps to save power and / or limit heat dissipation without compromising noise suppression performance.

[0015] In one embodiment, the first low-pass filter module includes a first RC filter, and the second low-pass filter module includes a second RC filter. In each sensing frame in which the first sample is not sampled by the first low-pass filter module, the first sample from the previous sensing frame is stored in the capacitor component of the first RC filter in the form of charge; and in each sensing frame in which the first sample is not sampled by the second low-pass filter module, the first sample from the previous sensing frame is stored in the capacitor component of the second RC filter in the form of charge. The capacitor component of the first RC filter includes a first plurality of capacitors, and in each sensing frame in which the first sample is sampled by the first low-pass filter module, a selected attenuation is applied to the charge representing information about the current under test by sampling the charge only from a selected subset of the first plurality of capacitors; and the capacitor component of the second RC filter includes a second plurality of capacitors, and in each sensing frame in which the first sample is sampled by the second low-pass filter module, a selected attenuation is applied to the charge representing information about the current under test by sampling the charge only from a selected subset of the second plurality of capacitors.

[0016] Accordingly, a circuit system is provided that allows for selective attenuation to be applied without the need for an amplifier or introducing additional noise sources. This promotes power savings and / or limits heat dissipation.

[0017] In one embodiment, a first sample and a second sample of the output from the first charge amplifier are obtained in each sensing frame, and the processing circuit is configured to perform correlated double sampling using the first sample and the second sample. The processing circuit further includes at least one additional low-pass filter module; and the device is configured to sample the second sample through the at least one additional low-pass filter module.

[0018] In one embodiment, the at least one additional low-pass filter module consists of one additional low-pass filter module; and the device is configured such that sampling of the second sample is performed only through the additional low-pass filter module for all sensing frames.

[0019] Implementing correlated double sampling using only a single additional low-pass filter module reduces the silicon area requirements relative to an arrangement providing multiple separate additional low-pass filter modules.

[0020] In one embodiment, within each sensing frame of samples obtained by each of the first low-pass filter module, the second low-pass filter module, and the additional low-pass filter module, the respective low-pass filter module is reset. The reset of the low-pass filter module is performed by bypassing the resistive component of the RC filter of each low-pass filter module. The timing of the reset of each low-pass filter module is such that the samples are obtained at equal times after the reset of the low-pass filter module that samples each of the first and second samples.

[0021] This method means that the first sample is obtained at exactly the same point during the stabilization of the low-pass filter module as the second sample, which means that any effect of stabilization is the same for both samples and the difference between the obtained samples is canceled when it is part of the correlated double sampling procedure.

[0022] In one embodiment, the at least one additional low-pass filter module includes a third low-pass filter module and a fourth low-pass filter module, and the device is configured such that sampling of the second sample alternates between sampling through the third low-pass filter module and sampling through the fourth low-pass filter module from one sensing frame to the next.

[0023] This method allows for the implementation of correlated double sampling using relatively simple circuit timing.

[0024] In one embodiment, the first charge amplifier is configured to perform integration of current across a first capacitor element and a second capacitor element simultaneously, and perform the reset of the first charge amplifier by allowing the charge stored on the second capacitor element to flow into the first capacitor element and at least partially cancel the charge stored on the first capacitor element.

[0025] This charge-balanced soft reset method promotes low-frequency noise reduction, such as noise that may be generated by noise folding. The method also allows for the integration of the input signal to be performed with minimal or no interruption, thereby allowing the circuit to react to events that would otherwise not be obtained during the reset period. Additionally, the method can eliminate the need for correlated double sampling, thereby providing the charge amplifier with more time to stabilize (e.g., for an entire sensing frame), which means that the amplifier bandwidth and bias current can be reduced, thereby reducing power consumption.

[0026] According to one aspect, there is provided a current measurement device, the current measurement device comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter an output from the first charge amplifier; and a second charge amplifier configured to integrate a current derived from the filtered output from the first charge amplifier, wherein: the first charge amplifier is configured to perform the integration of the current simultaneously across a first capacitive element and a second capacitive element, and to perform a reset of the first charge amplifier by allowing charge stored on the second capacitive element to flow onto the first capacitive element and at least partially cancel out the charge stored on the first capacitive element.

[0027] According to one aspect, there is provided a current measurement device, the current measurement device comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter an output from the first charge amplifier; and a second charge amplifier configured to integrate a current derived from the filtered output from the first charge amplifier, wherein: the processing circuit is configured to enable information about the current to be measured to propagate from the first charge amplifier to the second charge amplifier through the processing circuit in the form of an amount of charge representing the current to be measured.

[0028] According to one aspect, there is provided a method of measuring current, the method comprising: integrating a current to be measured using a first charge amplifier; filtering an output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module; and integrating a current derived from the filtered output from the first charge amplifier using a second charge amplifier, wherein: the first charge amplifier is reset at the start of each sensing frame of a plurality of sensing frames; at least a first sample of the output from the first charge amplifier is obtained within each sensing frame; and the sampling of the first sample alternates between sampling through the first low-pass filter module and sampling through the second low-pass filter module from one sensing frame to the next.

[0029] According to one aspect, there is provided a method of measuring current, the method comprising: integrating a current to be measured using a first charge amplifier; filtering an output from the first charge amplifier; and integrating a current resulting from the filtered output from the first charge amplifier using a second charge amplifier, wherein: the integration of the current by the first charge amplifier is performed simultaneously across a first capacitive element and a second capacitive element, and the reset of the first charge amplifier is performed by allowing charge stored on the second capacitive element to flow onto the first capacitive element and at least partially cancel out the charge stored on the first capacitive element.

[0030] According to one aspect, there is provided a method of measuring current, the method comprising: integrating a current to be measured using a first charge amplifier; filtering an output from the first charge amplifier using a processing circuit; and integrating a current resulting from the filtered output from the first charge amplifier using a second charge amplifier, wherein: the processing circuit is configured such that information about the current to be measured propagates through the processing circuit from the first charge amplifier to the second charge amplifier in the form of an amount of charge representative of the current to be measured. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 3 The foregoing has been described above. Embodiments of the present invention will now be described only by way of example, with reference to the remaining drawings, in which corresponding reference numerals indicate corresponding components, and in which:

[0032] Figure 4 depicts an example prior art signal processing chain for measuring current using Figure 1 a circuit;

[0033] Figure 5 depicts an example current measurement device;

[0034] Figure 6 depicts an example of a low-pass filter without an amplifier;

[0035] Figure 7 depicts a timing diagram for operating Figure 5 a low-pass filter without an amplifier;

[0036] Figure 8 depicts Figure 5 a portion of a current measurement device adapted to perform correlated double sampling;

[0037] Figure 9 depicts a timing diagram for operating Figure 8 a current measurement device;

[0038] Figure 10 depictsFigure 8 A variant of the current measurement device that requires fewer different low-pass filter modules;

[0039] Figure 11 Depicts the timing diagram for operating Figure 10 the current measurement device;

[0040] Figures 12 - 15 Is a schematic diagram that depicts the origin of the residual correlated double sampling noise and how to avoid said origin by extracting the first sample and the second sample at equal times after the reset operation;

[0041] Figure 16 Depicts an arrangement that provides a SAR ADC after the second charge amplifier to provide a digital output signal;

[0042] Figure 17 Depicts Figure 16 an example of an alternative arrangement based on a multi-slope ADC for

[0043] Figure 18 Depicts an example architecture for implementing readout from multiple channels in a matrix array;

[0044] Figure 19 Depicts a charge amplifier in a configuration suitable for detecting small currents from a sensor;

[0045] Figure 20 Depicts the timing diagram for operating Figure 19 the circuit;

[0046] Figure 21 Depicts Figure 19 the combination of a charge amplifier of the type depicted in

[0047] Figure 22 Depicts an example arrangement for implementing charge-balanced soft reset;

[0048] Figure 23 Depicts Figure 22 a variant of the arrangement in which the use of a buffer amplifier reduces the load on the operational amplifier;

[0049] Figure 24 Depicts a test circuit for selectively implementing a hard reset mode and a charge-balanced soft reset mode;

[0050] Figure 25 Is a graph comparing the noise of two reset modes obtained using Figure 24 the test circuit;

[0051] Figure 26 Is a schematic diagram illustrating how the use of the charge-balanced soft reset mode reduces switching noise;

[0052] Figure 27 depicts a part of a current measurement device adapted for a charge balance soft reset mode corresponding to Figure 8 the current measurement device;

[0053] Figure 28 depicts a timing diagram for operating Figure 27 the current measurement device;

[0054] Figure 29 depicts Figure 27 a variant of the arrangement in which only a single pair of resistor elements is used instead of two pairs of resistor elements to implement two low - pass filter modules;

[0055] Figure 30 depicts Figure 27 and 29 a variant of the arrangement in which no separate resistor elements are used to implement two low - pass filter modules;

[0056] Figure 31 depicts a molecular sensing device; and

[0057] Figure 32 depicts Figure 31 an example sensor arrangement of the molecular sensing device. Detailed Description

[0058] Figure 4 depicts the use of Figure 1Example prior art signal processing chain for measuring current in a circuit. The signal processing chain is configured to measure current in an array of cells. Each cell may be referred to as a pixel. The pixels may be arranged in columns and rows. Noise reduction is implemented using correlated double sampling (CDS) and a low pass (LP) filter. The current to be measured is input to a charge amplifier 102 at point 150. The output from the charge amplifier 102 is input to an RC filter 103 (acting as an LP filter). An RC filter buffer 104 is provided between the charge amplifier 102 and a CDS amplifier with a second stage gain 105. The output from the CDS amplifier with the second stage gain 105 is input to a pixel sample and hold buffer 106. The pixel sample and hold buffer 106 temporarily stores a quantity of charge representative of the measured current before the pixel can be read out. A row multiplexing system 107 is provided for performing row multiplexing. The output from the row multiplexing system 107 is input to a column sample and hold buffer 108. A column multiplexing system 109 is provided for performing column multiplexing. The output from the column multiplexing system 109 is input to an analog-to-digital converter (ADC) data buffer 110. The output from the ADC data buffer 110 is input to a successive approximation register (SAR) ADC 111 (including a digital-to-analog converter (DAC) 112 and a comparator 113).

[0059] Figure 4 The arrangement includes six amplifiers and one comparator (within the SAR ADC 111) for various configurations. Embodiments of the present disclosure reduce power consumption by providing an arrangement that allows for implementing the current measurement device 200 with fewer amplifiers.

[0060] Figure 5 An example current measurement device 200 is depicted. The current measurement device 200 includes a first charge amplifier 201 configured to integrate the current to be measured (input at point 250). Processing circuitry is provided that filters the output from the first charge amplifier 201. A second charge amplifier 202 integrates the current resulting from the filtered output from the first charge amplifier 201.

[0061] The current measurement device 200 reduces the number of amplifiers required relative to the Figure 4 arrangement by replacing the RC filter 103 and the RC filter buffer 104 with a low pass filter 204 without an amplifier, which provides the same noise suppression performance without the need for any amplifiers. Thereby, power consumption is reduced.

[0062] In one category of embodiments, the strategy of avoiding the use of an amplifier extends to the entire signal path between a first charge amplifier 201 and a second charge amplifier 202. In such embodiments, the processing circuit is configured such that information regarding the current under test propagates through the processing circuit from the first charge amplifier 201 to the second charge amplifier 202 in the form of an amount of charge representing the current under test (optionally only in the form of an amount of charge). This can be achieved by configuring the processing circuit (i.e., the circuitry that carries charge between the first charge amplifier 201 and the second charge amplifier 202) such that it consists only of passive components and externally controllable switches. The following embodiments describe various techniques for implementing this strategy effectively and with minimal silicon area requirements.

[0063] Reference Figure 6 and 7 describes an example operation of an amplifierless low-pass filter 204. As Figure 6 shown, the amplifierless low-pass filter 204 includes a first low-pass filter module 206 and a second low-pass filter module 207. The terms "first" and "second" are used herein as labels for differentiating between the two low-pass filter modules. The term "module" is used to refer to an element that provides the functionality required for each low-pass filter module and is interchangeable with other equivalent terms such as "unit" or "device". The first low-pass filter module 206 includes a first RC filter, and the second low-pass filter module 207 includes a second RC filter. The period of time during which a single distinct measurement of current (which may involve extracting one or more samples of the integrated current) is made is referred to herein as a sensing frame. By alternately using the first low-pass filter module 206 and the second low-pass filter module 207 within different sensing frames, the need for an RC filter buffer 104, such as the filter buffer used in the arrangement of Figure 4 , may be avoided.

[0064] Figure 7 depicts an example timing diagram that shows the example operation of the amplifierless low-pass filter 204 depicted in Figure 5 and 6 . Figure 7 The horizontal axis in Figure 7 represents time. The vertical axis shows the variation over time of five signals 211 - 215 (described below). In the timing diagram of

[0065] The reset signal 211 is applied at the switch labeled 211. When the reset signal 211 is high, the first charge amplifier 201 is reset. Thus, the first charge amplifier 201 is reset at the start of each sensing frame among the sensing frames 221, 222.

[0066] The flip signal 212 is applied on Figure 6 the line shown. When the flip signal 212 is high, the capacitive component of the first low-pass filter module 206 is connected to the output of the first charge amplifier 201. When the flip signal 212 is low, the capacitive component of the second low-pass filter module 207 is connected to the output of the first charge amplifier 201. The capacitive component of the first low-pass filter module 206 is thus connected to the output of the first charge amplifier 201 during each first sensing frame 221, and the capacitive component of the second low-pass filter module 207 is connected to the output of the first charge amplifier 201 during each second sensing frame 222.

[0067] The signal 213 represents the output 213 of the first charge amplifier 201. During each sensing frame 221, 222, the output 213 continuously ramps up as charge is integrated from the point immediately after the reset signal 211 goes low to the point when the reset signal 211 next goes high at the end of the sensing frames 221, 222. The processing circuit obtains at least one sample of the output 213 from the first charge amplifier 201 downstream of the first charge amplifier 201 in order to obtain a measure of the current input at point 250.

[0068] The signal 214 represents the signal level available for the output from the first low-pass filter module 206. The signal 214 ramps up within each first sensing frame 221 (when the first low-pass filter module 206 is connected to the output 213 of the first charge amplifier 201) and remains flat within each second sensing frame 222, while the capacitive component of the first low-pass filter module 206 holds the charge sampled during the previous first sensing frame 221. The first low-pass filter module 206 is thus in a storage mode during each second sensing frame 222. The charge sampled by the first low-pass filter module 206 within each first sensing frame 221 can be read out at any time during the subsequent second sensing frame 222.

[0069] Signal 215 represents the signal level available for the output from the second low-pass filter module 207. Signal 215 ramps up within each second sensing frame 222 (when the second low-pass filter module 207 is connected to the output 213 of the first charge amplifier 201) and remains flat within each first sensing frame 221, while the capacitive component of the second low-pass filter module 207 holds the charge sampled during the previous second sensing frame 222. The second low-pass filter module 207 is thus in a storage mode during each first sensing frame 221. The charge sampled by the second low-pass filter module 207 within each second sensing frame 222 can be read out at any time during the following first sensing frame 221.

[0070] By using the Figure 7 timing diagram according to Figure 6 the circuit, a first sample of the output 213 of the first charge amplifier 201 can be obtained within each sensing frame 221, 222 without the need for an RC filter buffer (and associated amplifier), due to alternating sampling between sampling by the first low-pass filter module 206 and sampling by the second low-pass filter module 207. The total number of amplifiers required to implement the processing circuit is reduced, and the power consumption and / or heat dissipation are also reduced.

[0071] Figure 5 The current measurement device 200 of Figure 6 implements a second stage gain by using a capacitive component of a plurality of capacitors each having a capacitance that is electrically connected in parallel with each other instead of the Figure 4 first low-pass filter module 206 and the second low-pass filter module 207 shown in

[0072] Thus, an embodiment is provided in which, within each sensing frame in which sampling is not performed by the first low-pass filter module 206 (e.g., Figure 7 the second sensing frame 222 in the example of Figure 7 ), the sample from the previous sensing frame (e.g.,

[0073] the first sensing frame 221 in the example of Figure 7 ), is stored in the capacitive component of the first plurality of capacitors 2061 in the first RC filter including the first low-pass filter module 206 in the form of charge. Figure 7In the example of, samples of the second sensing frame 222 are stored in the form of charge on the capacitance components of the second plurality of capacitors 2071 in the second RC filter including the second low-pass filter module 207.

[0074] Within each second sensing frame 222, a selected attenuation (i.e., negative gain) is applied to the charge representing information about the current under test by sampling the charge only from a selected subset of the first plurality of capacitors 2061. Similarly, within each first sensing frame 221, a selected attenuation (i.e., negative gain) is applied to the charge representing information about the current under test by reading out the charge only from a selected subset of the second plurality of capacitors 2071.

[0075] In Figure 5 the example of, the first plurality of capacitors 2061 includes four capacitors. In other embodiments, the first plurality of capacitors 2061 includes a different number of capacitors. In one embodiment, within each first sensing frame 221, all the capacitors in the first plurality of capacitors 2061 are connected to the circuit (all the switches shown in the first low-pass filter module 206 are closed), such that the first low-pass filter module 206 operates optimally in RC filter mode (i.e., to achieve maximum filtering). Within each second sensing frame 222, selected switches in the first low-pass filter module 206 are opened so as to connect only a subset of the capacitors of the first plurality of capacitors 2061 to the circuit. Thus, only a portion of the total charge stored on the first plurality of capacitors is available for readout, thereby applying the desired attenuation. At the readout time within each second sensing frame, the switch activated by the AND gate 2062 (when the signal 212 is low and the readout signal Srr is high) allows the charge stored on the first plurality of capacitors 2061 to be read out.

[0076] The second plurality of capacitors 2071 is configured to operate in a similar manner. In the example, the second plurality of capacitors 2071 includes four capacitors, but a different number may be provided if desired. Within each second sensing frame 222, all the capacitors in the second plurality of capacitors 2071 are connected to the circuit (all the switches shown in the second low-pass filter module 207 are closed), such that the second low-pass filter module 207 operates optimally in RC filter mode (i.e., to achieve maximum filtering). Within each first sensing frame 221, selected switches in the second low-pass filter module 207 are opened so as to connect only a subset of the capacitors of the second plurality of capacitors 2071 to the circuit. Thus, only a portion of the total charge stored on the second plurality of capacitors is available for readout, thereby applying the desired attenuation. At the readout time within each first sensing frame 221, the switch activated by the AND gate 2072 (when both 212 and Srr are high) allows the charge stored on the capacitors to be read out.

[0077] The example timing diagram is shown in the lower left of Figure 5 . The timing is shown for the case where there are multiple rows of pixels to allow reading out from the array. Then, multiple readout signals Srr-r0, Srr-r1, … Srr-rn are provided for the 0th row, 1st row, … nth row. The Srr signals are arranged to read out from each row in the row at different times.

[0078] Figure 8 and 10 depicts an alternative adjustment of the circuit for implementing correlated double sampling of Figure 5 . The two arrangements are examples of embodiments of a kind where, within each sensing frame 221, 222, a first sample and a second sample of the output 213 of the first charge amplifier 201 are obtained, and the processing circuit is configured to perform correlated double sampling using the first sample and the second sample.

[0079] Figure 8 An example timing diagram of the arrangement of Figure 9 is shown in Figure 10 An example timing diagram of the arrangement of Figure 11 is shown in Figure 7 . Signals 211 - 213 correspond to signals 211 - 213 described above with reference to

[0080] To perform correlated double sampling, the processing circuit includes at least one additional low-pass filter module with respect to the arrangement of Figure 5 . In an embodiment of a kind where Figure 8 and 10 are examples, the sampling of the first sample alternates between sampling by the first low-pass filter module 206 and sampling by the second low-pass filter module 207 from one sensing frame 221 to the next sensing frame 222. In the examples of Figure 8 and 9 , the first sample is sampled by the first low-pass filter module 206 within each first sensing frame 221 and read out from the first low-pass filter module 206 (when in the storage mode) within the next second sensing frame 222. The first sample is sampled by the second low-pass filter module 207 within each second sensing frame 222 and read out from the second low-pass filter module 207 (when in the storage mode) within the next first sensing frame 221. Figure 8 and10 Each depicts two possibilities for sampling a second sample in this scenario. In both cases, sampling of the second sample is performed by at least one additional low-pass filter module.

[0081] In Figure 8 the arrangement of, the at least one additional low-pass filter module includes a third low-pass filter module 208 and a fourth low-pass filter module 209. In this arrangement, sampling of the second sample alternates between sampling through the third low-pass filter module 208 and sampling through the fourth low-pass filter module 209 from one sensing frame 221 to the next sensing frame 222. In Figure 8 and 9 the example of, the second sample is sampled through the third low-pass filter module 208 within each first sensing frame 221 and read out from the third low-pass filter module 208 (when in storage mode) within the next second sensing frame 222. The second sample is sampled through the fourth low-pass filter module 209 within each second sensing frame 222 and read out from the fourth low-pass filter module 209 (when in storage mode) within the next first sensing frame 221.

[0082] In the illustrated example, the third low-pass filter module 208 includes a third RC filter, and the fourth low-pass filter module 209 includes a fourth RC filter. Each of the third RC filter and the fourth RC filter can be configured in any of the ways described above for the first RC filter and the second RC filter, respectively. In the illustrated embodiment, the capacitive component of the third RC filter includes a third plurality of capacitors 2081. In one embodiment, the capacitive component of the fourth RC filter includes a fourth plurality of capacitors 2091. In the illustrated example, each of the plurality of capacitors 2081 and 2091 includes four capacitors. In other embodiments, each of one or both of the third plurality of capacitors 2081 and the fourth plurality of capacitors 2091 can include a different number of capacitors. The third plurality of capacitors 2081 and the fourth plurality of capacitors 2091 can operate in the same manner as the first plurality of capacitors 2061 and the second plurality of capacitors 2071. That is, when the corresponding third or fourth RC filter operates in filter form, all the capacitors can be connected to the circuit to optimize filtering. When reading the corresponding third or fourth RC filter, only a subset of the capacitors can be connected to the circuit so that only a portion of the total charge stored on the plurality of capacitors is available for readout, thereby applying a desired attenuation.

[0083] In one embodiment, by having a low-pass filter module (e.g., Figure 8 as illustrated by the dashed box inFigure 8 The output of the first plurality of capacitors 2061 or the second plurality of capacitors 2071) is combined with the output from a low-pass filter module that stores the charge corresponding to the second sample (e.g., Figure 8 The output of the third plurality of capacitors 2081 or the fourth set of capacitors 2091) in is combined to implement the difference between the first sample and the second sample within each sensing frame 221, 222. Thus, with respect to the connection of the third low-pass filter module 208 and the fourth low-pass filter module 209 to the output lines 231 and 232, the first low-pass filter module 206 and the second low-pass filter module 207 are connected to the output lines 231 and 232 leading to the second charge amplifier 202 in a reverse configuration.

[0084] Figure 10 An example of an embodiment is depicted where sampling of the second sample is performed for all sensing frames by the same single low-pass filter in at least one additional low-pass filter module. In the example shown, there is only one additional low-pass filter module 208. For all sensing frames, sampling of the second sample is performed only by a single additional low-pass filter module. By arranging the reset of the low-pass filter modules under discussion within each sensing frame 221, 222 for which samples are to be obtained in each of the low-pass filters in the first low-pass filter module 206, the second low-pass filter module 207, and the additional low-pass filter module 208, it is possible to obtain the second sample without the need for two additional low-pass filter modules (as in the embodiments of Figure 8 and 9 ). For example, the first low-pass filter module 206 is reset at least within the sensing frame 221 in which the first low-pass filter module 206 obtains the first sample, the second low-pass filter module 207 is reset at least within the sensing frame 222 in which the second low-pass filter module 207 obtains the first sample, and the additional low-pass filter module 208 is reset within each sensing frame 221 and 222 used to obtain the second sample). The reset of the low-pass filter modules is performed by bypassing the resistance component of the RC filter of each low-pass filter module. Furthermore, low noise is achieved by arranging the timing of the reset of each low-pass filter module such that the samples are obtained at equal times after the reset of the low-pass filter module that samples each of the first sample and the second sample.

[0085] Figure 11 An example timing diagram is shown. Signals 211 - 213 correspond to signals 211 - 213 described above with reference to Figure 7 Additional signals 216 and 217 are provided to implement correlated double sampling. Further additional signals 218 and 219 are provided to perform the disconnection from Figure 10The switches in parallel with the resistors labeled R1 and R2 in the figure reset the low-pass filter modules 206, 207, and 208. Each of the low-pass filter modules 206, 207, and 208 in this example is thus reset by bypassing the resistive component of the RC filter in each low-pass filter module. Signals 211 - 213 and 216 - 219 cause a first sample to be obtained through the first low-pass filter module 206 within each first sensing frame 221 and a first sample to be obtained through the second low-pass filter module 207 within each second sensing frame 222. A second sample is obtained through the additional low-pass filter module 208 within each sensing frame (i.e., each first sensing frame 221 and each second sensing frame 222). This functionality is enabled by obtaining the samples at equal times after the reset of the low-pass filter module that samples each of the first and second samples, which in the illustrated example is achieved by having pulses in signal 218 or 219 that coincide with the start of each pulse in signals 216 and 217 and are shorter in length than each pulse in signals 216 and 217. Thus, at the start of each pulse in signal 216 that controls when the first sample is obtained, signal 218 resets all the low-pass filter modules (i.e., bypasses the resistive component so that the capacitive component is directly connected to the first charge amplifier 201). The reset of each low-pass filter module causes the plurality of capacitors to be quickly charged to the voltage defined by the charge at the output of the first charge amplifier 201 at the corresponding time point. After each reset of the low-pass filter module, the low-pass filter module is allowed to reach stability before extracting the first or second sample.

[0086] The two signals 216 and 217 that implement correlated double sampling overlap with the two signals 218 and 219 that implement the reset. Signals 216 and 218 operate together, and signals 217 and 219 operate together. The first and second samples are obtained at the falling edges of the pulses in signals 216 and 217. To achieve ideal noise performance, the time difference between 218 and the falling edge of the pulse in 216 should be the same as the time difference between 219 and the falling edge of the pulse in 217 (an example that meets the above optional requirement: obtaining the samples at the same time after the reset of the low-pass filter module that samples the first and second samples).

[0087] As referred to above Figure 10 and 11The noise in a circuit of the described type has two components: a switching component and a continuous component. When the reset of the first charge amplifier 201 is released (i.e., goes low), the broadband noise of the first charge amplifier 201 is folded into the baseband defined by the sampling frequency. This results in a change in the random offset of the first charge amplifier 201 for each field. This is the switching component of the noise. In addition to the switching component of the noise, the continuous component of the noise from, for example, the first charge amplifier also contributes.

[0088] Correlated double sampling is intended to reduce the switching component of the noise, i.e., the low-frequency component. RC filtering implemented by a low-pass filter module reduces the continuous component of the noise. However, the output from each low-pass filter module takes time to settle to the ramp output of the first charge amplifier 201. Thus, when performing correlated double sampling, a long delay may be introduced before the first sample is obtained. However, this is not desirable as it results in a reduction in the measured signal, effectively increasing the noise. An alternative is to obtain the first sample before the low-pass filter module has settled, but this may produce a residual switching component of the noise.

[0089] These effects are as Figures 12 - 15 shown. Figures 12 - 15 The horizontal axis in each of Figure 12 represents time. The vertical axis in Figure 13 represents the output 213 of the first charge amplifier 201 (showing a ramp corresponding to the integration of the current to be measured) for three example implementations (each representing a different realization of the random noise composed of the continuous component 301 and the switching component 302 mentioned above). The switching component of the noise causes the ramp (depicted by three smooth background curves) to shift vertically (after the first charge amplifier 201 exits reset and starts integrating charge). The continuous component of the noise is shown as a fast-fluctuating signal superimposed on top of each smooth background curve. Applying a low-pass filter to the output (e.g., one or more of the low-pass filter modules described above) results in a filtered output signal 214 as schematically shown in Figure 14 . Filtering smooths the continuous component 301 of the noise but has no effect on the switching component 302 of the noise. Correlated double sampling points corresponding to signals 216 and 217 are shown in the figure (the former indicating the time at which the first sample is taken and the latter indicating the time at which the second sample is taken). Correlated double sampling should completely remove the switching component 302 of the noise. However, as Figure 14 indicates (which shows the filtered output signal 214 with only the switching component 302 of the noise present (for clarity, the continuous component 301 of the noise has been artificially set to zero)), the first sample is taken before the filter has settled to the continuous (linear portion) ramp. This results in a residual correlated double sampling noise 303 as indicated by the dashed curve in

[0090] The method described above with reference to 10 and 11 reduces or eliminates any negative impact of this effect by arranging the samples obtained at the same time after the reset of the low-pass filter module that samples the first and second samples of the relevant double sampling. As a result, the first sample is obtained at exactly the same point as the second sample during the stabilization of the low-pass filter module.

[0091] Figure 15 The method is illustrated. The dashed curve 304 schematically depicts the stabilization of the low-pass filter module just before sampling each of the first and second samples (at points 216 and 217 respectively). Instead of waiting for the low-pass filter module to stabilize, the method obtains the first and second samples simultaneously after the start of stabilization. The relevant double sampling involves extracting the difference between two samples (the first sample and the second sample), and thus eliminates the residual switching component of the noise (the residual switching component makes the same contribution to the first and second samples). In Figure 11 , the timing diagram shows the pulses in the 216 and 217 signals. The output of the low-pass filter module starts to stabilize within the corresponding pulses in the 216 and 217 signals, and the first and second samples are sampled as the corresponding pulses in the 216 and 217 signals go low. Thus, when the pulses in the 216 and 217 signals are high, Figure 15 the dashed curve 304 in

[0092] Although more complex in terms of timing signals, Figure 10 and 11 's method can be implemented in the low-pass filter module using fewer capacitors and fewer resistors compared to Figure 8 and 9 's method, thereby saving silicon area.

[0093] Figure 16 An embodiment is depicted in which a SAR ADC 310 is provided after the second charge amplifier 202 to provide a digital output signal 312. This arrangement can be compatible with any of the embodiments discussed above with reference to Figures 5 - 15 . Using a SAR ADC reduces the power requirements relative to other ADCs, but other ADCs can still be used as an alternative. If a SAR ADC is used after the second charge amplifier 202, providing the SAR ADC after the second charge amplifier 202 improves the efficiency in terms of the amplifier (i.e., it can be implemented using fewer amplifiers).

[0094] The SAR ADC is one of the most power - efficient ADC architectures, but there are some issues to consider. The linearity of the SAR ADC is typically limited to 10 bits. Using techniques such as sigma - delta modulation can achieve higher linearity, but this may increase power consumption. Another issue is that the SAR ADC may be relatively large, so it may be desirable to multiplex several columns into each provided SAR ADC. This method will require driving a large input load of the SAR ADC quickly, which may increase power consumption.

[0095] Another ADC architecture is the multi - slope ADC. Using this architecture together with the second charge amplifier 202 allows charge read - out from the pixel and analog - to - digital conversion to be performed within the same module. This is efficient in terms of circuit area and power. Figure 17 An example arrangement of the multi - slope ADC architecture 320 incorporating the second charge amplifier 202 is shown. The multi - slope ADC architecture 320 can be used in combination with any of the embodiments discussed above Figures 5 - 15 discussed.

[0096] The multi - slope ADC architecture 320 includes a second charge amplifier 202, a first charge DAC feedback unit 321, a second charge DAC feedback unit 322, a comparator 323, and a digital control unit 324 configured to output a digital output signal 312. In operation, the charge received from the upstream circuitry led out from the first charge amplifier 202 (as described above with reference to Figures 5 - 15 ) is presented to the comparator 323 of the multi - slope ADC architecture 320 in the form of a voltage by the second charge amplifier 202. After stabilizing to an accurate voltage, the analog - to - digital conversion can proceed. This can be done through current or charge feedback. Figure 17 An example of charge feedback is depicted. Feedback is performed on a current or charge packet (such as in Figure 17 ) through the first charge DAC feedback unit 321 and the second charge DAC feedback unit 322 in the shown example, such that the output of the second charge amplifier 202 is pulled to the crossover point of the comparator 323. The number of current or charge steps required to perform this operation represents the most significant bit (MSB) value. The converter then changes to a second slope, in which the least significant bit (LSB) is found by the same method to achieve full digital data conversion. Additional slopes can be added if desired. The arrangement provides the dual function of charge read - out from the pixel and ADC conversion, which saves power and silicon area. The multi - slope ADC architecture 320 can be adapted to operate in a single - slope mode, but this reduces the conversion rate and may not be very practical for some applications.

[0097] Figure 18Schematically shows an architecture for implementing readout from multiple channels (which may be referred to as pixels) in a matrix array. Each channel is labeled C(i,j), where i represents the row number and j represents the column number. Each channel includes circuitry for measuring current, and the circuitry can be configured according to any of the embodiments described above with reference to Figures 5 - 15 In the illustrated example, each column provides N channels (arranged horizontally). The N channels can be read according to the timing diagram depicted in the lower portion as Figure 5 (by signals Srr-r0, Srr-r1, etc.). The N channels in each column are connected to an integrated component 340(j), which is configured to perform the dual functions of charge readout (through a second charge amplifier 202) and analog-to-digital conversion, as described above with reference to Figure 15 and 16 Any of the embodiments discussed above in connection with Figure 15 and 16 can be used to implement the integrated component 340(j). In the illustrated example, M columns are provided, so there are M integrated components 340(j), where each integrated component outputs a digital output signal 312 that can be read from the ASIC using a number of standard techniques. The channels are addressed by a row controller 330 that generates the Figure 5 shown Srr signal. The Srr signal is activated once within each sense frame 221, 222 for each channel C(i,j). In the illustrated embodiment, each integrated component 340(j) addresses a single column. In other embodiments, one or more of the integrated components 340(j) can be configured to address multiple columns.

[0098] The following description presents an alternative reset mechanism for resetting the charge amplifier, which is referred to herein as charge balance soft reset. After this introduction, embodiments utilizing charge balance soft reset will be described.

[0099] Figure 19 Depicts a charge amplifier 410 in a configuration suitable for detecting small currents from a sensor element. The sensor element behaves as a current source, and the charge amplifier performs charge-voltage conversion by integrating charge.

[0100] When the reset switch 400 is open, the input current i FB is integrated in the capacitor C in The gain of the circuit depends on the feedback network. In some applications, a resistor is used in parallel with the feedback capacitor, but this is impractical when currents in the pA range must be detected and thus very high gain is required. In such cases, the amplifier is reset after each integration interval as shown in Figure 20

[0101] During reset, the integration of the input current is interrupted. The reset operation causes noise folding, which increases the output noise level. The noise from the operational amplifier (OpAmp) 405 can be represented by the input noise voltage source v n ; see Figure 21 .

[0102] Figure 21 depicts Figure 19 a combination of a charge amplifier 410 of the type depicted in FB with a sensor 401 (represented as the source of the current measured by the charge amplifier 410). The combination of the charge amplifier 410 and the sensor 401 provides a voltage gain of Cs / C FB for the OpAmp 405 noise voltage vn. At the moment when the reset switch 400 is opened, the amplified OpAmp 405 noise is sampled on the integration capacitor C FB . In the time domain, this is seen as an offset voltage that varies randomly at the start of each integration period and is equivalent to the noise folding effect that is typically analyzed in the frequency domain. To limit the overall noise, the output signal of the charge amplifier 410 is usually filtered using low-pass and / or high-pass filters. The filters can be passive or discrete-time. For example, a correlated double sampling (CDS) filter can be applied as a high-pass filter. High-pass filters are an effective means of filtering out low-frequency noise that can be high for practical OpAmps 405. Most CMOS amplifiers are dominated by 1 / f noise at low frequencies.

[0103] An alternative charge-balanced soft reset method is now described. The charge-balanced soft reset method replaces the charge amplifier reset operation described above with a mechanism based on charge cancellation. The charge-balanced soft reset method promotes low-frequency noise reduction, such as noise that may be generated by noise folding. The charge-balanced soft reset method is also compatible with output filtering for further noise reduction. Figures 19 - 21 The charge-balanced soft reset method has the additional advantage that the integration of the input signal occurs without interruption. In the

[0104] hard reset method of the Figures 19 - 21 arrangement, the charge amplifier 410 does not respond to the input current when the charge amplifier 410 remains in reset. The charge-balanced soft reset method allows for uninterrupted integration, which makes it possible to respond to additional events that would otherwise not be captured during the reset period.

[0105] The charge-balanced soft reset method can be implemented in such a way that the charge amplifier 410 is still effectively reset once within the sensing frame T.

[0106] Figure 22 depicts an arrangement for implementing the charge-balanced soft reset method. If it is assumed that in Figure 22If an ideal OpAmp 405 is used within the charge amplifier 410 (e.g., without input offset, without noise, and with infinite open-loop gain), then at the end of the integration period, the voltage across the feedback capacitor C FB equals v out (T) – V ref . In the shown arrangement, a second capacitor C f is connected between the output and the reference voltage V ref provided that the control signal 403 is low.

[0107] As long as the control signal 403 is low, the voltage across C f equals the voltage across C FB , and if C f is selected to be equal to C FB , then the charge at C f will be equal to the charge at C FB . When the control signal 403 goes high, the capacitor C f is disconnected from the output and connected to the amplifier signal input, such as virtual ground. This causes the capacitor C f to discharge into C FB , which enables an effective reset of the capacitor C FB in a soft manner. During this charge balancing process, the integration of the input signal continues.

[0108] To precisely cancel the charge at the end of the integration period, C f needs to be selected to be equal to C FB . If the charge amplifier 410 has programmable gain through a programmable capacitor C FB , then the capacitor C f must also be programmable.

[0109] No additional control signal is required to implement the charge balancing soft reset. The reset signal 400 that controls the reset switch in the Figure 19 implementation can be used to control the charge balancing switch, such as the switch that receives the balance signal 403 in the circuit of Figure 22 in the Figure 22 circuit. Thus, the power dissipation is not increased.

[0110] Figure 22 The circuit of Figure 23 adds a capacitive load to the output of the OpAmp 405. Depending on the nature of the OpAmp 405 and the capacitor values, the stability of the circuit may be reduced. Figure 23 An alternative implementation that reduces the load on the OpAmp 405 by introducing a buffer amplifier 406 is shown in f . If the buffer amplifier 406 has a gain A, then the capacitor C f= C FB / A to achieve the correct charge amount during feedback. It is also possible to save chip area by introducing a buffer amplifier 406 in the case of a large capacitor area of C FB .

[0111] Due to mismatches, the value of the copy capacitor will not be an exact copy of the integrating capacitor. This results in a systematic offset of the output voltage. Other defects such as charge injection from the switching network can also cause a systematic output offset. If desired, this offset can be eliminated by high-pass filtering the output signal.

[0112] Figure 24 Depicts a test circuit capable of implementing both the hard reset mode and the charge-balanced soft reset mode described above with reference to Figures 19 - 21 . It is possible to select between the two modes for comparison. The noise spectral density of OpAmp 405 exhibits 1 / f at the frequencies of interest, e.g., f < 1 / T, where T is the integration interval (the size of the sensing frame). In the test experiment, the charge amplifier 410 was evaluated using an integration interval of T = 100 microseconds, while the low-pass filter 412 operates at a corner frequency of 10 kHz. The timing of the CDS high-pass filter is programmable and is defined by the signal 414. The measurement results of the input-referred noise current (vertical axis) are shown in Figure 25 as a function of time from the reset signal 400 to the CDS signal 414. The solid line shows the noise variation of the charge-balanced soft reset mode. The dashed line shows the noise variation of the hard reset mode. The charge-balanced soft reset mode achieves lower circuit noise in all cases. The minimum noise is reduced by approximately 15%. The impact of low-frequency noise is most pronounced shortly after the reset action, when up to a two-fold noise reduction is achieved.

[0113] The above with reference to Figure 8 The described current measurement device reduces the power requirement by reducing the number of amplifiers required to implement the current measurement function. However, the large number of components required for the implementation circuit means that a relatively large silicon area is needed. The above with reference to Figure 10 The described current measurement device reduces the amount of silicon area required for implementation by reducing the number of resistors and capacitors required for the low-pass filter module. In the above section, a charge-balanced soft reset mechanism is disclosed, which is used to achieve a combination of low-noise current detection with an RC filter and related double sampling.

[0114] The challenge with all these methods is that the circuit system for implementation must have sufficient speed, which can be achieved by providing appropriate amplifier bandwidth and bias current. For example, when using Figure 11When equalizing the timings depicted, the circuit needs to stabilize to its operating point within a much shorter time period than the sensing frame, e.g., at most 100 times shorter. Providing high amplifier bandwidth and bias current may lead to higher power requirements and higher noise (due to the wider bandwidth).

[0115] Embodiments are described below that utilize the charge-balanced soft reset mechanism described above to create a low-power circuit by eliminating the need for circuit stabilization and associated double sampling of the circuit during the reset period. Then only one sample is required for each sensing frame (as opposed to two samples for associated double sampling, one at the start of the sensing frame and one at the end of the sensing frame). This approach means that the amplifier involved can stabilize over the entire sensing frame rather than at most 1 / 100th of the sensing frame. This means that the amplifier bandwidth and bias current can be significantly reduced. This reduces power consumption. Low noise is also maintained. The circuitry required to implement this method is simple and adds little to the silicon area requirements.

[0116] As referred to above Figures 19 - 25 The principle of charge balancing (which can also be referred to as charge feedback), as described above, involves sampling the output of a charge amplifier and feeding the sampled output back to the input at regular intervals to bring the output back to the reset level. In principle, this compensates for the switching component of the noise. However, resetting the charge amplifier causes noise folding. Under normal reset conditions, the charge amplifier is a buffer with a gain of 1 up to its unity gain bandwidth. Now consider noise frequencies far beyond the sampling rate (e.g., 10 MHz when the sampling rate is 10 kHz). The noise is sampled in buffer mode and has a full gain of 1 when the charge amplifier is below the unity gain bandwidth. Then, when exiting reset to the inverting charge amplifier mode, the charge amplifier gets a gain given by the ratio of the capacitance at the input of the charge amplifier (e.g., the capacitance of the amphiphilic membrane when the device is used to measure the current associated with a nanopore) to the integration capacitance C FB (See, for example Figure 19 ) such as 30 to 300, but it takes a few microseconds to achieve this (i.e., the noise folds back to low frequencies). Since most of the noise is at high frequencies, this effect is significant and results in a large switching component of the noise, much larger than the continuous noise in charge mode. In the charge reset mode, the charge amplifier is always in the inverting charge amplification mode. Therefore, no gain is seen at high frequencies due to the amplifier characteristics (see above). When charge balancing is used, the noise folding results in a lower gain due to the charge amplifier characteristics. This means that the switching component of the noise is quite low. This improvement can be achieved regardless of the unity gain bandwidth of the amplifier (assuming unipolar amplifier characteristics).

[0117] Figure 26is a graph of the gain G against frequency, which schematically shows these concepts, where 421 represents the charge gain, 422 represents the uniform gain, and the gain reduction from the amplifier is represented by 423 (i.e., the noise gets a lower gain corresponding to curve 422 rather than the gain of curve 421, and thus has less impact). Analyzing the noise (in a simplified way for illustrative purposes), for the normal reset operation mode, the noise from the charge amplifier in the time domain can be characterized as two parts: the continuous component Vn of the noise and the switching component Vns of the noise. The comb and rect functions apply because the system resets in a short time period, and as the circuit discharges, the sampled noise value changes for each sensing frame. Thus, the comb function samples the noise value Vns once within each sensing frame, and the convolution with the rectangular function extends this to the integration time period within the sensing frame. The integration time period can be called Tint. Tint is a small quantity that is less than the sampling time period Ts. The reset time period Treset is very short. Assuming that the noise when the circuit resets is actually zero because the gain G is 1 (the charge amplifier is a uniform gain buffer), however, it is a large value in the integration mode (e.g., determined by the ratio of the capacitance of the amphiphilic membrane to the integration capacitance C FB ). It is possible to evaluate the noise through Fourier transformation. If the amplifier characteristics are added, the continuous component Vn of the noise has a gain related to the integrator, while the switching component of the noise has a gain related to the uniform gain buffer, and then when the mode switches to the charge integration mode and the noise is sampled in the buffer mode, it gets the gain G. The following equations show these steps, where C PORE represents the capacitance of the amphiphilic membrane, and C FB represents the integration capacitance:

[0118]

[0119] G = 1 + C PORE / C FB

[0120]

[0121] T S = T INT + T RESET

[0122] The Fourier transform gives the following:

[0123]

[0124] Adding the amplifier characteristics gives the following:

[0125]

[0126] If we now consider the charge feedback mode, the system is always in the charge integration mode. Therefore, when the amplifier characteristics are added, a slight change in the equation is seen, but the impact is significant.

[0127]

[0128] G = 1 + C PORE / C FB

[0129]

[0130] T s = T NT + T RESET

[0131] The Fourier transform gives the following:

[0132]

[0133] Adding the amplifier characteristics gives the following:

[0134]

[0135] If we take the ratio of the second term representing the switching component of the noise, we get that for high frequencies, i.e., when A(f) is less than G, the ratio is much greater than 1. Therefore, the charge balance soft reset method is superior to the normal hard reset method by a large factor:

[0136]

[0137] Taking A(f) to have a monopole at frequency f0 and integrating over all frequencies, it is found that the ratio becomes

[0138]

[0139] Note that in the case of correlated double sampling, due to non-perfect correlated double sampling, the switching component of the noise obtained in the circuit is a residual effect. Therefore, correlated double sampling also greatly reduces the switching noise. The key is that the variable balance soft reset method can avoid correlated double sampling because this method alone greatly reduces the switching noise.

[0140] Therefore, in summary, a circuit that does not perform correlated double sampling is provided. The circuit generates low noise and does not require a hard reset. Thus, the problems of the previous circuits are eliminated, and a single-sampling circuit with extremely low power and good noise performance can be created.

[0141] In addition, as referred to above Figure 8 and 10Circuits of the described type of embodiment require relatively large passive components (such as capacitors). The charge-balanced soft reset method can be implemented using fewer components compared to either of the methods corresponding to Figure 8 and 10 and single sampling (per sensing frame) means less storage is required. Thus, a circuit based on the charge-balanced soft reset method can provide efficiency in terms of the silicon area required for implementation. These advantages are illustrated in the example embodiments shown below.

[0142] Any of the embodiments discussed above with reference to Figures 5 - 18 can be adapted to use the charge-balanced soft reset method instead of a hard reset, but specific benefits in terms of power savings and silicon area requirements are obtained by avoiding the use of associated double sampling.

[0143] Examples are depicted in Figures 27 - 30 In an embodiment implementing the charge-balanced soft reset method, the first charge amplifier 201 is configured such that integration of current is performed simultaneously across a first capacitive element 431 (which may correspond to, for example, the integration capacitor referred to above as C FB ) and a second capacitive element 432. Then, reset of the first charge amplifier 201 is performed by allowing the charge stored on the second capacitive element 432 to flow to the first capacitive element 431 and at least partially cancel the charge stored on the first capacitive element.

[0144] Figure 27 An embodiment configured as described above in Figure 5 is depicted, except that instead of driving a hard reset signal 211 at the switch (as in Figure 5 ), instead the charge-balanced soft reset method is implemented. The timing diagram is shown in Figure 28 and closely corresponds to the timing diagram of Figure 7 (where corresponding elements have corresponding reference numerals). The first charge amplifier 201 integrates the current measured simultaneously across a first capacitive element 431 (e.g., one or more capacitors) and a second capacitive element 432 (e.g., one of a plurality of capacitors). Reset is then performed by allowing the charge stored on the second capacitive element 432 to flow to the first capacitive element 431 and cancel the charge stored on the first capacitive element.

[0145] As referenced in Figure 5As described in detail, the first charge amplifier 201 is periodically reset by a reset signal 211 that defines a series of sensing frames 221 and 222. A sensing frame in which the toggle signal 212 is predominantly high can be referred to as the first sensing frame 221. A sensing frame in which the toggle signal 212 is predominantly low can be referred to as the second sensing frame 222. The first sensing frame 221 and the second sensing frame 222 thus alternate in time. Sampling alternates between sampling performed by the first low-pass filter module 206 and sampling performed by the second low-pass filter module 207 to avoid the need for an RC filter buffer. The first low-pass filter module 206 filters the output of the first charge amplifier 201 within each first sensing frame 221, and at the end of the first sensing frame 221, the capacitor component of the RC filter of the first low-pass filter module is isolated by the toggle signal 212 to store charge. Within each second sensing frame 222, the second low-pass filter module 207 filters the output of the first charge amplifier 201, and at the end of the second sensing frame 222, the charge is isolated and stored by the non-toggle signal 212. Also within each second sensing frame 222, the Srr signal activates (after an AND with the toggle signal 212) the output switch of the channel, thereby sending charge along the output lines 231 and 232 towards the second charge amplifier 202. The first plurality of capacitors 2061 and the second plurality of capacitors 2071 operate as described above with reference to Figure 5 to allow a selected attenuation to be applied to the charge representing information about the current to be sensed by reading out charge only from a selected subset of either the first plurality of capacitors 2061 or the second plurality of capacitors 2071 (depending on which is read).

[0146] When the reset signal 211 goes high, the charge in the second capacitive element 432 is forced into the input of the first charge amplifier 201. By sending opposite charge through the first capacitive element 431, the first charge amplifier 201 is forced to remove this charge. This returns the first charge amplifier 201 to its center point, which effectively resets the first charge amplifier 201. Once all the charge in the first capacitive element 431 has been removed, the reset signal 211 can go high again, allowing the output of the first charge amplifier 201 to recharge the first capacitive element 431. Thus, the reset period is effectively zero, and the entire integration period is free to integrate current, which is not the case when performing a hard reset using a switch directly across the integration capacitor (e.g., Figure 5 as shown). This method increases the amount of time available to achieve the maximum signal and thus achieves low input-referred current noise. This effect is in addition to the effect of promoting low noise discussed above with reference to Figure 26 for example.

[0147] Figure 29 is depicted Figure 27Variants of the arrangement, in which only a single pair of resistor elements instead of two pairs of resistor elements are used to implement the two low-pass filter modules 206 and 207. Using the same timing (as Figure 28 depicted), but the connection to the capacitor is now after the resistor (to the right of the resistor in the orientation of Figure 29 ) instead of only after the first charge amplifier 201 (to the left of the resistor in the orientation of Figure 29 ). Reducing the number of components required reduces the silicon area requirements.

[0148] Figure 30 Another variant is depicted, in which the bandwidth of the first charge amplifier 201 is arranged to be so low that a differential resistor component is no longer required, i.e., the output impedance of the first charge amplifier 201 provides filtering of the combination of the signal and the capacitor. This further reduces the silicon area requirements.

[0149] The above embodiments are essentially completely different. A single-ended version of the circuit can be implemented as a routine based on the above teachings and will provide similar advantages. The performance of the single-ended version in terms of signal dynamic range and noise may generally be lower, but it can benefit from lower power requirements as no common-mode feedback circuitry is required within the amplifier.

[0150] One or more of the above current measurement devices can be used in a molecular entity sensing device 1 as schematically depicted in Figure 31 . The sensing device 1 includes a sensor device 2 and a detection circuit 3. In one embodiment, the sensor device 2 includes an array of sensor elements 56 (see Figure 32 ). In one embodiment, the detection circuit 3 includes a plurality of current measurement devices according to any of the embodiments disclosed above. Each current measurement device measures the current output by one or more of the sensor elements 56 and provides an output (e.g., a digital output) depending on the current output by one or more of the sensor elements 56.

[0151] In one embodiment, each of the sensor elements 56 includes an ion channel. In one embodiment, the ion channel includes a nanopore. In one embodiment, the ion channel includes a membrane protein. In one embodiment, the sensor elements 56 are each arranged to support an amphiphilic membrane into which a membrane protein can be inserted. The interaction between the molecular entity and the sensor element 56 in this case is the interaction between the molecular entity and the membrane protein in the amphiphilic membrane.

[0152] In one embodiment, the sensor device 2 is a device as described in detail in US2011 / 0120871A1, which is incorporated herein by reference. Without limiting the generality of what is taught therein, this type of sensor device 2 has a configuration including a body 20 as shown in the cross-section of Figure 32 in which a plurality of wells 21 are formed in the body, each well being a recess in which a well electrode 22 is disposed. A large number of wells 21 are provided to optimize the data collection rate of the device 1. Generally, any number of wells 21 may be present, typically 256 or 1024, but Figure 32 only a few wells 21 are shown in

[0153] Each well 21 and the corresponding well electrode 22 are examples of sensor elements 56.

[0154] In this embodiment, the body 20 is covered by a cover 23 that extends over the body 20 and is hollow to define a chamber 24 into which each of the wells 21 opens. A common electrode 25 is disposed within the cover 23. Each sensor element 56 is arranged to output a current that depends on the interaction between a molecular entity and the sensor element 56, as described with reference to the following exemplary configurations.

[0155] Other sensor devices suitable for the present invention are disclosed in WO2014064449A1.

[0156] For any given well 21, when an amphiphilic membrane has been formed and membrane proteins have been inserted therein, the well 21 can be used as part of a sensor element 56 configured to sense the interaction between a molecular entity and a membrane protein. These interactions are random physical events. The output electrical signal across the amphiphilic membrane depends on the interaction, as the interaction causes a change in the characteristics of the output electrical signal. For example, in the case where the membrane protein is a protein pore, there is typically an interaction between the protein pore and a specific molecular entity (analyte) that regulates the flow of ions through the pore. The regulation of ion flow through the pore results in a change in the characteristics of the current flowing through the pore. The molecular entity can be a molecule or a part of a molecule, such as a DNA base. Such interactions are typically very brief, and high time resolution and continuous monitoring are required if each interaction is to be detected.

[0157] Any membrane can be used in accordance with the various aspects described herein. Suitable membranes are well known in the art. The membrane can be an amphiphilic layer or a solid state layer. An amphiphilic layer is a layer formed from amphiphilic molecules such as phospholipids, which have both hydrophilic and lipophilic properties. The amphiphilic molecules can be synthetic or naturally occurring. Non-naturally occurring amphiphiles and amphiphiles that form monolayers are known in the art and include, for example, block copolymers (Gonzalez-Perez et al., Langmuir, 2009, 25, 10447-10450). The copolymer can be a triblock, tetrablock, or pentablock copolymer. The membrane can be a triblock or diblock copolymer membrane.

[0158] Membranes formed from block copolymers retain several advantages over biological lipid membranes. Since triblock copolymers are synthetic, the exact construction can be carefully controlled to provide the correct chain lengths and properties required to form the membrane and interact with pores and other proteins.

[0159] Block copolymers can also be constructed from subunits that are not classified as lipid submaterials. For example, hydrophobic polymers can be prepared from siloxanes or other non-hydrocarbon monomers. The hydrophilic sub-segments of the block copolymer can also possess low protein-binding properties, which allows for the production of membranes that are highly resistant when exposed to raw biological samples. This head group unit can also be derived from non-classical lipid head groups.

[0160] Compared to biological lipid membranes, triblock copolymer membranes also have increased mechanical and environmental stability, such as a much higher operating temperature or pH range. The synthetic nature of the block copolymer provides a platform for customizing polymer-based membranes for a wide range of applications.

[0161] The membrane can be one of the membranes disclosed in US2015 / 0265994A1 or US2015 / 0285781A1, which are hereby incorporated by reference in their entirety. These documents also disclose suitable polymers.

[0162] The amphiphilic molecule can be chemically modified or functionalized to facilitate the coupling of polynucleotides.

[0163] The amphiphilic layer can be a monolayer or a bilayer. The amphiphilic layer is typically planar. The amphiphilic layer can be curved. The amphiphilic layer can be supported. The amphiphilic layer can be concave. The amphiphilic layer can be suspended from a raised post such that the peripheral region of the amphiphilic layer (where it is attached to the post) is higher than the amphiphilic layer region. This can allow particles to travel, move, slide or roll along the membrane as described above.

[0164] The membrane can be a lipid bilayer. Suitable lipid bilayers are disclosed in WO2008 / 102121, WO2009 / 077734 and WO2006 / 100484.

[0165] Methods for forming lipid bilayers are known in the art. Lipid bilayers are typically formed by the method of Montal and Mueller (Proc. Natl. Acad. Sci. USA., 1972; 69: 3561 - 3566), in which lipid monolayers are carried at the aqueous solution / air interface on either side of a pore that is perpendicular to the interface.

[0166] The solid state layer can be formed from both organic and inorganic materials, including but not limited to: microelectronic materials, insulating materials such as Si3N4, A12O3 and SiO, organic polymers and inorganic polymers such as plastics such as and elastomers such as two - component addition - cured silicone rubber and glass. The solid state layer can be formed from graphene. Suitable graphene layers are disclosed in WO 2009 / 035647. Yusko et al., Nature Nanotechnology, 2011; 6: 253 - 260 and U.S. Patent Application No. 2013 / 0048499 describe the delivery of proteins into transmembrane pores in a solid state layer without the use of particles.

[0167] Any transmembrane pore can be used. The pore can be biological or artificial. Suitable pores include but are not limited to protein pores, polynucleotide pores and solid state pores. The pore can be a DNA origami pore (Langecker et al., Science, 2012; 338: 932 - 936).

[0168] The transmembrane pore can be a transmembrane protein pore. The transmembrane protein pore is a polypeptide or a collection of polypeptides that allows hydrated ions, such as by-products obtained by treating polynucleotides with a polymerase, to flow from one side of the membrane to the other side of the membrane. In one aspect of the present invention, the transmembrane protein pore is capable of forming a pore that allows hydrated ions driven by an applied potential to flow from one side of the membrane to the other side. The transmembrane protein pore can allow polynucleotides to flow from one side of the membrane, such as a triblock copolymer membrane, to the other side. The transmembrane protein pore allows polynucleotides such as DNA or RNA to move through the pore.

[0169] The transmembrane protein pore can be a monomer or an oligomer. The pore can be composed of several repeating subunits, such as at least 6, at least 7, at least 8, at least 9, at least 10, at least 11, at least 12, at least 13, at least 14, at least 15, or at least 16 subunits. The pore can be a hexamer, heptamer, octamer, or nonamer pore. The pore can be a homooligomer or a heterooligomer.

[0170] The transmembrane protein pore typically includes a barrel or channel through which ions can flow. The subunits of the pore typically surround a central axis and contribute strands to the transmembrane β-barrel or channel or the transmembrane α-helical bundle or channel. The barrel or channel of the transmembrane protein pore typically includes amino acids that facilitate the interaction with nucleotides, polynucleotides, or nucleic acids. These amino acids can be located near the constriction of the barrel or channel. The transmembrane protein pore typically includes one or more positively charged amino acids, such as arginine, lysine, or histidine, or aromatic amino acids such as tyrosine or tryptophan. These amino acids typically facilitate the interaction between the pore and nucleotides, polynucleotides, or nucleic acids.

[0171] The transmembrane protein pore for use according to the present invention can be derived from a β-barrel pore or an α-helical bundle pore. The transmembrane pore can be derived from or based on Msp, α-hemolysin (α-HL), cytolysin, CsgG, ClyA, Sp1, and fragaceatoxin C (FraC). The transmembrane protein pore can be derived from CsgG. Suitable pores derived from CsgG are disclosed in WO 2016 / 034591. The transmembrane pore can be derived from cytolysin. Suitable pores derived from cytolysin are disclosed in WO 2013 / 153359.

[0172] An analyte (including, for example, proteins, peptides, small molecules, polypeptides, polynucleotides) can be present in the analyte. The analyte can be any suitable sample. The analyte can be a biological sample. Any embodiment of the methods described herein can be performed in vitro on an analyte obtained or extracted from any organism or microorganism. The organism or microorganism is generally an archaea, prokaryote, or eukaryote, and generally belongs to one of five kingdoms: Plantae, Animalia, Fungi, Prokaryota, and Protista. In some embodiments, the methods of the various aspects described herein can be performed in vitro on an analyte obtained or extracted from any virus.

[0173] The analyte can be a fluid sample. The analyte can include a body fluid. The body fluid can be obtained from a human or an animal. The human or animal may have, be suspected of having, or be at risk of having a disease. The analyte can be urine, lymph fluid, saliva, mucus, semen, or amniotic fluid, but can be whole blood, plasma, or serum. Generally, the analyte is of human origin, but alternatively, it can be from another mammal, such as from a commercially farmed animal, such as a horse, cow, sheep, or pig, or alternatively can be a pet, such as a cat or dog.

[0174] Alternatively, the analyte can be of plant origin.

[0175] The analyte can be a non-biological sample. The non-biological sample can be a fluid sample. An ionic salt such as potassium chloride can be added to the sample to affect the flow of ions through the nanopore.

[0176] The polynucleotide can be single-stranded or double-stranded. At least a portion of the polynucleotide can be double-stranded.

[0177] The polynucleotide can be a nucleic acid, such as deoxyribonucleic acid (DNA) or ribonucleic acid (RNA). The polynucleotide can include an RNA strand hybridized to a DNA strand. The polynucleotide can be any synthetic nucleic acid known in the art, such as peptide nucleic acid (PNA), glycerol nucleic acid (GNA), threose nucleic acid (TNA), locked nucleic acid (LNA), or other synthetic polymers with nucleotide side chains. The polynucleotide can be of any length.

[0178] Any number of polynucleotides can be studied. For example, the method can involve characterizing 2, 3, 4, 5, 6, 7, 8, 9, 10, 20, 30, 50, 100, or more polynucleotides. If two or more polynucleotides are characterized, they can be different polynucleotides or two instances of the same polynucleotide.

[0179] The polynucleotide can be naturally occurring or artificial.

[0180] The method can involve measuring two, three, four, five or more properties of a polynucleotide. One or more properties can be selected from: (i) the length of the polynucleotide, (ii) the identity of the polynucleotide, (iii) the sequence of the polynucleotide, (iv) the secondary structure of the polynucleotide, and (v) whether the polynucleotide is modified.

[0181] For (iii), the sequence of the polynucleotide can be determined as previously described. Suitable sequencing methods, specifically those using electrical measurements, are described below: Stoddart D et al., Proceedings of the National Academy of Sciences of the United States of America, 12; 106(19):7702 - 7; Lieberman KR et al., Journal of the American Chemical Society (J Am Chem Soc.) 2010; 132(50):17961 - 72; and International Application WO 2000 / 28312.

[0182] The secondary structure can be measured in a variety of ways. For example, if the method involves electrical measurements, changes in the dwell time or changes in the ionic current flowing through the pore can be used to measure the secondary structure. This allows the distinction between regions of single - stranded and double - stranded polynucleotides.

[0183] The presence or absence of any modification can be measured. The method can include determining whether the polynucleotide is modified by methylation, by oxidation, by damage or not, using one or more proteins or one or more labels, tags or spacers. A particular modification will cause a particular interaction with the pore, which can be measured using the methods described below.

[0184] In some embodiments of the various aspects described herein, the method can involve further characterizing a target polynucleotide. When the target polynucleotide contacts the pore, one or more measurements are made as the polynucleotide moves relative to the pore, and the one or more measurements indicate one or more properties of the target polynucleotide.

[0185] The method can involve determining whether the polynucleotide is modified or not. The presence or absence of any modification can be measured. The method can include determining whether the polynucleotide is modified by methylation, by oxidation, by damage or not, using one or more proteins or one or more labels, tags or spacers.

[0186] A kit for characterizing a target polynucleotide is also provided. The kit includes components of the pore and the membrane as disclosed herein. The membrane can be formed from the components. The pore can be present in the membrane. The kit can include any of the components of the membranes disclosed above, such as amphiphilic layer or triblock copolymer membranes.

[0187] Also provided is a device for characterizing a target analyte, such as a target polynucleotide. The device includes a plurality of wells and a plurality of membranes as disclosed herein. The plurality of wells may be present in the plurality of membranes. The number of wells and membranes may be equal. A single well may be present in each membrane.

[0188] The device for characterizing a target analyte may include an array of wells as disclosed herein in a plurality of membranes.

[0189] The device may further include instructions for performing the method. The device may be any conventional device for analyte analysis, such as an array or a chip. Any embodiment discussed above with reference to the method is equally applicable to the device of the present invention. The device may further include any feature present in a kit as disclosed herein.

[0190] The device may be arranged to perform the method as disclosed herein.

[0191] The device may include: a sensor device that is capable of supporting the plurality of wells and membranes and is operable to perform analyte characterization using the wells and membranes; and at least one port for delivering materials for performing the characterization.

[0192] Alternatively, the device may include: a sensor device that is capable of supporting the plurality of wells and membranes and is operable to perform analyte characterization using the wells and membranes; and at least one reservoir for holding materials for performing the characterization.

[0193] The device may include: a sensor device that is capable of supporting the membranes and the plurality of wells and membranes and is operable to perform analyte characterization using the wells and membranes; at least one reservoir for holding materials for performing the characterization; a fluid system configured to controllably supply the materials from the at least one reservoir to the sensor device; and one or more containers for receiving respective samples, the fluid system being configured to selectively supply the analyte from the one or more containers to the sensor device.

[0194] The device may be any of those described in WO 2009 / 077734, WO 2010 / 122293, WO 2011 / 067559 or WO 00 / 28312.

[0195] The control of the movement of an analyte relative to a nanopore, such as translocation speed, rejection of the analyte, etc., can be managed by the systems and methods disclosed in US2017 / 0233804A1, which is incorporated herein by reference in its entirety. Rejection of an analyte by a nanopore sensor can include ejection of the analyte from the nanopore.

[0196] In accordance with the teachings herein, the features described above and in the drawings of the present invention are interchangeable and compatible. The present invention has been described above by way of example only, and can be modified within the spirit and scope of the present invention, which extends to equivalent forms of the features described and combinations of one or more of the features described herein. The present invention also lies in any individual feature described or implied herein.

Claims

1. A current measurement device, comprising: A first charge amplifier configured to integrate a current to be measured; A processing circuit configured to filter an output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module; And A second charge amplifier configured to integrate a current derived from the filtered output from the first charge amplifier, wherein: The device is configured to reset the first charge amplifier at the start of each sensing frame among a plurality of sensing frames; The processing circuit is configured to obtain at least a first sample of the output from the first charge amplifier within each sensing frame; and Sampling of the first sample alternates between sampling by the first low-pass filter module and sampling by the second low-pass filter module from one sensing frame to the next.

2. The device according to claim 1, wherein the first low-pass filter module includes a first RC filter, and the second low-pass filter module includes a second RC filter.

3. The device according to claim 2, configured such that any one or both of the following conditions are satisfied: Within each sensing frame in which sampling of the first sample is not performed by the first low-pass filter module, the first sample from the previous sensing frame is stored in the capacitance component of the first RC filter in the form of charge; and Within each sensing frame in which sampling of the first sample is not performed by the second low-pass filter module, the first sample from the previous sensing frame is stored in the capacitance component of the second RC filter in the form of charge.

4. The device according to claim 3, configured such that any one or both of the following conditions are satisfied: The capacitance component of the first RC filter includes a first plurality of capacitors, and within each sensing frame in which sampling of the first sample is performed by the first low-pass filter module, a selected attenuation is applied to the charge representing information about the current to be measured by sampling charge only from a selected subset of the first plurality of capacitors; and The capacitance component of the second RC filter includes a second plurality of capacitors, and within each sensing frame in which sampling of the first sample is performed by the second low-pass filter module, a selected attenuation is applied to the charge representing information about the current to be measured by sampling charge only from a selected subset of the second plurality of capacitors.

5. The device according to any of the preceding claims, configured such that a first sample and a second sample of the output from the first charge amplifier are obtained within each sensing frame, and the processing circuit is configured to perform correlated double sampling using the first sample and the second sample.

6. The device according to claim 5, wherein: The processing circuit further includes at least one additional low-pass filter module; and The device is configured to sample the second sample through the at least one additional low-pass filter module.

7. The apparatus according to claim 6, wherein: the at least one additional low-pass filter module consists of one additional low-pass filter module; and the apparatus is configured such that for all sensing frames, the sampling of the second sample is performed only through the additional low-pass filter module.

8. The apparatus according to claim 7, configured such that each low-pass filter module in the first low-pass filter module, the second low-pass filter module, and the additional low-pass filter module is reset within each sensing frame in which the respective low-pass filter module obtains a sample.

9. The apparatus according to claim 8, configured such that the reset of each low-pass filter module is performed by bypassing the resistive component of the RC filter of each low-pass filter module.

10. The apparatus according to claim 8 or 9, configured such that the timing of the reset of each low-pass filter module is such that the sample is obtained at an equal time after the reset of each low-pass filter module that samples each of the first sample and the second sample.

11. The apparatus according to claim 6, wherein the at least one additional low-pass filter module includes a third low-pass filter module and a fourth low-pass filter module, and the apparatus is configured such that the sampling of the second sample alternates between sampling through the third low-pass filter module and sampling through the fourth low-pass filter module from one sensing frame to the next sensing frame.

12. The apparatus according to claim 5, configured such that the difference between the first sample and the second sample within each sensing frame is implemented by combining the outputs of the low-pass filter module storing the charge corresponding to the first sample and the low-pass filter module storing the charge corresponding to the second sample, which have opposite polarities.

13. The apparatus according to claim 5, wherein the first charge amplifier is configured such that the integration of the current is performed simultaneously across a first capacitive element and a second capacitive element, and the reset of the first charge amplifier is performed by allowing the charge stored on the second capacitive element to flow to the first capacitive element and at least partially cancel the charge stored on the first capacitive element.

14. A current measurement apparatus, comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter the output from the first charge amplifier; and a second charge amplifier configured to integrate a current derived from the filtered output from the first charge amplifier, wherein: The first charge amplifier is configured to perform the integration of the current across the first and second capacitive elements simultaneously and to perform a reset of the first charge amplifier by allowing the charge stored on the second capacitive element to flow onto the first capacitive element and at least partially cancel the charge stored on the first capacitive element.

15. The device according to claim 14, wherein: Sampling of the first sample alternates between sampling by the first low-pass filter module and sampling by the second low-pass filter module from one sensing frame to the next sensing frame.

16. The apparatus according to any one of the preceding claims, wherein the processing circuit is configured such that information regarding the current to be measured propagates through the processing circuit from the first charge amplifier to the second charge amplifier only in the form of the amount of charge representing the current to be measured.

17. The apparatus according to claim 16, wherein the processing circuit consists only of passive components and externally controllable switches.

18. A molecular entity sensing apparatus, comprising: Sensor means including an array of sensor elements, each sensor element being arranged to output a current depending on the interaction between a molecular entity and the sensor element; and A plurality of current measuring apparatuses according to any one of the preceding claims, wherein each current measuring apparatus is configured to measure the current output by one or more of the sensor elements and to provide an output depending on the current output by one or more of the sensor elements.

19. The device according to claim 18, wherein: Each of the sensor elements includes a nanopore.

20. The apparatus according to claim 18 or 19, wherein the nanopore includes a membrane protein or a solid-state nanopore.

21. The apparatus according to claim 18 or 19, wherein the sensor elements are each arranged to support an amphiphilic membrane into which a membrane protein can be inserted.

22. A method of measuring a current, the method comprising: Integrating a current to be measured using a first charge amplifier; Filtering the output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module; and Integrating a current derived from the filtered output from the first charge amplifier using a second charge amplifier, wherein: The first charge amplifier is reset at the start of each of a plurality of sensing frames; At least a first sample of the output from the first charge amplifier is obtained within each sensing frame; and Sampling of the first sample alternates between sampling by the first low-pass filter module and sampling by the second low-pass filter module from one sensing frame to the next sensing frame.

23. A method of measuring a current, the method comprising: Integrating a current to be measured using a first charge amplifier; Filtering the output from the first charge amplifier; and Integrating a current derived from the filtered output from the first charge amplifier using a second charge amplifier, wherein: The integration of the current by the first charge amplifier is performed simultaneously across the first and second capacitive elements, and the reset of the first charge amplifier is performed by allowing the charge stored on the second capacitive element to flow onto the first capacitive element and at least partially cancel the charge stored on the first capacitive element.

24. A method of sensing a molecular entity, the method comprising using the method according to any one of claims 22 to 23 to measure a current that depends on the interaction between the molecular entity and the sensor element.

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