Rf semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a radio frequency (RF) device including a molded device die and a multi-layer redistribution structure under the molded device die. The molded device die includes a device region having a back end of line (BEOL) portion and a front end of line (FEOL) portion over the BEOL portion. The FEOL portion includes an active layer, a contact layer, and an isolation section. Herein, the active layer and the isolation section are over the contact layer, and the active layer is surrounded by the isolation section. A first molding compound is over the active layer without a silicon crystal without germanium content between the first molding compound and the active layer. The multi-layer redistribution structure includes a redistribution interconnect and a plurality of bump structures at a bottom of the multi-layer redistribution structure and electrically coupled to the molded device die through the redistribution interconnect.

Description

[0001] Related applications

[0002] This application claims the benefit of provisional patent application serial number 62 / 795,804, filed on January 23, 2019, the disclosure of which is incorporated herein by reference in its entirety.

[0003] This application relates to U.S. Patent Application No. 1001, entitled “RFDEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME”, which was filed concurrently and whose disclosure is incorporated herein by reference in its entirety. Technical Field

[0004] This disclosure relates to a radio frequency (RF) device and its manufacturing process, and more particularly to an RF device having enhanced thermal and electrical properties, and a wafer-level packaging process for providing the RF device with enhanced properties. Background Technology

[0005] The widespread use of cellular and wireless devices has driven the rapid development of radio frequency (RF) technology. The substrate on which RF devices are fabricated plays a crucial role in achieving high levels of performance in RF technology. Fabricating RF devices on conventional silicon substrates benefits from low-cost silicon materials, large-scale wafer fabrication capabilities, sophisticated semiconductor design tools, and advanced semiconductor manufacturing technologies.

[0006] While there are advantages to using conventional silicon substrates in RF device fabrication, it is well known in the industry that conventional silicon substrates can have two undesirable properties for RF devices: harmonic distortion and low resistivity. Harmonic distortion is a key obstacle to achieving high levels of linearity in RF devices built on silicon substrates. Additionally, high-speed and high-performance transistors are more densely integrated into RF devices. Therefore, due to the large number of transistors integrated on the RF device, a significant amount of power passes through the transistors, and / or the high transistor operating speed, the heat generated by the RF device will increase significantly. Therefore, it is desirable to package the RF device in a configuration that allows for better heat dissipation.

[0007] Wafer-level fan-out (WLFO) packaging technology and embedded wafer-level ball grid array (EWLB) technology are currently attracting widespread attention in portable RF applications. WLFO and EWLB technologies are designed to provide high-density input / output ports (I / O) without increasing package size. This capability allows for the dense packaging of RF devices within a single wafer.

[0008] To accommodate the increasing heat generation of RF devices and reduce harmful harmonic distortion, and leveraging the advantages of WLFO / EWLB packaging technology, the object of this disclosure is to provide an improved packaging process for enhanced thermal and electrical performance. Furthermore, there is a need to enhance the performance of RF devices without increasing package size. Summary of the Invention

[0009] This disclosure relates to a radio frequency (RF) device with enhanced thermal and electrical performance and its manufacturing process. The disclosed RF device includes a molded device die and a multilayer redistribution structure. The molded device die includes a first molding compound and a device region having a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion. The FEOL portion has an active layer, a contact layer, and an isolation segment. Herein, the active layer and the isolation segment are located above the contact layer, the isolation segment surrounds the active layer, and the active layer does not extend vertically beyond the isolation segment. The BEOL is located below the FEOL portion and includes a bonding layer. The first molding compound is located above the active layer of the FEOL portion, and there is no silicon crystal without germanium content between the first molding compound and the active layer. The multilayer redistribution structure is formed below the BEOL portion of the molded device die. The multilayer redistribution structure includes a plurality of bump structures on the bottom surface of the multilayer redistribution structure and redistribution interconnects within the multilayer redistribution structure. The bump structures are electrically coupled to the FEOL portion of the molding die via the redistribution interconnects and the connection layer within the BEOL portion.

[0010] In one embodiment of the RF device, a portion of the first molding compound is located above the isolation section.

[0011] In one embodiment of the RF device, the isolation section extends vertically beyond the top surface of the active layer to define an opening within the isolation section and above the active layer. Hereinafter, the first molding compound fills the opening.

[0012] According to another embodiment, the RF device further includes a passivation layer located directly above the top surface of the active layer and within the opening. Hereinafter, the passivation layer is formed of silicon dioxide, silicon nitride, or a combination of both; and the first molding compound is in contact with the passivation layer.

[0013] According to another embodiment, the RF device further includes an interface layer located directly above the top surface of the active layer and within the opening. Herein, the interface layer is formed of silicon germanium (SiGe); and the first molding compound is in contact with the interface layer.

[0014] In one embodiment of the RF device, the first molding compound is in contact with the top surface of the active layer.

[0015] In one embodiment of the RF device, the top surface of each isolation segment is coplanar with the top surface of the active layer, and the first molding compound is located on both the active layer and the isolation segment.

[0016] In one embodiment of the RF device, the thermal conductivity of the first molding compound is greater than 1 W / m·K.

[0017] In one embodiment of the RF device, the dielectric constant of the first molding compound is less than 8.

[0018] In one embodiment of the RF device, the dielectric constant of the first molding compound is between 3 and 5.

[0019] In one embodiment of the RF device, the FEOL section is configured to provide at least one of a switching field-effect transistor (FET), a diode, a capacitor, a resistor, and an inductor.

[0020] According to another embodiment, an alternative RF device includes a molded device die and a multilayer redistribution structure. The molded device die includes a first molding compound and a device region having a FEOL portion and a BEOL portion. The FEOL portion has an active layer, a contact layer, and an isolation segment. Herein, the active layer and the isolation segment are located above the contact layer, the isolation segment surrounds the active layer, and the active layer does not extend vertically beyond the isolation segment. The BEOL portion is located below the FEOL portion and includes a connection layer. The first molding compound is located above the active layer of the FEOL portion, and there is no silicon crystal without germanium content between the first molding compound and the active layer. The multilayer redistribution is formed below the BEOL portion of the molded device die and includes a plurality of bump structures on the bottom surface of the multilayer redistribution structure and redistributed interconnects within the multilayer redistribution structure. The bump structures are electrically coupled to the FEOL portion of the molded device die through the redistributed interconnects and the connection layer within the BEOL portion. The alternative RF device further includes a second molding compound situated on the multilayer redistribution structure and encapsulating the molding device die.

[0021] In one embodiment of the alternative RF device, the first molding compound is formed from the same material as the second molding compound.

[0022] In one embodiment of the alternative RF device, the first molding compound and the second molding compound are formed from different materials.

[0023] According to an exemplary process, a precursor wafer having multiple device regions is first provided. Each device region includes a BEOL portion and a FEOL portion located above the BEOL portion. The FEOL portion has an active layer, a contact layer, and an isolation segment. Herein, the active layer and the isolation segment are located above the contact layer, the isolation segment surrounds the active layer, and the active layer does not extend vertically beyond the isolation segment. Additionally, an interface layer formed of silicon germanium (SiGe) is located directly above the active layer of each device region, and a silicon processing substrate is located directly above each interface layer. Next, the silicon processing substrate is completely removed. Then, a first molding compound is applied to provide a molded device wafer containing multiple molded device dies. Herein, the first molding compound is applied above the active layer of each device region from the location where the silicon processing substrate is removed. There is no silicon crystal without germanium content between the active layer of each device region and the first molding compound. Each molded device die includes a corresponding device region and a portion of the first molding compound located above the active layer of the corresponding device region.

[0024] According to another embodiment, the exemplary process further includes bonding the precursor wafer to a temporary carrier via a bonding layer before removing the silicon processing substrate; and debonding the temporary carrier from the precursor wafer and removing the bonding layer from the precursor wafer after applying the first molding compound.

[0025] According to another embodiment, the exemplary process further includes forming a multilayer redistributed structure beneath the molding apparatus wafer. Herein, the multilayer redistributed structure includes a plurality of bump structures on the bottom surface of the multilayer redistributed structure and redistributed interconnects within the multilayer redistributed structure. Each bump structure is electrically coupled to an active layer of the corresponding molding apparatus die via the redistributed interconnects and a connection layer within the BEOL portion of the corresponding molding apparatus die.

[0026] According to another embodiment, the exemplary process further includes dicing the molding device wafer into a plurality of individual molding device dies. A second molding compound is then applied around and over the individual molding device dies to provide a dual-molding device wafer. Herein, the second molding compound encapsulates the top and side surfaces of each individual molding device die, while the bottom surface of each individual molding device die is exposed. The bottom surface of the dual-molding device wafer is a combination of the bottom surface of each individual molding device die and the bottom surface of the second molding compound. Next, a multilayer redistribution structure is formed beneath the dual-molding device wafer. The multilayer redistribution structure includes a plurality of bump structures on the bottom surface of the multilayer redistribution structure and redistribution interconnects within the multilayer redistribution structure. Each bump structure is electrically coupled to an active layer of the corresponding individual molding device die via the redistribution interconnects and a connection layer within the BEOL portion of the corresponding individual molding device die.

[0027] According to another embodiment, the exemplary process further includes removing the interface layer before applying the first molding compound, such that after applying the first molding compound, the active layer of each device region is in contact with the first molding compound.

[0028] According to another embodiment, the exemplary process further includes removing the interface layer before applying the first molding compound, and applying a passivation layer directly over the active layer in each device region. The passivation layer is formed of silicon dioxide, silicon nitride, or a combination of both; and after applying the first molding compound, the passivation layer contacts the first molding compound.

[0029] In one embodiment of the exemplary process, providing the precursor wafer begins with providing a Si-SiGe-Si wafer comprising a common silicon epitaxial layer, a common interface layer over the common silicon epitaxial layer, and a silicon processing substrate over the common interface layer. The interface layer is formed of SiGe. A complementary metal-oxide-semiconductor (CMOS) process is then performed to provide the precursor wafer. Herein, the isolation segment extends through the common silicon epitaxial layer and the common interface layer, and extends into the silicon processing substrate, such that the common interface layer is separated into a plurality of individual interface layers, and the common silicon epitaxial layer is separated into a plurality of individual silicon epitaxial layers. Each active layer of the device region is formed by a corresponding individual silicon epitaxial layer, each individual interface layer is directly over the top surface of the corresponding active layer, and the silicon processing substrate is directly over the individual interface layer.

[0030] In one embodiment of the exemplary process, providing the precursor wafer begins with providing a Si-SiGe-Si wafer comprising a common silicon epitaxial layer, a common interface layer over the common silicon epitaxial layer, and a silicon processing substrate over the common interface layer. The common interface layer is formed of SiGe and comprises a plurality of interface layers connected together. A CMOS process is then performed to provide the precursor wafer. Herein, isolation segments extend through the common silicon epitaxial layer and into the common interface layer, such that the common silicon epitaxial layer is separated into a plurality of individual silicon epitaxial layers, while the interface layers remain connected. Each active layer of the device region is formed by a corresponding individual silicon epitaxial layer, each interface layer is directly over the top surface of the corresponding active layer, and the silicon processing substrate remains directly over the common interface layer.

[0031] Those skilled in the art will understand the scope of this disclosure and recognize other aspects of it after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0033] Figure 1 An exemplary radio frequency (RF) device with enhanced thermal and electrical performance is shown according to an embodiment of the present disclosure.

[0034] Figure 2 An alternative RF device with enhanced thermal and electrical performance according to one embodiment of the present disclosure is shown.

[0035] Figure 3-14 Provided demonstration of manufacturing Figure 1 An exemplary wafer-level packaging process for the steps of the exemplary RF device shown.

[0036] Figure 15-20 Provided demonstration of manufacturing Figure 2 The steps of the alternative RF device shown represent an alternative wafer-level packaging process.

[0037] It should be understood that, for the sake of clarity, Figure 1-20 It is not necessary to draw it to scale. Detailed Implementation

[0038] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best manner in which the embodiments are practiced. Those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts not specifically set forth herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0039] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerations.

[0040] It should be understood that when an element such as a layer, region, or substrate is referred to as "on another element" or extends "to another element," it may be directly on or directly extended onto the other element, or intermediate elements may also exist. In contrast, when an element is referred to as "directly on another element" or "directly extended onto another element," no intermediate elements exist. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "on top of another element" or "extends over another element," it may be directly on or directly extended over the other element, or intermediate elements may also exist. In contrast, when an element is referred to as "directly on top of another element" or "extends directly over another element," no intermediate elements exist. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may exist. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0041] In this document, relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” or “vertical” may be used to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, these terms and those discussed above are intended to cover different orientations of the device.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0044] With anticipated shortages of conventional radio frequency silicon-on-insulator (RFSOI) wafers in the coming years, alternative technologies are being designed to utilize silicon wafers, trap-rich layer formation, and smart dicing SOI wafer processes to meet high resistivity requirements. One alternative technology is based on using a silicon-germanium (SiGe) interface layer between the silicon substrate and the silicon epitaxial layer instead of a buried oxide layer (BOX); however, this technology also suffers from harmful distortion effects caused by the silicon substrate, similar to those observed in RFSOI technology. This disclosure relates to a radio frequency (RF) device with enhanced thermal and electrical properties, and a wafer-level packaging process for manufacturing said device, based on a Si-SiGe-Si structure free from harmful distortion effects from the silicon substrate.

[0045] Figure 1 An exemplary RF device 10 formed from a Si-SiGe-Si wafer according to an embodiment of the present disclosure is shown (processing details are described in the following paragraphs). For the purposes of this illustration, the exemplary RF device 10 includes a molded device die 12 having a device region 14 and a first molding compound 16, and a multilayer redistribution structure 18 formed beneath the molded device die 12.

[0046] Specifically, device region 14 includes a front-end process (FEOL) portion 20 and a back-end process (BEOL) portion 22, the BEOL portion being located below the FEOL portion 20. In one embodiment, the FEOL portion 20 is configured to provide a switching field-effect transistor (FET) and includes an active layer 24 and a contact layer 26. Herein, the active layer 24 has a source 28, a drain 30, and a channel 32 between the source 28 and the drain 30. The source 28, drain 30, and channel 32 are formed from the same silicon epitaxial layer. The contact layer 26 is formed below the active layer 24 and includes a gate structure 34, a source contact 36, a drain contact 38, and a gate contact 40. The gate structure 34 may be formed of silicon oxide and extends horizontally below the channel 32 (from below the source 28 to below the drain 30). Source contact 36 is connected to and located below source 28, drain contact 38 is connected to and located below drain 30, and gate contact 40 is connected to and located below gate structure 34. Insulating material 42 may be formed around source contact 36, drain contact 38, gate structure 34, and gate contact 40 to electrically isolate source 28, drain 30, and gate structure 34. In different applications, FEOL section 20 may have different FET configurations or provide different device components such as diodes, capacitors, resistors, and / or inductors.

[0047] Additionally, FEOL portion 20 also includes an isolation segment 44 located above the insulating material 42 of contact layer 26 and surrounding active layer 24. Isolation segment 44 is configured to electrically isolate RF device 10, particularly active layer 24, from other devices (not shown) formed in a common wafer. Herein, isolation segment 44 may extend from the top surface of contact layer 26 and vertically beyond the top surface of active layer 24 to define an opening 46 within isolation segment 44 and above active layer 24. A first molding compound 16 fills opening 46 and may extend above isolation segment 44. Isolation segment 44 may be formed of silicon dioxide resistant to etching chemicals such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH).

[0048] In some applications, the RF device 10 may further include a passivation layer 48, which may be formed of silicon dioxide, silicon nitride, or a combination of both, directly above the top surface of the active layer 24 and within the opening 46. Thus, the first molding compound 16 is directly above the passivation layer 48. The passivation layer 48 is configured to terminate surface bonding of the active layer 24, which can be a cause of unwanted leakage. The passivation layer may also act as a barrier and is configured to protect the active layer 24 from moisture or ion contamination. If the passivation layer 48 is omitted, the first molding compound 16 may contact the top surface of the active layer 24. In some applications, the RF device 10 may further include an interface layer (described in the following paragraphs and not shown herein), formed of SiGe, directly above the top surface of the active layer 24 and within the opening 46. Thus, the first molding compound 16 may be directly above the interface layer. The interface layer is derived from a Si-SiGe-Si wafer used to fabricate the RF device 10 (processing details are described in the following paragraphs). If the interface layer is omitted, the first molding compound 18 can contact the top surface of the active layer 24. It should be noted that regardless of the passivation layer 48 or the interface layer, there is no silicon crystal without germanium content between the first molding compound 16 and the top surface of the active layer 24. Both the passivation layer 48 and the interface layer are silicon alloys.

[0049] Furthermore, in some applications, the top surface of each isolation segment 44 and the top surface of the active layer 24 are coplanar (not shown), and the opening 46 is omitted. The first molding compound 16 is located above both the active layer 24 and the isolation segment 44 of the FEOL portion 20. It should be noted that the active layer 24 never extends vertically beyond the isolation segment 44, otherwise the isolation segment 44 might not completely isolate the active layer 24 from other devices formed on the same wafer.

[0050] The BEOL portion 22 is located below the FEOL portion 20 and includes a plurality of interconnect layers 50 formed within a dielectric layer 52. Some of the interconnect layers 50 are encapsulated by the dielectric layer 52 (not shown), while some of the interconnect layers 50 have bottom portions not covered by the dielectric layer 52. Some of the interconnect layers 50 are electrically connected to the FEOL portion 20. For the purposes of this illustration, one of the interconnect layers 50 is connected to the source contact 36, and another interconnect layer 50 is connected to the drain contact 38.

[0051] The multilayer redistribution structure 18 formed beneath the BEOL portion 22 of the molding die 12 includes a plurality of redistribution interconnects 54, dielectric patterns 56, and a plurality of bump structures 58. Herein, each redistribution interconnect 54 is connected to a corresponding connection layer 50 within the BEOL portion 22 and extends above the bottom surface of the BEOL portion 22. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. The dielectric pattern 56 is formed around and beneath each redistribution interconnect 54. The bottom portion of each redistribution interconnect 54 is exposed through the dielectric pattern 56. Each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18 and is electrically coupled to the corresponding redistribution interconnect 54 via the dielectric pattern 56. Thus, the redistribution interconnects 54 are configured to electrically connect the bump structures 58 to certain connection layers of the FEOL portion 20 within the connection layer 50 of the BEOL portion 22. In this way, the bump structures 58 are electrically connected to the FEOL portion 20 via the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In addition, the bump structures 58 are separated from each other and extend under the dielectric pattern 56.

[0052] In some applications, some of the redistributed interconnects in redistributed interconnect 54 may be configured to connect the molded device die 12 to other device components (not shown) formed from the same wafer. In some applications, there may be additional redistributed interconnects (not shown) electrically coupled to the redistributed interconnect 54 via dielectric pattern 56, as well as additional dielectric patterns (not shown) formed beneath dielectric pattern 56, such that the bottom portion of each additional redistributed interconnect is exposed. Thus, each bump structure 58 is coupled to the corresponding additional redistributed interconnect via an additional dielectric pattern (not shown). Regardless of the number of layers of redistributed interconnects and / or dielectric patterns, the multilayer redistributed structure 18 may be glass fiber-free or glass-free. Herein, glass fiber refers to individual glass filaments twisted into larger groups. These glass filaments may then be woven into a fabric. The redistributed interconnect 54 may be formed of copper or other suitable metals. The dielectric pattern 56 may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structure 58 may be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm.

[0053] Heat generated in device region 14 can travel upwards to the bottom portion of the first molding compound 16 located above the active layer 24, and then downwards through device region 14 toward the multilayer redistribution structure 18, which dissipates the heat. Therefore, it is highly desirable for the first molding compound 16 to have a high thermal conductivity. The thermal conductivity of the first molding compound 16 can be greater than 1 W / m·K or greater than 10 W / m·K. Additionally, the low dielectric constant of the first molding compound 16 can be less than 8 or between 3 and 5 to produce low RF coupling. In one embodiment, the first molding compound 16 can be formed from a thermoplastic or thermosetting polymer material such as PPS (polyphenylene sulfide), or an epoxy resin doped with boron nitride, alumina, carbon nanotubes, or diamond-like carbon thermal additives. The thickness of the first molding compound 16 is based on the required thermal performance of the RF device 10, the device layout, the distance from the multilayer redistribution structure 18, and the details of the package and assembly. The thickness of the first molding compound 16 can be between 200 μm and 500 μm.

[0054] Figure 2 An alternative RF device 10A is shown, which further includes a second molding compound 60 compared to the RF device 10. Herein, the multilayer redistribution structure 18 extends horizontally beyond the molding device die 12, and the second molding compound 60 is situated above the multilayer redistribution structure 18 to encapsulate the molding device die 12. In this embodiment, the redistribution interconnects 54 of the multilayer redistribution structure 18 may extend horizontally beyond the molding device die 12, and the bump structures 58 of the multilayer redistribution structure 18 may not be confined within the periphery of the molding device die 12. The second molding compound 60 may be formed of the same or different material as the first molding compound 16. Unlike the first molding compound 16, the second molding compound 60 may not have thermal conductivity or dielectric constant requirements.

[0055] Figure 3-14 Provided demonstration of manufacturing Figure 1 The exemplary wafer-level packaging process of the exemplary RF device 10 shown is illustrated. Although the exemplary steps are shown in series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, the process within the scope of this disclosure may include more than […]. Figure 3-14 The steps shown are fewer or more.

[0056] First, such as Figure 3The illustration provides a Si-SiGe-Si wafer 62. The Si-SiGe-Si wafer 62 includes a common silicon epitaxial layer 64, a common interface layer 66 above the common silicon epitaxial layer 64, and a silicon processing substrate 68 above the common interface layer 66. Herein, the common interface layer 66, formed of SiGe, separates the common silicon epitaxial layer 64 from the silicon processing substrate 68.

[0057] In this document, the common silicon epitaxial layer 64 is formed of device-grade silicon material having the desired silicon epitaxial properties for forming electronic devices. The common interface layer 66 is formed of an alloy having any Si to Ge molar ratio. Higher Ge concentrations result in better etch selectivity between the silicon processing substrate 68 and the common interface layer 66, but also make epitaxial growth of the common silicon epitaxial layer 64 more difficult. In one embodiment, the Ge concentration of the common interface layer 66 can be greater than 15% or greater than 25%. The Ge concentration can be uniform throughout the common interface layer 66. In some applications, the Ge concentration can be vertically graded (between 1% and 50%) to provide the necessary strain relief for the growth of the common silicon epitaxial layer 64. The silicon processing substrate 68 can be composed of conventional, low-cost, low-resistivity, and high-dielectric-constant silicon. The common silicon epitaxial layer 64 has higher resistivity, lower harmonic generation, and lower dielectric constant than the silicon processing substrate 68. The thickness of the common silicon epitaxial layer 64 can be between 700 nm and 2000 nm, the thickness of the common interface layer 66 can be between 100 nm and 1000 nm, and the thickness of the silicon processing substrate 68 can be between 200 μm and 500 μm.

[0058] Next, a complementary metal-oxide-semiconductor (CMOS) process is performed on the Si-SiGe-Si wafer 62 to provide a precursor wafer 70 having multiple device regions 14, such as Figure 4A As shown. For illustrative purposes, the FEOL section 20 of each device region 14 is configured to provide a switching FET. In different applications, the FEOL section 20 may have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0059] In this embodiment, the isolation segment 44 of each device region 14 extends through the common silicon epitaxial layer 64 and the common interface layer 66, and extends into the silicon processing substrate 68. Thus, the common interface layer 66 is separated into multiple individual interface layers 66I, and the common silicon epitaxial layer 64 is separated into multiple individual silicon epitaxial layers 64I, each silicon epitaxial layer serving to form a corresponding active layer 24 in a device region 14. The isolation segment 44 can be formed by shallow trench isolation (STI).

[0060] The top surface of the active layer 24 contacts the corresponding interface layer 66I. A silicon processing substrate 68 lies on each individual interface layer 66I, and a portion of the silicon processing substrate 68 may lie on the isolation section 44. A BEOL portion 22 of the device region 14, comprising at least the plurality of interconnect layers 50 and dielectric layer 52, is formed beneath the contact layer 26 of the FEOL portion 20. Bottom portions of some interconnect layers 50 are exposed through the dielectric layer 52 located at the bottom surface of the BEOL portion 22.

[0061] In another embodiment, the isolation segment 44 does not extend into the silicon processing substrate 68. Instead, the isolation segment 44 extends only through the common silicon epitaxial layer 64 and into the common interface layer 66, as shown below. Figure 4B As shown herein, the common interface layer 66 remains continuous, and the individual interface layers 66I are interconnected. The common interface layer 66 lies directly over the top surface of each active layer 24 and directly over the top surface of each isolation segment 44. The silicon processing substrate 68 remains over the common interface layer 66. Further, the isolation segments 44 may extend through the common silicon epitaxial layer 64 but not into the common interface layer 66 (not shown). The top surface of each isolation segment 44 and the top surface of each active layer 24 may be coplanar (not shown). The common interface layer 66 and the silicon processing substrate 68 remain intact. The common interface layer 66 lies over each isolation segment 44 and each active layer 24, and the silicon processing substrate 68 lies over the common interface layer 66.

[0062] After the precursor wafer 70 is completed, the precursor wafer 70 is then bonded to the temporary carrier 72, as follows: Figure 5 As shown, the precursor wafer 70 can be bonded to the temporary carrier 72 via a bonding layer 74 that provides a planarized surface for the temporary carrier 72. From a cost and thermal expansion perspective, the temporary carrier 72 can be a thick silicon wafer, but it can also be understood as glass, sapphire, or other suitable carrier materials. The bonding layer 74 can be a span-on polymeric adhesive film, such as Brewer Science's WaferBOND temporary adhesive series.

[0063] The silicon processing substrate 68 is then selectively removed to provide an etched wafer 76, wherein selective removal stops at each interface layer 66I, as... Figure 6As shown. If the isolation segment 44 extends vertically beyond the interface layer 66I, the removal of the silicon processed substrate 68 will provide an opening 46 above each active layer 24 and within the isolation segment 44. Removal of the silicon processed substrate 68 can be provided by a chemical mechanical polishing and an etching process using a wet / dry etchant chemical, which can be TMAH, KOH, NaOH, ACH, or XeF2, or by the etching process itself. As an example, the silicon processed substrate 68 can be polished to a thinner thickness to reduce subsequent etching time. The etching process is then performed to completely remove the remaining silicon processed substrate 68. Because the silicon processed substrate 68 and the interface layer 66I have different properties, they may react differently to the same etching technique (e.g., different etching rates with the same etchant). Therefore, the etching system can identify the presence of the interface layer 66I and can indicate when to stop the etching process.

[0064] During the removal process, the isolation section 44 is not removed and the sides of each FEOL portion 20 are protected. The bonding layer 74 and the temporary carrier 72 protect the bottom surface of each BEOL portion 22. In this document, the top surface of each isolation section 44 and the top surface of each interface layer 66I are exposed after the removal process. If the isolation section 44 only extends into the common interface layer 66 without penetrating it (e.g....), Figure 4B If the top surface of each isolation segment 44 and the top surface of each active layer 24 are coplanar (not shown), then only the top surface of the common interface layer 66 is exposed (not shown).

[0065] Due to the narrow gap nature of SiGe material, interface layer 66I (or common interface layer 66) may be conductive. Interface layer 66I may cause significant leakage between the source 28 and drain 30 of active layer 24. Therefore, in some applications such as FET applications, it is desirable to remove interface layer 66I (or common interface layer 66), such as... Figure 7 As shown, the interface layer 66I can be removed using the same etching process used to remove the silicon processing substrate 68, or it can be removed using an alternative etching process such as an HCI dry etching system. If the interface layer 66I is thin enough, it may be completely depleted and may not cause any noticeable leakage between the source 28 and drain 30 of the FEOL portion 20. In this case, the interface layer 66I can remain intact.

[0066] In some applications, a passivation layer 48, which may be formed of silicon dioxide, silicon nitride, or a combination of both, may be formed directly on the active layer 24 of each FEOL portion 20, such as... Figure 8As shown. If an opening 46 exists above each active layer 24 and within the isolation section 44, a passivation layer 48 is formed within the opening 46. The passivation layer 48 is configured to terminate surface bonding at the top surface of the active layer 24, which could be a cause of unwanted leakage. The passivation layer 48 can be formed by CVD dielectric film or passivation plasma.

[0067] Next, a first molding compound 16 is applied onto the etched wafer 76 to provide a molding device wafer 78, as shown. Figure 9 As shown, the molding device wafer 78 includes a plurality of molding device dies 12, each of which includes a device region 14 and a portion of a first molding compound 16. Herein, the first molding compound 16 fills each opening 46 and contacts a passivation layer 48 within the opening 46. Additionally, a portion of the first molding compound 16 may extend over an isolation segment 44. If no passivation layer 48 is formed in each opening 46, the first molding compound 16 contacts the top surface (not shown) of each active layer 24. If an interface layer 66I remains above the top surface of each active layer 24, the first molding compound 16 contacts the interface layer 66I (not shown). The first molding compound 16 is always located above each active layer 24.

[0068] The first molding compound 16 can be applied through various processes, such as compression molding, sheet molding, overmolding, transfer molding, dike filling encapsulation, and screen printing encapsulation. The first molding compound 16 can have excellent thermal conductivity greater than 1 W / m·K or greater than 10 W / m·K, and can have a dielectric constant less than 8 or between 3 and 5. During the molding process of the first molding compound 16, a temporary carrier 72 provides mechanical strength and rigidity to the etched wafer 76. A curing process (not shown) is then performed to harden the first molding compound 16. The curing temperature is between 100°C and 320°C, depending on the material used as the first molding compound 16. After the curing process, the first molding compound 16 can be thinned and / or planarized (not shown).

[0069] Then, the temporary carrier 72 is decoupled from the molding device wafer 78, and the bonding layer 74 is removed from the molding device wafer 78, as follows: Figure 10As shown. Depending on the properties of the temporary carrier 72 and bonding layer 74 selected in the previous steps, various debonding and removal processes can be applied. For example, the temporary carrier 72 can be mechanically debonded using a lateralblade process after the stack has been heated to a suitable temperature. If the temporary carrier 72 is formed of a transparent material, other suitable processes involve UV light irradiation through the temporary carrier or chemical debonding using a suitable solvent. The bonding layer 74 can be removed by wet etching processes such as proprietary solvents and plasma cleaning, or dry etching processes. After the debonding and removal processes, the bottom portions of certain bonding layers in the bonding layers 50 that can be used as input / output (I / O) ports of the molding device die 12 are exposed through the dielectric layer 52 at the bottom surface of each BEOL portion 22. Thus, each molding device die 12 in the molding device wafer 78 can then be electrically verified to determine that the molding device die is functioning correctly.

[0070] refer to Figures 11 to 13 According to one embodiment of this disclosure, a multilayer redistribution structure 18 is formed under a molding apparatus wafer 78. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, the redistribution steps within the scope of this disclosure may include more than Figure 11-13 The steps shown are fewer or more.

[0071] First, multiple redistributed interconnects 54 are formed under each BEOL portion 22, such as Figure 11 As shown, each redistributed interconnect 54 is electrically coupled to the exposed bottom portion of the corresponding interconnect layer 50 within the BEOL portion 22 and can extend above the bottom surface of the BEOL portion 22. The connection between the redistributed interconnect 54 and the interconnect layer 50 is solderless. A dielectric pattern 56 is then formed under each BEOL portion 22 to partially encapsulate each redistributed interconnect 54, as shown. Figure 12 As shown. Thus, the bottom portion of each redistributed interconnect 54 is exposed through dielectric pattern 56. In different applications, there may be additional redistributed interconnects (not shown) electrically coupled to the redistributed interconnects 54 through dielectric pattern 56, as well as additional dielectric patterns (not shown) formed under dielectric pattern 56, such that the bottom portion of each additional redistributed interconnect is exposed.

[0072] Next, multiple bump structures 58 are formed to complete the multilayer redistribution structure 18, and a wafer-level fan-out (WLFO) package 80 is provided, such as Figure 13As shown, each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 via the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to electrically connect the bump structures 58 to certain connection layers in the connection layer 50 of the BEOL portion 22 and to the FEOL portion 20. Thus, the bump structures 58 are electrically connected to the FEOL portion 20 via the corresponding redistribution interconnect 54 and the corresponding connection layer 50. Furthermore, the bump structures 58 are separated from each other and extend beneath the dielectric pattern 56.

[0073] The multilayer redistribution structure 18 may be glass fiber-free or glass-free. Herein, glass fiber refers to individual glass filaments twisted into larger groups. These glass filaments can then be woven into a fabric. The redistribution interconnects 54 may be formed of copper or other suitable metals, the dielectric pattern 56 may be formed of BCB, polyimide, or other dielectric materials, and the bump structure 58 may be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm. Figure 14 The final step of dicing the WLFO package 80 into individual RF devices 10 is shown. The dicing step can be provided by probing and splitting processes at certain isolation sections 44.

[0074] In another embodiment, Figure 15-20 Provided demonstration of manufacturing Figure 2 Alternative wafer-level packaging processes for the steps of the alternative RF device 10A shown. Although exemplary steps are shown in series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, processes within the scope of this disclosure may include more than Figure 15-20 The steps shown are fewer or more.

[0075] like Figure 10 As shown, after the debonding and cleaning processes to provide a clean molded device wafer 78, a dicing step is then performed to dice the molded device wafer 78 into individual device dies 12, as... Figure 15 As shown. Each molded device die 12 may have the same height and includes a device region 14 with a FEOL portion 20 and a BEOL portion 22, as well as a first molding compound 16.

[0076] Next, a second molding compound 60 is applied around and over the molding device die 12 to provide a dual-molding device wafer 82, such as Figure 16As shown, the second molding compound 60 encapsulates the top and side surfaces of each molding die 12, while the bottom surface of each molding die 12, i.e., the bottom surface of the BEOL portion 22, is exposed. The bottom surface of the dual molding die wafer 82 is a combination of the bottom surface of each molding die 12 and the bottom surface of the second molding compound 60. Herein, the bottom portions of certain interconnect layers in the interconnect layer 50 remain exposed at the bottom surface of each molding die 12. The second molding compound 60 can be applied through various processes, such as sheet molding, overmolding, compression molding, transfer molding, dike filling encapsulation, or screen printing encapsulation. The second molding compound 60 can be formed from the same or different materials as the first molding compound 16. However, unlike the first molding compound 16, the second molding compound 60 has no thermal conductivity or resistivity requirements. The second molding compound 60 can be an organic epoxy resin system, etc. A curing process (not shown) is then used to harden the second molding compound 60. The curing temperature is between 100°C and 320°C, depending on which material is used as the second molding compound 60. A grinding process (not shown) can then be performed to provide a planarized top surface of the second molding compound 60.

[0077] refer to Figures 17 to 19 A multi-layer redistribution structure 18 is formed according to one embodiment of this disclosure. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, the redistribution steps within the scope of this disclosure may include more than Figure 17-19 The steps shown are fewer or more.

[0078] First, multiple redistributed interconnects 54 are formed under the dual-mold device wafer 82, such as Figure 17 As shown. Each redistributed interconnect 54 is electrically coupled to a corresponding interconnect layer 50 within the BEOL portion 22 and can extend horizontally beyond the corresponding molding die 12 and horizontally beneath the second molding compound 60. The connection between the redistributed interconnect 54 and the interconnect layer 50 is solderless. A dielectric pattern 56 is then formed under the dual molding die 82 to partially encapsulate each redistributed interconnect 54, as shown. Figure 18 As shown. Thus, the bottom portion of each redistributed interconnect 54 is exposed through dielectric pattern 56. In different applications, there may be additional redistributed interconnects (not shown) electrically coupled to the redistributed interconnects 54 through dielectric pattern 56, as well as additional dielectric patterns (not shown) formed under dielectric pattern 56, such that the bottom portion of each additional redistributed interconnect is exposed.

[0079] Next, multiple bump structures 58 are formed to complete the multilayer redistribution structure 18, and an alternative WLFO package 80A is provided, such as Figure 19 As shown, each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 via the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to connect the bump structure 58 to certain connection layers in the connection layer 50 of the BEOL portion 22, which are electrically connected to the FEOL portion 20. Thus, the bump structure 58 is electrically connected to the FEOL portion 20 via the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In this document, the bump structure 58 may not be limited to the periphery of the corresponding molding die 12. Furthermore, the bump structures 58 are separated from each other and extend beneath the dielectric pattern 56.

[0080] Figure 20 The final step of slicing the alternative WLFO package 80A into individual alternative RF devices 10A is shown. The slicing step can be provided by probing and splitting a portion of the second molding compound 60, which is horizontally located between adjacent molded device dies 12.

[0081] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A radio frequency device comprising: A molding device die, the molding device die including a device region, an additional layer, and a first molding compound, wherein: The device region includes a front-end process section and a back-end process section, the back-end process section being located below the front-end process section and including a connection layer; The front-end process includes an active layer, a contact layer, and an isolation section formed of silicon dioxide, wherein the active layer and the isolation section are located above the contact layer, the isolation section surrounds the active layer, the isolation section is not located above the active layer, and the isolation section extends vertically beyond the top surface of the active layer to define an opening within the isolation section and above the active layer. The additional layer contacts the top surface of the active layer of the front-end process portion and is located within the opening, wherein the additional layer is formed of silicon germanium or silicon nitride; and The first molding compound is located directly above the additional layer to fill the opening, wherein there is no silicon crystal without germanium content between the first molding compound and the active layer; and A multi-layer redistribution structure is formed beneath the back-end process portion of the molding apparatus die, wherein the multi-layer redistribution structure includes a plurality of bump structures on the bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure, wherein the plurality of bump structures are electrically coupled to the front-end process portion of the molding apparatus die via the redistribution interconnects and the connection layer within the back-end process portion.

2. The radio frequency device of claim 1, wherein a portion of the first molding compound is located above the isolation segment, wherein the first molding compound is formed of a thermoplastic or thermosetting polymer material.

3. The radio frequency device of claim 1, wherein the additional layer is formed of silicon nitride and completely covers the active layer of the front-end process.

4. The radio frequency device of claim 1, wherein the additional layer is formed of silicon germanium.

5. The radio frequency device according to claim 1, wherein the thermal conductivity of the first molding compound is greater than 1 W / m·K.

6. The radio frequency device of claim 1, wherein the dielectric constant of the first molding compound is less than 8.

7. The radio frequency device of claim 1, wherein the dielectric constant of the first molding compound is between 3 and 5.

8. The radio frequency device of claim 1, wherein the front-end process portion is configured to provide at least one of a switching field-effect transistor, a diode, a capacitor, a resistor, and an inductor.

9. A radio frequency device comprising: A molding device die, the molding device die including a device region, an additional layer, and a first molding compound, wherein: The device region includes a front-end process section and a back-end process section, the back-end process section being located below the front-end process section and including a connection layer; The front-end process includes an active layer, a contact layer, and an isolation section formed of silicon dioxide, wherein the active layer and the isolation section are located above the contact layer, the isolation section surrounds the active layer, the isolation section is not located above the active layer, and the isolation section extends vertically beyond the top surface of the active layer to define an opening within the isolation section and above the active layer. The additional layer contacts the top surface of the active layer of the front-end process portion and is located within the opening, wherein the additional layer is formed of silicon germanium or silicon nitride; and The first molding compound is located directly on the additional layer to fill the opening, wherein there is no silicon crystal without germanium content between the first molding compound and the active layer; A multi-layer redistribution structure is formed beneath the back-end process portion of the molding apparatus die. The multi-layer redistribution structure includes a plurality of bump structures on the bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure. The plurality of bump structures are electrically coupled to the front-end process portion of the molding apparatus die via the redistribution interconnects and a connecting layer within the back-end process portion. A second molding compound is located on top of the multilayer redistribution structure and encapsulates the molding device die.

10. The radio frequency device of claim 9, wherein the first molding compound is formed of the same material as the second molding compound.

11. The radio frequency device of claim 9, wherein the first molding compound and the second molding compound are formed of different materials.

12. A method for forming a radio frequency device, comprising: Provide a precursor wafer having multiple device regions, wherein: Each of the plurality of device regions includes a back-end process portion and a front-end process portion located above the back-end process portion; The front-end process includes an active layer, a contact layer, and an isolation section, wherein the active layer and the isolation section are located above the contact layer, the isolation section surrounds the active layer, and the active layer does not extend vertically beyond the isolation section; An interface layer formed of silicon-germanium is directly located above the active layer of each of the plurality of device regions; and The silicon-processed substrate is located directly on each interface layer; Completely remove the silicon-treated substrate; Remove the interface layer to expose the active layer of each of the plurality of device regions; and A first molding compound is applied to provide a molding device wafer comprising multiple molding device dies; wherein: The first molding compound is applied over the active layer of each of the plurality of device regions after the interface layer is removed; In each of the plurality of device regions, there is no silicon crystal without germanium content between the active layer and the first molding compound; and Each of the plurality of molding device dies includes a corresponding device region and a portion of the first molding compound located above the active layer of the corresponding device region.

13. The method of claim 12, further comprising: Before removing the silicon processing substrate, the precursor wafer is bonded to the temporary carrier via a bonding layer; as well as After applying the first molding compound, the temporary carrier is debonded from the precursor wafer and the bonding layer is removed from the precursor wafer.

14. The method of claim 12, further comprising forming a multilayer redistribution structure beneath the molding apparatus wafer, wherein the multilayer redistribution structure includes a plurality of bump structures on the bottom surface of the multilayer redistribution structure and redistribution interconnects within the multilayer redistribution structure, wherein each of the plurality of bump structures is electrically coupled to an active layer of the corresponding molding apparatus die via the redistribution interconnects and a connection layer within the back-end process portion of the corresponding molding apparatus die.

15. The method of claim 12, further comprising: The molding device wafer is diced into multiple individual molding device dies; A second molding compound is applied around and over the plurality of individual molding device dies to provide a dual-molding device wafer, wherein: The second molding compound encapsulates the top and side surfaces of each of the plurality of individual molding die tubes, while the bottom surface of each of the plurality of individual molding die tubes is exposed; and The bottom surface of the dual-molding device wafer is a combination of the bottom surface of each of the plurality of individual molding device dies and the bottom surface of the second molding compound; and A multilayer redistribution structure is formed beneath the dual-mold device wafer, wherein the multilayer redistribution structure includes a plurality of bump structures on the bottom surface of the multilayer redistribution structure and redistribution interconnects within the multilayer redistribution structure, wherein each of the plurality of bump structures is electrically coupled to an active layer of the corresponding individual mold device die through the redistribution interconnects and a connection layer within the back-end process portion of the corresponding individual mold device die.

16. The method of claim 12, wherein after the first molding compound is applied, the active layer of each of the plurality of device regions is in contact with the first molding compound.

17. The method of claim 12, further comprising applying a passivation layer directly over the active layer in each of the plurality of device regions before applying the first molding compound, wherein: The passivation layer is formed of silicon dioxide, silicon nitride, or a combination of both. and After the first molding compound is applied, the passivation layer comes into contact with the first molding compound.

18. The method of claim 12, wherein providing the precursor wafer comprises: A Si-SiGe-Si wafer is provided, the Si-SiGe-Si wafer comprising a common silicon epitaxial layer, a common interface layer above the common silicon epitaxial layer, and a silicon processing substrate above the common interface layer, wherein the interface layer comprises silicon germanium; and A complementary metal-oxide-semiconductor (CMOS) process is performed to provide the precursor wafer, wherein: The isolation section extends through the common silicon epitaxial layer and the common interface layer and into the silicon processing substrate, such that the common interface layer is separated into multiple individual interface layers, and the common silicon epitaxial layer is separated into multiple individual silicon epitaxial layers. Each active layer of the plurality of device regions is formed by a corresponding individual silicon epitaxial layer; and Each of the plurality of individual interface layers is located directly on the top surface of the corresponding active layer, and the silicon processing substrate is located directly on the plurality of individual interface layers.

19. The method of claim 12, wherein providing the precursor wafer comprises: A Si-SiGe-Si wafer is provided, the Si-SiGe-Si wafer comprising a common silicon epitaxial layer, a common interface layer located above the common silicon epitaxial layer, and a silicon processing substrate located above the common interface layer, wherein: The common interface layer is formed of silicon-germanium; and The common interface layer includes multiple interconnected interface layers; and A complementary metal-oxide-semiconductor (CMOS) process is performed to provide the precursor wafer, wherein: The isolation section extends through the common silicon epitaxial layer and into the common interface layer, such that the common silicon epitaxial layer is separated into multiple individual silicon epitaxial layers, while the multiple interface layers remain connected. Each active layer of the plurality of device regions is formed by a corresponding individual silicon epitaxial layer; and Each of the plurality of interface layers is located directly on the top surface of the corresponding active layer, and the silicon processing substrate is still located directly on the common interface layer.

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