LLC chip and cache system

Abstract

The present application discloses an LLC chip and a cache system, the LLC chip includes a storage wafer, an interface logic unit and a packaging substrate, the interface logic unit and the storage wafer are sequentially arranged on the packaging substrate, the storage wafer and the interface logic unit are three-dimensionally integrated to form an LLC chip, a plurality of processing components are connected to the interface logic unit, so as to perform read and write operations on the storage wafer through the interface logic unit; the storage wafer includes at least one storage space, and a plurality of processing components perform read and write operations on any storage space to achieve non-shared independent storage access or shared storage access; wherein the storage space of the storage wafer is divided according to the access amount or access speed of the plurality of processing components. The present application integrates the storage wafer and the interface logic unit in three dimensions, and then improves the signal transmission bandwidth through a plurality of distributed interfaces, and performs data caching through a non-shared mode or a shared mode, so as to improve the efficiency of the processing components in accessing data.

Description

Technical Field

[0001] This application relates to the field of data caching, and in particular to an LLC chip and caching system. Background Technology

[0002] In the prior art, in order to implement LLC (last-level cache), the CPU (Central Processing Unit) adds a NoC (network-on-chip) between the CPU's MLC (mid-level cache) and LLC to increase the bandwidth for CPU access to LLC. LLC caches data by using MRAM memory modules, where MRAM memory is a medium memory with a small capacity. Summary of the Invention

[0003] This application provides at least one LLC chip and cache system for implementing large-capacity, high-bandwidth LLC.

[0004] The first aspect of this application provides an LLC chip, which includes a memory wafer, an interface logic unit, and a packaging substrate. The interface logic unit and the memory wafer are sequentially disposed on the packaging substrate. The memory wafer and the interface logic unit are three-dimensionally integrated to form the LLC chip. Multiple processing components are connected to the interface logic unit to perform read and write operations on the memory wafer through the interface logic unit.

[0005] A storage wafer includes at least one storage space, and multiple processing components perform read and write operations on a specific storage space or any storage space to achieve non-shared independent storage access or shared storage access; wherein, the storage space of the storage wafer is divided according to the access volume or access speed of the multiple processing components.

[0006] Optionally, the interface logic unit includes multiple independent interfaces, controllers, and registers, and the storage wafer includes multiple independent DRAM arrays. The multiple independent interfaces, controllers, and registers form independent access paths to the multiple DRAM arrays. Multiple processing components are connected to the paths through their respective interfaces to perform non-shared independent storage access to their respective DRAM arrays.

[0007] Optionally, at least one of the multiple processing components performs read and write operations on the DRAM array corresponding to it through the interface logic unit.

[0008] Optionally, the memory wafer includes at least one DRAM wafer, and multiple DRAM arrays are distributed in different regions of the same DRAM wafer; or, multiple DRAM arrays are distributed across multiple memory wafers, corresponding to multiple memory wafer layers or the projected overlapping regions of multiple memory wafers.

[0009] Optionally, the storage space of the storage wafer is the capacity of a DRAM array, which is allocated according to the access volume or access speed of multiple processing components.

[0010] Optionally, the memory wafer further includes multiple first bonding pillars, the interface logic unit further includes multiple second bonding pillars and multiple bumps, and the packaging substrate includes multiple lead ports.

[0011] Each first bonding post is connected to a corresponding second bonding post to enable the memory wafer to connect to the interface logic unit. The interface logic unit is connected to the packaging substrate through multiple bumps, and the packaging substrate is connected to multiple processing components through multiple lead ports.

[0012] Optionally, the interface logic unit also includes an on-chip network, each node of which is connected to a single controller. The controller is used to access the storage wafer. One end of the register is connected to the controller, and the other end of the register is connected to the storage wafer. The register is used for data buffering.

[0013] The processing component inputs an address through the interface logic unit. Based on the address, the interface logic unit drives the controller connected to the node corresponding to the address, so that the processing component can perform read and write operations on the storage wafer.

[0014] Optionally, the controller includes a cache coherence protocol controller, and the LLC chip also includes a DDR controller and DDR memory. The cache coherence protocol controller accesses the DDR controller through an on-chip network to perform read and write operations on the DDR memory.

[0015] Among them, the cache coherency protocol controllers of multiple controllers communicate with each other through an on-chip network.

[0016] Optionally, the LLC chip includes multiple memory wafers, which are stacked sequentially on the interface logic unit, and adjacent memory wafers are connected by bonding.

[0017] The second aspect of this application provides a caching system, which includes an LLC chip as described above and multiple processing components. Each processing component includes at least two central processing units, at least two L1 caches and one L2 cache. The multiple processing components are connected to the LLC chip to perform read and write operations.

[0018] The caching system divides the storage space of the storage wafer according to the access volume or access speed of multiple processing components, so that each central processing unit can perform read and write operations on the corresponding storage space.

[0019] Alternatively, any central processing unit among multiple processing components may perform read and write operations on any storage space of the storage wafer.

[0020] The beneficial effects of this application are as follows: Unlike the prior art, this application integrates the storage wafer and the interface logic unit in three dimensions, thereby improving the signal transmission bandwidth of the LLC chip through multiple distributed interfaces; at the same time, this application performs data caching in non-shared mode or shared mode, so that the processing component can perform read and write operations on the storage wafer, thereby improving the efficiency of the processing component in accessing data.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a first structural schematic diagram of an embodiment of the LLC chip of this application;

[0024] Figure 2 This is a second structural schematic diagram of an embodiment of the LLC chip of this application;

[0025] Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment of the interface logic unit;

[0026] Figure 4 yes Figure 1 A schematic diagram of another embodiment of the interface logic unit;

[0027] Figure 5 This is a schematic diagram of another embodiment of the LLC chip in this application;

[0028] Figure 6 This is a schematic diagram of another embodiment of the LLC chip in this application;

[0029] Figure 7 This is a schematic diagram of the DRAM array arrangement in this application;

[0030] Figure 8 This is a schematic diagram of another embodiment of the LLC chip in this application;

[0031] Figure 9 This is a flowchart illustrating the read / write operations of the LLC chip in this application.

[0032] Figure 10 This is a schematic diagram of the caching system in this application. Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions of this application, the LLC chip and cache system provided in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It is understood that the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0035] In existing technologies, CPUs cache data using methods including FLC (first-level cache), MLC (mid-level cache), and LLC (last-level cache), corresponding to L1, L2, and L3 caches, respectively. Compared to L1 and L2 caches, L3 cache offers the advantages of higher frequency and lower latency data access.

[0036] To implement LLC, existing technologies increase the bandwidth for CPU access to LLC by adding a NoC between the CPU's MLC and LLC. Meanwhile, LLC uses an MRAM memory module for data caching, but MRAM is a medium-sized memory with limited capacity.

[0037] Therefore, this application provides an LLC chip for implementing a high-capacity, high-bandwidth LLC.

[0038] Please see Figure 1 and Figure 2 , Figure 1 This is a first structural schematic diagram of an embodiment of the LLC chip of this application. Figure 2 This is a second structural schematic diagram of an embodiment of the LLC chip in this application. Figure 1As shown, the LLC chip 1 includes a packaging substrate 10, an interface logic unit 20, and a memory wafer 30. The interface logic unit 20 and the memory wafer 30 are sequentially disposed on the packaging substrate 10, and the memory wafer 30 and the interface logic unit 20 are three-dimensionally integrated on the packaging substrate 10 to form the LLC chip 1.

[0039] The packaging substrate 10 is connected to the interface logic unit 20, and the interface logic unit 20 is further connected to the storage wafer 30.

[0040] The CPU is interconnected with the LLC chip via the LLC chip's packaging substrate 10. Specifically, the CPU and LLC chip are interconnected via an additional packaging substrate and / or a circuit board; or the CPU is mounted on the LLC chip's packaging substrate and interconnected with the LLC chip. The following example illustrates the interconnection of the CPU and LLC chip via an additional packaging substrate and / or a circuit board.

[0041] like Figure 2 As shown, the storage wafer 30 includes a plurality of first bonding pillars 31, the interface logic unit 20 includes a plurality of second bonding pillars 22 and a plurality of bumps 21, and the packaging substrate 10 includes a plurality of lead ports 11.

[0042] In this configuration, multiple first bonding posts 31 are correspondingly arranged with multiple second bonding posts 22, and each first bonding post 31 is connected to a corresponding second bonding post 22, so that the memory wafer 30 is connected to the interface logic unit 20. The interface logic unit 20 is connected to the packaging substrate 10 through multiple bumps 21, and the packaging substrate 10 is connected to the central processing unit through multiple lead ports 11.

[0043] When the central processing unit outputs read / write instructions to LLC chip 1, the storage wafer 30 is connected to the central processing unit in sequence through interface logic unit 20 and packaging substrate 10, so that the central processing unit can perform read / write operations on the storage wafer 30.

[0044] In this embodiment, the LLC chip 1 integrates the storage wafer 30 and the interface logic unit 20 in three dimensions. The storage wafer 30 and the interface logic unit 20 are connected by a plurality of first bonding posts 31 and a plurality of second bonding posts 22, thereby improving the signal transmission bandwidth through multiple distributed interfaces.

[0045] Optionally, in this embodiment, the bonding between the first bonding post 31 and the second bonding post 22 is one of the ways to connect the storage wafer 30 and the interface logic unit 20. In other embodiments, the storage wafer 30 and the interface logic unit 20 can also be connected via TSV (Through Silicon Via), RDL (ReDistribution Layer), or Bump.

[0046] Combination Figure 1-2 For further information Figure 3 , Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment of the interface logic unit. (See diagram below.) Figure 3 As shown, the interface logic unit 20 includes an on-chip network 23, a controller 24, and a register 25.

[0047] The central processing unit (CPU) 2 is connected to the interface logic unit 20 via interface 40. The CPU 2 integrates an L1 cache 201 and an L2 cache 202 to form a processing component 200. The processing component 200 is further connected to the LLC chip 1 via interface 40, i.e., connected to the L3 cache. In another embodiment, the L2 cache 202 integrated in the CPU 2 can be omitted.

[0048] Optionally, interface 40 can be an existing LLC logic interface. Specifically, in this embodiment, interface 40 can be composed of multiple bumps 21 of interface logic unit 20, package substrate 10, and multiple lead ports 11 of package substrate 10.

[0049] One end of the on-chip network 23 is connected to interface 40, and the other end of the on-chip network 23 is connected to one end of controller 24. The other end of controller 24 is connected to one end of register 25, and the other end of register 25 is connected to storage wafer 30.

[0050] Interface 40 is used to connect the central processing unit 2 and the on-chip network 23, so that the interface logic unit 20 can find the node corresponding to the on-chip network 23 according to the input information of the central processing unit 2, and then drive the controller 24 corresponding to the node; the controller 24 is used to access the storage wafer 30; and the register 25 is used for data buffering.

[0051] Specifically, register 25 is connected to storage wafer 30 via multiple ports for data buffering.

[0052] When the central processing unit 2 of the processing component 200 outputs read / write instructions to the LLC chip 1, the central processing unit 2 sequentially performs read / write operations on the storage wafer 30 through the L1 cache 201, L2 cache 202, interface 40, on-chip network 23, controller 24, and register 25. In one embodiment, the read / write operation behavior conforms to a cache coherence protocol, such as the MESI protocol.

[0053] In this embodiment, the storage wafer 30 is a DRAM (Dynamic Random Access Memory) wafer, which includes at least one DRAM array 32. The interface logic unit 20 is connected to at least one DRAM array 32 to enable the central processing unit 2 to perform read and write operations.

[0054] DRAM is a volatile memory. Unlike non-volatile memory, DRAM can access data faster and has lower data access latency.

[0055] In this embodiment, LLC chip 1 uses a DRAM wafer of volatile memory as storage wafer 30 to improve data access speed and further improve the speed of read and write operations performed by the central processing unit 2 on LLC chip 1. At the same time, in this embodiment, LLC chip 1 is equipped with register 25 connected to storage wafer 30 and controller 24 to reduce the performance loss caused by frequent data switching.

[0056] Combination Figure 1-3 For further information Figure 4 , Figure 4 yes Figure 1 A schematic diagram of another embodiment of the interface logic unit. (See diagram below.) Figure 4 As shown, unlike the above embodiments, the interface logic unit 20 in this embodiment includes multiple controllers 24 and multiple registers 25.

[0057] The on-chip network 23 connects to multiple controllers 24, and each controller 24 is connected to the storage wafer 30 through a register 25.

[0058] Optionally, the on-chip network 23 includes multiple interconnected routers to form multiple nodes, each node being connected to a single controller 24. The central processing unit 2 can access the controller 24 corresponding to the router by accessing the router's address to perform data read and write operations.

[0059] That is, the central processing unit 2 inputs an address through the interface logic unit 20, and the interface logic unit 20 drives the controller 24 connected to the node corresponding to the address according to the address, so that the central processing unit 2 can perform read and write operations on the storage wafer 30.

[0060] In this embodiment, there may be two central processing units (CPUs) 2. Each CPU 2 integrates an L1 cache 201, and the two CPUs 2 share an L2 cache 202. The two CPUs 2, the two L1 caches 201, and the shared L2 cache 202 constitute a processing component 200, which is connected to the LLC chip 1 via an interface 40.

[0061] The processing component 200 can perform read and write operations on the LLC chip 1 through non-shared independent memory access or shared memory access.

[0062] Specifically, the storage wafer 30 includes at least one storage space, and the two central processing units 2 in the processing component 200 correspond to different storage spaces. The processing component 200 enables a specific central processing unit 2 to access the storage by performing read and write operations on a specific storage space.

[0063] When LLC chip 1 receives read / write instructions from at least one of the two central processing units 2, at least one of the central processing units 2 performs read / write operations on the DRAM array 32 corresponding to it through the interface logic unit 20, that is, performs read / write operations on a specific storage space.

[0064] Optionally, the two central processing units 2 can simultaneously or individually perform read and write operations on the storage wafer 30, thereby realizing the non-shared mode cache data of the LLC chip 1.

[0065] Optionally, in other embodiments, LLC chip 1 can also perform data caching in a shared mode. Specifically, any central processing unit 2 in processing component 200 can perform read and write operations on any DRAM array 32 in storage wafer 30 through on-chip network 23, that is, perform read and write operations on any storage space of storage wafer 30. When central processing unit 2 performs read and write operations on DRAM array 32, the next central processing unit 2 to be run, whether it wants to further perform read and write operations on the DRAM array 32 on which the current central processing unit 2 is performing read and write operations, or to perform read and write operations on another DRAM array 32, must wait for the current central processing unit 2 to complete the corresponding read and write operation before it can access the target DRAM array 32 to be executed in order to perform the read and write operation.

[0066] In this embodiment, LLC chip 1 connects to multiple controllers 24 via on-chip network 23. By mapping addresses to controllers 24, it enables rapid location of the target controller 24, thereby achieving large-scale high-speed computing. Simultaneously, LLC chip 1 in this embodiment performs data caching in either non-shared or shared mode, allowing the central processing unit 2 to perform read and write operations on the target DRAM array 32, thus improving the efficiency of data access by the central processing unit 2.

[0067] Combination Figure 1-4 For further information Figure 5 , Figure 5 This is a schematic diagram of another embodiment of the LLC chip in this application. Figure 5 As shown, unlike the above embodiments, this embodiment may include multiple central processing units 2, wherein at least two central processing units 2 share an L2 cache 202 to form a processing component 200, and the multiple processing components 200 are connected to LLC chip 1 through interface 40.

[0068] Specifically, each processing component 200 has a different access volume or access speed, and therefore requires different storage space, i.e., a different number of DRAM arrays 32. Thus, multiple processing components 200 can connect to different numbers of DRAM arrays 32 as needed, serving as their respective storage spaces.

[0069] Optionally, the DRAM array 32 has a certain number of rows and columns. The DRAM array 32 can be divided into individual DRAM arrays 32 with a preset number of rows and columns, and different processing components 200 correspond to different numbers of individual DRAM arrays 32.

[0070] Alternatively, the number of rows of the DRAM array 32 can be divided according to the proportion of storage space requirements of different processing components 200, with each processing component 200 containing a corresponding number of rows of the DRAM array 32.

[0071] Alternatively, the number of columns of the DRAM array 32 can be divided according to the proportion of storage space requirements of different processing components 200, with each processing component 200 containing a DRAM array 32 with a corresponding number of columns.

[0072] Alternatively, in another embodiment, the processing component 200 includes only a central processing unit 2, an L1 cache 201, and an L2 cache 202.

[0073] Combination Figure 1-5 For further information Figure 6 , Figure 6 This is a schematic diagram of another embodiment of the LLC chip in this application. Figure 6 As shown, unlike the above embodiments, at least one central processing unit 2 shares the L2 cache 202 to form a processing component 200. At least one processing component 200 is connected to the controller 24 and register 25 in LLC chip 1 through independent corresponding interfaces 40 to perform non-shared independent memory access to the independent corresponding DRAM array 32.

[0074] Specifically, LLC chip 1 includes multiple interfaces 40, each interface 40 corresponding to a DDR memory array access channel, which is accessed independently and via an independent controller 24 and an independent register 25, respectively. It is a non-shared DRAM array 32.

[0075] The controller 24 includes a memory access controller (not shown) for the DRAM array 32, used to establish memory access to the corresponding DRAM array 32; and a cache coherence protocol controller (not shown), used to access the DDR controller 26 through the on-chip network 23, thereby enabling read and write operations on the DDR memory 50 (main memory).

[0076] The cache coherence protocol controllers in the multiple controllers 24 also communicate with each other via the on-chip network 23 to realize data exchange between at least part of the processing components 200, so as to overcome the data synchronization between multiple central processing units 2 in the non-shared memory structure and improve the function of the cache coherence protocol.

[0077] In a non-shared storage architecture, each processing component 200 can independently read and write to the large-capacity, high-bandwidth LLC storage space. Independent cache lines can be designed for each processing component 200 to increase cache swapping efficiency. The cache line bit width of some or all processing components 200 can also be increased to fully utilize the ultra-high bandwidth advantage of the three-dimensional integrated memory-bonded storage wafer 30.

[0078] Optionally, multiple sets of DDR controllers 26 can be designed to interconnect with the on-chip network 23 to form multiple DDR channels, which control multiple sets of DDR memory 50 respectively.

[0079] Optionally, multiple DRAM arrays can be arranged in a 32-array configuration as follows: Figure 7 As shown, Figure 7 This is a schematic diagram of the DRAM array arrangement in this application.

[0080] Specifically, such as Figure 7 As shown in (a), multiple DRAM arrays 32 can be distributed in different regions of the same memory wafer 30.

[0081] like Figure 7 As shown in (b), multiple DRAM arrays 32 can also be distributed on multiple memory wafers 30, each memory wafer 30 being a memory wafer layer, and the multiple DRAM arrays 32 being distributed on multiple memory wafer layers respectively.

[0082] like Figure 7 As shown in (c), multiple DRAM arrays 32 can also be distributed across multiple memory wafers 30. This schematic diagram uses two memory wafers 30 as an example. The projections of the two memory wafers 30 onto a plane parallel to the memory wafers 30 have a partial overlap area, and the DRAM arrays 32 are distributed in this partial overlap area. When there are multiple memory wafers 30, the projections of different memory wafers 30 onto a plane parallel to the memory wafers 30 have different partial overlap areas, and the multiple DRAM arrays 32 correspond to different partial overlap areas of the projections of the memory wafers 30.

[0083] The storage wafer 30 contains a DRAM array 32, and the resulting storage capacity (hundreds of megabytes to tens of gigabytes) is 2 to 4 orders of magnitude higher than that of the prior art (tens of megabytes). This is sufficient to provide each group of processing components 200 with an independent non-shared LLC storage space. The storage capacity is still much greater than that of the prior art, which greatly increases the LLC hit rate and reduces the frequency of storage access to the main memory.

[0084] The storage wafer 30 contains a DRAM array 32, which is connected to the LLC chip 1 through three-dimensional integrated bonding. The interconnect density is extremely high (1-micron pitch, millions of connection points per square millimeter). This allows for the establishment of a very large bus width (thousands to hundreds of thousands) between the storage wafer 30 and the LLC chip 1, which is 2 to 4 orders of magnitude higher than the existing technology (64-bit). By splitting the extremely large bus width between the storage wafer 30 and the LLC chip 1, an independent non-shared LLC memory access channel is provided for at least some or all of the processing components 200, and the memory access bandwidth is still much greater than that of the existing technology.

[0085] In the non-shared memory structure, each processing component 200 can independently read and write to the large-capacity, high-bandwidth LLC memory space, freeing it from the constraints of the bus of the controller 24 in the shared memory LLC structure. It does not require the establishment of a mutual waiting time-sharing access mechanism, which not only simplifies the design difficulty of the controller 24, but also enables the processing component 200 to concurrently read and write to the large-capacity, high-bandwidth LLC memory space, fully releasing the ultra-high bandwidth advantage of the three-dimensional integrated bonded memory wafer 30.

[0086] Combination Figure 1-7 For further information Figure 8 , Figure 8 This is a schematic diagram of another embodiment of the LLC chip in this application. Figure 8 As shown, unlike the above embodiments, the LLC chip 1 includes a plurality of storage wafers 30. Optionally, the number of storage wafers 30 can be 2, 3, 4, etc.

[0087] Multiple memory wafers 30 are stacked sequentially on the interface logic unit 20, and two adjacent memory wafers 30 are connected by bonding.

[0088] Optionally, in this embodiment, each of the multiple storage wafers 30 of the LLC chip 1 includes a DRAM array 32. In this embodiment, when the central processing unit 2 uses a non-shared mode to cache data, the multiple central processing units 2 can divide the storage space according to their needs. This can be done by treating the DRAM array 32 of a single storage wafer 30 as an individual DRAM array 32, with different central processing units 2 corresponding to different numbers of individual DRAM arrays 32, that is, different central processing units 2 corresponding to different numbers of storage wafers 30.

[0089] Optionally, in other embodiments, when the central processing unit 2 caches data in a non-shared mode, the multiple central processing units 2 can divide the storage space according to their needs. This can be done by taking the overlapping regions of the projected portions of different storage wafers 30 in the storage wafer array composed of multiple stacked storage wafers 30 as individual DRAM arrays 32. Different central processing units 2 correspond to individual DRAM arrays 32 with different capacities, that is, different central processing units 2 correspond to the overlapping regions of the projected portions of different areas in the storage wafer array.

[0090] Alternatively, in other embodiments, when the central processing unit 2 uses a shared mode to cache data, multiple central processing units 2 do not need to divide the storage space and can directly access the corresponding DRAM array 32 according to the address.

[0091] In this embodiment, the LLC chip 1 is increased by stacking multiple storage wafers 30 in sequence, thereby increasing the data capacity of the LLC chip 1. The data access rate is increased by bonding the multiple storage wafers 30 together, thereby achieving a large-capacity, high-bandwidth data cache.

[0092] This application integrates a three-dimensional storage wafer 30 and an interface logic unit 20, and connects the storage wafer 30 and the interface logic unit 20 by a plurality of first bonding posts 31 and a plurality of second bonding posts 22, thereby improving the signal transmission bandwidth through multiple distributed interfaces.

[0093] Secondly, this application uses a volatile DRAM wafer as the storage wafer 30 to improve the bandwidth and speed of data access, further increasing the speed at which the central processing unit 2 performs read and write operations on the LLC chip 1. Simultaneously, this application uses a non-shared mode for data caching, enabling the central processing unit 2 to perform read and write operations on the target DRAM array 32, thereby improving the efficiency of data access by the central processing unit 2.

[0094] Furthermore, this application increases the data capacity of LLC chip 1 by stacking multiple storage wafers 30 sequentially, and improves the data access rate by bonding the multiple storage wafers 30 together, thereby achieving a large-capacity, high-bandwidth data cache.

[0095] This application also provides a method for performing read and write operations on an LLC chip, the flowchart of which is shown below. Figure 9 As shown. Please refer to... Figure 1-8 See Figure 9 , Figure 9 This is a flowchart illustrating the read / write operation of the LLC chip in this application. Specifically, the method for performing read / write operations on the LLC chip in this embodiment may include the following steps:

[0096] Step S11: Receive input information from the central processing unit.

[0097] LLC chip 1 receives information from central processing unit 2 through multiple pin ports 11. Specifically, the input information includes read / write instructions and address information. When the read / write instruction is a write instruction, the input signal also includes the data to be stored.

[0098] Step S12: Drive the corresponding controller according to the input information.

[0099] The input information is transmitted sequentially to the interface logic unit 20 through multiple lead ports 11 of the packaging substrate 10, the packaging substrate 10, and multiple bumps 21. The interface logic unit 20 finds the node corresponding to the address information in the on-chip network 23 according to the address information contained in the input information, and then drives the controller 24 connected to the node. In addition, the data information in the input information is temporarily stored in the register 25 by the controller 24.

[0100] Step S13: Access the DRAM array to perform read and write operations.

[0101] When the storage space of register 25 is full, the central processing unit 2 further accesses the storage wafer 30 and transmits the temporarily stored data through register 25 to the DRAM array 32 contained in the storage wafer 30 through the port for read and write operations.

[0102] When the input information contains a read instruction, the CPU 2 reads the data information stored in the DRAM array 32 corresponding to the CPU 2 through the controller 24 and register 25. This data information is pre-stored in register 25. When the storage space of register 25 is full, register 25 further transmits the data information to the CPU 2 through the controller 24 and the on-chip network 23.

[0103] This application also provides a caching system; please refer to [link / reference]. Figure 10 , Figure 10 This is a schematic diagram of the caching system in this application. (See diagram for example.) Figure 10 As shown, the cache system may specifically be the DDR memory 50 described in the previous embodiments. The cache system may include an LLC chip 51 and multiple processing components 52. The LLC chip 51 is the LLC chip 1 disclosed in the above embodiments, and the processing components 52 are the processing components 200 disclosed in the above embodiments, which will not be described again here.

[0104] Multiple processing components 52 are respectively connected to LLC chip 51 to perform read and write operations on LLC chip 51. Specifically, the multiple processing components 52 can perform read and write operations on LLC chip 51 individually, or multiple processing components 52 can perform read and write operations on LLC chip 51 simultaneously, or at least two of the multiple processing components 52 can perform read and write operations on LLC chip 51 simultaneously.

[0105] Optionally, the caching system divides the storage space of the storage wafer 30 according to the access volume or access speed of the multiple processing components 52, so that each processing component 52 can perform read and write operations on the corresponding storage space. The specific division method is as described above and will not be repeated here.

[0106] Alternatively, in another embodiment, multiple processing components 52 are packaged within the same device.

[0107] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An LLC chip, characterized in that: The LLC chip includes a storage wafer, an interface logic unit and a packaging substrate, wherein the interface logic unit and the storage wafer are sequentially arranged on the packaging substrate, the storage wafer and the interface logic unit are three-dimensionally integrated to form the LLC chip, and a plurality of processing components are connected to the interface logic unit to perform read and write operations on the storage wafer through the interface logic unit; The storage wafer includes at least one storage space, and multiple processing components perform read and write operations on any of the storage spaces to achieve non-shared independent storage access or shared storage access; wherein the storage space of the storage wafer is divided according to the access volume or access speed of the multiple processing components, and the two central processing units in the processing components respectively correspond to different storage spaces for storage access.

2. The LLC chip according to claim 1, characterized in that: The interface logic unit includes multiple independent interfaces, controllers and registers, the storage wafer includes multiple independent DRAM arrays, the multiple independent interfaces, controllers and registers form a path for independently accessing the multiple DRAM arrays, and the multiple processing components are connected to the path through the corresponding interfaces respectively to perform non-shared independent storage access to the independently corresponding DRAM arrays.

3. The LLC chip according to claim 2, characterized in that: At least one of the plurality of processing components performs read and write operations on the DRAM array corresponding thereto through the interface logic unit.

4. The LLC chip according to claim 2, characterized in that: The storage wafer includes at least one DRAM wafer, and the multiple DRAM arrays are distributed in different areas of the same DRAM wafer; or, the multiple DRAM arrays are distributed in multiple storage wafers, corresponding to multiple storage wafer layers or multiple projection overlapping areas of the storage wafers.

5. The LLC chip according to claim 4, characterized in that: The storage space of the storage wafer is the DRAM array capacity, and the DRAM array capacity is allocated according to the access volume or access speed of the multiple processing components.

6. The LLC chip according to claim 2, characterized in that: The storage wafer further comprises a plurality of first bonding pillars, the interface logic unit further comprises a plurality of second bonding pillars and a plurality of bumps, and the packaging substrate comprises a plurality of lead ports. Each of the first bonding pillars is connected to the corresponding second bonding pillar so that the storage wafer is connected to the interface logic unit, the interface logic unit is connected to the packaging substrate through a plurality of the bumps, and the packaging substrate is connected to a plurality of the processing components through a plurality of the lead ports.

7. The LLC chip according to claim 6, characterized in that: The interface logic unit further includes an on-chip network, each node of the on-chip network is connected to a single controller, the controller is used to access the storage wafer, one end of the register is connected to the controller, the other end of the register is connected to the storage wafer, and the register is used to perform data buffering; The processing component inputs an address through the interface logic unit, and the interface logic unit drives the controller connected to the node corresponding to the address according to the address, so that the processing component performs read and write operations on the storage wafer.

8. The LLC chip according to claim 7, characterized in that: The controller includes a cache consistency protocol controller, and the LLC chip also includes a DDR controller and a DDR memory, and the cache consistency protocol controller accesses the DDR controller through the on-chip network to implement read and write operations on the DDR memory; Wherein, cache coherence protocol controllers of the plurality of controllers communicate with each other via the on-chip network.

9. The LLC chip according to claim 1, characterized in that: The LLC chip includes a plurality of storage wafers, and the plurality of storage wafers are stacked in sequence on the interface logic unit, and two adjacent storage wafers among the plurality of storage wafers are connected by bonding.

10. A cache system, characterized in that: The method comprises the LLC chip according to any one of claims 1 to 9 and a plurality of processing components, each of the processing components comprising at least two central processing units, at least two L1 caches and one L2 cache, and the plurality of processing components are connected to the LLC chip to perform read and write operations; The cache system divides the storage space of the storage wafer according to the access volume or access speed of the plurality of processing components, so that each central processor performs read and write operations on the corresponding storage space; Alternatively, any central processing unit in the plurality of processing components performs read and write operations on any storage space of the storage wafer, and two central processing units in the processing components respectively perform storage access corresponding to different storage spaces.

Images