Non-volatile memory device and driving method thereof

Abstract

A non-volatile memory device and a driving method thereof, the non-volatile memory device includes a plurality of memory planes, and the driving method includes: pre-charging at least one word line and at least one bit line of a first memory plane; if the at least one word line and the at least one bit line of the first memory plane have been pre-charged for a first time length or reach respective corresponding voltage thresholds, pre-charging at least one word line and at least one bit line of a second memory plane; performing a first data operation on at least one memory cell disposed at an intersection of the at least one word line and the at least one bit line of the first memory plane; and performing a second data operation on at least one memory cell disposed at an intersection of the at least one word line and the at least one bit line of the second memory plane.

Description

Technical Field

[0001] This invention relates to a driving method for a non-volatile memory device, and more particularly to a non-volatile memory device and driving method thereof that can reduce surge current. Background Technology

[0002] NAND flash memory is widely used in solid-state drives, mobile devices, and handheld game consoles, offering advantages such as shock resistance and high data transfer speeds. The physical structure of NAND flash memory can be hierarchically divided into memory chips, memory planes, blocks, and physical pages, from largest to smallest, based on storage capacity. Current technology accesses multiple memory planes simultaneously to accelerate data transfer speeds, but this generates large surge currents in the memory chips, potentially damaging the associated power modules. Summary of the Invention

[0003] This invention provides a driving method for a non-volatile memory device, the non-volatile memory device comprising a plurality of memory planes, and the driving method comprising the following steps: pre-charging at least one word line and at least one bit line of a first memory plane among the plurality of memory planes; if the at least one word line and at least one bit line of the first memory plane have been pre-charged for a first time length or have reached their respective corresponding voltage thresholds, then pre-charging at least one word line and at least one bit line of a second memory plane among the plurality of memory planes; performing a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at the intersection of at least one word line and at least one bit line of the first memory plane; performing a second data operation on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at the intersection of at least one word line and at least one bit line of the second memory plane.

[0004] This invention provides a driving method for a non-volatile memory device, the non-volatile memory device comprising a plurality of memory planes, and the driving method comprising the following steps: pre-charging at least one word line and at least one bit line of a first memory plane among the plurality of memory planes; if the pre-charging of at least one word line and at least one bit line of the first memory plane has reached a second time length shorter than a first time length, then pre-charging at least one word line and at least one bit line of a second memory plane among the plurality of memory planes, and continuing to pre-charge at least one word line and at least one bit line of the first memory plane; when the first memory plane has reached the first time length, performing a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at the intersection of at least one word line and at least one bit line of the first memory plane; when the at least one memory cell of the second memory plane has reached the first time length, performing a second data operation on the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at the intersection of at least one word line and at least one bit line of the second memory plane.

[0005] The present invention also provides a non-volatile memory device comprising a memory chip and a control circuit. The memory chip includes a plurality of memory planes. The control circuit is coupled to the memory chip and configured to perform the following operations: pre-charging at least one word line and at least one bit line of a first memory plane in the plurality of memory planes; if the at least one word line and at least one bit line of the first memory plane have been pre-charged for a first time length or have reached a corresponding voltage threshold, then pre-charging at least one word line and at least one bit line of a second memory plane in the plurality of memory planes; performing a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at the intersection of at least one word line and at least one bit line of the first memory plane; and performing a second data operation on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at the intersection of at least one word line and at least one bit line of the second memory plane.

[0006] The aforementioned driving method and non-volatile memory device can reduce surge current. Attached Figure Description

[0007] Figure 1 This is a simplified functional block diagram of a non-volatile memory device according to an embodiment of the present invention.

[0008] Figure 2 This is a flowchart of a driving method according to an embodiment of the present invention.

[0009] Figure 3 This is a waveform diagram of a portion of word lines and bit lines in a memory plane during the pre-charge process according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of the operation timing of multiple memory planes according to an embodiment of the present invention.

[0011] Figure 5 This is a flowchart of a driving method according to another embodiment of the present invention.

[0012] Figure 6 This is a schematic diagram of the operation timing of multiple memory planes according to another embodiment of the present invention.

[0013] Figure 7 This is a schematic diagram of the operation timing of multiple memory planes according to another embodiment of the present invention.

[0014] [Symbol Explanation]

[0015] 100...Non-volatile memory devices

[0016] 110...Input / output circuit

[0017] 120... control circuit

[0018] 130... Address Buffer

[0019] 140... bias configuration circuit

[0020] 150... Command buffer

[0021] 160...Return Circuit

[0022] 170-1~170-n... Memory Plane

[0023] 172-1~172-n... Memory Array

[0024] 174-1~174-n... Column decoder

[0025] 176-1~176-n... line decoder

[0026] 178-1~178-n... Sensing Amplifier and Data Input Structure

[0027] MC... Memory chip

[0028] Ce... storage unit

[0029] DI... Data Input

[0030] CI... Command Input

[0031] CLE... Command latch signal

[0032] WE... Write enable signal

[0033] RE...Read enable signal

[0034] SD1~SDn... Data to be written

[0035] AD1~ADn... Address

[0036] WL... lettering

[0037] BL...bitline

[0038] 200, 500… driving methods

[0039] S202~S222, S504~S522... Process

[0040] LA…First Time Length

[0041] LB…Second time length

[0042] TP1~TPn… Programming Period

[0043] PTa…First Time Point

[0044] PTb…Second Time Point Detailed Implementation

[0045] The embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0046] Figure 1 This is a simplified functional block diagram of a non-volatile memory device 100 according to an embodiment of the present invention. The non-volatile memory device 100 includes an input / output circuit 110, a control circuit 120, an address buffer 130, a bias configuration circuit 140, a command buffer 150, a report circuit 160, and a memory chip MC, wherein the memory chip MC includes multiple memory planes 170-1 to 170-n. Memory plane 170 includes a memory array 172, a column decoder 174, a row decoder 176, and a sense amplifier and data input structure 178. For the sake of simplicity and ease of explanation, other components and connections in the non-volatile memory device 100 are not shown. Figure 1 middle.

[0047] The indices 1 to n used in the component numbers used in this specification and accompanying drawings are for convenience in referring to individual components and are not intended to limit the number of the aforementioned components to a specific number. In this specification and accompanying drawings, if a component number is used without specifying its index, it means that the component number refers to any unspecified component within its component group. For example, component number 170-1 refers to memory plane 170-1, while component number 170 refers to any unspecified memory plane among memory planes 170-1 to 170-n. As another example, component number 172-1 refers to memory array 172-1, while component number 172 refers to any unspecified memory array among memory arrays 172-1 to 172-n.

[0048] Input / output circuit 110 is used to determine whether to read command input CI and data input DI into non-volatile memory device 100, and to determine whether to output from data self-sensing amplifier and data input structure 178. For example, input / output circuit 110 can determine whether to write command input CI into command buffer 150 based on command latch enable signal CLE. As another example, input / output circuit 110 can determine whether to read data input DI and whether to output data based on write enable signal WE and read enable signal RE, respectively.

[0049] Additionally, the input / output circuit 110 is also used to write one or more addresses AD1~ADn from the command input CI into the address buffer 130, which in turn allocates the addresses AD1~ADn to the column decoders 174 and row decoders 176 of the corresponding memory planes 170. The input / output circuit 110 is also used to convert the data input DI into one or more data to be written SD1~SDn, and allocate the data to be written SD1~SDn to the corresponding sense amplifiers and data input structures 178.

[0050] Control circuit 120 is coupled to bias configuration circuit 140, command buffer 150, report circuit 160, and memory planes 170-1 to 170-n. Control circuit 120 is used to perform data operations (e.g., programming, reading, and / or erasing) on ​​memory plane 170 according to command input CI. Control circuit 120 is also used to control the output voltage of bias configuration circuit 140 according to command input CI, wherein bias configuration circuit 140 sets multiple word lines WL and multiple bit lines BL of memory plane 170 to appropriate voltages corresponding to the current data operation on memory plane 170.

[0051] Column decoder 174 and row decoder 176 are coupled to memory array 172 via multiple word lines WL and multiple bit lines BL, respectively. Column decoder 174 and row decoder 176 receive one or more addresses AD1~ADn from address buffer 130 and perform data operations on memory array 172 based on the received addresses. In this embodiment, memory array 172 may contain multiple blocks, each block may contain multiple physical pages, and each physical page may contain multiple memory cells Ce. Each memory cell Ce is located at the intersection of a corresponding word line WL and a corresponding bit line BL; that is, the control gate of each memory cell Ce is defined by the overlapping portion of the corresponding word line WL and the corresponding bit line BL. Furthermore, memory array 172 may be implemented as a two-dimensional memory array or a three-dimensional memory array.

[0052] Figure 2 This is a flowchart of a driving method 200 according to an embodiment of the present invention. Figure 3 This is a waveform diagram of a portion of the word line WL and bit line BL during the pre-charging process according to an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the operation timing of memory planes 170-1 to 170-n according to an embodiment of the present invention. The term "precharge" in this invention refers to pre-setting the voltage of the corresponding word lines and bit lines to be close to the operating voltage required for the read, program, or erase operation before they are used. As the size of the memory array 172 increases, longer bit lines and word lines may be required. Precharge can be used to offset some of the increased RC delay of the word lines and bit lines and to speed up the voltage setup of the memory array 172. Please refer to [reference needed]. Figure 2 The non-volatile memory device 100 can execute the driving method 200 to perform data operations such as reading, programming, and erasing. For ease of explanation, the following description will use programming as an example. In process S202, the control circuit 120 determines whether the command input CI is a multi-plane operation command. If the command input CI is a multi-plane operation command, the non-volatile memory device 100 will then execute processes S204 to S216. Otherwise, the non-volatile memory device 100 will execute processes S218 to S222.

[0053] In process S204, the control circuit 120 can select one of the memory planes 170-1 to 170-n according to a target parameter to precharge at least one word line BL and at least one bit line WL, wherein the target parameter can be stored in advance in the non-volatile memory device 100. For example, when the target parameter is 1, the control circuit 120 can control the bias configuration circuit 140 to precharge the memory plane 170-1. In this invention, precharging refers to setting the corresponding word line WL and bit line BL to a suitable and stable voltage before performing data operations to prevent parasitic elements on the word line WL and bit line BL from causing data operation failures. For example, as Figure 3 As shown, when memory plane 170 is precharged, control circuit 120 can boost at least one word line WL and at least one bit line BL of memory plane 170 to the corresponding voltage. For simplicity, Figure 3 The voltage waveforms of an unselected bit line Usel_BL, a selected bit line Sel_BL, an unselected word line Usel_WL, and a selected word line Sel_WL are illustrated only as an example. The unselected bit line Usel_BL is subjected to an inhibit voltage (e.g., 3V), the selected bit line Sel_BL is first subjected to an inhibit voltage and then to a ground voltage (e.g., 0V), the unselected word line Usel_WL is subjected to a passing voltage (e.g., 10V), and the selected word line Sel_WL is subjected to a programming voltage (e.g., 20V).

[0054] The voltage waveforms of word line WL and bit line BL can be Figure 3 The stepped wave in the circuit can also be a square wave. In some embodiments, the control circuit 120 may first use a high-power external power supply (not shown) to charge the word line WL and bit line BL to the first-order voltage of their stepped waves to accelerate the charging speed, and then use the bias configuration circuit 140 to charge the word line WL and bit line BL to the second-order voltage of their stepped waves, but the invention is not limited thereto. In other embodiments, the control circuit 120 may also use the bias configuration circuit 140 to charge the word line WL and bit line BL throughout the pre-charging process without using an external power supply.

[0055] Please refer to Figure 2In process S206, the control circuit 120 determines whether the memory plane 170 currently being precharged (e.g., memory plane 170-1) has been precharged for a predetermined first time length LA. When the memory plane 170 currently being precharged has been precharged for the first time length LA, the control circuit 120 determines that precharging is complete, and the non-volatile memory device 100 then executes process S208 to program at least one memory cell Ce at the intersection of at least one word line WL and at least one bit line BL of the precharged memory plane 170 (e.g., memory plane 170-1). Otherwise, the non-volatile memory device 100 can execute process S204 again.

[0056] In process S210, the control circuit 120 determines whether all memory planes 170-1 to 170-n have been programmed, for example, by determining whether the target parameter is less than the total number of memory planes 170-1 to 170-n. If not all memory planes 170 have been programmed, the non-volatile memory device 100 executes process S212 to accumulate the value of the target parameter, for example, by setting the target parameter to the target parameter plus 1. The non-volatile memory device 100 can execute process S204 again after process S212 is completed. At this time, the control circuit 120 selects another corresponding memory plane among 170-1 to 170-n (for example, memory plane 170-2) to precharge at least one word line WL and at least one bit line BL.

[0057] In this embodiment, process S208 can be executed simultaneously with processes S210~S212 and other processes following process S212. Please refer to... Figure 4 When memory plane 170-1 is precharged and programming is performed, control circuit 120 can control memory plane 170-2 to start precharging. When memory plane 170-2 is precharged and programming is performed, control circuit 120 can control memory plane 170-3 to start precharging while memory plane 170-1 and / or memory plane 170-2 are still being programmed.

[0058] In other words, since memory planes 170-1 to 170-n are not precharged simultaneously, driving method 200 helps to reduce surge current in non-volatile memory device 100.

[0059] Furthermore, programming operations on multiple memory planes 170-1 to 170-n can be performed in parallel, meaning that multiple programming periods TP1 to TPn corresponding to programming memory planes 170-1 to 170-n can at least partially overlap. Therefore, the driving method 200 helps to accelerate the programming speed of the non-volatile memory device 100.

[0060] Please refer to this again. Figure 2 In process S214, the control circuit 120 determines whether each of the memory planes 170-1 to 170-n has been successfully programmed. For example, in some embodiments, the non-volatile memory device 100 is programmed using Incremental-Step-Pulse Programming (ISPP) technology. The control circuit 120 can determine whether the programming was successful based on the total number of programming pulses provided to the target word line WL. If the control circuit 120 determines that all memory planes 170-1 to 170-n have been successfully programmed, the control circuit 120 can use the reporting circuit 160 to output a signal representing successful programming to an external processor or external logic circuit (not shown) and end the execution of the drive method 200. Otherwise, the non-volatile memory device 100 can execute process S216 to reset the target parameters and execute process S204 again. For example, the non-volatile memory device 100 can reset the target parameter to 1 in process S216 so that the memory planes 170-1 to 170-n can be reprogrammed starting from memory plane 170-1 in subsequent processes.

[0061] When the command input CI is not a multi-memory plane operation command, the non-volatile memory device 100 executes process S218 to precharge at least one word line WL and at least one bit line BL of one of the memory planes 170-1 to 170-n. Then, when the precharge reaches a first time length LA, the non-volatile memory device 100 executes process S220 to program at least one memory cell Ce of one of the memory planes 170-1 to 170-n.

[0062] Process S222 is similar to process S214. In process S222, the control circuit 120 determines whether one of the memory planes 170-1 to 170-n has been successfully programmed. If the control circuit 120 determines that one of the memory planes 170-1 to 170-n has been successfully programmed, the non-volatile memory device 100 terminates the driving method 200. Otherwise, the non-volatile memory device 100 can execute process S218 again.

[0063] In some embodiments, when the non-volatile memory device 100 reads the memory chip MC using the driving method 200, the non-volatile memory device 100 can perform the read operation in processes S208 and S220 without performing the programming operation. Similarly, in other embodiments, when the non-volatile memory device 100 erases the memory chip MC using the driving method 200, the non-volatile memory device 100 can perform the erase operation in processes S208 and S220 without performing the programming operation.

[0064] Figure 5 This is a flowchart of a driving method 500 according to another embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the operation timing of memory planes 170-1 to 170-n according to another embodiment of the present invention. Please refer to [the diagram first]. Figure 5 The non-volatile memory device 100 can execute the driving method 500 to perform data operations such as reading, programming, and erasing. For ease of explanation, the following description will use programming as an example. The non-volatile memory device 100 will first execute the aforementioned process S202. If the command input CI is a multi-memory plane operation command, the non-volatile memory device 100 will then execute processes S504 to S522. Otherwise, the non-volatile memory device 100 will execute the aforementioned processes S218 to S222.

[0065] In process S504, the control circuit 120 can select one of the memory planes 170-1 to 170-n according to the target parameter to precharge at least one word line BL and at least one bit line WL. Next, in process S506, the control circuit 120 determines whether all memory planes 170-1 to 170-n have been precharged, for example, by determining whether the target parameter is less than the total number of memory planes 170-1 to 170-n. If not all memory planes 170 have been precharged, the non-volatile memory device 100 executes processes S508 to S514. Otherwise, the non-volatile memory device 100 executes process S516.

[0066] In process S508, the control circuit 120 determines whether at least one word line WL and at least one bit line BL in the pre-charged memory plane 170 (e.g., memory plane 170-1) have reached their respective voltage thresholds. For example, the control circuit 120 may determine whether each of the at least one bit line BL has reached a voltage threshold close to the prohibition voltage (e.g., 2.8V), whether a particular word line WL has reached a voltage threshold close to the programming voltage (e.g., 18V), and whether other word lines WL have reached voltage thresholds close to the pass voltage (e.g., 8V). If the control circuit 120 determines that the at least one word line WL and the at least one bit line BL in the pre-charged memory plane 170 have reached their respective voltage thresholds, the non-volatile memory device 100 executes process S510. Otherwise, the non-volatile memory device 100 may repeat process S508.

[0067] In process S510, the control circuit 120 accumulates the target parameter, for example, by setting the target parameter to be one. The non-volatile memory device 100 can execute process S504 again after process S510 ends. At this time, the control circuit 120 will select another corresponding memory plane 170-1 to 170-n (e.g., memory plane 170-2) to precharge at least one word line WL and at least one bit line BL.

[0068] When the non-volatile memory device 100 executes processes S508-S510 and other processes following process S510, the non-volatile memory device 100 may simultaneously execute processes S512-S514. Please also refer to... Figure 5 and Figure 6 In process S512, the control circuit 120 determines whether the memory plane 170 currently being precharged (e.g., memory plane 170-1) has been precharged for a predetermined first time length LA. When the memory plane 170 currently being precharged has been precharged for the first time length LA, the control circuit 120 determines that precharging is complete, and the non-volatile memory device 100 then executes process S514 to program at least one memory cell Ce at the intersection of at least one word line WL and at least one bit line BL of the precharged memory plane 170 (e.g., memory plane 170-1). Otherwise, the non-volatile memory device 100 may repeat process S512.

[0069] like Figure 6 As shown, when at least one word line WL and at least one bit line BL of a certain memory plane 170 (e.g., memory plane 170-1) reach their respective voltage thresholds at the first time point PTa, the control circuit 120 will not only control the bias configuration circuit 140 to continue precharging the memory plane 170, but also control the bias configuration circuit 140 to start precharging at least one word line WL and at least one bit line BL of the next memory plane 170 (e.g., memory plane 170-2) without waiting for the memory plane 170 to complete precharging. Similarly, when at least one word line WL and at least one bit line BL of the next memory plane 170 (e.g., memory plane 170-2) reach their respective voltage thresholds at the second time point PTb, the control circuit 120 will not only control the bias configuration circuit 140 to continue precharging the next memory plane 170, but also control the bias configuration circuit 140 to start precharging at least one word line WL and at least one bit line BL of the next memory plane 170 after that (e.g., memory plane 170-3).

[0070] Since the pre-charge process is nearly complete when at least one word line WL and at least one bit line BL of memory plane 170 reach their respective voltage thresholds, the current supplied to memory plane 170 by bias configuration circuit 140 has decreased significantly compared to the start of pre-charge due to the charging and discharging characteristics of capacitors. Therefore, even if multiple memory planes 170 are pre-charged simultaneously, it will not cause excessive surge current.

[0071] As described above, when the non-volatile memory device 100 executes the driving method 500, memory planes 170-1 to 170-n will sequentially begin pre-charging. Therefore, the driving method 500 helps to reduce surge current in the non-volatile memory device 100.

[0072] Furthermore, without causing excessive surge current, multiple memory planes 170-1 to 170-n can be pre-charged simultaneously. Therefore, the driving method 500 can further accelerate the programming speed of the non-volatile memory device 100.

[0073] Please refer to this again. Figure 5 When the control circuit 120 determines in process S506 that the target parameter is greater than or equal to the total number of memory planes 170-1 to 170-n, the non-volatile memory device 100 executes process S516, which is similar to process S512. When the control circuit 120 determines that the memory plane 170 currently being precharged (e.g., memory plane 170-n) has been precharged for a first time length LA, the control circuit 120 determines that precharging is complete and executes process S518 to program at least one memory cell Ce of the precharged memory plane 170. Otherwise, the non-volatile memory device 100 can execute process S516 again to continue precharging the memory plane 170.

[0074] Process S520 is similar to Figure 2 The process S214. When the control circuit 120 determines that all memory planes 170-1 to 170-n have been successfully programmed, the non-volatile memory device 100 can terminate the driving method 500. Otherwise, the non-volatile memory device 100 can execute the process S214. Figure 2 The process S216 is similar to process S522 to reset the target parameters. The non-volatile memory device 100 can re-execute process S504 after process S522 is completed.

[0075] In some embodiments, such as Figure 7As shown, in process S508, control circuit 120 determines whether the memory plane 170 currently being precharged has been precharged for a predetermined second time length LB, wherein the aforementioned first time length LA is greater than the second time length LB. When the memory plane 170 currently being precharged has been precharged for the second time length LB, non-volatile memory device 100 executes process S510. Otherwise, non-volatile memory device 100 executes process S508 again to continue precharging memory plane 170. The second time length LB can be pre-stored in non-volatile memory device 100, wherein by selecting an appropriate second time length LB, it is possible to prevent excessive surge current from occurring when multiple memory planes 170-1 to 170-n are precharged simultaneously.

[0076] In other embodiments, when the non-volatile memory device 100 executes the driving method 500 to read the memory chip MC, the non-volatile memory device 100 can perform the read operation in processes S514 and S518 without performing the programming operation. Similarly, in yet other embodiments, when the non-volatile memory device 100 erases the memory chip MC using the driving method 500, the non-volatile memory device 100 can perform the erase operation in processes S514 and S518 without performing the programming operation.

[0077] Although Figure 1 Only one memory chip MC is illustrated, but the present invention is not limited thereto. In practice, the non-volatile memory device 100 may include multiple memory chips MC to improve storage density, and the non-volatile memory device 100 may execute driving method 200 or 500 for each memory chip MC.

[0078] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element through other elements or connection means.

[0079] The use of "and / or" herein includes any combination of one or more of the listed items. Furthermore, unless otherwise specified in the specification, any singular term also includes the plural meaning.

[0080] The above are merely preferred embodiments of the present invention. All equivalent variations and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A driving method of a non-volatile memory device, the non-volatile memory device comprising a plurality of memory planes, and the driving method comprising: pre-charging at least one word line and at least one bit line of a first memory plane of the plurality of memory planes; if the at least one word line and the at least one bit line of the first memory plane have been pre-charged for a first predetermined length of time or have reached a respective corresponding voltage threshold, then pre-charging at least one word line and at least one bit line of a second memory plane of the plurality of memory planes, wherein, two word lines of the at least one word line of the first memory plane have different voltage thresholds; performing a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at an intersection of the at least one word line and the at least one bit line of the first memory plane; and performing a second data operation on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at an intersection of the at least one word line and the at least one bit line of the second memory plane; wherein the first data operation is performed in a first time period, the second data operation is performed in a second time period, a beginning of the first time period is earlier than a beginning of the second time period, and the first time period at least partially overlaps with the second time period.

2. The driving method of claim 1, wherein, wherein the at least one word line and the at least one bit line of the second memory plane are pre-charged if the at least one word line and the at least one bit line of the first memory plane have been pre-charged for the first length of time, and the driving method further comprises: pre-charging at least one word line and at least one bit line of a third memory plane of the plurality of memory planes if the at least one word line and the at least one bit line of the second memory plane have been pre-charged for the first length of time.

3. The driving method of claim 1, wherein, wherein the at least one word line and the at least one bit line of the second memory plane are pre-charged if the at least one word line and the at least one bit line of the first memory plane reach respective corresponding voltage thresholds, and the at least one word line and the at least one bit line of the first memory plane are continued to be pre-charged, wherein the first data operation on the at least one memory cell of the first memory plane comprises: performing the first data operation on the at least one memory cell of the first memory plane when the at least one word line and the at least one bit line of the first memory plane have been pre-charged for the first length of time.

4. The driving method of claim 3, further comprising: pre-charging at least one word line and at least one bit line of a third memory plane of the plurality of memory planes if the at least one word line and the at least one bit line of the second memory plane reach respective corresponding voltage thresholds, and the at least one word line and the at least one bit line of the second memory plane are continued to be pre-charged; wherein wherein the second data operation on the at least one memory cell of the second memory plane comprises: performing the second data operation on the at least one memory cell of the second memory plane when the at least one word line and the at least one bit line of the second memory plane have been pre-charged for the first length of time.

5. The driving method of claim 1, wherein, the at least one word line and the at least one bit line of the first memory plane have a stepped voltage waveform when the at least one word line and the at least one bit line of the first memory plane are pre-charged.

6. A driving method of a non-volatile memory device, the non-volatile memory device comprising a plurality of memory planes, and the driving method comprising: pre-charging at least one word line and at least one bit line of a first memory plane of the plurality of memory planes; if the at least one word line and the at least one bit line of the first memory plane have been pre-charged for a scheduled second time length shorter than a first time length, then pre-charging at least one word line and at least one bit line of a second memory plane of the plurality of memory planes, and continuing to pre-charge the at least one word line and the at least one bit line of the first memory plane; when the at least one word line and the at least one bit line of the first memory plane have been pre-charged for the first time length, performing a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at an intersection of the at least one word line and the at least one bit line of the first memory plane; and when the at least one word line and the at least one bit line of the second memory plane have been pre-charged for the first time length, performing a second data operation on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at an intersection of the at least one word line and the at least one bit line of the second memory plane; wherein, the first data operation is performed in a first time period, the second data operation is performed in a second time period, a beginning of the first time period is earlier than a beginning of the second time period, and the first time period at least partially overlaps with the second time period.

7. The driving method of claim 6, further comprising: if the at least one word line and the at least one bit line of the second memory plane have been pre-charged for the second time length, then pre-charging at least one word line and at least one bit line of a third memory plane of the plurality of memory planes, and continuing to pre-charge the at least one word line and the at least one bit line of the second memory plane.

8. A non-volatile memory device, comprising: a memory chip comprising a plurality of memory planes; and a control circuit coupled to the memory chip and configured to perform operations comprising: pre-charging at least one word line and at least one bit line of a first memory plane of the plurality of memory planes; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a first prescribed length of time or have reached respective corresponding voltage thresholds, then precharge at least one word line and at least one bit line of a second memory plane of the plurality of memory planes, wherein, two word lines of the at least one word line of the first memory plane have different voltage thresholds; performing a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at an intersection of the at least one word line and the at least one bit line of the first memory plane; and performing a second data operation on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at an intersection of the at least one word line and the at least one bit line of the second memory plane; wherein the first data operation is performed in a first time period, the second data operation is performed in a second time period, a beginning of the first time period is earlier than a beginning of the second time period, and the first time period at least partially overlaps with the second time period. ​

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