Semiconductor Structure and Method for Forming the Same

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same, including depositing a dielectric layer on a substrate and depositing a patterned layer on the dielectric layer. The method also includes performing a first etching process on the patterned layer to form a first region having a plurality of first blocks with a first pattern density and a second region having a plurality of second blocks with a second pattern density, and the second pattern density is less than the first pattern density. The method also includes performing a second etching process on the second blocks to reduce the width of each second block; and using the first blocks and the second blocks to etch the dielectric layer and the substrate to form a plurality of fin structures.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures, and particularly to forming fin structures with consistent lateral dimensions in regions of different pattern densities. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, the functional density (such as the number of interconnect devices per unit chip area) generally increases as the geometric dimensions (such as the smallest components or lines that can be produced by the adopted manufacturing process) shrink. The process of shrinking the dimensions is beneficial for increasing production capacity and reducing related costs. Summary of the Invention

[0003] In some embodiments, a method of forming a semiconductor structure includes: forming a semiconductor structure having a substrate, a dielectric layer, a lower patterned layer, and an upper patterned layer. The dielectric layer is located on the substrate, the lower patterned layer is located on the dielectric layer, and the upper patterned layer is located on the lower patterned layer. The method also includes performing a first etching process on the upper patterned layer to form a patterned upper patterned layer. The patterned upper patterned layer includes a first region with a first pattern density and a second region with a second pattern density, and the second pattern density is less than the first pattern density. The method also includes performing a second etching process on the lower patterned layer to form a patterned lower patterned layer. The patterned lower patterned layer includes a plurality of first blocks in the first region and a plurality of second blocks in the second region, and each second block has a trapezoidal cross-sectional profile. The method also includes performing a third etching process on the first blocks and the second blocks at a first etching rate and a second etching rate respectively to form an adjusted patterned lower patterned layer. The first etching rate is lower than the second etching rate. The method also includes using the patterned upper patterned layer and the adjusted patterned lower patterned layer as masks and performing a fourth etching process on the substrate and the dielectric layer to form a plurality of fins.

[0004] In some embodiments, a method of forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterned layer on the dielectric layer. The method also includes performing a first etching process on the patterned layer to form a first region containing a plurality of first blocks with a first pattern density and a second region containing a plurality of second blocks with a second pattern density, and the second pattern density is less than the first pattern density. The method also includes performing a second etching process on the second blocks to reduce the width of each second block; and using the first blocks and the second blocks to etch the dielectric layer and the substrate to form a plurality of fin structures.

[0005] In some embodiments, a semiconductor structure includes a substrate and a plurality of fin structures formed on the substrate. The fin structures include a plurality of first fin structures having a first pattern density. A first width of each first fin structure is substantially equal to a critical dimension of a lithographic apparatus. A first separation between adjacent first fin structures is between about 20 nm and about 70 nm. The fin structures also include a plurality of second fin structures having a second pattern density, and the second pattern density is less than the first pattern density. A second width of each second fin structure is substantially equal to the first width. A second separation between adjacent second fin structures is between about 10 nm and about 20 nm. A dielectric layer is formed on the first fin structures and the second fin structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view of a semiconductor structure in some embodiments.

[0007] Figures 2 to 6 is a cross-sectional view of various fabrication stages of a semiconductor structure forming fin structures with different pattern densities in some embodiments.

[0008] Figure 7 is a flowchart of a method for forming fin structures with different pattern densities and substantially the same width in some embodiments.

[0009] Wherein, the reference numerals are described as follows:

[0010] α, β: angles

[0011] D, D1, D2: distances

[0012] t, 118t, 120t, 122t: thicknesses

[0013] W: width

[0014] 100: fin field-effect transistor

[0015] 102, 202: substrates

[0016] 104, 604: fin structures

[0017] 106: source / drain regions

[0018] 108: gate structures

[0019] 110: spacers

[0020] 110a, 110b, 110c: spacer portions

[0021] 112: shallow trench isolation regions

[0022] 116: gates

[0023] 118: dielectric layers

[0024] 120: Gate cap layer

[0025] 121: Fin region

[0026] 122: Gate work function layer

[0027] 124: Gate metal fill layer

[0028] 200, 300, 400, 500, 600: Semiconductor structures

[0029] 230: Etch adjustment layer

[0030] 240: Lower side patterned layer

[0031] 250: Upper side patterned layer

[0032] 306: Dense region

[0033] 308: Loose region

[0034] 310: First etching process

[0035] 350: Patterned upper side patterned layer

[0036] 410: Second etching process

[0037] 440: Patterned lower side patterned layer

[0038] 440A, 440B, 540B: Masses

[0039] 510: Third etching process

[0040] 510H: Horizontal etching process

[0041] 540: Adjusted patterned lower side patterned layer

[0042] 610: Fourth etching process

[0043] 700: Fabrication process

[0044] 702, 704, 706, 708, 710: Steps Detailed Description

[0045] The following detailed description may be accompanied by the drawings for a better understanding of the aspects of the present disclosure. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is normal in the industry. In fact, for clarity of illustration, the dimensions of the various structures may be arbitrarily increased or decreased.

[0046] The different embodiments or examples provided below can implement different structures of the present disclosure. The embodiments of the specific components and arrangements below are used to simplify the present disclosure content rather than limit the present disclosure. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two rather than in direct contact. In addition, in the embodiments where the structure of the present disclosure is formed on another structure, connected to another structure, and / or coupled to another structure, the structure can be in direct contact with another structure, or additional structures can be formed between the structure and another structure (i.e., the structure is not in contact with another structure). In addition, multiple examples of the present disclosure may reuse the same reference numerals for the sake of simplicity, but the elements with the same reference numerals in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0047] In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", or similar terms can be used to simplify the description of the relative relationship between one element and another element in the drawings. The spatial relative terms can extend to elements used in other directions, rather than being limited to the directions in the drawings. The element can also be rotated 90° or other angles, so the directional terms are only used to illustrate the directions in the drawings.

[0048] The term "substantially" refers to the expected or target value of the characteristics or parameters of a component or process operation in the design stage of a product or process, as well as values above and / or below the required value. The numerical range usually comes from the slight variations in the process or tolerance.

[0049] The terms "about" and "substantially" herein refer to that the numerical value of a given quantity can vary according to the technology node related to semiconductor devices. In some embodiments, the terms "about" and "substantially" can indicate that the value of a given quantity varies within 5% (e.g., ±1%, ±2%, ±3%, ±4%, or ±5% of the numerical value), depending on the specific technology node.

[0050] With the progress of technology, integrated circuits are characterized by smaller sizes than those of the previous generation of devices. As planar semiconductor devices such as metal-oxide-semiconductor field-effect transistors are scaled down to various technology nodes, other method advancements can increase device density and speed. One method is the fin field-effect transistor device, which is a three-dimensional field-effect transistor containing fin-like structures (such as fins) extending from a substrate. The width of the fin-like structure is usually designed to be equal to the critical dimension of the lithography equipment used to form the transistor. The critical dimension can be about 7 nm, about 5 nm, about 3 nm, or any suitable dimension. The source, drain, and channel of the transistor can be formed on the fin. The fin field-effect transistor can be compatible with existing complementary metal-oxide-semiconductor processes, and its three-dimensional structure can significantly reduce the size and maintain gate control and mitigate the short-channel effect.

[0051] Implementing these structures and processes poses challenges. As the fin size and the spacing between fins shrink, the loading effects on all devices on the same wafer or die may be exacerbated. For example, fins designed to be substantially the same width may have different fin widths because of different etch rates in regions of different pattern densities. Due to different pattern properties such as pattern density, structure aspect ratio, and / or the composition or reflectivity of the structure, the etch rates across the semiconductor device vary, causing loading effects. For example, due to the physical and chemical characteristics of the plasma etch process, regions with higher pattern density may have lower etch rates and higher plasma scattering, while regions with lower density patterns may have higher etch rates and lower plasma scattering. Thus, the changing behavior of the plasma etchant results in different profiles after plasma etching, causing loading effects for different patterns.

[0052] Methods provided by various embodiments of the present disclosure can form fin structures that have consistent lateral dimensions in regions of different pattern densities. The method of forming the fin structure can be to form one or more patterned layers on a substrate and then perform a plasma etch process. An etch adjustment layer can be deposited between the substrate and the one or more patterned layers. The one or more patterned layers can include one or more hard mask layers. During one or more stages of the plasma etch process, the etch adjustment layer can impede the downward etch process and enhance the lateral etch process to achieve substantially the same etch profile in the sparse region (such as a region of lower pattern density) and the dense region (such as a region of higher pattern density). In some embodiments, the choice of precursors used in the plasma etch process is based on their mobilities in the sparse region and the dense region. For example, precursors with higher mobilities in the sparse region and lower mobilities in the dense region can be selected for one or more stages of the plasma etch process.

[0053] Figure 1 is an isometric view of a fin field-effect transistor. Figures 2 to 6 is a semiconductor device during various fabrication stages of forming a fin structure, and the fin structure has substantially the same cross-sectional profile in the sparse region and the dense region. Figure 7 is an exemplary flowchart showing a method of forming multiple fin structures in a sparse region and a dense region.

[0054] Figure 1 is an isometric view of a fin field-effect transistor in some embodiments. The fin field-effect transistor 100 can be included in a microprocessor, a memory cell, or other integrated circuits. Figure 1 The fin field-effect transistor in is shown for illustrative purposes and is not drawn to scale. The fin field-effect transistor 100 can include additional suitable structures, such as additional spacers, liner layers, contact structures, and any other suitable structures, which are not shown in Figure 1to seek clarity in the diagrams.

[0055] The fin field-effect transistor 100 may be formed on a substrate 102 and may include a fin structure 104 having a fin region 121 and source / drain regions 106, a gate structure 108 located on the fin structure 104, spacers 110 located on both sides of each gate structure 108, and shallow trench isolation regions 112. Figure 1 Three fin structures 104 and five gate structures 108 are shown. In accordance with the content described herein, the fin field-effect transistor 100 may have more or fewer fin structures or gate structures. Additionally, the fin field-effect transistor 100 may be incorporated into an integrated circuit by other structural components (omitted herein for clarity, such as source / drain contact structures, gate contact structures, conductive vias, conductive lines, dielectric layers, and passivation layers).

[0056] The substrate 102 may be a semiconductor material such as silicon. In some embodiments, the substrate 102 includes a crystalline silicon substrate such as a wafer. In some embodiments, the substrate 102 includes (i) a semiconductor element such as germanium; (ii) a semiconductor compound such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) a semiconductor alloy such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, gallium indium phosphide, gallium indium arsenide, gallium indium phosphide arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) a combination of the above. Additionally, the substrate 102 may be doped according to design requirements (such as a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (such as boron, indium, aluminum, or gallium) or an n-type dopant (such as phosphorus or arsenic). In some embodiments, a semiconductor structure such as the fin field-effect transistor 100 may also include a processed integrated circuit wafer buried in the substrate 102. For example, the substrate 102 may include various transistors, capacitors, resistors, and logic, digital, or radio frequency components formed by interconnects, not shown in Figure 1 to simplify the diagrams.

[0057] The fin structure 104 refers to the current-carrying structure of the fin field-effect transistor 100 and can pass through the gate structure 108 along the Y-axis. Each fin structure of the fin structure 104 can have a width W, which is substantially equal to or greater than the critical dimension of the lithography equipment used to fabricate the fin field-effect transistor 100. For example, the width W can be about 3 nm, about 5 nm, about 7 nm, or any suitable dimension. The fin structures of the fin structure 104 can be separated by a distance D, which can vary in size across the entire wafer or die. For example, the separation between fins in the sparse region can be greater than the separation between fins in the dense region. In some embodiments, the distance D can be between about 20 nm and about 70 nm in the sparse region and between about 10 nm and about 20 nm in the dense region. For example, the distance D in the sparse region can be between about 20 nm and about 30 nm, between about 30 nm and about 50 nm, between about 50 nm and about 70 nm, or any suitable distance. In some embodiments, the distance D in the dense region can be between about 10 nm and about 15 nm, between about 15 nm and about 20 nm, or any suitable distance. In some embodiments, the ratio W / D can be between about 0.1 and about 0.5 in the sparse region and between about 1 and about 2 in the dense region. In some embodiments, the distance D in the sparse region or the dense region can be different. The fin structure 104 can include (i) a portion of the fin region 121 under the gate structure 108; and (ii) source / drain regions 106 located on a portion of the fin region 121, which can be formed on both sides of each gate structure 108. The portion of the fin region 121 of the fin structure 104 under the gate structure 108 (not shown in Figure 1 the figure) can extend above the shallow trench isolation region 112, and one of the corresponding gate structures 108 can cover the portion of the fin region 121. The fin region 121 on both sides of the gate structure 108 can be re-etched, and the source / drain regions 106 can be epitaxially grown on the re-etched portions of the fin region 121.

[0058] The material included in the fin region 121 of the fin structure 104 can be similar to that of the substrate 102. The source / drain regions 106 can include epitaxially grown semiconductor materials. In some embodiments, the epitaxially grown semiconductor material is the same as the material of the substrate 102. In some embodiments, the epitaxially grown semiconductor material is different from the material of the substrate 102. The epitaxially grown semiconductor material can include (i) semiconductor materials such as germanium or silicon; (ii) semiconductor compound materials such as gallium arsenide or aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium or gallium phosphide arsenide. Other materials used for the fin structure 104 also fall within the scope of the embodiments of the present disclosure.

[0059] In some embodiments, the method of growing the source / drain regions 106 may be (i) chemical vapor deposition such as low-pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, remote plasma chemical vapor deposition, or a suitable chemical vapor deposition process; (ii) molecular beam epitaxy process; (iii) a suitable epitaxy process; or (iv) a combination of the above. In some embodiments, the method of growing the source / drain regions 106 may be epitaxial deposition and a partial etching process, which may repeat at least one epitaxial deposition and partial etching process. These repeated deposition and partial etching processes may also be referred to as a cyclic deposition-etching process. In some embodiments, the method of growing the source / drain regions 106 may be selective epitaxial growth, which adds an etching gas to promote the selective growth of semiconductor material on the exposed surface of the fin structure without growing semiconductor material on the insulating material (such as the dielectric material of the shallow trench isolation region 112). Other methods for epitaxially growing the source / drain regions 106 are also within the scope of the embodiments of the present disclosure. The source / drain regions 106 may be p-type regions or n-type regions. In some embodiments, the p-type source / drain regions 106 may comprise silicon germanium and may be in-situ doped with a p-type dopant such as boron, indium, or gallium during epitaxial growth. For p-type in-situ doping, a p-type doping precursor such as diborane, boron trifluoride, or other p-type doping precursors may be used. In some embodiments, the n-type source / drain regions 106 may comprise silicon and may be in-situ doped with an n-type dopant such as phosphorus or arsenic during the epitaxial growth process. For n-type in-situ doping, an n-type doping precursor such as phosphine, arsine, or other n-type doping precursors may be used. In some embodiments, the source / drain regions 106 are not in-situ doped, and ion implantation may be performed to dope the source / drain regions 106.

[0060] The spacer 110 may comprise a spacer portion 110a formed on the sidewalls of the gate structure 108 and contacting the dielectric layer 118, a spacer portion 110b formed on the sidewalls of the fin structure 104, and a spacer portion 110c formed as a protective layer on the shallow trench isolation region 112. Each spacer portion may also be a multi-spacer structure containing more than one spacer structure. For example, the spacer portion 110a may comprise a plurality of spacers and air gaps formed between the gate structure 108 and the fin structure 104. A sealing material may be formed on the air gaps to seal and protect the air gaps from the influence of subsequent fabrication processes. Figure 1The air gap and the sealing material are not shown to simplify the drawing. The spacer 110 may comprise an insulating material such as silicon oxide, silicon nitride, a low dielectric constant material, or a combination of the foregoing. The spacer 110 may comprise a low dielectric constant material having a dielectric constant lower than 3.9 (such as lower than 3.5, 3, or 2.8). Since the dielectric constant of the air gap is about 1, the effective dielectric constant of the spacer 110 can be further reduced compared to using only a low dielectric constant spacer. The low dielectric constant material used for the spacer 110 may be formed by a deposition process such as atomic layer deposition. In some embodiments, the deposition method of the spacer 110 may employ chemical vapor deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, remote plasma chemical vapor deposition, physical vapor deposition, any other suitable deposition process, or a combination of the foregoing. In some embodiments, the sealing material may be a high-rigidity material such as HRSCO. In some embodiments, the sealing material may be a double-layer sealing material, and the forming method thereof may be depositing a first sealing material on top of the opening between the gate structure 108 and the source / drain region 106, and then depositing a second sealing material on the first sealing material to form a housing having a gas sealed in the opening. Other materials and thicknesses used for the spacer 110 and the sealing material also fall within the scope of the embodiments of the present disclosure.

[0061] Each gate structure 108 may comprise a gate 116, a dielectric layer 118 adjacent to and in contact with the gate 116, and a gate capping layer 120. The forming method of the gate structure 108 may be a gate replacement process.

[0062] In some embodiments, the composition of the dielectric layer 118 may employ a high dielectric constant dielectric material (such as a dielectric material having a dielectric constant greater than about 3.9). The forming method of the dielectric layer 118 may be chemical vapor deposition, atomic layer deposition, physical vapor deposition, electron beam evaporation, or other suitable processes. In some embodiments, the dielectric layer 118 may comprise (i) a layer of silicon oxide, silicon nitride, and / or silicon oxynitride, (ii) a high dielectric constant dielectric material such as hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicate, zirconium oxide, or zirconium silicate, (iii) a high dielectric constant dielectric material such as an oxide containing lithium, beryllium, magnesium, calcium, strontium, scandium, yttrium, zirconium, aluminum, lanthanum, cerium, praseodymium, niobium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium, or (iv) a combination of the foregoing. The forming method of the high dielectric constant dielectric layer may be atomic layer deposition and / or other suitable methods. In some embodiments, the dielectric layer 118 may comprise a single layer or a stack of insulating material layers. Other materials and forming methods used for the dielectric layer 118 also fall within the scope of the embodiments of the present disclosure. For example, a portion of the dielectric layer 118 may be formed on a horizontal surface, such as the upper surface of the shallow trench isolation region 112. Although not shown in Figure 1 , the dielectric layer 118 may also be formed on the top and sidewalls of the fin region 121 under the gate 116.

[0063] In some embodiments, a dielectric layer 118 is also formed between the sidewalls of the gate 116 and the spacer portion 110a, as Figure 1 shown. In some embodiments, the thickness 118t of the dielectric layer 118 may be from about 1 nm to about 5 nm.

[0064] The gate 116 may include a gate work function metal layer 122 and a gate metal fill layer 124. In some embodiments, the gate work function metal layer 122 is located on the dielectric layer 118. The gate work function metal layer 122 may include a single metal layer or a stack of metal layers. The work functions of the metals included in the stack of metal layers may be the same or different from each other. In some embodiments, the gate work function metal layer 122 may include aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, tantalum carbide, tantalum silicon nitride, tantalum carbonitride, titanium aluminum, titanium aluminum nitride, tungsten nitride, a metal alloy, or a combination of the foregoing. The gate work function metal layer 122 may be formed by a suitable process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or a combination of the foregoing. In some embodiments, the thickness 122t of the gate work function layer 122 is from about 2 nm to about 15 nm. Other materials, formation methods, and thicknesses of the gate work function layer 122 are also within the scope of the embodiments of the present disclosure.

[0065] The gate metal fill layer 124 may include a single metal layer or a stack of metal layers. The stack of metal layers may include metals different from each other. In some embodiments, the gate metal fill layer 124 may include a suitable conductive material, such as titanium, silver, aluminum, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten nitride, copper, tungsten, cobalt, nickel, titanium carbide, titanium aluminum carbide, tantalum aluminum carbide, a metal alloy, or a combination of the foregoing. The formation method of the gate metal fill layer 124 may be atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes. Other materials and formation methods used for the gate metal fill layer 124 are also within the scope of the embodiments of the present disclosure.

[0066] In some embodiments, the thickness 120t of the gate capping layer 120 is from about 5 nm to about 50 nm, and may protect the gate structure 108 in subsequent processes of the fin field effect transistor 100. The gate capping layer 120 may include a nitride material such as silicon nitride, silicon-rich nitride, or silicon oxynitride. Other materials used for the gate capping layer 120 are also within the scope of the embodiments of the present disclosure.

[0067] The shallow trench isolation region 112 can electrically isolate the fin field-effect transistor 100 from adjacent active and passive elements (not shown herein, integrated into or deposited on the substrate 102). The shallow trench isolation region 112 can have a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric material, or other suitable insulating materials. In some embodiments, the shallow trench isolation region 112 can include a multi-layer structure. The cross-sectional shapes of the fin structure 104, source / drain regions 106, gate structure 108, spacers 110, and the shallow trench isolation region 112 are merely illustrative and not limiting of the embodiments of the present disclosure.

[0068] Figure 7 The illustrated fabrication process 700 can form fin structures of a semiconductor device that can have substantially the same width in different regions of the semiconductor substrate (such as the relaxed region and the dense region of the semiconductor substrate). Figures 2 to 6 Provide Figure 7 Multiple diagrams of the semiconductor device during the illustrated fabrication process are provided. The fabrication process can incorporate an etch adjustment layer between one or more patterned layers and the substrate. The fabrication process provided herein is merely illustrative, and other processes not shown herein can be performed in accordance with the embodiments of the present disclosure. Figures 2 to 6 The illustrated fabrication process and semiconductor device are for illustrative purposes only. For example, Figure 6 The illustrated fabrication process can be used to form any suitable three-dimensional transistor, such as a fin field-effect transistor or a gate-all-around device. In some embodiments, the fabrication process can be used to form any suitable semiconductor device, including multiple raised structures with different pattern densities.

[0069] As Figure 7 In some of the illustrated embodiments, step 702 forms an etch adjustment layer, a lower patterned layer, and an upper patterned layer on the substrate. Figure 2 FIG. is a cross-sectional view of the semiconductor structure 200 after placing the etch adjustment layer 230, the lower patterned layer 240, and the upper patterned layer 250 on the substrate 202.

[0070] The semiconductor structure 200 includes a substrate 202. In some embodiments, the substrate 202 can be (i) another semiconductor such as germanium; (ii) a semiconductor compound such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, gallium indium phosphoarsenide, and / or indium antimonide; (iii) a semiconductor alloy such as silicon germanium; or (iv) a combination of the above. In some embodiments, the substrate 202 can be a semiconductor-on-insulator. In some embodiments, the substrate 202 can be an epitaxial material. In some embodiments, the substrate 202 can be similar to Figure 1 the above-described substrate 102 shown.

[0071] In some embodiments, an etch adjustment layer 230 may be formed on a substrate 202 to avoid etching the substrate 202 when forming a patterned layer. The composition of the etch adjustment layer 230 may employ a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, any suitable dielectric material, and / or a combination of the foregoing. In some embodiments, the composition of the etch adjustment layer 230 may be one or more layers of material. For example, the etch adjustment layer 230 may be formed by a first sub-layer, a second sub-layer, and a third sub-layer, and their compositions may employ silicon oxide, silicon nitride, and silicon oxynitride, respectively. In some embodiments, the composition of the etch adjustment layer 230 may employ a low dielectric constant dielectric material (such as a dielectric material with a dielectric constant lower than about 3.9). In some embodiments, the composition of the etch adjustment layer 230 may employ a metal oxide material such as hafnium oxide, zirconium oxide, any suitable metal oxide material, and / or a combination of the foregoing. In some embodiments, the composition of the etch adjustment layer 230 may employ a material suitable for an etch stop layer. The deposition method of the etch adjustment layer 230 may be any suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, high density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, electroplating, any suitable deposition method, and / or a combination of the foregoing. In some embodiments, the thickness t of the etch adjustment layer 230 may be between about 3 nm and about 5 nm. In some embodiments, the thickness t of the etch adjustment layer 230 may be greater than about 5 nm. For example, the thickness t may be between about 3 nm and about 4 nm, between 4 nm and about 5 nm, between about 5 nm and about 7 nm, between about 7 nm and about 10 nm, between about 10 nm and about 15 nm, or any suitable thickness. In some embodiments, reducing the thickness of the etch adjustment layer 230 to less than about 3 nm may reduce the durability of the etch adjustment layer 230 during subsequent etching processes. In some embodiments, increasing the thickness of the etch adjustment layer 230 to more than 5 nm may prolong the etching process and damage one or more patterned layers formed on the etch adjustment layer 230.

[0072] The lower patterned layer 240 is located on the upper surface of the etch adjustment layer 230, and the composition can be a dielectric material. For example, the composition of the lower patterned layer 240 can be silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric material, and / or other suitable insulating materials. In some embodiments, the thickness of the lower patterned layer 240 can be between about 3 nm and about 8 nm. For example, the thickness of the lower patterned layer 240 can be between about 3 nm and about 5 nm, between about 5 nm and about 8 nm, or any suitable thickness. Increasing the thickness of the lower patterned layer 240 can provide more protection to the underlying substrate during the etching process for forming fins. The deposition method of the lower patterned layer 240 can be any suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, high density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, other suitable methods, and / or combinations of the above.

[0073] The upper patterned layer 250 is located above the upper surface of the lower patterned layer 240, and its composition can be a dielectric material or a photoresist material. For example, the composition of the upper patterned layer 250 can be silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric material, and / or any other suitable insulating material. In some embodiments, the compositions of the upper patterned layer 250 and the lower patterned layer 240 can use different materials. For example, the composition of the upper patterned layer 250 is a photoresist material, and the composition of the lower patterned layer 240 can be silicon oxide.

[0074] As Figure 7 shown in some embodiments, step 704 performs a first etching process on the upper patterned layer to form a patterned upper patterned layer. Figure 3 is a cross-sectional view of the semiconductor structure 300 after the patterned upper patterned layer 350 is formed. The method for forming the patterned upper patterned layer 350 can be patterning Figure 2 of the upper patterned layer 250. The patterned upper patterned layer 350 can include a plurality of blocks formed on the upper surface of the lower patterned layer 240.

[0075] In some embodiments, the composition of the upper patterned layer 250 can use a dielectric material. The first etching process 310 of the upper patterned layer 250 can include depositing a photoresist material on the dielectric material, exposing and patterning the photoresist layer to expose a portion of the dielectric material, and etching the exposed portion of the dielectric material. In some embodiments, the first etching process 310 can be a plasma etching process or a wet chemical etching process.

[0076] In some embodiments, the composition of the upper patterning layer 250 may employ a photoresist material. The first etching process 310 of the upper patterning layer 250 may include exposing the photoresist material to a pattern on a photomask, performing a post-exposure bake process, and developing the exposed photoresist material in a solution.

[0077] The patterned upper patterning layer 350 may have different pattern densities across the substrate 202. For example, the patterned upper patterning layer may include a dense region 306 (such as a region with a relatively large pattern density) and a sparse region 308 (such as a region with a relatively small pattern density). In some embodiments, each block of the patterned upper patterning layer 350 may have a width W that is substantially equal to or greater than the critical dimension of the photolithography equipment used for the patterned upper patterning layer 250. For example, the width may be about 3 nm, about 5 nm, about 7 nm, or any other suitable dimension. In the dense region 306, each block of the patterned upper patterning layer 350 may be separated by a consistent distance D1. In some embodiments, the distance D1 in the dense region 306 may vary. In some embodiments, the distance D1 may be between about 5 nm and about 20 nm. In some embodiments, the distance D1 may be between about 5 nm and about 20 nm. For example, the distance D1 may be between about 5 nm and about 7 nm, between about 7 nm and about 14 nm, or between about 14 nm and about 20 nm. For example, the distance D1 may be about 15 nm. In some embodiments, the dense region 306 may be a region of the substrate 202 where one or more structures are separated from each other by a minimum design rule space such as a critical dimension. In some embodiments, the ratio of the width W to the distance D1 may be between about 1 and about 2.

[0078] In some embodiments, each block of the patterned upper patterning layer 350 in the sparse region 308 may also have a width W that is substantially equal to or greater than the critical dimension. In the sparse region 308, the blocks of the patterned upper patterning layer 350 may be spaced apart by different distances. In some embodiments, the blocks of the patterned upper patterning layer 350 may be spaced apart by a substantially same distance such as distance D2, which is greater than distance D1. In some embodiments, the ratio of distance D2 to distance D1 may be between about 1.5 and about 6. In some embodiments, distance D2 may be between about 30 nm and about 200 nm. For example, distance D2 may be between about 30 nm and about 50 nm, between about 50 nm and about 70 nm, between about 70 nm and about 100 nm, between about 100 nm and about 200 nm, or any suitable size. The greater the ratio of distance D2 to D1, the greater the pattern density contrast between the dense region 306 and the sparse region 308. In some embodiments, the ratio of distance D2 to D1 may be greater than about 6, such as about 10, about 20, about 30, or any suitable ratio. The thickness t of the etch adjustment layer 230 may be adjusted according to various parameters. For example, the thickness t may be adjusted according to the ratio of distance D2 to D1. In some embodiments, the greater the thickness t of the etch adjustment layer 230, the higher the ratio of distance D2 to D1 that can be used for the semiconductor device. The greater the thickness of the etch adjustment layer 230, the better the etch adjustment ability of the profile adjustment process that continues for a longer time as required in the sparse region 308. In some embodiments, the sparse region 308 may include a mixed arrangement, where one group of blocks is spaced by the critical dimension and another group of blocks is spaced by a distance greater than the critical dimension. In some embodiments, the ratio of width W to distance D2 may be between about 0.1 and about 0.2. The width W and distances D1 and D2 described herein are only examples and may be changed according to the design.

[0079] As Figure 7 shown in some embodiments, step 706 performs a second etch process on the lower patterning layer to form a patterned lower patterning layer. Figure 4 is a cross-sectional view of the semiconductor structure 400 after the patterned lower patterning layer 440 is formed. The method of forming the patterned lower patterning layer 440 may be to pattern the lower patterning layer 240, as Figure 2 shown.

[0080] Using the blocks in the patterned upper patterned layer 350 as a mask layer, the second etching process 410 can selectively remove portions of the lower patterned layer 240 without etching the patterned upper patterned layer 350. The second etching process 410 can be continued until the underlying etch adjustment layer 230 between the blocks of the patterned lower patterned layer 440 is exposed. In some embodiments, the second etching process 410 can be a plasma etching process that has a greater etching selectivity for the lower patterned layer 240 than for the patterned upper patterned layer 350. For example, the second etching process 410 can be a plasma etching process that applies a bias voltage to the substrate to increase the etching rate in the vertical direction (such as the z-direction). Since the precursor movement patterns in the dense region 306 and the sparse region 308 are different, the removal rates of the lower patterned layer 240 in these regions may be different. As a result, the etching profile of the patterned lower patterned layer 440 in the dense region 306 can be different from the etching profile of the patterned lower patterned layer 440 in the sparse region 308. Taking Figure 4 as an example, the sidewall of the block 440A in the dense region 306 can be substantially perpendicular to the upper surface of the etch adjustment layer 230. In contrast, the angle α of the sidewall of the block 440B in the sparse region 308 with respect to the upper surface of the etch adjustment layer 230 is less than 90°. In some embodiments, the angle α can be greater than about 75° and less than about 90°. Therefore, the block 440B in the sparse region 308 can have a substantially trapezoidal cross-sectional profile.

[0081] As Figure 7 shown in some embodiments, step 708 performs a third etching process on the lower patterned layer to finely adjust the cross-sectional profile of the patterned lower patterned layer until the cross-sectional profiles of each block of the patterned lower patterned layer are substantially the same. Figure 5 is a cross-sectional view of the semiconductor structure 500, which has substantially the same etching profile for the blocks in the sparse region 308 and the dense region 306.

[0082] As Figure 5As shown, a third etching process 510 is performed on the semiconductor structure 500. The third etching process can be a substantially lateral (in the x direction) etching. The etch adjustment layer 230 can enable the third etching process 510 to selectively adjust the etching profile of the blocks in the loose region 308 without vertically etching into the substrate 202. The horizontal etching rate of the third etching process 510 can be substantially greater than the vertical etching rate. For example, the horizontal etching rate in the loose region 308 can be about 10 times to about 50 times the vertical etching rate. The third etching process 510 can be set such that the horizontal etching process 510H in the loose region 308 is substantially greater than any horizontal etching process in the dense region 306. By various methods, a greater horizontal etching rate in the loose region 308 can be achieved. For example, the third etching process 510 can be a plasma etching, and the possibility of its precursor entering a wider opening is higher than that of entering a narrower opening. In some embodiments, the third etching process 510 can be a plasma etching process that does not apply a bias voltage to the substrate to promote lateral (such as in the x direction) etching. In some embodiments, the third etching process 510 can employ a fluorine-based precursor having a chemical composition C x H y F z variation. For example, the third etching process 510 can employ precursors such as fluoroform, fluoromethane, butyne, carbon tetrafluoride, any suitable precursor, and / or a combination of the above. In one embodiment, the third etching process 510 can also employ a chlorine-based precursor such as chlorine gas. In some embodiments, the third etching process 510 can employ a bromine-based precursor such as hydrogen bromide. In some embodiments, the third etching process 510 can employ additives to assist in selectively adjusting the process. For example, the third etching process 510 can employ additives such as hydrogen gas, oxygen gas, carbon dioxide, silicon tetrachloride, any suitable additive, and / or a combination of the above. In some embodiments, the third etching process 510 can also employ any suitable inert gas to assist in adjusting the profile. For example, the inert gas can reduce the precursor gas concentration or increase the ion bombardment to assist in adjusting the profile. In some embodiments, the third etching process 510 can employ inert gases such as helium, argon, any suitable inert gas, and / or a combination of the above.

[0083] During the profile adjustment process, the etch adjustment layer 230 can protect the underlying substrate 202. The material used for the etch adjustment layer 230 is substantially inert relative to the first, second, and third etch processes. Depending on the materials used for the lower patterning layer 240 and the upper patterning layer 250, different materials can be used for the etch adjustment layer 230 to achieve etch selectivity. For example, the compositions of the lower patterning layer 240 and the upper patterning layer 250 can be silicon nitride or silicon oxide respectively, and the composition of the etch adjustment layer 230 can be hafnium oxide. The thickness of the etch adjustment layer 230 can be between about 3 nm and about 5 nm. Increasing the thickness of the etch adjustment layer 230 can provide more protection to the underlying layer. Reducing the thickness of the etch adjustment layer 230 can shorten the etch time when removing a portion of the etch adjustment layer 230 in subsequent etch processes.

[0084] The third etch process 510 can be continued until Figure 4 the cross-sectional profile of the block 440B of the patterned lower patterning layer 440 shown is substantially the same as the cross-sectional profile of the block 440A. In some embodiments, the physical dimensions of the block 440A in the dense region 306 during the third etch process 510 can be maintained substantially the same. As Figure 5 shown, the sidewall of the block 440A in the dense region 306 is substantially perpendicular to the upper surface of the etch adjustment layer 230. The third etch process 510 can be continued until the blocks in the sparse region 308 also have sidewalls that are substantially perpendicular to the upper surface of the etch adjustment layer 230. Thus, the cross-sectional profile of the patterned lower patterning layer 440 in the sparse region 308 can be adjusted to form the adjusted patterned lower patterning layer 540. For example, the angle β between the sidewall of the block 540B of the adjusted patterned lower patterning layer 540 in the sparse region 308 and the upper surface of the etch adjustment layer 230 can be about 90°.

[0085] As Figure 7 shown in some embodiments, step 710 performs a fourth etch process to etch the etch adjustment layer and the substrate to form a fin structure. Figure 6FIG. 600 is a cross-sectional view of a semiconductor structure after forming a fin structure. A fourth etching process 610 can be performed on the semiconductor structure 600, which uses a patterned upper patterned layer 350 and an adjusted patterned lower patterned layer 540 as mask layers. In some embodiments, the physical size of the block 440A in the dense region 306 during the fourth etching process 610 remains substantially the same. The fourth etching process 610 can include a first step of etching the etch adjustment layer 230 exposed between the blocks of the patterned upper patterned layer 350 and the adjusted patterned lower patterned layer 540, and a second step of etching into the substrate 202 to form the fin structure 604. The fourth etching process 610 can be continued until the fin structure 604 reaches a nominal height. As the contour of the blocks of the adjusted patterned lower patterned layer 540 is adjusted to be substantially the same, each fin of the fin structure 604 can have a substantially the same width. Thus, as the size of the semiconductor device continues to shrink, the method described herein can form fin structures with substantially the same width in the dense region 306 and the sparse region 308. In some embodiments, after forming the fin structure 604, the patterned upper patterned layer 350 and the adjusted patterned lower patterned layer 540 can be removed. In some embodiments, the etch adjustment layer 230 can be retained on the fin structure 604. Semiconductor structures such as gates, gate dielectric layers, source / drain structures, contact structures, and Figure 1 any suitable semiconductor structure shown, can be formed on the fin structure 604 and are not detailed herein to simplify the description.

[0086] The methods provided by various embodiments of the present disclosure can form fin structures with consistent lateral dimensions in regions of different pattern densities. The method of forming the fin structure can be to form one or more patterned patterned layers on a substrate, and then perform a plasma etching process. An etch adjustment layer can be deposited between the substrate and the one or more patterned patterned layers. The one or more patterned patterned layers can include one or more hard mask layers. During one or more stages of the plasma etching process, the etch adjustment layer can impede the downward etching progress and enhance the lateral etching progress to achieve substantially the same etching profile in the sparse region (such as a region with a lower pattern density) and the dense region (such as a region with a higher pattern density).

[0087] In some embodiments, the step of forming the lower patterned layer includes depositing a dielectric material.

[0088] In some embodiments, the step of forming the upper patterned layer includes depositing a photoresist material.

[0089] In some embodiments, the above method further includes using the patterned upper patterned layer and the adjusted patterned lower patterned layer as masks to form a plurality of fin structures.

[0090] In some embodiments, the third etching process includes etching the second block in a lateral direction.

[0091] In some embodiments, the second etching process includes making the sidewalls of the first block substantially perpendicular to the upper surface of the dielectric layer.

[0092] In some embodiments, the second etching process further includes making the angle between the sidewalls of the second block and the upper surface of the dielectric layer less than about 90°.

[0093] In some embodiments, the third etching process includes etching the sidewalls of the second block such that the sidewalls of the second block are substantially perpendicular to the upper surface of the dielectric layer.

[0094] In some embodiments, the first block is inert to the third and fourth etching processes.

[0095] In some embodiments, the third etching process includes a plasma etching process and does not apply a bias voltage to the substrate.

[0096] In some embodiments, a method of forming a semiconductor structure includes: forming a semiconductor structure having a substrate, a dielectric layer, a lower patterned layer, and an upper patterned layer. The dielectric layer is on the substrate, the lower patterned layer is on the dielectric layer, and the upper patterned layer is on the lower patterned layer. The method also includes performing a first etching process on the upper patterned layer to form a patterned upper patterned layer. The patterned upper patterned layer includes a first region with a first pattern density and a second region with a second pattern density, and the second pattern density is less than the first pattern density. The method also includes performing a second etching process on the lower patterned layer to form a patterned lower patterned layer. The patterned lower patterned layer includes a plurality of first blocks in the first region and a plurality of second blocks in the second region, and each second block has a trapezoidal cross-sectional profile. The method also includes performing a third etching process on the first and second blocks at a first etching rate and a second etching rate, respectively, to form an adjusted patterned lower patterned layer. The first etching rate is lower than the second etching rate. The method also includes using the patterned upper patterned layer and the adjusted patterned lower patterned layer as masks and performing a fourth etching process on the substrate and the dielectric layer to form a plurality of fins.

[0097] In some embodiments, a method of forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterned layer on the dielectric layer. The method also includes performing a first etching process on the patterned layer to form a first region having a plurality of first blocks with a first pattern density and a second region having a plurality of second blocks with a second pattern density, and the second pattern density is less than the first pattern density. The method also includes performing a second etching process on the second blocks to reduce the width of each second block; and using the first blocks and the second blocks to etch the dielectric layer and the substrate to form a plurality of fin structures.

[0098] In some embodiments, the first etching process has a higher lateral etching rate in the first region than in the second region.

[0099] In some embodiments, the second etching process is continued until the width of each second block is substantially equal to the width of each first block.

[0100] In some embodiments, the second etching process includes a plasma etching process without applying a bias voltage to the substrate.

[0101] In some embodiments, the first blocks are inert to the second etching process.

[0102] In some embodiments, a semiconductor structure includes a substrate and a plurality of fin structures formed on the substrate. The fin structures include a plurality of first fin structures with a first pattern density. The first width of each first fin structure is substantially equal to the critical dimension of a lithographic apparatus. The first separation between adjacent first fin structures is between about 20 nm and about 70 nm. The fin structures also include a plurality of second fin structures with a second pattern density, and the second pattern density is less than the first pattern density. The second width of each second fin structure is substantially equal to the first width. The second separation between adjacent second fin structures is between about 10 nm and about 20 nm. A dielectric layer is formed on the first fin structures and the second fin structures.

[0103] In some embodiments, the thickness of the dielectric layer is between about 3 nm and about 5 nm.

[0104] In some embodiments, the ratio of the first width to the first separation is between about 0.1 and about 0.5.

[0105] In some embodiments, the ratio of the second width to the second separation is between about 1 and about 2.

[0106] In some embodiments, the dielectric layer includes hafnium oxide.

[0107] It should be understood that portions of the embodiments, rather than the abstract, are used to interpret the claims. The abstract may provide one or more but not all exemplary embodiments and thus is not used to limit the claims.

[0108] The features of the above embodiments are conducive to those with ordinary knowledge in the technical field to understand the present disclosure. Those with ordinary knowledge in the technical field should understand that the present disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent substitutions do not depart from the spirit and scope of the present disclosure, and can be changed, replaced, or modified without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Form a semiconductor structure having a substrate, a dielectric layer, a lower patterned layer, and an upper patterned layer, wherein the dielectric layer is on the substrate, the lower patterned layer is on the dielectric layer, and the upper patterned layer is on the lower patterned layer; Perform a first etching process on the upper patterned layer to form a patterned upper patterned layer, wherein the patterned upper patterned layer includes a first region with a first pattern density and a second region with a second pattern density, and the second pattern density is less than the first pattern density; Perform a second etching process on the lower patterned layer to form a patterned lower patterned layer, wherein the patterned lower patterned layer includes a plurality of first blocks in the first region and a plurality of second blocks in the second region, and each of the second blocks has a trapezoidal cross-sectional profile; Perform a third etching process on the first blocks and the second blocks at a first etching rate and a second etching rate respectively to form an adjusted patterned lower patterned layer, wherein the first etching rate is lower than the second etching rate; And Use the patterned upper patterned layer and the adjusted patterned lower patterned layer as masks and perform a fourth etching process on the substrate and the dielectric layer to form a plurality of fins, wherein the plurality of fins includes a plurality of first fin structures with the first pattern density and a plurality of second fin structures with the second pattern density, and a second width of each of the second fin structures is substantially equal to a first width of each of the first fin structures.

2. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the lower patterned layer includes: depositing a dielectric material.

3. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the upper patterned layer includes: depositing a photoresist material.

4. The method for forming a semiconductor structure according to claim 1, further comprising: Use the patterned upper patterned layer and the adjusted patterned lower patterned layer as masks to form a plurality of fin structures.

5. The method for forming a semiconductor structure according to claim 1, wherein, The third etching process includes: etching the second blocks in a lateral direction.

6. The method for forming a semiconductor structure according to claim 1, wherein, The second etching process includes: making sidewalls of the first blocks substantially perpendicular to an upper surface of the dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, wherein, The second etching process further includes: making an angle between sidewalls of the second blocks and the upper surface of the dielectric layer less than 90°.

8. The method for forming a semiconductor structure according to claim 7, wherein, The third etching process includes: etching sidewalls of the second blocks to make sidewalls of the second blocks substantially perpendicular to the upper surface of the dielectric layer.

9. The method for forming a semiconductor structure according to claim 1, wherein, The first blocks are inert to the third etching process and the fourth etching process.

10. The method for forming a semiconductor structure according to claim 1, wherein, The third etching process includes a plasma etching process and does not apply a bias voltage to the substrate.

11. A method for forming a semiconductor structure, comprising: Deposit a dielectric layer on a substrate; Deposit a patterned layer on the dielectric layer; Perform a first etching process on the patterned layer to form a first region containing a plurality of first blocks with a first pattern density and a second region containing a plurality of second blocks with a second pattern density, and the second pattern density is less than the first pattern density, Perform a second etching process on the second blocks to reduce a width of each of the second blocks; And Employ the first block and the second block and etch the dielectric layer and the substrate to form a plurality of fin structures, wherein the plurality of fin structures include a plurality of first fin structures with the first pattern density and a plurality of second fin structures with the second pattern density, and a second width of each of the second fin structures is substantially equal to a first width of each of the first fin structures.

12. The method for forming a semiconductor structure according to claim 11, wherein, The lateral etching rate of the first etching process in the first region is greater than that in the second region.

13. The method for forming a semiconductor structure according to claim 12, wherein, Continue the second etching process until the width of each of the second blocks is substantially equal to the width of each of the first blocks.

14. The method for forming a semiconductor structure according to claim 11, wherein, The second etching process includes a plasma etching process without applying a bias voltage to the substrate.

15. The method for forming a semiconductor structure according to claim 11, wherein,The first block is inert to the second etching process.

16. A semiconductor structure, comprising: A substrate; A plurality of fin structures formed on the substrate and including: A plurality of first fin structures with a first pattern density, wherein a first width of each of the first fin structures is substantially equal to a critical dimension of a lithographic apparatus; And A first separation between adjacent first fin structures is between 20 nm and 70 nm; and A plurality of second fin structures with a second pattern density, and the second pattern density is less than the first pattern density, wherein a second width of each of the second fin structures is substantially equal to the first width; and A second separation between adjacent second fin structures is between 10 nm and 20 nm; and A dielectric layer formed on the first fin structures and the second fin structures.

17. The semiconductor structure according to claim 16, wherein, The thickness of the dielectric layer is between 3 nm and 5 nm.

18. The semiconductor structure according to claim 16, wherein, The ratio of the first width to the first separation is between 0.1 and 0.

5.

19. The semiconductor structure according to claim 16, wherein, The ratio of the second width to the second separation is between 1 and 2.

20. The semiconductor structure according to claim 16, wherein, The dielectric layer includes hafnium oxide.

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