Semiconductor structure and method of forming the same
By employing a hybrid bonding design of microbumps and vias in the semiconductor structure, the challenge of connecting high I/O number chips to fan-out substrates is solved, achieving high yield, low cost, thin packaging, good heat dissipation, and excellent signal integrity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-24
- Publication Date
- 2026-03-20
AI Technical Summary
Existing technologies cannot effectively connect high input/output chips to fan-out substrates, especially in densely packed circuit areas where laser drilling is difficult. Furthermore, the electrical characteristics of solder ball connections are not suitable for high-speed, high-frequency signals, resulting in low yield, high cost, large package thickness, and poor heat dissipation and signal integrity in semiconductor structures.
A hybrid fan-out design is adopted, using microbumps to connect in densely packed areas of the circuitry, and vias to make electrical connections between the first and second circuit layers in sparsely packed areas of the circuitry. The vias are formed by laser drilling and conductive material is filled at the connection points to introduce a 2.3D structure to improve connection reliability.
It improves the yield of semiconductor structures to over 95%, reduces costs, decreases package thickness, and enhances heat dissipation and signal integrity.
Smart Images
Figure CN113644044B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to a semiconductor structure and a method of forming the same. BACKGROUND
[0002] In response to the requirements of high-end products, the size of packages (PKG) is getting larger, the number of input / output (I / O) is getting larger, and the number of substrate layers is also getting larger, so hybrid fan-out substrate technology is used to meet the requirements of high-end products. The fan-out substrate is combined with the fan-out circuit layer and the substrate through the adhesive layer, and the electrical channel between the circuit layer and the substrate is connected through the via. SUMMARY
[0003] In view of the problems in the related art, the purpose of the present application is to provide a semiconductor structure and a method of forming the same to optimize the performance of the semiconductor structure.
[0004] To achieve the above-mentioned purpose, the present application provides a semiconductor structure, comprising: a second circuit layer; a first circuit layer bonded to the top surface of the second circuit layer through a plurality of bumps, the first circuit layer having a circuit dense area and a circuit sparse area; a via passing through the circuit sparse area of the first circuit layer to electrically connect the first circuit layer to the second circuit layer.
[0005] In some embodiments, the plurality of bumps are located below the circuit dense area.
[0006] In some embodiments, the ratio of the volume of the dielectric layer in the circuit sparse area to the volume of the circuit sparse area is greater than 89.83%, and the ratio of the volume of the dielectric layer in the circuit dense area to the volume of the circuit dense area is less than 89.83%.
[0007] In some embodiments, the circuit sparse area is located around the circuit dense area.
[0008] In some embodiments, a plurality of electronic elements are embedded in the second circuit layer, and the electronic elements are electrically connected to the first circuit layer.
[0009] In some embodiments, the electronic elements are wafers.
[0010] In some embodiments, the plurality of electronic elements are located below the circuit dense area.
[0011] In some embodiments, it further comprises: a filling material located between the first circuit layer and the second circuit layer, and the via passes through the filling material.
[0012] In some embodiments, the filling material surrounds the plurality of bumps.
[0013] In some embodiments, the via is a thermal via.
[0014] Embodiments of the present application also provide a method of forming a semiconductor structure, comprising: providing a second wiring layer; bonding a first wiring layer to the second wiring layer through a plurality of bumps, the first wiring layer having a wiring dense region and a wiring sparse region; forming a via through the wiring sparse region of the first wiring layer, the via being electrically connected to the second wiring layer.
[0015] In some embodiments, the second wiring layer has a plurality of pads located at an upper surface of the second wiring layer, the plurality of bumps and the plurality of pads being connected one-to-one.
[0016] In some embodiments, the plurality of bumps are a plurality of solder balls located under the wiring dense region.
[0017] In some embodiments, when the first wiring layer is bonded to the second wiring layer through the plurality of bumps, a filling material is formed between the first wiring layer and the second wiring layer, the filling material surrounding the plurality of bumps.
[0018] In some embodiments, the via also passes through the filling material to be electrically connected to the second wiring layer.
[0019] In some embodiments, the wiring sparse region is located around the wiring dense region.
[0020] In some embodiments, a plurality of electronic components are embedded in the second wiring layer, the plurality of electronic components being located under the wiring dense region.
[0021] In some embodiments, the plurality of electronic components are electrically connected to the wiring dense region through the plurality of bumps.
[0022] In some embodiments, the step of forming the via comprises: forming an opening through the wiring sparse region using a laser drilling process, and filling a conductive material in the opening to form the via.
[0023] In some embodiments, the via is electrically connected to a conductive pillar in the second wiring layer. BRIEF DESCRIPTION OF DRAWINGS
[0024] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that, in accordance with standard practice in the industry, the various elements are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily increased or decreased for clarity of discussion.
[0025] Figures 1A-4 A process of forming a semiconductor structure according to embodiments of the present application is shown. DETAILED DESCRIPTION
[0026] For a better understanding of the spirit of embodiments of the present application, the following further describes the same in combination with some preferred embodiments of the present application.
[0027] Embodiments of the present application will be described in detail below. Throughout the present application, like or similar components and components having like or similar functions are denoted by like reference numerals. The embodiments described herein with reference to the drawings are illustrative in nature, diagrammatic in nature, and are intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
[0028] As used herein, the terms "approximately," "about," "substantially," and "near," are used to describe and account for small variations. When utilized in connection with an event or circumstance, such terms can refer to instances in which the event or circumstance occurs exactly, as well as instances in which the event or circumstance occurs with a minor approximation. For example, when utilized in connection with a numerical value, the terms can refer to a range of variation that is less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be considered "substantially" the same if the difference between the two values is less than or equal to ±10% of the average of the values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).
[0029] In this description, relative terms such as "central," "longitudinal," "lateral," "forward," "rearward," "rightward," "leftward," "internal," "external," "lower," "higher," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description only and do not require that the application be practiced with any particular orientation.
[0030] In addition, quantities, ratios and other numerical values are sometimes presented in a range format. It is to be understood that such range format is used for convenience and brevity and should be construed as having been followed had each numerical value within the range been individually listed. For example, a range of "1 to 6" indicates each numerical value between (and including) the low and high limit of the range. That is, the range of "1 to 6" means "1, 2, 3, 4, 5, and 6."
[0031] Furthermore, for ease of description, "first," "second," "third," and the like can be used herein to distinguish one figure, group of figures, or a subset of these thereof from another figure, group of figures, or subset thereof. "First," "second," "third," and the like are not intended to denote an importance of the respective elements.
[0032] If a wafer with high input / output (I / O) count is used and a fan-out substrate (FOSub) structure is used, laser drilling cannot be performed in the circuit-dense area of the fan-out substrate / circuit layer, mainly because the aperture of laser drilling is too large (e.g., > 50 pm), and there is almost no space for laser drilling in the circuit-dense area; if a 2.3-dimensional (2.3D) structure is used, i.e., the fan-out circuit layer and the substrate are connected by solder balls, the solder balls (about 25 pm to 50 pm in diameter) have worse electrical properties than copper, especially for high-speed high-frequency signals, and the solder balls can affect the integrity of the signals. For high-end products, the diameter of the fan-out micro-bumps is about 25 pm to 50 pm, while the current laser drilling aperture is about 60 pm, so the current laser drilling aperture is about twice the size of the micro-bump. Therefore, the current fan-out substrate / circuit layer technology cannot be used for high-end products.
[0033] The semiconductor structure and the method for forming the same will be described in detail below with reference to the accompanying drawings.
[0034] Referring to Figure 1A The first circuit layer 10 has a circuit-dense area 12 and a circuit-sparse area 14 surrounding the circuit-dense area 12. In embodiments, the first circuit layer 10 is a redistribution layer (RDL). A plurality of bumps 16 is on the lower surface of the first circuit layer 10. In some embodiments, the plurality of bumps 16 is a plurality of solder balls under the circuit-dense area 12.
[0035] Figure 1B is Figure 1A The first circuit layer 10 is shown in plan view in FIG. 1. In some embodiments, the ratio of the volume of the dielectric layer 18 in the circuit-sparse area 14 to the volume of the circuit-sparse area 14 is greater than 89.83%, and the ratio of the volume of the dielectric layer 18 in the circuit-dense area 12 to the volume of the circuit-dense area 12 is less than or equal to 89.83%. That is, the ratio of the volume of the circuit 19 in the circuit-sparse area 14 to the volume of the circuit-sparse area 14 is less than 10.17%, and the ratio of the volume of the circuit 19 in the circuit-dense area 12 to the volume of the circuit-dense area 12 is greater than or equal to 10.17%. In some embodiments, the material of the circuit 19 includes Cu.
[0036] Figure 1CA schematic embodiment of a top view of the line sparse region 14 is shown, without limitation. There is only one via hole with a diameter of 60 μm as a line 19 in a unit area (500*500 μm) of the line sparse region 14. The area of the via hole is 3.14*30 μm*30 μm = 2826 μm 2 , the area of the dielectric layer 18 is 500 μm*500 μm - 2826 μm 2 = 247174 μm 2 , the ratio of the area of the dielectric layer 18 in the line sparse region 14 to the area of the line sparse region 14 is 98.86%.
[0037] Figure 1D A schematic embodiment of a top view of the line dense region 12 is shown, without limitation. There are nine via holes with a diameter of 60 μm as lines 19 in a unit area (500*500 μm) of the line dense region 12. The area of the via holes is 9*3.14*30 μm*30 μm = 25434 μm 2 , the area of the dielectric layer 18 is 500 μm*500 μm - 25434 μm 2 = 224566 μm 2 , the ratio of the area of the dielectric layer 18 in the line dense region 12 to the area of the line dense region 12 is 89.83%.
[0038] Referring to Figure 2 , the second line layer 20 has a plurality of electronic elements 22 embedded therein. In some embodiments, the second line layer 20 is a substrate. In some embodiments, the electronic elements 22 are dies, further, the electronic elements 22 are core dies. The second line layer 20 further has a plurality of conductive pillars 24 surrounding the plurality of electronic elements 22, and a plurality of pads 28 on the plurality of electronic elements 22. In some embodiments, the material of the pads 28 includes Ni or Au. In some embodiments, the material of the conductive pillars 24 includes Cu.
[0039] Referring to Figure 3 , the first line layer 10 is bonded to the second line layer 20 by a plurality of bumps 16, the plurality of bumps 16 and the plurality of pads 28 are one-to-one corresponding, the plurality of bumps 16 are under the line dense region 12, the plurality of electronic elements 22 are under the line dense region 12, the plurality of electronic elements 22 are electrically connected to the line dense region 12 by the plurality of bumps 16. When the first line layer 10 is bonded to the second line layer 20 by the plurality of bumps 16, a filling material 30 is formed between the first line layer 10 and the second line layer 20, the filling material 30 surrounds the plurality of bumps 16. In some embodiments, the filling material 30 is, for example but not limited to, an underfill.
[0040] Referring to Figure 4, forming a via 40 through the line sparse region 14 of the first line layer 10, the via 40 electrically connected to the second line layer 20, the via 40 also passing through the filler material 30 to electrically connect to the second line layer 20, the via 40 electrically connected to the conductive pillar 24 in the second line layer 20. In some embodiments, the step of forming the via 40 includes: using a laser drilling process to form an opening through the line sparse region 14, and filling the opening with a conductive material to form the via 40. In some embodiments, the via 40 is a thermal via to thermally transfer the second line layer 20 to the outside through the via 40 to provide better heat dissipation function to reduce the impact of thermal effects.
[0041] Embodiments of the present application provide a semiconductor structure, comprising: a second line layer 20; a first line layer 10 bonded to the top surface of the second line layer 20 through a plurality of bumps 16, the first line layer 10 having a line dense region 12 and a line sparse region 14; a via 40 passing through the line sparse region 14 of the first line layer 10 to electrically connect the first line layer 10 to the second line layer 20. In some embodiments, the plurality of bumps 16 is located below the line dense region 12. In some embodiments, the ratio of the volume of the dielectric layer in the line sparse region 14 to the volume of the line sparse region 14 is greater than 89.83%, and the ratio of the volume of the dielectric layer in the line dense region 12 to the volume of the line dense region 12 is less than 89.83%. In some embodiments, the line sparse region 14 is located around the line dense region 12. In some embodiments, a plurality of electronic elements 22 is embedded in the second line layer 20, the electronic elements 22 electrically connected to the first line layer 10. In some embodiments, the electronic elements 22 are dies. In some embodiments, the plurality of electronic elements 22 is located below the line dense region 12. In some embodiments, further comprising: a filler material 30 located between the first line layer 10 and the second line layer 10, the via 40 passing through the filler material 30. In some embodiments, the filler material 30 surrounds the plurality of bumps 16. In some embodiments, the via 40 is a thermal via.
[0042] Embodiments of the present application also provide a method of forming a semiconductor structure, comprising: providing a second wiring layer 20; joining a first wiring layer 10 to the second wiring layer 20 through a plurality of bumps 16, the first wiring layer 10 having a wiring dense region 12 and a wiring sparse region 14; forming a via 40 through the wiring sparse region 14 of the first wiring layer 10, the via 40 electrically connected to the second wiring layer 20. In some embodiments, the second wiring layer 20 has a plurality of pads 28 located at an upper surface of the second wiring layer 20, the plurality of bumps 16 and the plurality of pads 28 are connected one-to-one. In some embodiments, the plurality of bumps 16 are a plurality of solder balls 16 located under the wiring dense region 12. In some embodiments, when the first wiring layer 10 is joined to the second wiring layer 20 through the plurality of bumps 16, a filling material 30 is formed between the first wiring layer 10 and the second wiring layer 20, the filling material 30 surrounding the plurality of bumps 16. In some embodiments, the via 40 also passes through the filling material 30 to electrically connect to the second wiring layer 20. In some embodiments, the wiring sparse region 14 is located around the wiring dense region 12. In some embodiments, a plurality of electronic components 22 are embedded in the second wiring layer 20, the plurality of electronic components 22 located under the wiring dense region 12. In some embodiments, the plurality of electronic components 22 are electrically connected to the wiring dense region 12 through the plurality of bumps 16. In some embodiments, the step of forming the via 40 comprises: forming an opening through the wiring sparse region 14 using a laser drilling process, and filling a conductive material in the opening to form the via 40. In some embodiments, the via 40 is electrically connected to a conductive pillar 24 in the second wiring layer 20.
[0043] Embodiments of the present application introduce the concept of fan-out substrate into 2.3 dimensional structures, using bumps and vias to connect the fan-out wiring layer and the substrate / another wiring layer, respectively. Micro bumps are used in the wiring dense region, and vias are used in the wiring sparse region for the connection between the first wiring layer and the second wiring layer. By mixing the fan-out design concept, the yield of the semiconductor structure is improved to more than 95%, and compared with the conventional fan-out substrate, the semiconductor structure of the present application has low cost, high yield, thin packaging thickness, better heat dissipation performance and electrical performance, and better signal integrity.
[0044] The above descriptions are only the preferred embodiments of the present application, and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor structure, characterized in that, include: Second line layer; The first circuit layer is connected to the top surface of the second circuit layer by multiple bumps. The first circuit layer has a dense circuit area and a sparse circuit area. A via, passing through the line de-escalation area of the first line layer, to electrically connect the first line layer to the second line layer. The plurality of bumps are located below the densely packed line area.
2. The semiconductor structure according to claim 1, characterized in that, The ratio of the volume of the dielectric layer in the line sparse area to the volume of the line sparse area is greater than 89.83%, while the ratio of the volume of the dielectric layer in the line dense area to the volume of the line dense area is less than 89.83%.
3. The semiconductor structure according to claim 1, characterized in that, The line evacuation zone is located around the line-dense area.
4. The semiconductor structure according to claim 1, characterized in that, The second circuit layer contains a plurality of electronic components, which are electrically connected to the first circuit layer.
5. The semiconductor structure according to claim 4, characterized in that, The electronic component is a wafer.
6. The semiconductor structure according to claim 4, characterized in that, The plurality of electronic components are located below the densely packed circuit area.
7. The semiconductor structure according to claim 1, characterized in that, Also includes: A filler material is located between the first circuit layer and the second circuit layer, and the via passes through the filler material.
8. The semiconductor structure according to claim 7, characterized in that, The filling material surrounds the plurality of bumps.
9. The semiconductor structure according to claim 1, characterized in that, The through hole is a heat through hole.
Citation Information
Patent Citations
Chip package structure forming method
CN110875194A
Semiconductor device package and method for manufacturing same
CN112054006A