Monolithic semiconductor device and hybrid semiconductor device

Abstract

A single-chip semiconductor device has: a substrate (11); a first nitride semiconductor layer (102) formed on the substrate (11); a second nitride semiconductor layer (103) formed on the first nitride semiconductor layer (102) and having a larger band gap than the first nitride semiconductor layer (102); a first transistor (12) of a HEMT type for power amplification, which is formed on the substrate (11) and is composed of the first nitride semiconductor layer (102) and the second nitride semiconductor layer (103); and a first bias circuit (20) formed on the substrate (11), which applies a bias voltage to a gate of the first transistor (12) and includes a second transistor (21) of a HEMT type disposed outside a propagation path of a high-frequency signal input to the first transistor (12).

Description

Technical Field

[0001] This disclosure relates to monolithic semiconductor devices and hybrid semiconductor devices. Background Technology

[0002] High Electron Mobility Transistors (HEMTs) employing nitride semiconductors such as gallium nitride (GaN) have power densities that are more than 10 times greater than HEMTs employing gallium arsenide-based semiconductors. Therefore, an amplifier circuit is proposed that uses a HEMT employing nitride semiconductors as a high-power device (see, for example, Patent Document 1).

[0003] (Existing technical literature)

[0004] (Patent Documents)

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-23098

[0006] However, in the technology of Patent Document 1, because the manufacturing inhomogeneity (i.e., individual variation) of the threshold voltage of the transistors constituting the amplifier circuit is not taken into account, the drain current (i.e., idle current) flowing into the transistors of the output stage when there is no signal varies in each manufactured amplifier circuit. Due to the idle current, power gain, distortion, efficiency, etc., change. Since it is a trade-off, the idle current needs to be kept within a certain range to obtain the desired performance. The idle current of the amplifier circuit can be adjusted by the gate voltage of the transistors, but due to the individual differences of the transistors, it is difficult to keep the idle current within the allowable error range with a certain gate voltage; therefore, the gate voltage needs to be adjusted for each individual transistor. Summary of the Invention

[0007] Therefore, the purpose of this disclosure is to provide a monolithic semiconductor device and a hybrid semiconductor device that include transistors capable of individually adjusting gate voltages and that can reduce operating time.

[0008] To achieve the above objectives, one embodiment of the present disclosure includes a monolithic semiconductor device comprising: a substrate; a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer, the band gap of the second nitride semiconductor layer being larger than that of the first nitride semiconductor layer; a first transistor formed on the substrate, which is a HEMT-type power amplifier transistor composed of the first nitride semiconductor layer and the second nitride semiconductor layer; and a first bias circuit formed on the substrate, which applies a bias voltage to the gate of the first transistor and includes a second HEMT-type transistor disposed outside the propagation path of a high-frequency signal input to the first transistor.

[0009] Furthermore, in order to achieve the above objectives, one embodiment of the present disclosure relates to a hybrid semiconductor device having the first monolithic semiconductor device described above, and a second monolithic semiconductor device that is different from the first monolithic semiconductor device and has a resistive element, which is used as part of the first bias circuit.

[0010] The monolithic semiconductor device and hybrid semiconductor device disclosed herein enable the gate voltage to be adjusted separately and reduce operating time. Attached Figure Description

[0011] Figure 1 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 1.

[0012] Figure 2 This is a circuit diagram of the hybrid semiconductor device involved in Embodiment 2.

[0013] Figure 3 This is a diagram used to illustrate the first resistor and the second resistor involved in Embodiment 3.

[0014] Figure 4 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 4.

[0015] Figure 5 This is a structural diagram of the first resistor and the second resistor involved in Embodiment 5.

[0016] Figure 6 This is a diagram used to illustrate the first resistor and the second resistor involved in Embodiment 6.

[0017] Figure 7 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 7.

[0018] Figure 8 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 8.

[0019] Figure 9 This is a diagram used to illustrate the enable control circuit involved in Embodiment 9.

[0020] Figure 10 This is a plan view of the hybrid semiconductor device according to Embodiment 10.

[0021] Figure 11 This is a circuit diagram of the noise suppression circuit involved in Implementation Method 11.

[0022] Figure 12 This is a circuit diagram of the noise suppression circuit involved in Implementation Method 12.

[0023] Figure 13 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 13.

[0024] Figure 14 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 14.

[0025] Figure 15 This is a plan view of the monolithic semiconductor device according to Embodiment 15.

[0026] Figure 16 This is a plan view of the monolithic semiconductor device according to Embodiment 16.

[0027] Figure 17 This is a plan view of the monolithic semiconductor device according to Embodiment 17.

[0028] Figure 18 This is a plan view of the monolithic semiconductor device according to Embodiment 18.

[0029] Figure 19 This is a plan view of the monolithic semiconductor device according to Embodiment 19.

[0030] Figure 20 This is a plan view of the hybrid semiconductor device according to Embodiment 20.

[0031] Figure 21 This is a plan view of the hybrid semiconductor device according to Embodiment 21.

[0032] Figure 22 This is a plan view of the hybrid semiconductor device according to Embodiment 22.

[0033] Figure 23 This is a plan view of the hybrid semiconductor device according to Embodiment 23.

[0034] Figure 24 This is a plan view of the hybrid semiconductor device according to Embodiment 24.

[0035] Figure 25 This is a plan view of the hybrid semiconductor device according to Embodiment 25.

[0036] Figure 26 This is a plan view of the hybrid semiconductor device according to Embodiment 26.

[0037] Figure 27 This is a plan view of the hybrid semiconductor device according to Embodiment 27.

[0038] Figure 28 This is a plan view of the hybrid semiconductor device according to Embodiment 28.

[0039] Figure 29 This is a plan view of the hybrid semiconductor device according to Embodiment 29.

[0040] Figure 30 This is a plan view of the monolithic semiconductor device according to Embodiment 30.

[0041] Figure 31 This is a plan view of the monolithic semiconductor device according to embodiment 31.

[0042] Figure 32 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 32.

[0043] Figure 33 This is a diagram used to illustrate the monolithic semiconductor device involved in Embodiment 33. Detailed Implementation

[0044] The nitride semiconductor device according to the embodiments will be specifically described below with reference to the accompanying drawings. Furthermore, the embodiments described below are all specific examples of this disclosure. The numerical values, shapes, materials, constituent elements, arrangement positions of constituent elements, and connection methods shown in the following embodiments are all examples and are not intended to limit the scope of this disclosure. Also, the figures are not strictly illustrative. In the various figures, substantially identical components are assigned the same numbering, and there are instances of omission or simplification of repeated descriptions. The expression "on a substrate" or "on an object" includes two situations as follows: one is the case of contact with the object, and the other is the case of not contacting the object.

[0045] (Implementation Method 1)

[0046] First, the monolithic semiconductor device involved in Embodiment 1 will be described.

[0047] Figure 1 This is a diagram illustrating the monolithic semiconductor device 10 according to Embodiment 1. More specifically, Figure 1 (a) is a circuit diagram of the monolithic semiconductor device 10. Figure 1 (b) shows Figure 1 The cross-sectional structure of the first transistor 12 and the second transistor 21 in (a). Figure 1 In (c), the threshold voltage of the second transistor 21 (i.e., the non-uniformity of the threshold voltage) is used as the horizontal axis, the drain current (dashed line) of the second transistor 21 when there is no signal (i.e., the inactive current) is used as the left vertical axis, and the drain voltage (solid line) of the second transistor 21 is used as the right vertical axis, illustrating the threshold voltage dependence of the second transistor 21. Figure 1 In (d), the threshold voltage of the first transistor 12 (i.e., the non-uniformity of the threshold voltage) is plotted on the horizontal axis, and the drain current (solid line) of the first transistor 12 when there is no signal (i.e., the inactive current) is plotted on the vertical axis, showing the threshold voltage dependence of the first transistor 12. Additionally, in Figure 1 In (d), for reference, the threshold voltage dependence (dashed line) obtained when the gate bias voltage of the first transistor 12 is fixed without the first bias circuit 20 connected is also shown.

[0048] The monolithic semiconductor device 10 is a single-chip semiconductor device, having: a semiconductor substrate 11, a first HEMT-type power amplifier transistor 12 formed on the substrate 11, and a first bias circuit 20, the first bias circuit 20 including a second HEMT-type transistor 21 formed on the substrate 11, and applying a bias voltage to the gate of the first transistor 12.

[0049] The first bias circuit 20 consists of a first resistor 22, a second transistor 21, and a second resistor 23 connected in series. The connection point between the first resistor 22 and the drain of the second transistor 21 corresponds to the bias voltage output node of the first bias circuit 20 and is connected to the gate of the first transistor 12. The second transistor 21 is positioned outside the propagation path of the high-frequency signal input to the first transistor 12. One end of the second resistor 23 is connected to the source of the second transistor 21, and the other end is connected to the gate of the second transistor 21. Furthermore, the propagation path of the high-frequency signal refers to the path through which most of the high-frequency signal input to the gate terminal 13 is propagated.

[0050] Furthermore, the monolithic semiconductor device 10 includes: a gate terminal 13 connected to the gate of the first transistor 12, a drain terminal 14 connected to the drain of the first transistor 12, a first bias terminal 15 connected to one end of the first resistor 22, and a second bias terminal 16 connected to the other end of the second resistor 23. Additionally, the source of the first transistor 12 is grounded. A higher voltage is applied to the first bias terminal 15 than to the second bias terminal 16. Either the first bias terminal 15 or the second bias terminal 16 may also be grounded.

[0051] like Figure 1 As shown in (b), a first nitride semiconductor layer 102 made of GaN or the like is formed on a substrate 11 made of Si or the like. A second nitride semiconductor layer 103 is formed on the first nitride semiconductor layer 102. The second nitride semiconductor layer 103 is made of AlGaN or the like, which has a larger band gap than the first nitride semiconductor layer 102. A drain electrode 110, a gate electrode 111, and a source electrode 112, separated by an insulating layer 106, are formed on the second nitride semiconductor layer 103. The insulating layer 106 is made of SiN or the like. In addition, a two-dimensional electron gas layer 107 is formed at the interface between the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103. Furthermore, an element separation layer 104 is formed on the substrate 11 to insulate the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103 from other circuit elements.

[0052] The gate electrode 111 is in Schottky contact with the second nitride semiconductor layer 103, and the drain electrode 110 and source electrode 112 are in ohmic contact with the two-dimensional electron gas layer 107, which functions as a channel, by applying heat treatment or the like. Thus, the first transistor 12 and the second transistor 21 are HEMT-type transistors formed on the substrate 11 by the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103.

[0053] In the monolithic semiconductor device 10 of this embodiment with such a configuration, when a high-frequency signal is input to the gate terminal 13 while applying appropriate bias voltages to the first bias terminal 15 and the second bias terminal 16 respectively, the first transistor 12 is used as a high-power device to amplify power, and the amplified output signal is output from the drain terminal 14.

[0054] Generally, the drain current of a transistor varies with the difference between the threshold voltage and the gate bias voltage. Even with a fixed gate bias voltage, variations in the threshold voltage due to manufacturing imperfections can cause significant changes in the drain current. For example, as the threshold voltage increases, the drain current decreases.

[0055] The current situation is that unevenness occurs when the threshold voltage of the first transistor 12 is high. In this embodiment, the second transistor 21, which has the same structure as the first transistor 12 and is formed on the same substrate 11, also experiences unevenness when the threshold voltage is high. Since the second transistor 21 and the second resistor 23 constitute a constant current source circuit, when the threshold voltage of the second transistor 21 increases, the drain current (i.e., ineffective current) of the second transistor 21 decreases. Figure 1(c) In this case, the voltage drop between the drain current of the second transistor 21 and the first resistor 22 will decrease. Thus, as the gate voltage of the first transistor 12 increases, the gate bias voltage of the first transistor 12 also increases with the increase in the threshold voltage of the first transistor 12. Accordingly, compared to the case where the gate bias voltage is fixed, the reduction in the drain current (i.e., the ineffective current) of the first transistor 12 is suppressed. Figure 1 (d) Therefore, in this embodiment, the first bias circuit 20, which changes the gate voltage of the first transistor 12 according to the unevenness of the threshold voltage, can keep the invalid current within the allowable error even if it is a constant voltage source, and can reduce the time required to adjust the gate voltage separately.

[0056] (Implementation Method 2)

[0057] Next, the hybrid semiconductor device according to Embodiment 2 will be described.

[0058] Figure 2 This is a circuit diagram of the hybrid semiconductor device 30 according to Embodiment 2. The hybrid semiconductor device 30 basically has the same circuit configuration as the monolithic semiconductor device 10 according to Embodiment 1, except that it is formed as two substrates 11 and 11a (i.e., a semiconductor device constituting two chips).

[0059] The hybrid semiconductor device 30 includes two substrates 11 and 11a, and includes, as circuit elements, a first transistor 12, a second transistor 21, a first resistor 22, a second resistor 23, a gate terminal 13, a drain terminal 14, a first bias terminal 15, and a second bias terminal 16. Among these circuit elements, the first transistor 12, the second transistor 21, the gate terminal 13, and the drain terminal 14 are formed on the substrate 11, while the first resistor 22, the second resistor 23, the first bias terminal 15, and the second bias terminal 16 are formed on the substrate 11a.

[0060] The monolithic semiconductor device formed using substrate 11 can be referred to as the first monolithic semiconductor device 10a, and the monolithic semiconductor device formed using substrate 11a can be referred to as the second monolithic semiconductor device 10b. The hybrid semiconductor device 30 is composed of the first monolithic semiconductor device 10a and the second monolithic semiconductor device 10b. In addition, the first monolithic semiconductor device 10a and the second monolithic semiconductor device 10b are connected by wires or wiring patterns (not shown) formed on the base substrate.

[0061] In addition to the effects of Embodiment 1, the hybrid semiconductor device 30 according to this embodiment, with its circuitry distributed across two substrates 11 and 11a, achieves the following benefits: Signal amplification transistors, such as the first transistor 12, generate heat due to operating current, potentially heating other circuit components. In the hybrid semiconductor device 30 of this embodiment, since the first resistor 22 and the second resistor 23 are formed on a different substrate 11a than the first transistor 12, the effects of heat generation from the first transistor 12 are reduced, ensuring stable operation of the hybrid semiconductor device 30.

[0062] (Implementation Method 3)

[0063] Next, as Embodiment 3, the specific structures of the first resistor 22 and the second resistor 23 of the second monolithic semiconductor device 10b in Embodiment 2 will be described.

[0064] Figure 3 This is a diagram illustrating the first resistor 22 and the second resistor 23 involved in Embodiment 3. More specifically, Figure 3 (a) shows the planar layout of the first resistor 22 and the second resistor 23. Figure 3 (b) shows the drain current of the first transistor 12 according to embodiment 2, which includes the first resistor 22 and the second resistor 23. Figure 3 In (b), the horizontal axis represents the resistance ratio (resistance ratio) of the first resistor 22 divided by the resistance of the second resistor 23, and the vertical axis represents the drain current of the first transistor 12. Additionally, in Figure 3 In (b), in addition to the range of values ​​in this embodiment, the range of values ​​in the general case (in the case of not having the features of a planar layout in this embodiment) is also shown for reference.

[0065] like Figure 3 As shown in (a), in the plan view of the second monolithic semiconductor device 10b, the first resistor 22 and the second resistor 23 are placed adjacent to each other in such a way that there are no other elements between the two resistors, and are configured such that the direction of the current flowing through each resistor element is consistent.

[0066] When the ratio of the resistance values ​​of the first resistor 22 and the second resistor 23 changes, the gate voltage of the first transistor 12 also changes. Although the drain current of the first transistor 12 changes, in this embodiment, as... Figure 3As shown in (a), since the first resistor 22 and the second resistor 23 are formed with the same structure, the same width (the same length in the direction orthogonal to the direction of current flow), and the same current direction, the influence of manufacturing unevenness on the resistance ratio of the first resistor 22 and the second resistor 23 can be reduced. Thus, as... Figure 3 As shown in (b), the unevenness of the drain current of the first transistor 12 in Embodiment 2, which has a first resistor 22 and a second resistor 23 having the same characteristics as described above, is reduced compared to the case where the transistor is constructed without a first resistor and a second resistor having the same characteristics as described above (the normal case).

[0067] (Implementation Method 4)

[0068] Next, the monolithic semiconductor device according to Embodiment 4 will be described.

[0069] Figure 4 This is a diagram illustrating the monolithic semiconductor device 10c according to Embodiment 4. More specifically, Figure 4 (a) shows a circuit diagram of the monolithic semiconductor device 10c. Figure 4 (b) shows the dependence of the resistance value of the second resistor 23 on the noise power (vertical axis) at the gate terminal of the first transistor 12 when noise is applied to the second bias terminal 16. Additionally, in Figure 4 In (b), the noise power (dashed line) under the normal (short circuit) condition when the second resistor 23 is not present is also shown for reference.

[0070] like Figure 4 As shown in (a), the monolithic semiconductor device 10c includes: a substrate 11, a first HEMT-type power amplifier transistor 12 formed on the substrate 11, and a second bias circuit 20a that applies a bias voltage to the gate of the first transistor 12. The second bias circuit 20a includes at least two resistive elements, namely a first resistor 22 and a second resistor 23 connected in series. The bias voltage is a voltage divider generated by the first resistor 22 and the second resistor 23. Furthermore, the first transistor 12 is a transistor composed of a first nitride semiconductor layer 102 and a second nitride semiconductor layer 103, as in Embodiment 1.

[0071] The gate bias voltage of the first transistor 12, which serves as a signal amplification transistor, is applied from the outside, resulting in noise overlap. However, in this embodiment, since the gate terminal of the first transistor 12 is connected to the outside of the substrate 11 via the second resistor 23, the noise from the outside is attenuated by the second resistor 23 before being input to the gate terminal of the first transistor 12. Thus, as... Figure 4As shown in (b), compared to the case where there is no second resistor 23 (short circuit), the impact of external noise can be reduced.

[0072] (Implementation Method 5)

[0073] Next, as embodiment 5, the specific structures of the first resistor 22 and the second resistor 23 of the monolithic semiconductor device 10c involved in embodiment 4 will be described.

[0074] Figure 5 This is a structural diagram of the first resistor 22 and the second resistor 23 involved in Embodiment 5. More specifically, Figure 5 (a) shows the planar layout of the first resistor 22 and the second resistor 23. Figure 5 (b) shows Figure 5 The cross-sectional structure at the VV line in (a).

[0075] A first nitride semiconductor layer 102, composed of GaN or the like, is formed on a substrate 11. A second nitride semiconductor layer 103, composed of AlGaN or the like, with a band gap larger than that of the first nitride semiconductor layer 102, is formed on the first nitride semiconductor layer 102. A first electrode 113 and a second electrode 114, separated by an insulating layer 106, are formed on the second nitride semiconductor layer 103. A two-dimensional electron gas layer 107 is formed near the interface between the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103. Furthermore, a component separation layer 104 is formed on the substrate 11 to insulate the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103 from other circuit components. The first electrode 113 and the second electrode 114 are brought into ohmic contact with the two-dimensional electron gas layer 107, which functions as a resistive element, by applying heat treatment or the like, thus forming two connection terminals for the resistive element.

[0076] The first resistor 22 and the second resistor 23 of this embodiment, having this configuration, have the characteristic that their resistance increases at high temperatures because the two-dimensional electron gas layer functions as a resistive element. Therefore, by using the first resistor 22 and the second resistor 23 of this embodiment as resistive elements (first resistor 22 and second resistor 23) in the second bias circuit 20a of the monolithic semiconductor device 10c of Embodiment 4, resistor integration can be achieved without adding processes, thereby reducing the current flowing into the second bias circuit 20a at high temperatures.

[0077] In addition, although both the first resistor 22 and the second resistor 23 are resistive elements that use two-dimensional electron gas layers as resistive elements, it is also possible that only one of them is a resistive element that uses two-dimensional electron gas layers as resistive elements, while the other can be a conventional resistive element such as a chip resistor.

[0078] (Implementation Method 6)

[0079] Next, as Embodiment 6, the specific structures of the first resistor 22 and the second resistor 23 of the monolithic semiconductor device 10c in Embodiment 4 will be described.

[0080] Figure 6 This is a diagram illustrating the first resistor 22 and the second resistor 23 involved in Embodiment 6. More specifically, Figure 6 (a) shows the planar layout of the first resistor 22 and the second resistor 23. Figure 6 (b) shows the drain current of the first transistor 12 according to embodiment 4, which includes the first resistor 22 and the second resistor 23. Figure 6 In (b), the horizontal axis represents the resistance ratio (resistance ratio) of the first resistor 22 divided by the resistance of the second resistor 23, and the vertical axis represents the drain current of the first transistor 12. Additionally, in Figure 6 In (b), in addition to the range of values ​​in this embodiment, the range of values ​​in the normal case (without the features of the planar layout in this embodiment) is also shown for reference.

[0081] like Figure 6 As shown in (a), in the plan view of the monolithic semiconductor device 10c, the first resistor 22 and the second resistor 23 are placed adjacent to each other in such a way that there are no other elements between the two resistors, and are configured such that the current flowing through each resistor element is in the same direction.

[0082] When the ratio of the resistance values ​​of the first resistor 22 and the second resistor 23 changes, the gate voltage of the first transistor 12 changes, and the drain current of the first transistor 12 also changes. However, in this embodiment, as... Figure 6 As shown in (a), since the first resistor 22 and the second resistor 23 are formed with the same structure, the same width, and the same current direction, the influence of manufacturing non-uniformity on the resistance ratio of the first resistor 22 and the second resistor 23 is reduced. Thus, as... Figure 6 As shown in (b), the unevenness of the drain current of the first transistor 12 in Embodiment 4, which has a first resistor 22 and a second resistor 23 having the same characteristics, is reduced compared to the case where it is constructed without a first resistor and a second resistor having the same characteristics (the normal case).

[0083] (Implementation Method 7)

[0084] Next, the monolithic semiconductor device according to Embodiment 7 will be described.

[0085] Figure 7This is a diagram used to illustrate the monolithic semiconductor device 10d according to Embodiment 7. More specifically, Figure 7 (a) is a circuit diagram of a monolithic semiconductor device 10d. Figure 7 (b) is a characteristic diagram showing the threshold voltage dependence of the second transistor 21. Figure 7 In (b), the threshold voltage of the second transistor 21 (i.e., the non-uniformity of the threshold voltage) is used as the horizontal axis, the drain current (dashed line) (i.e., invalid current) of the second transistor 21 when there is no signal is used as the left vertical axis, and the drain voltage (solid line) of the second transistor 21 is used as the right vertical axis. Figure 7 (c) is a characteristic diagram illustrating the threshold voltage dependence of the first transistor 12. Figure 7 In (c), the threshold voltage of the first transistor 12 (i.e., the non-uniformity of the threshold voltage) is used as the horizontal axis, and the drain current (solid line) of the first transistor 12 when there is no signal (i.e., the inactive current) is used as the vertical axis.

[0086] The monolithic semiconductor device 10d according to this embodiment has essentially the same circuit configuration as the monolithic semiconductor device 10 according to Embodiment 1. The first resistor 22 and the second resistor 23 constituting the first bias circuit 20 are resistive elements that use the two-dimensional electron gas layer described in Embodiment 5 as the resistive element. As shown in the description of Embodiment 6, they are formed with the same structure, the same width, and the same current direction, which is different from Embodiment 1, which does not limit itself to such resistive elements.

[0087] Even in the monolithic semiconductor device 10d according to this embodiment, unevenness occurs when the threshold voltage of the first transistor 12 is high. Similarly, when the threshold voltage of the second transistor 21, which has the same structure as the first transistor 12, is formed on the substrate 11, unevenness also occurs when the threshold voltage is high. Since a constant current source circuit is formed by the second transistor 21 and the second resistor 23, as in Embodiment 1, when the threshold voltage of the second transistor 21 increases, the drain current of the second transistor 21 decreases. Figure 7 (b) Due to the drain current of the second transistor 21 and the first resistor 22, the voltage drop is reduced. Thus, as the gate voltage of the first transistor 12 increases, the gate bias voltage of the first transistor 12 also increases when the threshold voltage of the first transistor 12 increases. Accordingly, compared to the case where the gate bias voltage is fixed, the reduction in the drain current (i.e., the ineffective current) of the first transistor 12 is suppressed. Figure 7 (c) Therefore, in this embodiment, by using the first bias circuit 20 to change the gate voltage of the first transistor 12 according to the unevenness of the threshold voltage, even a constant voltage source can control the invalid current within the allowable error, thus reducing the time required to adjust each gate voltage.

[0088] Furthermore, the first resistor 22 and the second resistor 23 constituting the first bias circuit 20 are resistive elements that function as resistive elements in a two-dimensional electron gas layer. They have the characteristic that the resistance value increases at high temperatures. Therefore, the current flowing into the first bias circuit 20 can be reduced at high temperatures.

[0089] Furthermore, since the first resistor 22 and the second resistor 23 have the same structure, the same current direction, and other characteristics, the unevenness of the drain current of the first transistor 12 can be reduced compared to the case without such the same characteristics.

[0090] (Implementation Method 8)

[0091] Next, the monolithic semiconductor device according to Embodiment 8 will be described.

[0092] Figure 8 This is a diagram used to illustrate the monolithic semiconductor device 10e according to Embodiment 8. More specifically, Figure 8 (a) is a circuit diagram of the monolithic semiconductor device 10e. Figure 8 (b) to (d) show examples of the first to third planar layouts of the monolithic semiconductor device 10e, respectively.

[0093] like Figure 8 As shown in (a), in addition to the configuration of the monolithic semiconductor device 10 according to Embodiment 1, the monolithic semiconductor device 10e also includes a third HEMT-type power amplifier transistor 40 formed on the substrate 11 by a first nitride semiconductor layer 102 and a second nitride semiconductor layer 103, and a third bias circuit 20b that applies a bias voltage to the gate of the third transistor 40.

[0094] The third bias circuit 20b consists of a third resistor 24 and a fourth resistor 25 connected in series. The connection point of the third resistor 24 and the fourth resistor 25 corresponds to the bias voltage output node of the third bias circuit 20b and is connected to the gate of the third transistor 40. Furthermore, the third bias circuit 20b does not include a HEMT-type transistor.

[0095] Furthermore, in addition to the terminals described in Embodiment 1, the monolithic semiconductor device 10e also includes a gate terminal 41 connected to the gate of the third transistor 40, a drain terminal 42 connected to the drain of the third transistor 40, a third bias terminal 43 connected to one end of the third resistor 24, and a fourth bias terminal 44 connected to one end of the fourth resistor 25. A higher voltage is applied to the third bias terminal 43 than to the fourth bias terminal 44. One of the third bias terminal 43 or the fourth bias terminal 44 can be grounded.

[0096] Furthermore, the monolithic semiconductor device 10e constitutes a Doherty amplifier circuit with the first transistor 12 as a carrier amplifier and the third transistor 40 as a peak amplifier. The Doherty amplifier circuit has a configuration in which the output of a Class B or Class AB amplifier, which is called the carrier amplifier, is directly connected to the output of a Class C amplifier, which is called the peak amplifier, which is only at peak power. It is a high-frequency amplifier with good efficiency even in the region where the output level is relatively low.

[0097] exist Figure 8 In the first planar layout example shown in (b), in order to avoid heat and signal interference between the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier), the distance between the two closest gates is set to be more than twice the thickness of the substrate 11 (for example, more than 200 μm if the thickness of the substrate 11 is 100 μm). Furthermore, considering the heat dissipation of the first transistor 12 (carrier amplifier), the shortest distance between the gate of the first transistor 12 (carrier amplifier) ​​and the end of the substrate 11 is set to be more than or equal to the thickness of the substrate 11 (for example, more than 100 μm if the thickness of the substrate 11 is 100 μm). Additionally, in this embodiment, the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier) ​​are comb-shaped (i.e., multi-finger type) transistors.

[0098] The first bias circuit 20 for the first transistor 12 (carrier amplifier) ​​is arranged directly below the first transistor 12 (carrier amplifier) ​​in a planar layout, and the second transistor 21 constituting the first bias circuit 20 is arranged near the center of the first transistor 12 (carrier amplifier) ​​in the direction of the arrangement of the fingers of the first transistor 12 (carrier amplifier).

[0099] With this arrangement, the first transistor 12 (carrier amplifier) ​​and the second transistor 21 constituting the first bias circuit 20 are arranged close to each other, thereby reducing the characteristic difference between the two by aligning their positions in the direction of arrangement of these fingers.

[0100] exist Figure 8In the second planar layout example shown in (c), considering the heat dissipation of the first transistor 12 (carrier amplifier), the shortest distance between the gate of the first transistor 12 (carrier amplifier) ​​and the end of the substrate 11 is set to be greater than or equal to the thickness of the substrate 11 (for example, if the thickness of the substrate 11 is 100 μm, then it is 100 μm or more). Furthermore, the first bias circuit 20 for the first transistor 12 (carrier amplifier) ​​is disposed between the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier), and the second transistor 21 constituting the first bias circuit 20 is disposed in the range extending in the arrangement direction of the fingers of the first transistor 12 (carrier amplifier).

[0101] Furthermore, the gate spacing between the first transistor 12 (carrier amplifier) ​​and the second transistor 21 can be as close as 50 μm or less. Also, the bias resistors (third resistor 24 and fourth resistor 25) used for the third transistor 40 (peak amplifier) ​​can be configured to be as close as 50 μm or less to the second transistor 21.

[0102] By arranging two bias circuits (first bias circuit 20 and third bias circuit 20b) in the space between the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier), the spacing between the closest gates of the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier) ​​can be ensured to be more than twice the thickness of the substrate 11, thereby suppressing thermal and signal interference between the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier).

[0103] With this layout, high area optimization can be achieved because the bias circuit can be used in the space between the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier). Furthermore, by placing the first transistor 12 (carrier amplifier) ​​close to the second transistor 21 constituting the first bias circuit 20 and aligning their positions in a direction orthogonal to the arrangement direction of the fingers, the characteristic difference between the two can be reduced.

[0104] exist Figure 8In the third planar layout example shown in (d), in order to suppress heat and signal interference between the first transistor 12 (carrier amplifier) ​​and the third transistor 40 (peak amplifier), the spacing between the closest gates of the two transistors is set to be more than twice the thickness of the substrate 11 (for example, 200 μm or more if the thickness of the substrate 11 is 100 μm). Furthermore, the first bias circuit 20 for the first transistor 12 (carrier amplifier) ​​is disposed between the end of the first transistor 12 (carrier amplifier) ​​and the substrate 11, and the second transistor 21 constituting the first bias circuit 20 is disposed in the range extending from the arrangement direction of the fingers of the first transistor 12 (carrier amplifier).

[0105] In addition, the gate spacing between the first transistor 12 (carrier amplifier) ​​and the second transistor 21 can be as close as 50 μm or less.

[0106] With this layout, the first bias circuit 20 can be used in the space between the first transistor 12 (carrier amplifier) ​​and the end of the substrate 11, thus achieving high area optimization. Furthermore, by arranging the first transistor 12 (carrier amplifier) ​​and the second transistor 21 constituting the first bias circuit 20 close together and aligning their positions in a direction perpendicular to the arrangement direction of the fingers, the characteristic difference between the two can be reduced.

[0107] Generally, in Doherty amplifier circuits, compared to a carrier amplifier operating normally, a peak amplifier operating only at peak power is subjected to a gate voltage in the low-power region that prevents drain current from flowing in. Therefore, compared to a carrier amplifier, the characteristic variation caused by uneven gate bias voltage is less. In the monolithic semiconductor device 10e according to this embodiment, a first bias circuit 20 including a second transistor 21 is integrated as a bias circuit for the first transistor 12, which constitutes a carrier amplifier that is greatly affected by variations in gate bias voltage. Accordingly, both the difference compensation effect of the carrier amplifier and the chip size of the peak amplifier can be suppressed.

[0108] Furthermore, the description of setting the distance between the closest gates of the first transistor 12 and the third transistor 40 to more than twice the thickness of the substrate 11 is based on the inventors' experience and is not limited thereto.

[0109] (Implementation Method 9)

[0110] Next, as embodiment 9, the enable control circuit that can be attached to the bias circuit in embodiments 1 to 8 will be described.

[0111] Figure 9 This is a diagram illustrating the enable control circuit 45 according to embodiment 9. More specifically, Figure 9(a) is a circuit diagram of the enable control circuit 45. Here is a circuit example of the monolithic semiconductor device 10f after the enable control circuit 45 is added to the monolithic semiconductor device 10c according to embodiment 4. Figure 9 (b) and (c) show Figure 9 The enable control terminal 46 in (a) is dependent on voltage. That is, Figure 9 (b) shows the relationship between the voltage of the enable control terminal 46 (horizontal axis), the voltage of the first bias terminal 15 (vertical axis, dashed line), and the gate voltage of the first transistor 12 (vertical axis, solid line). Additionally, in Figure 9 The threshold voltage (dashed line) of the first transistor 12 is also shown in (b). Figure 9 (c) shows the relationship between the voltage (horizontal axis) of the enable control terminal 46 and the drain current (vertical axis) of the first transistor 12.

[0112] like Figure 9 As shown in (a), an enable control circuit 45 for controlling the active state of the bias voltage applied to the gate of the first transistor 12 is formed on the substrate 11 of the monolithic semiconductor device 10f. Furthermore, an enable control terminal 46, serving as an input terminal of the enable control circuit 45, and an enable output terminal 47, serving as an output terminal of the enable control circuit 45 and connected to the first bias terminal 15, are provided on the substrate 11. Additionally, a voltage lower than the threshold voltage of the first transistor 12 is applied to the second bias terminal 16.

[0113] The enable control circuit 45 is a circuit composed of switching elements, etc., which selectively outputs a voltage lower or higher than the threshold voltage of the first transistor 12 from the enable output terminal 47 according to the change (High voltage / Low voltage) of the voltage applied to the enable control terminal 46 above 0V.

[0114] When a Low voltage is input to the enable control terminal 46 of the enable control circuit 45, a voltage lower than the threshold voltage of the first transistor 12 is output from the enable output terminal 47, and this voltage is applied to the first bias terminal 15. Figure 9 (b)). Thus, since the gate voltage of the first transistor 12 is lower than the threshold voltage of the first transistor 12, it is in an off (cut-off) state where no drain current flows. Figure 9 (c)).

[0115] Additionally, when a High voltage is input to the enable control terminal 46 of the enable control circuit 45, a voltage higher than the threshold voltage of the first transistor 12 is output from the enable output terminal 47, and this voltage is applied to the first bias terminal 15. Figure 9(b) The voltage applied to the first bias terminal 15 is divided by the first resistor 22 and the second resistor 23 of the second bias circuit 20a. Here, the first resistor 22 and the second resistor 23 are set such that the voltage after voltage division is higher than the threshold voltage of the first transistor 12. Thus, the first transistor 12 is in the on (conducting) state, with drain current flowing, because its gate voltage is higher than its threshold voltage. Figure 9 (c)).

[0116] The enable control circuit 45 of this embodiment, having this configuration, can switch the first transistor 12 to an off state or an on state according to a voltage of 0V or higher applied to the enable control terminal 46. Therefore, compared to the case where a fixed power supply voltage is applied to the first bias terminal 15, the drain current can be easily reduced when no amplification operation is performed, thereby reducing power consumption.

[0117] Furthermore, although an example of an enable control circuit 45 being added to the monolithic semiconductor device 10c according to Embodiment 4 has been described in this embodiment, the enable control circuit 45 may also be added to any of the semiconductor devices in Embodiments 1 to 8.

[0118] Alternatively, the enable control circuit 45 can also be formed on a semiconductor substrate or base substrate different from the monolithic semiconductor device 10c, and can be connected to the monolithic semiconductor device 10c by wiring or wires.

[0119] (Implementation Method 10)

[0120] Next, the hybrid semiconductor device according to Embodiment 10 will be described.

[0121] Figure 10 This is a plan view of the hybrid semiconductor device 30a according to Embodiment 10. The hybrid semiconductor device 30a includes a base substrate 32 that is rectangular in shape in the plan view, and a monolithic semiconductor device 10f according to Embodiment 9 that is mounted on the base substrate 32.

[0122] The base substrate 32 is a substrate such as resin or ceramic, and a plurality of terminals 33 are formed on its outer periphery. The substrate terminals 33 include a high-frequency signal input substrate terminal 33a and an enable control input substrate terminal 33b. The high-frequency signal input substrate terminal 33a is disposed on the first outer periphery of the four outer peripheries of the base substrate 32, and is connected to the gate terminal 13 of the monolithic semiconductor device 10f via wiring 34a and wires 35a on the base substrate 32. The enable control input substrate terminal 33b is disposed on the substrate terminal position of the second outer periphery of the four outer peripheries of the base substrate 32, but not at the position where the corner substrate terminal is disposed. The second outer periphery is the outer periphery where the high-frequency signal input substrate terminal 33a is not disposed. The enable control input substrate terminal 33b is connected to the enable control terminal 46 of the monolithic semiconductor device 10f via wiring 34b and wires 35b on the base substrate 32.

[0123] With this arrangement of the hybrid semiconductor device 30a according to this embodiment, interference between the signal input to the high-frequency signal input substrate terminal 33a and the signal input to the enable control input substrate terminal 33b can be reduced, thereby suppressing malfunctions caused by the input signal input to the high-frequency signal input substrate terminal 33a leaking to the enable control terminal 46, or the degradation of the input signal caused by noise input to the enable control terminal 46 being input to the high-frequency signal input substrate terminal 33a.

[0124] (Implementation Method 11)

[0125] Next, as Embodiment 11, a circuit applicable to a semiconductor device having a bias circuit including at least two transistors in the semiconductor devices described in Embodiments 1 to 10 above will be described. This circuit has the effect of suppressing noise mixed in from the bias terminal and reducing RF (radio frequency) leakage to the bias circuit.

[0126] Figure 11 This is a circuit diagram of the noise suppression circuit according to Embodiment 11. Here is a circuit example in which a fifth resistor 26 is added as a noise suppression circuit to the first bias circuit 20 according to Embodiment 1. The fifth resistor 26 is a resistive element connected between the bias voltage output node of the first bias circuit 20 (i.e., the connection point between the first resistor 22 and the drain terminal of the second transistor 21) and the gate of the first transistor 12.

[0127] When noise is superimposed on the second bias terminal 16, the noise is applied to the gate terminal 13 of the first transistor 12 via the capacitance between the gate and drain of the second transistor 21, and is amplified and output by the first transistor 12. In this embodiment, since the fifth resistor 26 is connected between the bias voltage output node of the first bias circuit 20 and the gate of the first transistor 12, the noise mixed in from the second bias terminal 16 is attenuated by the fifth resistor 26, thus reducing the amount of noise input to the gate terminal 13 of the first transistor 12.

[0128] (Implementation Method 12)

[0129] Next, as embodiment 12, a circuit applicable to a semiconductor device having a bias circuit including at least two transistors in the semiconductor device described in embodiments 1 to 10 above will be described. This circuit is another circuit capable of suppressing noise mixed in from the bias terminal.

[0130] Figure 12 This is a circuit diagram of the noise suppression circuit according to Embodiment 12. An example circuit is shown here in which a sixth resistor 27 is added as a noise suppression circuit to the first bias circuit 20 according to Embodiment 1. The sixth resistor 27 is a connection resistor element connected between the second bias terminal 16, which supplies power to the first bias circuit 20, and the gate of the second transistor 21.

[0131] When noise is superimposed on the second bias terminal 16, the noise is applied to the gate terminal 13 of the first transistor 12 via the capacitance between the gate and drain of the second transistor 21, and is amplified and output by the first transistor 12. In this embodiment, since a sixth resistor 27 is connected between the second bias terminal 16 and the gate of the second transistor 21, the noise mixed in from the second bias terminal 16 is attenuated by the sixth resistor 27, thus reducing the amount of noise input to the gate terminal 13 of the first transistor 12.

[0132] (Implementation Method 13)

[0133] Next, the monolithic semiconductor device according to Embodiment 13 will be described.

[0134] Figure 13 This is a diagram used to illustrate the monolithic semiconductor device 10g according to Embodiment 13. More specifically, Figure 13 (a) is a planar layout diagram of the monolithic semiconductor device 10g. Figure 13(b) is a circuit diagram of the monolithic semiconductor device 10g used in the Doherty amplifier. The monolithic semiconductor device 10g includes: a substrate 11, a first HEMT-type power amplifier transistor 50 formed on the substrate 11, and a second HEMT-type power amplifier transistor 60 formed on the substrate 11 with a conduction current capability greater than that of the first transistor 50. The monolithic semiconductor device 10g is used in a Doherty amplifier circuit where the first transistor 50 acts as a carrier amplifier and the second transistor 60 acts as a peak amplifier.

[0135] Furthermore, the cross-sectional structures of the first transistor 50 and the second transistor 60 are similar to... Figure 1 The structure shown in (b) is the same. Specifically, a first nitride semiconductor layer 102 made of GaN or the like is formed on the substrate 11; a second nitride semiconductor layer 103 made of AlGaN or the like, with a larger band gap than the first nitride semiconductor layer 102, is formed on the first nitride semiconductor layer 102; a drain electrode 110, a gate electrode 111, and a source electrode 112, isolated by an insulating layer 106 made of SiN or the like, are formed on the second nitride semiconductor layer 103; and a two-dimensional electron gas layer 107 is formed at the interface between the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103. The first transistor 50 and the second transistor 60 are HEMT-type transistors formed on the substrate 11, consisting of the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103.

[0136] like Figure 13 As shown in (a), the first transistor 50 is composed of four parallel-connected unit transistors formed in a continuous first active region 51, having four gate electrodes 52, two drain electrodes 53, and three source electrodes 54. The second transistor 60 is composed of six parallel-connected unit transistors formed in a continuous second active region 61, having six gate electrodes 62, three drain electrodes 63, and four source electrodes 64.

[0137] Here, the monolithic semiconductor device 10g is configured such that the gate electrode width of each gate electrode of the first transistor 50 is set to a first unit gate electrode width (200 μm in this case), the gate electrode width of each gate electrode of the second transistor 60 is set to a second unit gate electrode width (200 μm in this case), the number of gate electrodes of the first transistor 50 is set to a first number of gate electrodes (4 in this case), and the number of gate electrodes of the second transistor 60 is set to a second number of gate electrodes (6 in this case), such that the value of the second unit gate electrode width multiplied by the second number of gate electrodes (1200) is greater than the value of the first unit gate electrode width multiplied by the first number of gate electrodes (800). With this configuration, the conduction current capability of the second transistor 60 is greater than that of the first transistor 50.

[0138] Given that the peak power to average power ratio (PAPR) of the modulated signal in a Doherty amplifier circuit is equal to the on-current capability of the carrier amplifier and the peak amplifier in the Doherty amplifier circuit, it can be known that the highest efficiency can be obtained when PAPR = 6dB.

[0139] Since the conduction current capability of the second transistor 60, which is a peak amplifier, is greater than that of the first transistor 50, which is a carrier amplifier, the Doherty amplifier circuit with a higher PAPR than 6dB can be realized by amplifying a signal.

[0140] The first transistor 50 (carrier amplifier) ​​operates by applying a higher gate voltage than the second transistor 60 (peak amplifier). Normally, both the first transistor 50 (carrier amplifier) ​​and the second transistor 60 (peak amplifier) ​​require gate voltage adjustments. However, in this embodiment, since both are configured on the same substrate 11, their threshold voltages are approximately equal. Figure 13 As shown in (b), for example, by connecting the gate terminals of the two transistors via a level shifting circuit 58, the gate voltages of the first transistor 50 (carrier amplifier) ​​and the second transistor 60 (peak amplifier) ​​can be determined by performing a single gate voltage adjustment, thereby reducing the gate voltage adjustment time by half.

[0141] (Implementation Method 14)

[0142] Next, as Embodiment 14, a monolithic semiconductor device in Embodiment 13 in which the conduction current capability of the second transistor is more than 1.5 times and less than 1.7 times that of the first transistor will be described.

[0143] Figure 14 This is a diagram used to illustrate the monolithic semiconductor device 10h according to Embodiment 14. More specifically, Figure 14 (a) is a planar layout diagram of the monolithic semiconductor device 10h. Figure 14 (b) shows the ratio of the size of the peak amplifier (second transistor 60a) to the size of the carrier amplifier (first transistor 50a) of the monolithic semiconductor device 10h (PA size / CA size, horizontal axis), and the relationship between thermal resistance (solid line, left vertical axis) and efficiency (dashed line, right vertical axis). Figure 14 Figure (c) shows the relationship between the thermal resistance (horizontal axis) and efficiency (vertical axis) of the monolithic semiconductor device over 10 hours. Here, the dimensions of the peak amplifier and the carrier amplifier are the product of the width of each unit gate electrode and the number of gate electrodes.

[0144] The monolithic semiconductor device 10h involved in this embodiment is the same as that in embodiment 13, and is used in a Doherty amplifier circuit that uses the first transistor 50a as a carrier amplifier and the second transistor 60a as a peak amplifier.

[0145] like Figure 14 As shown in (a), the first transistor 50a is composed of four parallel-connected unit transistors formed within a continuous first active region 51a, having four gate electrodes 52a, two drain electrodes 53a, and three source electrodes 54a. The second transistor 60a is composed of six parallel-connected unit transistors formed within a continuous second active region 61a, having six gate electrodes 62a, three drain electrodes 63a, and four source electrodes 64a.

[0146] Here, the width of each gate electrode of the first transistor 50a, i.e., the width of the first unit gate electrode, is 200 μm, and the width of each gate electrode of the second transistor 60a, i.e., the width of the second unit gate electrode, is 215 μm. Therefore, in this embodiment, the monolithic semiconductor device 10h is configured such that the value (1290) of the second unit gate electrode width (215 μm) multiplied by the number of second gate electrodes (6) is more than 1.5 times and less than 1.7 times the value (800) of the first unit gate electrode width (200 μm) multiplied by the number of first gate electrodes (4). With this configuration, the conduction current capability of the second transistor 60a is more than 1.5 times and less than 1.7 times that of the first transistor 50.

[0147] Generally speaking, high-frequency amplifier circuits can achieve high efficiency when operating at power close to saturation. In the Doherty amplifier circuit, if the size of the carrier amplifier (transistor 50a) is reduced, the carrier amplifier can operate at power close to saturation and achieve high efficiency. Figure 14 (b) dashed line). However, reducing the size of the carrier amplifier leads to a decrease in thermal resistance ( Figure 14 (b) solid line). Generally speaking, in Doherty amplifier circuits such as Figure 14 As shown in (b), a certain efficiency and a certain thermal resistance are required.

[0148] In this embodiment, since the PA size / CA size is 1.5 to 1.7 (approximately 1.6), it is possible to achieve efficiency exceeding the required value and thermal resistance below the required value. Figure 14 (c)).

[0149] (Implementation Method 15)

[0150] Next, as Embodiment 15, based on Embodiment 13, a monolithic semiconductor device in which the area of ​​the first active region of the first transistor formed in the plan view of the substrate is larger than the area of ​​the second active region of the second transistor formed will be described.

[0151] Figure 15 This is a plan view of the monolithic semiconductor device 10i according to Embodiment 15. The monolithic semiconductor device 10i according to this embodiment is the same as that in Embodiment 13, and is used in a Doherty amplifier circuit that uses the first transistor 50b as a carrier amplifier and the second transistor 60b as a peak amplifier.

[0152] like Figure 15 As shown, the first transistor 50b consists of four parallel-connected unit transistors formed within a continuous first active region 51b, having four gate electrodes 52b, two drain electrodes 53b, and three source electrodes 54b. The second transistor 60b consists of six parallel-connected unit transistors formed within a continuous second active region 61b, having six gate electrodes 62b, three drain electrodes 63b, and four source electrodes 64b.

[0153] Here, the first unit gate electrode width of each gate electrode of the first transistor 50b is 200 μm, and the second unit gate electrode width of each gate electrode of the second transistor 60b is 200 μm. Furthermore, the length of the first active region 51b is 600 μm, and the length of the second active region 61b is 500 μm. Therefore, in this embodiment, in the plan view of the substrate 11, the area of ​​the first active region 51b is 120000 μm. 2 The area of ​​the second active region 61b is 100,000 μm larger than that of the second active region 61b. 2 )big.

[0154] In the Doherty amplifier circuit, the carrier amplifier (first transistor 50b) operating normally generates more heat than the peak amplifier (second transistor 60b) operating only at the peak power of the signal. In the monolithic semiconductor device 10i according to this embodiment, since the area of ​​the first active region 51b where the first transistor 50b is formed is larger than the area of ​​the second active region 61b where the second transistor 60b is formed, the heat source of the carrier amplifier (first transistor 50b), which generates more heat, can be distributed, thereby enabling the carrier amplifier (first transistor 50b) to operate at a lower temperature.

[0155] (Implementation Method 16)

[0156] Next, as Embodiment 16, based on Embodiment 13, a monolithic semiconductor device in which the area of ​​the first active region divided by the conduction current capability of the first transistor in the plan view of the substrate is larger than the area of ​​the second active region divided by the conduction current capability of the second transistor.

[0157] Figure 16 This is a plan view of the monolithic semiconductor device 10j according to Embodiment 16. The monolithic semiconductor device 10j according to this embodiment is the same as that in Embodiment 13, and is used in a Doherty amplifier circuit in which the first transistor 50c is used as a carrier amplifier and the second transistor 60c is used as a peak amplifier.

[0158] like Figure 16 As shown, the first transistor 50c consists of four parallel-connected unit transistors formed within a continuous first active region 51c, having four gate electrodes 52c, two drain electrodes 53c, and three source electrodes 54c. The second transistor 60c consists of six parallel-connected unit transistors formed within a continuous second active region 61c, having six gate electrodes 62c, three drain electrodes 63c, and four source electrodes 64c.

[0159] Here, the first unit gate electrode width of each gate electrode of the first transistor 50c is 200 μm, and the second unit gate electrode width of each gate electrode of the second transistor 60c is 200 μm. Furthermore, the length of the first active region 51c is 400 μm, and the length of the second active region 61c is 500 μm. Therefore, in the plan view of the substrate 11 in this embodiment, the area of ​​the first active region 51c is 80000 μm. 2 The area of ​​the second active region 61c is 100,000 μm. 2 .

[0160] Furthermore, since the conduction current capability of a transistor is proportional to the value obtained by multiplying the unit gate electrode width and the number of gate electrodes, the ratio of the conduction current capability of the first transistor 50c to that of the second transistor 60c is 2:3.

[0161] Therefore, in the plan view of the substrate 11 in this embodiment, the area of ​​the first active region 51c is 80000 μm. 2 The value (40000) obtained by dividing the conduction current capability (2) of the first transistor 50c is greater than the area (100000μm) of the second active region 61c. 2 The value obtained by dividing by the conduction current capability of the second transistor 60c (3) is large (approximately 33333).

[0162] This feature allows the heat sources of the carrier amplifier (first transistor 50c), which generates more heat, to be distributed, thereby enabling the carrier amplifier (first transistor 50c) to operate at a lower temperature.

[0163] (Implementation Method 17)

[0164] Next, as embodiment 17, a monolithic semiconductor device with characteristics in the source region constituting the first transistor in embodiment 13 will be described.

[0165] Figure 17 This is a planar layout diagram of the monolithic semiconductor device 10k according to Embodiment 17. Furthermore, the planar layout of the characteristic first transistor 50d is shown in this diagram, while the illustration of the second transistor is omitted. More specifically, Figure 17 (a) shows only the planar layout of the first transistor 50d. Figure 17 (b) shows the planar layout of the first transistor 50d, including the source wiring.

[0166] like Figure 17 As shown in (a), the first transistor 50d is composed of four parallel-connected unit transistors formed in a continuous first active region 51d, and has: four gate electrodes 52d formed in the gate region of the first active region 51d, two drain electrodes 53d formed in the drain region of the first active region 51d, and three source electrodes 54d formed in the source region of the first active region 51d.

[0167] The central source electrode 54d of the three source electrodes 54d is formed in a shared source region 55, which is shared by two adjacent unit transistors. The length of the shared source region 55 is 50 μm. The lengths of the other source regions, including the source region formed closest to the outer periphery of the substrate 11, are 20 μm. Furthermore, two drain electrodes 53d are formed in a shared drain region 56, which is shared by two adjacent unit transistors.

[0168] In the monolithic semiconductor device 10k of this embodiment having this configuration, in the first direction in which the source regions, gate regions and drain regions of the plurality of unit transistors constituting the first transistor 50d are arranged, the length of the source region (20 μm) and the length of half the length of the common source region 55 (25 μm) are not fixed (i.e. different).

[0169] Furthermore, in the first direction in which the source region, gate region and drain region of the plurality of unit transistors constituting the first transistor 50d are arranged, the length (20 μm) of the source region formed closest to the outer periphery of the substrate 11 is shorter than half the length (25 μm) of the common source region 55.

[0170] This planar layout reduces the size of the source region at the ends, allowing for heat dissipation through the freed-up space. It also enables the placement of solder pads, achieving both good heat dissipation and minimizing chip size increases.

[0171] And, as Figure 17 As shown in the planar layout of (b), since the source electrode 54d is grounded, it is connected to the source wiring 54d1 connected to the back side of the substrate 11 through the via 54d2. Furthermore, in this embodiment, although the vias 54d2 are arranged in two rows to reduce source inductance, the vias at both ends can also be arranged in a single row since the current in the adjacent source region is halved. With this arrangement, components such as solder pads can be placed directly below the row of vias 54d2 at both ends, thereby achieving high area optimization.

[0172] (Implementation Method 18)

[0173] Next, as Embodiment 18, based on Embodiment 13, a monolithic semiconductor device having features in the position of the gate region constituting the first transistor will be described.

[0174] Figure 18 This is a plan view of the monolithic semiconductor device 10l according to Embodiment 18. Furthermore, in this figure, only the plan view of the first transistor 50e, which has distinctive features, is shown; the illustration of the second transistor is omitted.

[0175] like Figure 18 As shown, the first transistor 50e is composed of four parallel-connected unit transistors formed in a continuous first active region 51e, and has: four gate electrodes 52e formed in the gate region of the first active region 51e, two drain electrodes 53e formed in the drain region of the first active region 51e, and three source electrodes 54e formed in the source region of the first active region 51e.

[0176] The central source electrode 54e of the three source electrodes 54e is formed in a shared source region 55a, which is shared by two adjacent unit transistors. The length of the shared source region 55a is 50 μm. The lengths of the other source regions, including the source region formed closest to the outer periphery of the substrate 11, are 20 μm. Furthermore, two drain electrodes 53e are formed in a shared drain region 56a, which is shared by two adjacent unit transistors.

[0177] Here, in the first direction in which the source region, gate region and drain region of the plurality of unit transistors constituting the first transistor 50e are arranged, the length from the outer periphery of the substrate 11 to the gate region formed closest to the outer periphery is 70 μm, which is longer than half the length of the common source region 55a (25 μm).

[0178] This planar layout reduces the source region at the ends, freeing up space for heat dissipation and allowing for features such as solder pads. This achieves both good heat dissipation and prevents chip size from increasing.

[0179] (Implementation Method 19)

[0180] Next, as Embodiment 19, based on Embodiment 13, a monolithic semiconductor device having characteristics of a common source region and a common drain region constituting the first transistor will be described.

[0181] Figure 19 This is a planar layout diagram of the monolithic semiconductor device 10m according to Embodiment 19. Furthermore, in this diagram, only the planar layout of the characteristic first transistor 50f is shown; the illustration of the second transistor is omitted.

[0182] like Figure 19 As shown, the first transistor 50f is composed of four parallel-connected unit transistors formed in a continuous first active region 51f, and has: four gate electrodes 52f formed in the gate region in the first active region 51f, two drain electrodes 53f formed in the drain region in the first active region 51f, and three source electrodes 54f formed in the source region in the first active region 51f.

[0183] The central source electrode 54f of the three source electrodes 54f is formed in a shared source region 55b, which is shared by two adjacent unit transistors. The length of the shared source region 55b is 100 μm. Furthermore, two drain electrodes 53f are formed in a shared drain region 56b, which is shared by two adjacent unit transistors. The length of the shared drain region 56b is 20 μm. Thus, in the first direction of the arrangement of the source, gate, and drain regions of the multiple unit transistors constituting the first transistor 50f, the length of the shared source region 55b (100 μm) is longer than the length of the shared drain region 56b (20 μm).

[0184] Generally speaking, when the source of a transistor and the back of the substrate are grounded, the capacitance formed by the drain region and the back of the substrate becomes equivalent to the capacitance between the drain and source of the transistor. Therefore, the increase in the capacitance between the drain and source will lead to a decrease in the efficiency of the amplifier circuit.

[0185] In the monolithic semiconductor device 10m described in this embodiment, since the length of the common source region 55b is longer than the length of the common drain region 56b, the heat-generating area can be expanded without increasing the capacitance between the drain and source, thereby reducing the thermal resistance.

[0186] (Implementation Method 20)

[0187] Next, the hybrid semiconductor device according to Embodiment 20 will be described.

[0188] Figure 20 This is a plan view of the hybrid semiconductor device 30b according to Embodiment 20. The hybrid semiconductor device 30b includes: a base substrate 32a; a first monolithic semiconductor device 70 mounted on the base substrate 32a, which is a monolithic semiconductor device 10g constituting the Doherty amplifier circuit according to Embodiment 13; an input matching circuit region 71 for the first monolithic semiconductor device 70; a second monolithic semiconductor device 72; an output matching circuit region 73 for the second monolithic semiconductor device 72; and a coupler 74 that distributes the output signal from the output matching circuit region 73 into a signal for a first transistor 50 and a signal for a second transistor 60, and outputs it to the input matching circuit region 71. The second monolithic semiconductor device 72 has an amplifier circuit that amplifies high-frequency signals and inputs them to the first monolithic semiconductor device 70.

[0189] In the hybrid semiconductor device 30b of this embodiment with such a configuration, since the Doherty amplifier circuit and its preceding amplifier circuit are composed of different monolithic semiconductor devices, the output matching circuit of the second monolithic semiconductor device 72, the coupler 74, and the input matching circuit of the first monolithic semiconductor device 70 can be provided between them, thereby enabling the implementation of a multi-stage Doherty amplifier circuit with a small area.

[0190] (Implementation Method 21)

[0191] Next, the hybrid semiconductor device according to Embodiment 21 will be described.

[0192] Figure 21 This is a plan view of the hybrid semiconductor device 30c according to Embodiment 21. In addition to the hybrid semiconductor device 30b according to Embodiment 20, the hybrid semiconductor device 30c also includes a third monolithic semiconductor device 75. The third monolithic semiconductor device 75 has a first bias circuit that applies a bias voltage to the gate of the first transistor 50 of the first monolithic semiconductor device 70 and the gate of the transistor of the second monolithic semiconductor device 72. The first bias circuit is, for example, the bias circuit in Embodiment 1 or Embodiment 4.

[0193] In the hybrid semiconductor device 30c of this embodiment with such a configuration, by having a bias circuit within the hybrid semiconductor device 30c, a bias circuit outside the hybrid semiconductor device 30c is not required, thus enabling the amplification circuit to be implemented in a small area.

[0194] (Implementation Method 22)

[0195] Next, the hybrid semiconductor device according to Embodiment 22 will be described.

[0196] Figure 22 This is a plan view of the hybrid semiconductor device 30d according to Embodiment 22. The hybrid semiconductor device 30d has basically the same configuration as the hybrid semiconductor device 30b according to Embodiment 20. However, in this embodiment, the second monolithic semiconductor device 72a constituting the hybrid semiconductor device 30d is composed of a multi-stage amplifier consisting of multiple cascaded amplifier circuits.

[0197] The hybrid semiconductor device 30d of this embodiment, having this configuration, has a high gain because it has a second monolithic semiconductor device 72a configured as a multi-stage amplifier. This allows it to reduce the strength of the input signal to the hybrid semiconductor device 30d, thereby enabling highly efficient amplification.

[0198] (Implementation Method 23)

[0199] Next, the hybrid semiconductor device according to Embodiment 23 will be described.

[0200] Figure 23 This is a plan view of the hybrid semiconductor device 30e according to Embodiment 23. The hybrid semiconductor device 30e has basically the same configuration as the hybrid semiconductor device 30b according to Embodiment 20. However, in this embodiment, the second monolithic semiconductor device 72b constituting the hybrid semiconductor device 30e is composed of a single-stage amplifier.

[0201] The hybrid semiconductor device 30e of this embodiment, having this configuration, has a second monolithic semiconductor device 72b configured as a first-stage amplifier. Therefore, the area of ​​the second monolithic semiconductor device 72b can be reduced, thereby enabling the realization of a high-gain amplifier circuit with a small area.

[0202] (Implementation Method 24)

[0203] Next, the hybrid semiconductor device according to Embodiment 24 will be described.

[0204] Figure 24This is a plan view of the hybrid semiconductor device 30f according to Embodiment 24. The hybrid semiconductor device 30f has essentially the same configuration as the hybrid semiconductor device 30e according to Embodiment 23. However, in this embodiment, the first monolithic semiconductor device 70 and the second monolithic semiconductor device 72b constituting the hybrid semiconductor device 30f are arranged on the base substrate 32a in such a way that the transmission directions of their high-frequency signals are not parallel to each other in the plan view (in this case, orthogonal).

[0205] In this embodiment, the coupler 74a is formed by a wiring pattern on the base substrate 32a. That is, the coupler 74a is disposed between the amplifier circuit of the second monolithic semiconductor device 72b, the first transistor 50 of the first monolithic semiconductor device 70, and the second transistor 60 through the wiring pattern. The high-frequency output signal from the amplifier circuit of the second monolithic semiconductor device 72b is distributed and sent to the respective gates of the first transistor 50 and the second transistor 60.

[0206] In the hybrid semiconductor device 30f of this embodiment with such a configuration, since the first monolithic semiconductor device 70 and the second monolithic semiconductor device 72b are configured such that their respective high-frequency signal transmission directions are not parallel, it is not necessary to configure the output matching circuit region 73 for the second monolithic semiconductor device 72b between the first monolithic semiconductor device 70 and the second monolithic semiconductor device 72b, thereby enabling the Doherty amplifier circuit to be implemented in a small area.

[0207] Furthermore, since the coupler 74a is formed by the wiring pattern on the base substrate 32a, no special components are required for the coupler 74a, thus enabling the Doherty amplifier circuit to be implemented at low cost.

[0208] (Implementation Method 25)

[0209] Next, the hybrid semiconductor device according to Embodiment 25 will be described.

[0210] Figure 25 This is a plan view of the hybrid semiconductor device 30g according to Embodiment 25. The hybrid semiconductor device 30g has essentially the same configuration as the hybrid semiconductor device 30e according to Embodiment 23. However, in this embodiment, the first monolithic semiconductor device 70a constituting the hybrid semiconductor device 30g, in addition to having a first transistor 50 and a second transistor 60, also has a first preamplifier 150 as a preamplifier of the first transistor 50 and a second preamplifier 160 as a preamplifier of the second transistor 60.

[0211] The first monolithic semiconductor device 70a functions as a Doherty amplifier circuit, similar to embodiment 23. Here, the multistage amplifier combining the first preamplifier 150 and the first transistor 50 functions as the carrier amplifier of the Doherty amplifier circuit, and the multistage amplifier combining the second preamplifier 160 and the second transistor 60 functions as the peak amplifier of the Doherty amplifier circuit.

[0212] In the hybrid semiconductor device 30g of this embodiment with such a configuration, since the first monolithic semiconductor device 70a is configured as a multi-stage amplifier, the output power of the second monolithic semiconductor device 72b can be reduced, the operating current can be reduced, and a high-efficiency amplifier circuit can be realized.

[0213] (Implementation Method 26)

[0214] Next, the hybrid semiconductor device according to Embodiment 26 will be described.

[0215] Figure 26 This is a plan view of the hybrid semiconductor device 30h according to Embodiment 26. The hybrid semiconductor device 30h has essentially the same circuit configuration as the hybrid semiconductor device 30g according to Embodiment 25. However, in the hybrid semiconductor device 30h according to this embodiment, the first transistor 50 and the second transistor 60 from Embodiment 25 are disposed on the first monolithic semiconductor device 70, and the first preamplifier 150 and the second preamplifier 160 are disposed on the fourth monolithic semiconductor device 76. That is, the first preamplifier 150 and the second preamplifier 160 are disposed on the base substrate 32a at positions other than the first monolithic semiconductor device 70.

[0216] In the hybrid semiconductor device 30h of this embodiment with such a configuration, since the preamplifier and the postamplifier are configured on different monolithic semiconductor devices (the fourth monolithic semiconductor device 76 and the first monolithic semiconductor device 70, respectively), the thermal interference between the fourth monolithic semiconductor device 76 and the first monolithic semiconductor device 70 can be reduced, thereby achieving a high heat dissipation effect.

[0217] (Implementation Method 27)

[0218] Next, the hybrid semiconductor device according to Embodiment 27 will be described.

[0219] Figure 27This is a plan view of the hybrid semiconductor device 30i according to Embodiment 27. The hybrid semiconductor device 30i includes: a base substrate 32b, a carrier amplifier 80 and a peak amplifier 81 configured as a Doherty amplifier circuit disposed on the base substrate 32b, a bias circuit 82 disposed on the base substrate 32b for applying a bias voltage to the carrier amplifier 80, and a coupler 83 for distributing and transmitting the input high-frequency signal to the carrier amplifier 80 and the peak amplifier 81 respectively.

[0220] More specifically, the carrier amplifier 80 is, for example, the first transistor 12 in embodiment 8. The peak amplifier 81 is, for example, the third transistor 40 in embodiment 8. The bias circuit 82 is, for example, the first bias circuit 20 in embodiment 8. The coupler 83 is, for example, the coupler 74a in embodiment 24.

[0221] In the hybrid semiconductor device 30i of this embodiment with such a configuration, since the bias circuit 82 is provided within the hybrid semiconductor device 30i, there is no need for a bias circuit outside the hybrid semiconductor device 30i, thereby enabling the Doherty amplifier circuit to be implemented in a small area.

[0222] In addition, the bias circuit 82 can not only apply a bias voltage to the carrier amplifier 80, but also apply a bias voltage to both the carrier amplifier 80 and the peak amplifier 81.

[0223] (Implementation Method 28)

[0224] Next, the hybrid semiconductor device according to Embodiment 28 will be described.

[0225] Figure 28 This is a plan view of the hybrid semiconductor device 30j according to Embodiment 28. The hybrid semiconductor device 30j has essentially the same circuit configuration as the hybrid semiconductor device 30i according to Embodiment 27. However, the carrier amplifier 80 and the peak amplifier 81 are configured in the same fifth monolithic semiconductor device 77. The carrier amplifier 80 and the peak amplifier 81 are composed of a single-stage amplifier.

[0226] In the hybrid semiconductor device 30j of this embodiment with such a configuration, since the carrier amplifier 80 and the peak amplifier 81 are arranged on the same monolithic semiconductor device, the difference in characteristics of the transistors constituting the two amplifiers can be reduced, thereby enabling a stable Doherty amplifier circuit.

[0227] Furthermore, in the hybrid semiconductor device 30j according to this embodiment, since the Doherty amplifier circuit is configured as a single-stage amplifier, the area of ​​the fifth monolithic semiconductor device 77 can be reduced, thereby enabling the Doherty amplifier circuit to be implemented with a small area.

[0228] (Implementation Method 29)

[0229] Next, the hybrid semiconductor device according to Embodiment 29 will be described.

[0230] Figure 29 This is a plan view of the hybrid semiconductor device 30k according to Embodiment 29. The hybrid semiconductor device 30k has essentially the same circuit configuration as the hybrid semiconductor device 30i according to Embodiment 27. However, the carrier amplifier 80a and the peak amplifier 81a are configured in the same sixth monolithic semiconductor device 78. Furthermore, the carrier amplifier 80a and the peak amplifier 81a are configured as multi-stage amplifiers. The sixth monolithic semiconductor device 78 is, for example, the first monolithic semiconductor device 70a in Embodiment 25.

[0231] In the hybrid semiconductor device 30k of this embodiment with this configuration, since the Doherty amplifier circuit is composed of a multi-stage amplifier, a high-gain Doherty amplifier circuit can be realized. In this way, the strength of the input signal of the hybrid semiconductor device 30k can be reduced, and high-efficiency amplification can be achieved.

[0232] (Implementation Method 30)

[0233] Next, the monolithic semiconductor device according to Embodiment 30 will be described.

[0234] Figure 30 This is a plan view of the monolithic semiconductor device 10n according to Embodiment 30. The monolithic semiconductor device 10n has a substrate 11, a HEMT-type first transistor 50g and a second transistor 60g formed on the substrate 11. The monolithic semiconductor device 10n is used in a Doherty amplifier circuit where the first transistor 50g is used as a carrier amplifier and the second transistor 60g is used as a peak amplifier.

[0235] like Figure 30 As shown, the first transistor 50g and the second transistor 60g are each composed of a plurality of first unit transistors 50g1 and a plurality of second unit transistors 60g1 formed in a continuous active region 57. The plurality of first unit transistors 50g1 and the plurality of second unit transistors 60g1 are configured such that the first unit transistors and the second unit transistors are arranged alternately.

[0236] Furthermore, the cross-sectional structure of the multiple first-unit transistors 50g1 and the multiple second-unit transistors 60g1 is similar to... Figure 1 The structure shown in (b) is the same. Specifically, a first nitride semiconductor layer 102 made of GaN or the like is formed on the substrate 11; a second nitride semiconductor layer 103 made of AlGaN or the like, with a band gap larger than that of the first nitride semiconductor layer 102, is formed on the first nitride semiconductor layer 102; a drain electrode 110, a gate electrode 111, and a source electrode 112, isolated by an insulating layer 106 made of SiN or the like, are formed on the second nitride semiconductor layer 103; and a two-dimensional electron gas layer 107 is formed at the interface between the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103. The plurality of first unit transistors 50g1 and the plurality of second unit transistors 60g1 are HEMT-type transistors formed on the substrate 11, composed of the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103.

[0237] In the monolithic semiconductor device 10n of this embodiment with such a configuration, by expanding the heat-generating region of the first unit transistor 50g1 for the carrier amplifier with high heat generation, and arranging the second unit transistor 60g1 for the peak amplifier with low heat generation between the two first unit transistors 50g1, the thermal resistance can be reduced without increasing the area of ​​the substrate 11.

[0238] (Implementation Method 31)

[0239] Next, the monolithic semiconductor device according to Embodiment 31 will be described.

[0240] Figure 31 This is a plan view of the monolithic semiconductor device 10o according to Embodiment 31. The monolithic semiconductor device 10o has basically the same circuit configuration as the monolithic semiconductor device 10n according to Embodiment 30. However, in the monolithic semiconductor device 10o according to this embodiment, the plurality of first unit transistors 50g1 and the plurality of second unit transistors 60g1 use their respective source regions as a common source region, and the adjacent formation locations are different from those in Embodiment 30.

[0241] More specifically, each of the plurality of first unit transistors 50g1 has a first gate region with a gate electrode 52, a first drain region with a drain electrode 53, and a first source region with active electrodes 54a and 54b within the active region 57. Furthermore, each of the plurality of second unit transistors 60g1 has a second gate region with a gate electrode 62, a second drain region with a drain electrode 63, and a second source region with active electrodes 64a and 64b within the active region 57. The plurality of first unit transistors 50g1 and the plurality of second unit transistors 60g1 are formed adjacent to each other, sharing a common source region between the first source region with active electrode 54b and the second source region with active electrode 64a.

[0242] In the monolithic semiconductor device 10o of this embodiment with such a configuration, by expanding the heat-generating region of the first unit transistor 50g1 for the carrier amplifier with high heat generation, and arranging the second unit transistor 60g1 for the peak amplifier with low heat generation between the two first unit transistors 50g1, the thermal resistance can be reduced without increasing the area of ​​the substrate 11.

[0243] (Implementation Method 32)

[0244] Next, the monolithic semiconductor device according to Embodiment 32 will be described.

[0245] Figure 32 This is a diagram illustrating the monolithic semiconductor device 10p according to embodiment 32. More specifically, Figure 32 (a) shows the planar layout of the monolithic semiconductor device 10p. Figure 32 (b) shows the relationship between thermal resistance (solid line, left vertical axis) for the length (horizontal axis) of the common source region and transistor area (solid line, right vertical axis).

[0246] The monolithic semiconductor device 10p includes a substrate 11 and a HEMT-type power amplifier transistor 90 formed on the substrate 11. The transistor 90 is composed of a plurality of unit transistors 90a to 90d formed within consecutive active regions 91. Each of the plurality of unit transistors 90a to 90d has a source region forming an active electrode 94, a gate region forming a gate electrode 92, and a drain region forming a drain electrode 93 within the active region 91. Adjacent unit transistors among the plurality of unit transistors 90a to 90d have a common source region 95 sharing their respective source regions and a common drain region 96 sharing their respective drain regions. In the arrangement direction of the source, gate, and drain regions of the plurality of unit transistors 90a to 90d, the length of the common source region 95 is 200 μm or more and 340 μm or less.

[0247] In addition, the cross-sectional structure of multiple unit transistors 90a-90d is similar to Figure 1 The structure shown in (b) is the same. Specifically, a first nitride semiconductor layer 102 made of GaN or the like is formed on the substrate 11; a second nitride semiconductor layer 103 made of AlGaN or the like, with a band gap larger than that of the first nitride semiconductor layer 102, is formed on the first nitride semiconductor layer 102; a drain electrode 110, a gate electrode 111, and a source electrode 112 are formed on the second nitride semiconductor layer 103 and isolated by an insulating layer 106 made of SiN or the like; and a two-dimensional electron gas layer 107 is formed at the interface between the first nitride semiconductor layer 102 and the second nitride semiconductor layer 103. Multiple unit transistors 90a to 90d are HEMT-type transistors formed from the first nitride semiconductor layer 102 and the second nitride semiconductor layer formed on the substrate 11.

[0248] like Figure 32 As shown in (b) "Transistor Area", the longer the common source region, the transistor area increases almost linearly. Furthermore, as... Figure 32 As shown in (b) "thermal resistance", the longer the common source region is, the larger the spacing of the main heat source in the amplifier, namely the gate region. Although the thermal resistance gradually decreases, the degree of decrease becomes smaller when it exceeds about 200 μm.

[0249] Therefore, in the monolithic semiconductor device 10p according to this embodiment, since the length of the common source region 95 is more than 200 μm and less than 340 μm, low thermal resistance can be ensured without needlessly increasing the transistor area.

[0250] (Implementation Method 33)

[0251] Next, the monolithic semiconductor device according to Embodiment 33 will be described.

[0252] Figure 33 This is a diagram used to illustrate the monolithic semiconductor device 10q according to embodiment 33. More specifically, Figure 33 (a) shows the planar layout of the monolithic semiconductor device 10q. Figure 33 (b) shows the phase difference (solid line) of the signal across the gate region and the phase difference (dashed line) of the signal across the drain region, with respect to the width of the gate region (horizontal axis). Figure 33 (c) shows the relationship between the phase difference of the signals at both ends of the drain region and the gain of the transistor.

[0253] The monolithic semiconductor device 10q has essentially the same structure as embodiment 32. However, the length of the gate region, i.e. the width of the gate region (the length between (A) and (B) in the figure), in the direction orthogonal to the arrangement direction of the source region, gate region, and drain region of the plurality of unit transistors 90a to 90d, is 260 μm or less.

[0254] In high-frequency amplification transistors, generally, the signal is input from the gate and output from the drain, the opposite end to the input. Although the signal undergoes phase rotation within the gate and drain regions, the phase rotation within the gate region is greater than that within the drain region. Therefore, the phase of the signal amplified at the transistor's input deviates from that at the transistor's output. As the width of the gate and drain regions (orthogonal to the alignment directions of the source, gate, and drain regions) increases, the phase deviation also increases. Figure 33 (b) will reduce the gain. Figure 33 (c)).

[0255] In the monolithic semiconductor device 10q according to this embodiment, the width of the gate region is 260 μm or less, and the phase difference of the output in signals with frequencies above 3 GHz is suppressed to 15 degrees or less. Figure 33 (b)) thus enabling the suppression of gain reduction ( Figure 33 (c)).

[0256] The monolithic semiconductor device and hybrid semiconductor device of this disclosure have been described above based on embodiments 1 to 33. However, this disclosure is not limited to these embodiments 1 to 33. Within the scope of this disclosure, various modifications that can be conceived by those skilled in the art to be performed on each embodiment 1 to 33, and other forms constructed by combining some of the constituent elements of each embodiment, are included within the scope of this disclosure.

[0257] The monolithic semiconductor device and hybrid semiconductor device disclosed herein can be used as monolithic semiconductor devices and hybrid semiconductor devices that include transistors capable of adjusting their respective gate voltages and can reduce operating time, for example, as Doherty amplifier circuits.

[0258] Symbol Explanation

[0259] 10, 10c~10q Monolithic semiconductor devices

[0260] 10a, 70, 70a First Monolithic Semiconductor Device

[0261] 10b, 72, 72a, 72b Second monolithic semiconductor device

[0262] 11, 11a substrate

[0263] 12, 50, 50a~50g First Transistor

[0264] 13, 41 Gate terminals

[0265] 14, 42 Leakage extremes

[0266] 15 First bias terminal

[0267] 16 Second bias terminal

[0268] 20 First Bias Circuit

[0269] 20a Second Bias Circuit

[0270] 20b Third Bias Circuit

[0271] 21, 60, 60a~60c, 60g Second transistor

[0272] 22 First resistor

[0273] 23 Second Resistor

[0274] 24. Third Resistor

[0275] 25. 4th Resistor

[0276] 26. 5th Resistor

[0277] 27. 6th Resistor

[0278] 30, 30a-30k hybrid semiconductor devices

[0279] 32, 32a, 32b Base plate

[0280] 33 Base board terminals

[0281] 33a High-frequency signal input board terminal

[0282] 33b Enable control input board terminal

[0283] Wiring on the base plate of 34a and 34b

[0284] 35a and 35b wires

[0285] 40. The third transistor

[0286] 43 Third bias terminal

[0287] 44 Fourth bias terminal

[0288] 45 Enable control circuit

[0289] 46 Enable control terminal

[0290] 47 Enable output terminal

[0291] 50g1 First unit transistor

[0292] 51, 51a~51f First active region

[0293] 52, 52a~52f, 62, 62a~62c, 92 gate electrodes

[0294] 53, 53a~53f, 63, 63a~63c, 93 Drain electrodes

[0295] 54, 54a~54f, 64, 64a~64c, 94 Source electrodes

[0296] 54d1 source wiring

[0297] 54d2 pilot hole

[0298] 55, 55a, 55b, and 95 share a common source region.

[0299] 56, 56a, 56b, and 96 share a common drain region.

[0300] 57, 91 active regions

[0301] 58 Level shifting circuit

[0302] 60g1 Second Unit Transistor

[0303] 61, 61a~61c Second active region

[0304] 71 Input Matching Circuit Area

[0305] 73 Output Matching Circuit Area

[0306] 74, 74a, 83 Couplers

[0307] 75 Third Monolithic Semiconductor Device

[0308] 76 Fourth Monolithic Semiconductor Device

[0309] 77 Fifth Monolithic Semiconductor Device

[0310] 78 The 6th Monolithic Semiconductor Device

[0311] 80, 80a carrier amplifier

[0312] 81, 81a peak amplifiers

[0313] 82 Bias Circuit

[0314] 90 transistors

[0315] 90a~90d unit transistor

[0316] 102 First Nitride Semiconductor Layer

[0317] 103 Second Nitride Semiconductor Layer

[0318] 104 Component Separation Layer

[0319] 106 Insulation Layer

[0320] 110 Drain electrode

[0321] 111 Gate electrode

[0322] 112 Source Electrode

[0323] 113 First Electrode

[0324] 114 Second Electrode

[0325] 150 First Preamplifier

[0326] 160 Second Preamplifier

Claims

1. A monolithic semiconductor device, The monolithic semiconductor device includes: The substrate has a nitride semiconductor layer; The first HEMT-type transistor is formed on the substrate, constituting the carrier amplifier of the Doherty amplifier circuit. HEMT stands for High Electron Mobility Transistor. The first bias circuit applies a bias voltage to the gate of the first transistor. The first bias circuit includes a first resistive element, a HEMT-type second transistor formed on the substrate, and a second resistive element, wherein the first resistive element, the second transistor, and the second resistive element are connected in series between a first bias terminal and a second bias terminal in this order, and the voltage applied to the second bias terminal is lower than the voltage applied to the first bias terminal. The connection point between the first resistive element and the second transistor is connected to the gate. The first transistor is composed of a plurality of first unit transistors formed in consecutive active regions. Each of the plurality of first unit transistors has a source region, a first gate finger, and a drain region within the active region. The second gate finger of the second transistor extends in the same direction as the first gate finger. The length of the second gate finger is shorter than the length of the first gate finger.

2. The monolithic semiconductor device as described in claim 1, Adjacent first unit transistors among the plurality of first unit transistors have a common source region that shares a common source region, or a common drain region that shares a common drain region. In the first direction in which the source regions, the first gate fingers, and the drain regions of the plurality of first unit transistors are arranged, the length of the source region that is closest to the outer periphery of the substrate is shorter than half the length of the common source region.

3. The monolithic semiconductor device as described in claim 1, Adjacent first unit transistors among the plurality of first unit transistors have a common source region that shares a common source region, or a common drain region that shares a common drain region. In a first direction in which the source regions, the first gate fingers, and the drain regions of the plurality of first unit transistors are arranged, The length from the outer periphery of the substrate to the first gate finger formed closest to the outer periphery is longer than half the length of the common source region.

4. The monolithic semiconductor device as described in claim 1, Adjacent first unit transistors among the plurality of first unit transistors have a common source region that shares a common source region, or a common drain region that shares a common drain region. In a first direction in which the source regions, the first gate fingers, and the drain regions of the plurality of first unit transistors are arranged, the length of the common source region is 200 μm or more and 340 μm or less. In the plan view of the substrate, the length of the first gate finger is less than 260 μm in a direction orthogonal to the first direction.

5. The monolithic semiconductor device as described in claim 1, The monolithic semiconductor device includes a third HEMT-type transistor formed on the substrate, the third transistor constituting the peak amplifier of the Doherty amplifier circuit, and having a greater current-carrying capability than the first transistor.

6. The monolithic semiconductor device as described in claim 5, The monolithic semiconductor device further includes a second bias circuit formed on the substrate, the second bias circuit applying a bias voltage to the gate of the third transistor. The second bias circuit does not include HEMT-type transistors.

7. The monolithic semiconductor device as described in claim 5, The first transistor has a first active region. The third transistor has a second active region with an area smaller than the first active region.

8. The monolithic semiconductor device as described in claim 5, The first bias circuit is located between the first transistor and the third transistor in the direction in which the first transistor and the third transistor are arranged, or between the outer periphery of the substrate and the first transistor.

9. The monolithic semiconductor device as claimed in claim 5, The third transistor is formed within a continuous active region and is composed of a plurality of second unit transistors. The plurality of first unit transistors have a first source region, a first gate region, and a first drain region within the active region. The plurality of second unit transistors have a second source region, a second gate region, and a second drain region within the active region. The plurality of first unit transistors and the plurality of second unit transistors are formed adjacent to each other, with the first source region and the second source region being a shared source region.

10. A hybrid semiconductor device comprising: Base plate; A first monolithic semiconductor device mounted on the base substrate, wherein the first monolithic semiconductor device is the monolithic semiconductor device as described in claim 5; as well as A second monolithic semiconductor device is mounted on the base substrate, the second monolithic semiconductor device having an amplification circuit that amplifies and outputs a high-frequency signal to the first monolithic semiconductor device.

11. The hybrid semiconductor device of claim 10, In the plan view of the base substrate, the first monolithic semiconductor device and the second monolithic semiconductor device are arranged on the base substrate in such a way that their respective transmission directions for transmitting high-frequency signals are not parallel to each other.

12. The hybrid semiconductor device of claim 10, The hybrid semiconductor device further comprises a third monolithic semiconductor device, including a portion of the elements of the first bias circuit, mounted on the base substrate.

13. A hybrid semiconductor device comprising: A first monolithic semiconductor device, which is a monolithic semiconductor device formed by removing at least one of the constituent elements of the monolithic semiconductor device of claim 1; and A second monolithic semiconductor device, wherein at least one of the first resistive element and the second resistive element is formed in the second monolithic semiconductor device.

14. A hybrid semiconductor device, The hybrid semiconductor device includes: The base plate is rectangular in shape in the case of a plan view; and The monolithic semiconductor device of claim 1, mounted on the base substrate, The base plate has: High-frequency signal input substrate terminals located on the outer periphery of the base substrate; and An enable control input terminal located on the outer periphery of the base substrate controls the active state of the first bias circuit. The enable control input substrate terminal is configured in the substrate terminal positions of the four outer peripheries of the base substrate where the high-frequency signal input substrate terminal is not configured, and in addition to the substrate terminal positions at the corners.

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