Switch leakage compensation circuit

Abstract

Apparatus and methods associated with a switch leakage compensation delay circuit (405a) include a compensation transistor (T0) configured to passively bypass leakage current around a capacitor (C0) connected in series with a control transistor (M0). In an illustrative example, the capacitor (C0) and the compensation transistor (T0) can be connected in parallel between a first node (a0) and a second node (b0). The gate of the compensation transistor (T0) can, for example, be directly connected to its source and the second node (b0). The control transistor (M0) can have its drain connected to the second node (b0). When a control signal turns off the control transistor (M0), the leakage current of the control transistor (M0) can be provided by the leakage current of the compensation transistor (T0), so that the voltage across the capacitor (C0) can remain substantially constant. The delay circuit (405a) can advantageously mitigate the voltage drop across the capacitor (C0) to reduce clock timing skew, for example, in low-speed interleaved ADC operation.

Description

Technical Field

[0001] Various embodiments generally relate to switch leakage compensation. Technical Background

[0002] Data represents information that has useful value. Data can be stored in a form. Data storage can be in analog form. Data storage can also be in digital form.

[0003] Data in digital format can be communicated between two nodes. At the receiver in a digital communication system, a digitally encoded data stream can be received as an analog signal and converted to a digital format by an analog-to-digital converter (ADC). The analog-to-digital converter interprets the data stream as a function of time. For example, some ADCs can be synchronized with a clock signal, where the clock signal determines when the voltage signal is sampled. For example, accurate recovery of a digital data stream may depend on accurate clock timing. In some embodiments, the timing of the clock signal can determine whether a symbol in the data stream is interpreted as, for example, 1 or 0. Sometimes, a clock signal is received, but its phase information may be uncertain. In order to improve data accuracy and data integrity, various clock signal phase alignment operations can sometimes be performed before starting the data or when receiving the data so that accurate clock phase information can be provided to the ADC.

[0004] In integrated circuit applications, ADCs typically use one or more transistor-implemented circuit stages to perform critical timing functions. In various ADC circuits, some transistors may operate in linear mode to process analog signals. In some ADC circuits, certain transistors may be designed to operate as ideal switches (e.g., digital signals). An ideal transistor switch can operate in either an on or off state in response to a control signal. However, in reality, transistors in real integrated circuits may exhibit non-ideal behavior related to inherent device characteristics and / or external parameters (e.g., device process parameters, applied voltage, and device temperature). Summary of the Invention

[0005] Apparatus and methods related to a switch leakage compensation delay circuit include a compensation transistor configured to passively bypass leakage current around a capacitor connected in series with a control transistor. In an illustrative example, the capacitor and the compensation transistor can be connected in parallel between a first node and a second node. For example, the compensation transistor gate can be directly connected to its source and the second node. The control transistor can have its drain connected to the second node. When a control signal turns off the control transistor, leakage current of the control transistor can be provided by leakage current of the compensation transistor, so that the voltage across the capacitor can be maintained substantially constant. The delay circuit can advantageously mitigate voltage drops across the capacitor to reduce clock timing skew, for example, in low-speed interleaved ADC operation.

[0006] Various embodiments can achieve one or more advantages. For example, MOS capacitors can advantageously reduce the number of manufacturing steps and area of ​​the delay circuit. Transistors of the same size and type as the switch can compensate for leakage caused by the switch across process, voltage, and temperature. In some embodiments, the spatial position of the transistor can be made slightly higher than the switch to reduce the negative impact on area. By introducing a switch leakage compensation delay circuit, some embodiments can enable the time offset DAC to be used over a large clock frequency range, because leakage problems are a major limitation of applications over a large clock frequency range. Some embodiments can enable the ADC to operate across frequency, process, voltage, temperature (PVT), and mismatch without any disadvantages. Some embodiments can be flexibly used in, for example, programmable logic, such as a field programmable gate array (FPGA), which can allow the delay circuit to be reconfigured for the field. In some embodiments, for example, when implemented on a fixed hardware platform such as an application specific integrated circuit (ASIC), cost, size, or power can be reduced.

[0007] In one exemplary aspect, the delay circuit is configured to obtain a predetermined delay. The delay circuit includes a capacitor coupled between a first node and a second node. The delay circuit also includes a first transistor. The drain of the first transistor is connected to the second node, the source of the first transistor is connected to a reference node, and the gate of the first transistor is coupled to a first gate control signal. The first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal. The delay circuit also includes a second transistor having a drain and a source and coupled in parallel with the capacitor, the gate of which is coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor. When in a first mode, the first gate control signal applies a voltage to the first gate that is less than the first threshold voltage of the first transistor, and the voltage across the capacitor is substantially constant.

[0008] In some embodiments, in the first mode, the first transistor can provide a first leakage current I leak1 , the first leakage current I leak1 and the second leakage current I provided by the second transistor leak2Basically matched. The second drain can be connected to the first node, and the second source can be connected to the second gate and the second node. The second transistor can be on the same die as the first transistor and have substantially the same size. The first transistor can be an n-channel metal oxide semiconductor field effect transistor (NMOSFET) or a p-channel metal oxide semiconductor field effect transistor (PMOSFET). The first transistor can also be a transmission gate. In some embodiments, the second transistor can be an n-channel metal oxide semiconductor field effect transistor (NMOSFET). The capacitor can be a metal oxide semiconductor transistor. In some embodiments, the potential of the reference node can be a circuit ground potential. The second gate of the second transistor can be connected to the second node.

[0009] In another exemplary aspect, a system includes a buffer output coupled to drive a first node to perform a predetermined delay on an input clock signal. The system also includes at least one delay circuit configured to achieve the predetermined delay. Each of the at least one delay circuits includes a capacitor coupled between a first node and a second node. Each of the at least one delay circuits also includes a first transistor having a drain connected to the second node, a source connected to a reference node, and a gate coupled to a first gate control signal. The first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal. Each of the at least one delay circuits also includes a second transistor having a drain and a source coupled in parallel with the capacitor, and a gate coupled to apply a voltage to the gate of the second transistor that is less than a second threshold voltage of the second transistor. In a first mode, when the first gate control signal applies a voltage to the first gate that is less than the first threshold voltage of the first transistor, the voltage across the capacitor is substantially constant.

[0010] In some embodiments, in the first mode, the first transistor can provide a first leakage current I leak1 , the first leakage current I leak1 and the second leakage current I provided by the second transistor leak2 The second transistor may be substantially matched to the first transistor. The second transistor may be on the same die as the first transistor and have the same size. The first transistor may be an NMOSFET or a PMOSFET. The first transistor may also be a transmission gate. The second transistor may be an NMOSFET. The capacitor may be a metal oxide semiconductor transistor. In some embodiments, the potential of the reference node may be a circuit ground potential. In some embodiments, the gate of the second transistor may be connected to the second node.

[0011] In another exemplary aspect, a method includes providing a capacitor coupled between a first node and a second node, and providing a capacitor coupled between the first node and the second node. The method also includes providing a first transistor having a first drain connected to the second node, a first source connected to a reference node, and a first gate coupled to a first gate control signal, wherein the first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal. The method also includes providing a second transistor having a second drain and a second source, the second transistor being coupled in parallel with the capacitor and having a second gate coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor. In addition, the method also includes, in a first mode, when the first gate control signal applies a voltage less than the first threshold voltage of the first transistor to the first gate, using the second transistor to provide a first leakage current I substantially drawn by the first transistor to the first transistor. leak1 , so that the voltage across the capacitor remains essentially constant.

[0012] In some embodiments, in the first mode, the second transistor can substantially match the first drain current I leak1 The second drain may be connected to the first node, the second source may be connected to the second gate and the second node. The potential of the reference node may be a circuit ground potential. The second gate may be connected to the second node.

[0013] The details of various embodiments are set forth in the drawings and the description that follows. Other features and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 An exemplary programmable integrated circuit (IC) is depicted upon which the disclosed circuits and processes may be implemented.

[0016] Figure 2 An exemplary interleaved analog-to-digital converter (ADC) with a switch leakage compensation delay system is depicted.

[0017] Figure 3A depicts a delay system for an interleaved ADC.

[0018] FIG. 3B depicts a prior art delay circuit when a switch in the delay circuit is open in an idealized model.

[0019] Figure 3C Depicted is an exemplary timing diagram for a delay circuit when a switch in the delay circuit is open and has leakage current associated with the switch.

[0020] Figure 4A An exemplary switch leakage compensation delay circuit is depicted.

[0021] Figure 4B Another exemplary switch leakage compensation delay circuit is depicted.

[0022] Figure 4C Depicted in Figure 2 An exemplary switch leakage compensation delay system implemented in.

[0023] Figure 5A Depicts exemplary experimental results showing that Figure 3C Timing diagram of the delay circuit in .

[0024] Figure 5B Depicts exemplary experimental results showing that Figure 4C Timing diagram of the switch leakage compensation delay circuit in .

[0025] Figure 6A Depicts Figure 3C Example simulation results of the delay circuit in .

[0026] Figure 6B Depicts Figure 4C Example simulation results of the switch leakage compensation delay circuit in .

[0027] Figure 7 A flow chart of an exemplary method of performing switch leakage compensation is depicted.

[0028] Like reference symbols in the various drawings denote like elements.

[0029] Detailed description

[0030] Apparatus and methods related to a switch leakage compensation delay circuit include a compensation transistor configured to passively bypass leakage current around a capacitor connected in series with a control transistor. In an illustrative example, the capacitor and the compensation transistor can be connected in parallel between a first node and a second node. For example, the compensation transistor gate can be directly connected to its source and the second node. The control transistor can have its drain connected to the second node. When a control signal turns off the control transistor, the leakage current of the control transistor can be provided from the leakage current of the compensation transistor so that the voltage across the capacitor can be maintained substantially constant. The delay circuit, such as reference Figure 4A The described exemplary delay circuit 405a may advantageously mitigate capacitor voltage drops to reduce clock timing skew, for example, during low-speed interleaved ADC operation.

[0031] To help understanding, this article is organized as follows. First, refer to Figure 1 An example platform (e.g., FPGA) suitable for performing analog-to-digital conversion is briefly described. Figure 2-4C, turns to a discussion of how to use an exemplary circuit to introduce a predetermined delay and compensate for the leakage current provided by the switch. Then, refer to Figure 5A and Figure 6B , discusses exemplary experimental results and simulation results of exemplary circuits disclosed. Finally, reference Figure 7 , an exemplary method for performing switch leakage compensation is discussed. By using a delay circuit, leakage current can be compensated and time-skewed digital-to-analog converter (DAC) functionality at low speeds can be advantageously addressed.

[0032] Figure 1 Depicts an exemplary programmable integrated circuit (IC) on which the disclosed circuits and processes may be implemented. Programmable integrated circuit 100 includes FPGA logic. Programmable integrated circuit 100 may be implemented with various programmable resources and may be referred to as a system on a chip (SOC). Various examples of FPGA logic may include several different types of programmable logic blocks in an array.

[0033] For example, Figure 1 The diagram shows a programmable integrated circuit 100 that includes a large number of different programmable tiles, including multi-gigabit transceivers (MGTs) 101, configurable logic blocks (CLBs) 102, random access memory blocks (BRAMs) 103, input / output blocks (IOBs) 104, configuration and clock logic (CONFIG / CLOCKS) 105, digital signal processing blocks (DSPs) 106, dedicated input / output blocks (I / Os) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable integrated circuit 100 includes a dedicated processor block (PROC) 110. The programmable integrated circuit 100 may include internal and external reconfiguration ports (not shown).

[0034] In various examples, a serializer / deserializer can be implemented using the MGT 101. The MGT 101 can include various data serializers and deserializers. The data serializer can include various multiplexer implementations. The data deserializer can include various demultiplexer implementations.

[0035] In some examples of FPGA logic, each programmable slice includes a programmable interconnect element (INT) 111 having standardized interconnects 124 to and from corresponding interconnect elements in each adjacent slice. Thus, the programmable interconnect elements together implement the programmable interconnect structure of the illustrated FPGA logic. The programmable interconnect element INT 111 includes internal connections 120 to and from programmable logic elements within the same slice, such as Figure 1The programmable interconnect element INT 111 includes internal INT connections 122 to and from the programmable interconnect element INT 111 within the same chip, as shown in FIG. Figure 1 as shown in the included examples.

[0036] For example, CLB 102 may include a configurable logic element (CLE) 112 that can be programmed to implement user logic, plus a single programmable interconnect element INT 111. BRAM 103 may include a BRAM logic element (BRL) 113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a slice may depend on the height of the slice. In the illustrated embodiment, one BRAM slice has the same height as five CLBs, but other numbers (e.g., four) are possible. DSP slice 106 may include a DSP logic element (DSPL) 114 and one or more programmable interconnect elements. IOB 104 may include, for example, two instances of input / output logic element (IOL) 115 and one instance of programmable interconnect element INT 111. For example, the actual I / O bonding pads connected to I / O logic element 115 may be fabricated using metal layered above the various illustrated logic blocks and may not be limited to the area of ​​input / output logic element 115.

[0037] In the illustrated embodiment, the columnar region ( Figure 1 Horizontal regions 109 extending from the columns distribute clock and configuration signals across the width of programmable integrated circuit 100. Note that the terms "column-shaped" and "horizontal" regions are relative to viewing the diagram in a vertical orientation.

[0038] Some use Figure 1 The programmable integrated circuit of the illustrated architecture may include additional logic blocks that disrupt the conventional columnar structure that makes up the majority of the programmable integrated circuit. The additional logic blocks may be programmable blocks and / or dedicated logic. For example, Figure 1 Processor block PROC 110 is shown spanning multiple columns of CLBs 102 and BRAMs 103 .

[0039] Figure 1 An exemplary programmable IC architecture is shown. The number of logic blocks in a column, the relative widths of the columns, the number and order of the columns, the types of logic blocks contained in the columns, the relative sizes of the logic blocks, and the implementation of the interconnect / logic are provided purely as examples. For example, in an actual programmable IC, regardless of where CLBs 102 appear, more than one adjacent column of CLBs 102 may be included to facilitate efficient implementation of user logic.

[0040] At least one transceiver can be embedded in an FPGA to transmit and receive data during communications. Analog-to-digital conversion is the process of converting a continuous range of analog signal levels into digital codes. Analog signal levels can be converted into digital voltage, current, or charge signals using an ADC. ADCs are used in many applications, such as communications systems. Switches and capacitors can be used in ADCs to control ADC sampling. Switch leakage compensation circuits can be used to compensate for leakage current introduced by switches and maintain conversion accuracy.

[0041] Figure 2 An exemplary interleaved analog-to-digital converter (ADC) with a switch leakage compensation delay system is depicted. Communication system 200 includes base station 205. Base station 205 can be used to transmit and receive data to and from a number of data communication devices. In this exemplary example, base station 205 receives an analog signal from a cellular phone 210. Base station 205 includes an FPGA 215 to facilitate data communication via antenna 220 between base station 205 and cellular phone 210. Antenna 220 transmits received analog signal 225 to filter 230. Filter 230 filters errors and / or noise from analog signal 225. The filtered analog signal is amplified by amplifier 235 to generate processed analog signal 240. Processed analog signal 240 is converted to digital signal 250 by analog-to-digital converter (ADC) system 245. Digital signal 250 is then processed, for example, by digital signal processor (DSP) 255.

[0042] High-speed electronic devices (e.g., 5G technology) may require ADCs with high sampling rates. For example, a receiver may use a 5 Gigasamples per second (GSPS) ADC with a 1 GHz, DC-coupled, fully differential amplifier front end. Each signal may be sampled every 200 ps. A time-interleaved ADC can be used to achieve high sampling rates. For example, by using a time-interleaved ADC comprising four sub-ADCs, each of the four sub-ADCs may only need to have a sampling rate of, for example, 1.25 GSPS.

[0043] In the depicted example, the processed analog signal 240 is received by the buffer 260 and then sampled by the four sub-ADCs 265a, 265b, 265c, and 265d. For example, the first sample may be sampled by the first ADC 265a. Each of the four sub-ADCs 265a, 265b, 265c, and 265d is driven by a sampling driver circuit. Each sampling driver circuit generates a different sampling clock signal. For example, the first sampling clock signal used by the first sub-ADC 265a may have a 0-degree phase difference with the reference clock signal. The second sampling clock signal used by the second sub-ADC 265b may have a 90-degree phase difference with the reference clock signal. The third sampling clock signal used by the third sub-ADC 265c may have a 180-degree phase difference with the reference clock signal. The fourth sampling clock signal used by the fourth sub-ADC 265d may have a 270-degree phase difference with the reference clock signal.

[0044] Each of the sub-ADCs 265a, 265b, 265c, and 265d can sample at a precise time (e.g., the first sub-ADC 265a can sample at 0 s, the second sub-ADC 265b can sample at 800 ps, ​​the third sub-ADC 265c can sample at 1600 ps, ​​and the fourth sub-ADC 265d can sample at 2400 ps). Due to manufacturing or technical limitations, the electrical characteristics of each sub-ADC may vary. Mismatches between the sub-ADCs can generate harmonic and interleaving spurs. For example, the first sub-ADC 265a can sample at 800 ps ± 10 fs. Even a small number like 10 fs can result in timing deviations, especially when the highest intermediate frequency of interest is in the GHz range and there are strict specifications for interleaving tones. In the depicted example, each sampling driver circuit includes a first buffer (e.g., inverter) 270 and a second buffer (e.g., inverter) 275 to maintain the phase of the sampled signal. Between the first buffer 270 and the second buffer 275, a switch leakage compensation delay system 280 is arranged to introduce a predetermined delay on the reverse processed analog signal to solve the time offset problem. Figures 4A-4C , an example of the switch leakage compensation delay system 280 will be described in more detail.

[0045] Each of the sub-ADCs 265a, 265b, 265c, and 265d is connected to a selection circuit 285 (eg, a multiplexer) that selectively outputs the signals sampled by the four sub-ADCs 265a, 265b, 265c, and 265d to form a digital signal 250.

[0046] FIG3A depicts a prior art delay system for an alternating ADC. In the prior art, a delay system 300 is provided between a first buffer 270 and a second buffer 275. The delay system 300 includes one or more delay circuits 305 connected in parallel. For example, the first delay circuit 305 includes a first capacitor C0, which is arranged to introduce a delay on an incoming sampling clock signal. In some embodiments, the capacitor C0 may be a MOS capacitor. The other end of the capacitor C0 is connected to a first switch M0 via a node b0. The first switch M0 is controlled by a control signal D0. In the depicted example, the switch M0 includes an N-channel metal oxide semiconductor field effect transistor (NMOSFET). The drain of the NMOSFET is connected to the node b0. The source of the NMOSFET is grounded. The gate of the NMOSFET is controlled by a controlled signal D0.

[0047] By closing or opening the switches of each delay circuit, the capacitors in the delay circuit can be added to or not added to the circuit. Then the control signals D0, D1...D N-1 To program the delay. The corresponding waveform at node b0 is depicted. During the rising edge of CLK_BAR at the start of sampling, the voltage at node b0 rises to V dda . V dda (eg, 0.9 v) is the power supply for buffer 270 and the high level of the clock signal through buffer 270 and buffer 275 .

[0048] FIG3B depicts a prior art delay circuit when the switch in the delay circuit is open in an idealized model. In this depicted example, the first transistor M0 has no leakage current and the parasitic capacitance C b0 The corresponding waveform at the second node b0 is depicted. When the transistor M0 has no leakage current, the waveform of the sampling clock signal appears to be well maintained.

[0049] Figure 3C An exemplary timing diagram for a delay circuit is depicted when a switch in the delay circuit is open and has leakage current associated with the switch. In practice, the first transistor M0 has leakage current. When transistor M0 has leakage current and the ADC speed is low, the waveform of the sampling clock signal is not an ideal sampling clock signal because the leakage current may cause transistor M0 to no longer be turned off, even if the gate voltage of transistor M0 (e.g., an N-channel MOSFET) is 0V. The timing diagram reveals the undesirable effect of the capacitor voltage drop at the junction between the capacitor and transistor M0.

[0050] The corresponding waveform at the second node b0 is shown. During the rising edge of CLK_BAR at the start of sampling, due to C b0 The voltage at the second node b0 does not rise to V ddaThe voltage at the second node b0 rises to V b0H .

[0051] V b0H =(V dda *C0) / (C0+C b0 ). The leakage current may cause the voltage at the second node b0 to leak to zero. Figure 3C As shown in Figure 1, transistor M0 is not turned off during the end of sampling, which may affect the time offset DAC function at low speeds. Due to the negative voltage, the drain of M0 becomes the source of M0, and the source of M0 becomes the drain of M0. Therefore, transistor M0 can go from the cutoff state to the saturation state. For example, the impedance between b0 and ground may be 1 / g of M0. m , which may be a low value compared to the on-resistance of M0.

[0052] Figure 4A An exemplary switch leakage compensation delay circuit is depicted. Delay circuit 405a includes a first capacitor C0. First capacitor C0 is disposed between a first node a0 and a second node b0. First capacitor C0 is configured to introduce a predetermined delay to a sampling clock signal received via first node a0. In some embodiments, capacitor C0 may be a MOS capacitor for accuracy and reduced area.

[0053] The other end of capacitor C0 is connected to the first transistor M0 via a second node b0. In the depicted example, transistor M0 is an N-channel metal oxide semiconductor field effect transistor (NMOSFET). The drain of transistor M0 is connected to the second node b0. The source of transistor M0 is connected to a reference node (e.g., ground potential). The gate of transistor M0 is controlled by a controlled signal D0. In response to the controlled signal D0, transistor M0 modulates the connectivity between the drain and the source. When the voltage applied between the gate and source of transistor M0 is less than the threshold voltage V T1 When the transistor M0 provides a first leakage current I due to the subthreshold effect, leak1 .like Figure 3C As discussed in the first section, the first leakage current I leak1 This will cause time deviation.

[0054] Delay circuit 405a also includes a second transistor T0. In the depicted example, second transistor T0 is an NMOSFET. Second transistor T0 is connected in parallel with capacitor C0. The drain of second transistor T0 is coupled to first node a0. The source of second transistor T0 is coupled to second node b0. The gate of second transistor T0 is coupled to a voltage. When the voltage applied to the gate is such that the voltage difference V between the gate and source of second transistor T0 is gs is less than the threshold voltage V of the second transistor T0 T2When the second transistor T0 has no conduction path between the second source and the second drain, the second transistor T0 will also introduce a second leakage current I due to the subthreshold effect. leak2 The second leakage current I leak2 Offset and compensate the first leakage current I leak1 , which can make the voltage at the second node b0 substantially constant over time.

[0055] In this example, the gate and source of the second transistor T0 are both coupled to the second node b0. By connecting the source and the gate, the voltage difference V between the source and the gate is gs is 0, which is less than the threshold voltage V of the second transistor T0 T2 By connecting the source and the gate, the complexity of wiring connections, the area of ​​the delay circuit, and the steps of the manufacturing process can be advantageously reduced.

[0056] In some embodiments, the second transistor T0 can be designed to substantially replicate the transistor M0, and / or can be on the same die and have the same type and substantially the same size as the transistor M0. The leakage current of the transistor M0 can be substantially accurately matched (e.g., in scale) across processes, voltages, and temperatures. In some embodiments, the position of the second transistor T0 can be arranged to be higher than the position of the transistor M0. In some embodiments, the increased capacitance of the second transistor T0 can be compensated by reducing the capacitance value of C0.

[0057] By introducing the second transistor T0 in the delay circuit 405a, the voltage V b0H Keep constant. V b0H =(V dda *C0) / (C0+C b0 ), where Cb0 is the parasitic capacitance of transistor M0.

[0058] Figure 4B Another exemplary switch leakage compensation delay circuit is depicted. Delay circuit 405b includes a first capacitor C0'. The first capacitor C0' is arranged between a reference node (e.g., ground potential) and a second node b0'. The first capacitor C0' is used to introduce a predetermined delay on the incoming sampling clock signal transmitted to the first node a0'. In some embodiments, capacitor C0' may be a MOS capacitor for accuracy and small area.

[0059] The other end of the capacitor C0' is connected to the first transistor M0' through the second node b0'. In this depicted example, the first transistor M0' is a P-channel metal oxide semiconductor field effect transistor (PMOSFET). In some embodiments, the first transistor M0' can be a transmission gate. The delay circuit 405b also includes a second transistor T0'. In this described example, the second transistor T0' is a PMOSFET. In some embodiments, the second transistor T0' can be a transmission gate because both the power supply and the ground need to be passed to the capacitor on the rising edge and the falling edge, respectively. In fact, due to the subthreshold effect, the second transistor T0' in the delay circuit 405b will introduce a leakage current, which can be used to compensate for the leakage current provided by the first transistor M0'. In this way, the voltage V at the second node b0' b0H Keep constant.

[0060] Figure 4C Depicted in Figure 2 The exemplary switch leakage compensation delay system implemented in FIG. The switch leakage compensation delay system 280 includes at least one delay circuit 405a connected in parallel. In each delay circuit 405a, switches M0, M1 . . . M N-1 The binary voltage signals D0, D1...D N-1 Control. Apply to switches M0, M1...M N-1 The binary voltage signals D0, D1...D N-1 , a programmable delay can be obtained. Switches M0, M1…M N-1 The leakage current introduced can pass through transistors T0, T1...T N-1 Compensation is performed. When M0, M1…M N-1 When some of the transistors are turned on, the buffer 270 can be turned off by the corresponding transistors (T0, T1...T N-1 The on-resistance of buffer 270 can be low because it is required to meet the jitter specification or conversion time in all systems implementing a time-shift DAC.

[0061] In some embodiments, the switch leakage compensation delay system 280 may include at least one delay circuit 405b connected in parallel. N-1 'Can be respectively represented by binary voltage signals D0, D1...D N-1 Control. Apply to switches M0', M1'...M N-1 The binary voltage signals D0', D1'...D N-1 ', a programmable delay can be obtained. Switches M0', M1'...M N-1The leakage current introduced can pass through transistors T0', T1'...T N-1 'Make compensation.

[0062] Figure 5A Shown Figure 3C Example experimental results of the timing diagram of the delay circuit in . In this experiment, an ADC with a sampling rate of 125MSPS was tested at the fast fast corner (FF corner). The duration of the sampling pulse is about 2ns. The falling edge of the sampling clock is important. The leakage current of switch M0 was detected at 110°C. The threshold of switch M0 is 0.25V. Figure 5A As shown, there is a significant drop after 2ns, which causes a negative spike in the voltage at node b0 and a positive spike in the transconductance of transistor M0 at the end of 2ns. The transconductance of M0 rises to 205uS (about 5k Ohm), while the voltage at a0 drops from 0.9V to 0V. Due to the low resistance value of transistor M0, transistor M0 turns on and capacitor C0 is connected between a0 and ground through the 5k resistor.

[0063] Figure 5B Shown Figure 4C Example experimental results of the timing diagram of the switch leakage compensation delay circuit in FIG. In this experiment, an ADC with a sampling rate of 125MSPS was tested at the fast fast corner (FF corner). The duration of the sampling pulse is about 2ns. The falling edge of the sampling clock is important here. The leakage current of switch M0 and the leakage current of switch T0 were detected at 110°C. The threshold voltage of switch M0 is 0.25V. Figure 5B As shown in the figure, even if there is a slight drop after 2 ns, the drop is almost invisible, and there is no negative spike at the end of 2 ns. The leakage current of switch M0 is almost the same as the leakage current of switch T0, so the leakage current of switch M0 can be offset by the leakage current of switch T0.

[0064] Figure 6A Shown Figure 3CExample simulation results of the delay circuit in . In this simulation, the basic unit of the time offset DAC is designed to provide an 8fs step size at the end of sampling. Each sub-ADC runs at 625MSPS (the overall ADC runs at 5GSPS with an interval of 8) and the sampling period is 200ps. The 100-point Monte-Carlo simulation is completed at 125MSPS (1 / 5 of the full speed). As shown in the table, the maximum sampling start is 10.08fs and the maximum sampling end is 21.79fs. The sampling end point may be significantly affected by the leakage current of switch M0. Since many closed units are turned on, the maximum step size value is more than doubled, which may result in lost time steps.

[0065] Figure 6B Shown Figure 4C The exemplary simulation results of the switch leakage compensation delay circuit in the same simulation environment are shown in FIG. Figure 4C The delay system shown has a maximum sampling end of 11.43fs, which is significantly smaller than Figure 6A This solves the mismatch problem caused by switch leakage.

[0066] Figure 7 A flow chart of an exemplary method for performing switch leakage compensation is shown. The method 700 for compensating for switch leakage includes, at 705, providing a capacitor (e.g., C0) coupled between a first node (e.g., a0) and a second node (e.g., b0). The method 700 also includes, at 710, providing a first transistor (e.g., M0), wherein the drain of the first transistor M0 is connected to the second node (b0), the source of the first transistor M0 is connected to a reference node, and the gate of the first transistor M0 is coupled to a first gate control signal (e.g., D0). The first transistor M0 modulates connectivity between the drain and source of the first transistor M0 in response to the first gate control signal D0.

[0067] The method 700 further includes, at 715, providing a second transistor (e.g., T0), wherein the drain and source of the second transistor T0 are coupled in parallel with the capacitor (C0), and the gate of the second transistor T0 is coupled to apply a voltage less than a second threshold voltage of the second transistor (T0) to the gate of the second transistor T0. At 720, dynamically monitoring whether the first transistor M0 is enabled. If the first transistor M0 is enabled by the first gate control signal D0, the method 700 further includes, at 725, providing a first leakage current I substantially drawn by the first transistor M0 through the second transistor (T0). leak1 , so that the voltage across capacitor C0 remains substantially constant.

[0068] Although various embodiments have been described with reference to the accompanying drawings, other embodiments are possible. For example, the second node b0 may be connected to V dda In some embodiments, switches M0, M1...M N-1 can be replaced by transistors with high threshold voltage. In some embodiments, M0, M1...M N-1 The length can be increased.

[0069] In some embodiments, the delay circuit can be used in other systems. For example, in a voltage-controlled delay line (VCDL), a transistor can be used as a switch. Another transistor can be introduced to compensate for the leakage current provided by the transistor in the VCDL.

[0070] While various embodiments may be implemented using reconfigurable programmable logic blocks (e.g., FPGAs), other embodiments may be implemented in fixed implementations (e.g., ASICs.) While dedicated hard-block circuitry in an ASIC implementation may not be reconfigurable once instantiated in an integrated circuit, in some embodiments, an ASIC implementation may provide a minimized platform with respect to, for example, power consumption and / or die area.

[0071] Various examples of delay circuits can be implemented using circuits, including various electronic hardware. As an example and not limitation, the hardware can include transistors, resistors, capacitors, switches, integrated circuits, and / or other circuits. In various examples, the delay circuit can include analog and / or digital logic, discrete components, traces, and / or memory circuits, which can be manufactured on a silicon substrate including various integrated circuits (e.g., FPGAs, ASICs, SoCs). In some embodiments, the delay circuit can involve the execution of pre-programmed instructions and / or software executed by a control circuit. For example, a control circuit can be used to generate a predetermined control signal to control a switch in the delay circuit.

[0072] In various embodiments, the communication system may communicate using suitable communication methods, devices, and techniques. For example, the system may communicate with compatible devices (e.g., devices capable of transmitting data to and / or receiving data from the system) using point-to-point communication, where messages are transmitted directly from the source to the receiver via a dedicated physical link (e.g., a fiber optic link, an infrared link, an ultrasonic link, point-to-point wiring, a daisy chain). The components of the system may exchange information via any form or medium of analog or digital data communication, including packet-based messaging over a communication network. Examples of communication networks include, for example, LANs (local area networks), WANs (wide area networks), MANs (metropolitan area networks), wireless and / or optical networks, and the computers and networks that form the Internet. Other embodiments may transmit messages by broadcasting to all or substantially all devices coupled together via the communication network, such as by using omnidirectional radio frequency (RF) signals. Other embodiments may transmit messages with highly directional characteristics, such as RF signals transmitted using directional (i.e., narrow beam) antennas or infrared signals optionally used with focusing optics. Other implementations are possible using appropriate interfaces and protocols, such as, by way of example and not limitation, USB 2.0, FireWire, ATA / IDE, RS-232, RS-422, RS-485, 802.11a / b / g / n, Wi-Fi, WiFi-Direct, Li-Fi, Bluetooth, Ethernet, IrDA, FDDI (Fiber Distributed Data Interface), Token Ring networks, or frequency-, time-, or code-division multiplexing techniques. Some implementations may optionally include features such as error checking and correction (ECC) for data integrity, or security measures such as encryption (e.g., WEP) and password protection.

[0073] A number of embodiments have been described. However, it should be understood that various modifications are possible. For example, advantageous results may be achieved if the steps of the disclosed techniques are performed in a different order, or if the components of the disclosed systems are combined in a different manner, or if these components are supplemented with other components. Therefore, other embodiments are within the scope of the following claims.

Claims

1. A delay circuit, characterized in that: The delay circuit comprises: a capacitor coupled between a first node and a second node and configured to introduce a first delay on an input clock signal received by the delay circuit; a first transistor having a first drain connected to the second node, a first source connected to a reference node, and a first gate configured to receive a modulated first gate control signal, wherein the first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal; and a second transistor having a second drain and a second source, the second transistor coupled in parallel with the capacitor, the second transistor further comprising a second gate coupled to apply a voltage less than a second threshold voltage of the second transistor to the second gate; Wherein, in a first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistor, a substantially constant voltage is maintained across the capacitor.

2. The delay circuit according to claim 1, wherein In the first mode, the first transistor provides a first leakage current I leak1 , the first leakage current I leak1 The second drain current I provided by the second transistor leak2 Basic match.

3. The delay circuit according to claim 1, wherein The second drain is connected to the first node, and the second source is connected to the second gate and the second node.

4. The delay circuit according to claim 1, wherein The potential of the reference node includes circuit ground potential.

5. The delay circuit according to claim 1, wherein The second gate is connected to the second node.

6. The delay circuit according to claim 1, wherein The second transistor is on the same die as the first transistor and has substantially the same size.

7. The delay circuit according to claim 1, wherein The first transistor includes an n-channel metal oxide semiconductor field effect transistor (NMOSFET).

8. The delay circuit according to claim 1, wherein The first transistor includes a p-channel metal oxide semiconductor field effect transistor (PMOSFET).

9. The delay circuit according to claim 1, wherein The first transistor includes a transmission gate.

10. The delay circuit according to claim 1, wherein The capacitor includes a metal oxide semiconductor transistor.

11. A delay system, characterized in that The system comprises: a buffer output coupled to drive a first node that provides a predetermined delay on an input clock signal; and at least one delay circuit, the at least one delay circuit being configured to introduce the predetermined delay on the input clock signal, each delay circuit of the at least one delay circuit comprising: a capacitor coupled between the first node and a corresponding second node and configured to introduce a first delay on the input clock signal; a first transistor having a first drain connected to a corresponding one of the second nodes, a first source connected to a reference node, and a first gate coupled to a corresponding first gate control signal, wherein the first transistor modulates connectivity between the corresponding first drain and the corresponding first source in response to the corresponding first gate control signal; and a second transistor having a second drain and a second source, the second transistor coupled in parallel with the corresponding capacitor, the second transistor further having a corresponding second gate coupled to apply a voltage less than a second threshold voltage of the second transistor to the second gate; In the first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the corresponding first transistor, the voltage across the corresponding capacitor is substantially constant.

12. The system according to claim 11, wherein: In the first mode, for each delay circuit in the at least one delay circuit, each of the first transistors provides a corresponding first leakage current I leak1 , the corresponding first leakage current I leak1 and the corresponding second leakage current I provided by the corresponding second transistor leak2 Basic match.

13. A delay method, characterized in that: The method comprises: providing a capacitor coupled between the first node and the second node, wherein the capacitor is configured to introduce a first delay on an input clock signal received by the delay circuit; providing a first transistor having a first drain connected to the second node, a first source connected to a reference node, and a first gate coupled to a first gate control signal, wherein the first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal; providing a second transistor having a second drain and a second source, the second transistor coupled in parallel with the capacitor, and the second transistor having a second gate coupled to apply a voltage less than a second threshold voltage of the second transistor to the second gate; and In a first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistor, the second transistor is used to provide a first leakage current I substantially drawn by the first transistor. leak1 , so that the voltage across the capacitor remains substantially constant.

14. The method according to claim 13, characterized in that In the first mode, the second transistor substantially matches the first leakage current I leak1 .

15. The method according to claim 13, characterized in that The second drain is connected to the first node, and the second source is connected to the second gate and the second node.

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