Encapsulated device and method for forming the same

Abstract

Embodiments include wafer-on-wafer bonding, where each wafer includes a seal ring structure around a die area defined in the wafer. Embodiments provide another seal ring spanning the interface between the wafers. Embodiments can extend an existing seal ring of the wafer, provide an extended seal ring structure separate from the existing seal ring of the wafer, or a combination thereof. Embodiments of the present application provide a packaged device and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packaged devices and methods of forming the same. Background Art

[0002] In wafer-to-wafer bonding technology, various methods have been developed to bond two packaging components (e.g., wafers) together. Available bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, etc. In fusion bonding, the oxide surface of a wafer is bonded to the oxide surface or silicon surface of another wafer. In eutectic bonding, two eutectic materials are placed together and applied by high pressure and high temperature. Thus, the eutectic material is melted. When the melted eutectic material solidifies, the wafers are bonded together. In direct metal-to-metal bonding, two metal pads are pressed against each other at an elevated temperature, and the interdiffusion of the metal pads causes the bonding of the metal pads. In hybrid bonding, the metal pads of two wafers are bonded to each other by direct metal-to-metal bonding, and the oxide surface of one of the two wafers is bonded to the oxide surface or silicon surface of the other wafer. Summary of the Invention

[0003] Embodiments of the present application disclose a packaged device, including: a first die, including: a first seal ring structure disposed around a periphery of the first die and in a first interconnect of the first die; a first dielectric layer located above the first interconnect; and a first seal ring extension disposed in the first dielectric layer, the first seal ring extension being aligned with and physically connected to the first seal ring structure, the first seal ring extension continuously extending around the periphery of the first die; and a second die, including: a second dielectric layer disposed below a second interconnect; and a second seal ring extension disposed in the second dielectric layer, the second seal ring extension being aligned with and physically connected to the first seal ring extension.

[0004] Embodiments of the present application provide a packaged device, including: a first die including a first seal ring around a periphery of the first die; a second die including a second seal ring around a periphery of the second die; and a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring.

[0005] Embodiments of the present application also provide a method, including: bonding a first connector of a first wafer to a second connector of a second wafer, where the first wafer includes a first sealing ring and the second wafer includes a second sealing ring; forming a third sealing ring around the first connector and the second connector, the third sealing ring spanning an interface between the first wafer and the second wafer; and singulating the first wafer and the second wafer to singulate a first package from the first wafer and the second wafer.

[0006] Embodiments of the present application provide an extended sealing ring structure on a wafer stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A schematic top view of a wafer according to some embodiments is shown;

[0009] Figures 2 to 7 Various views showing intermediate steps of forming a sealing ring extension according to some embodiments are shown;

[0010] Figures 8 to 12 Various views showing intermediate steps of forming a sealing ring extension including a sealing ring extension through hole according to some embodiments are shown;

[0011] Figure 13 A schematic top view of a wafer according to some embodiments is shown;

[0012] Figure 14 A cross-sectional view of a wafer according to some embodiments is shown;

[0013] Figures 15 to 19 Various views showing intermediate steps of forming a sealing ring extension through a wafer stack and a device package according to some embodiments are shown;

[0014] Figure 20 A cross-sectional view of a wafer according to some embodiments is shown;

[0015] Figures 21 to 25 Various views showing intermediate steps of forming a sealing ring extension through a wafer stack and a device package according to some embodiments are shown;

[0016] Figures 26 to 34 Various views showing intermediate steps of forming a sealing ring extension through a wafer stack and a device package according to some embodiments are shown;

[0017] Figures 35 to 40 Shows various views of intermediate steps of forming a seal ring extension through a wafer stack and a device package in accordance with some embodiments;

[0018] Figures 41 to 47 Shows various views of a seal ring extension through a wafer stack and a device package in accordance with some embodiments;

[0019] Figure 48 Shows device packages incorporated in different device configurations in accordance with some embodiments;

[0020] Figure 49 Shows device packages incorporated in different device configurations in accordance with some embodiments. Detailed Description

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0022] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0023] Embodiments of the present invention advantageously provide an extended seal ring structure for wafer-level packaging. The seal ring structure is used to surround the die area to provide mechanical stress support and to provide a seal to prevent moisture ingress. When a wafer is bonded to another wafer in a wafer-on-wafer process and the dies are singulated from the wafer, debris appears at the die interface. The debris spreads along the interface and exposes the bond pads, allowing moisture to penetrate. The moisture causes an increase in the ohmic resistance at the bond interface and can lead to chip scrap and / or failure. To address this issue, embodiments of the present invention utilize an extended seal ring structure to extend the seal ring structure upward through the bond interface, thereby creating a seal ring bond between the two wafers and spanning the bond interface between the two wafers. The extended seal ring provides better mechanical stress support for the bond interface and resists moisture penetration into the wafer-level bond. As described below, the extended seal ring structure can be formed by a metal-to-metal bonding process, a solder bump process, or a through-silicon via process.

[0024] Figure 1 A schematic top view of a wafer 100 according to some embodiments is shown. The wafer 100 includes dies 112, and adjacent scribe lines or streets 114 and scribe lines or streets 116, where the streets 114 and 116 separate the dies 112 from each other. The street 114 has a length direction parallel to the X direction, and the street 116 has a length direction parallel to the Y direction, which is perpendicular to the X direction. In each die 112, there may be one or more seal rings, where the outer boundary of the seal ring defines the outer boundary of the die 112. Each street 114 is located between and adjacent to two rows of dies 112, and each street 116 is located between and adjacent to two columns of dies 112. It should be noted that the wafer 100 is only intended as an example, and the sizes of the dies 112, streets 114, and streets 116, etc. may vary according to the die design.

[0025] The die 112 may include logic devices, complementary metal oxide semiconductor (CMOS) devices, microelectromechanical systems (MEMS) devices, integrated passive devices (IPD), drivers, or memory devices such as memory cells including but not limited to static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, magnetoresistive random access memory (MRAM) cells, etc. The die 112 may include other types of devices.

[0026] Figures 2 to 12 An intermediate view of a process for forming an extended seal ring structure for the die 112 is shown.

[0027] Figure 2 A cross-sectional view of the die 112 is shown. Figure 2 The cross-section of is along Figure 4A portion of the cross-section taken along line A-A, but for the purposes of discussion, the details of each view may vary. Die 112 includes a substrate 122, which may be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Group III-V compound semiconductor substrate, etc. Device region 118 is formed on or within the surface of substrate 122. Device region 118 may include active devices or passive devices such as transistors, resistors, capacitors, diodes, etc. Exemplary transistor device 108 is shown located within device region 118. In some embodiments, device region 118 may include a sealed die.

[0028] In some embodiments, interconnect structure 126 may be used to make redistribution connections between various active and passive devices. Interconnect structure 126 may include insulating layers 128 such as interlayer dielectrics (ILD) and / or intermetallic dielectric layers (IMD), and conductive components (such as metal wires 127 and vias 129) formed in alternating layers above substrate 122 using any suitable method. Interconnect structure 126 may connect various active and / or passive devices in device region 118 of substrate 122 to form a functional circuit. Insulating layer 128 may include a low-k dielectric material having a k-value, for example, less than about 4.0 or even less than 2.8. The thickness of interconnect structure 126 may be between about 0.1 μm and about 6 μm, for example, about 4 μm. Other thicknesses may be used.

[0029] More specifically, in some embodiments, interconnect structure 126 may be formed by first depositing insulating layer 128 over substrate 122 and device region 118. In some embodiments, insulating layer 128 may be formed by a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc., which may be patterned using a photolithography mask. In other embodiments, insulating layer 128 is formed by materials such as nitrides such as silicon nitride; oxides such as silicon oxide, undoped silicon glass (USG), PSG, BSG, BPSG; spin-on carbon; and so on. Insulating layer 128 may be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0030] Then, insulating layer 128 is patterned. The patterning may form openings to expose portions of substrate 122 and device region 118, which include contacts (not shown) to the devices. The patterning may be formed by an acceptable process, for example, by exposing insulating layer 128 to light when insulating layer 128 is a photosensitive material, or by etching using, for example, anisotropic etching. If insulating layer 128 is a photosensitive material, insulating layer 128 may be developed after exposure.

[0031] To form the first layer of metal wires 127 and vias 129, a seed layer (not shown) can be formed over the insulating layer 128 and in the openings through the insulating layer 128. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD or the like. Then, photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the pattern of the metal wires 127. Patterning can form openings through the photoresist to expose the seed layer. Conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process (such as using oxygen plasma or the like). Once the photoresist is removed, the exposed portions of the seed layer can be removed, for example, by using an acceptable etching process, such as wet etching or dry etching. The remaining portions of the seed layer and the conductive material form the patterns of the metal wires 127 and the vias 129. The vias 129 are formed in openings through the insulating layer 128 to, for example, the substrate 122 or the device region 118.

[0032] Then, the insulating layer 128 can be subsequently deposited over the metal wires 127 and the vias 129, and the process can be repeated as needed to form the interconnect structure 126, which forms a circuit and provides input / output to the substrate 122 and the device region 118.

[0033] When forming each layer of the interconnect structure 126, a seal ring structure 132 can also be formed. Two seal ring structures 132A and 132B are shown, but any number of seal ring structures 132 can be used. The seal ring structure 132 can be formed with a via portion 134 and a metal ring portion 136. The via portion 134 of the seal ring structure 132 can be formed simultaneously with the vias 129 discussed above and using the same process and materials. Similarly, the metal ring portion 136 can be formed simultaneously with the metal wires 127 discussed above and using the same process and materials.

[0034] In some embodiments, the via portions 134 can each include elongated trenches through the insulating layer 128, which are filled with conductive material (such as the conductive material of the vias 129) to form a vertical ring around the die 112. In other embodiments, the via portions 134 can be circular or square protrusions through the insulating layer 128 to interconnect different layers of the metal ring portion 136. The metal ring portion 136 forms a solid horizontal ring around the perimeter of the die 112.

[0035] In Figure 3 , a bonding dielectric layer 138 is deposited over the interconnect structure 126. The bonding dielectric layer 138 can be formed by depositing an insulating material. In some embodiments, the bonding dielectric layer 138 is formed of a polymer, which can be a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. In other embodiments, the bonding dielectric layer 138 is formed of materials such as nitrides such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG; and so on. The bonding dielectric layer 138 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. The bonding dielectric layer 138 can have a thickness between about 0.01 μm and 2 μm, for example, a thickness of about 0.9 μm. Other thicknesses can be used.

[0036] The bonding dielectric layer 138 is patterned to form an opening 139 and an opening 151 therein, exposing the top metal wire 127 of the interconnect structure 126 and the top metal layer of the metal ring portion 136 of the seal ring structure 132, respectively. The patterning can be performed by an acceptable process, such as by exposing the bonding dielectric layer 138 to light when the bonding dielectric layer 138 is a photosensitive material, or by etching using, for example, anisotropic etching. If the bonding dielectric layer 138 is a photosensitive material, the bonding dielectric layer 138 can be developed after exposure.

[0037] Figure 4 A top view of an enlarged portion of the wafer 100 after the formation of the opening 139 and the opening 151 is shown. As Figure 4 shown, the top metal layer of the metal ring portion 136 of the seal ring structure 132 and the top metal layer of the metal wire 127 are exposed through the bonding dielectric layer 138. The opening 139 is shown as a circle located above the metal wire 127, and the opening 151 is shown as an annular opening located above the seal ring structure 132.

[0038] In Figure 5 , a conductive material 140 such as copper, titanium, titanium nitride, aluminum, etc., or a combination thereof can be deposited in the opening 139 and the opening 151 by a suitable deposition process such as PVD, CVD, or a plating process (such as electroless plating, electroplating, etc.). The deposition process can fill both the opening 139 and the opening 151 simultaneously. An optional conductive seed layer can be first deposited in the opening 139 and the opening 151 by a suitable process such as PVD. An optional barrier layer can also be deposited in the opening 139 and the opening 151 before the optional seed layer. The optional barrier layer can be deposited using any suitable process and is used to inhibit the diffusion of the conductive material into the surrounding bonding dielectric layer 138.

[0039] InFigure 6 In this case, excess material of the conductive material 140 can be removed from above the bonding dielectric layer 138 to form a bonding pad 142 and a seal ring extension 152. Any suitable process can be used to remove the excess material of the conductive material 140, such as a planarization process, such as a CMP process. After the removal process, the upper surfaces of the bonding pad 142 and the seal ring extension 152 can be flush with the upper surface of the bonding dielectric layer 138.

[0040] Figure 7 A top view of an enlarged portion of the wafer 100 after forming the bonding pad 142 and the seal ring extension 152 is shown. As Figure 7 shown, the bonding pads 142 are formed in a regular pattern, however, any distribution of the bonding pads 142 can be used. The seal ring extension 152 fills the opening 151 and is shown as an annular structure located above the seal ring structure 132 (shown in dashed lines).

[0041] Figures 8 to 15 The formation of an optional bonding pad via hole 146 is shown. By using the bonding pad via hole 146, it is possible to allow the use of integrated test pads, high-density microcapacitors, and other structures disposed within the dielectric layer 144 of the bonding pad via hole 146. The bonding pad 142 can be electrically connected to the metal wire 127 and the via hole 129 through the corresponding bonding pad via hole 146 for each active bonding pad 142. The bonding pad via hole 146 and its formation described below can be incorporated into any other embodiments described below, but are omitted from the figures for simplicity.

[0042] In Figure 8 this case, the dielectric layer 144 can be formed above the interconnect structure 126. In some embodiments, the dielectric layer 144 is an oxide layer, which can include silicon oxide. In other embodiments, the dielectric layer 144 includes other silicon and / or oxygen-containing materials such as SiON, SiN, etc., and can be formed by any suitable deposition technique. The dielectric layer 144 can be deposited to any suitable thickness, such as between 0.01 μm and about 1000 μm.

[0043] In Figure 9In [the figure], the dielectric layer 144 is patterned to form openings 145 and 155 therein, exposing the top metal wire 127 of the interconnect structure 126 and the top metal layer of the metal ring portion 136 of the seal ring structure 132, respectively. The patterning can be performed by any acceptable process. In one embodiment, a photolithography mask is deposited over the dielectric layer 144, patterned using photolithography techniques, and used as a mask to etch the openings 145 and 155 by using, for example, anisotropic etching. In some embodiments, the opening 155 may include separate through-holes exposing separate regions of the metal ring portion 136; while in other embodiments, the opening 155 may include trenches formed to expose a continuous region of the metal ring portion 136 of the seal ring structure 132.

[0044] In Figure 10 [the figure], metal vias are formed by performing a suitable deposition process such as PVD, CVD or a plating process such as electroless plating, electroplating, etc. on an optional seed layer first deposited in the openings, and depositing a conductive material 147 such as copper, titanium, titanium nitride, aluminum, etc., or a combination thereof, in the openings 145 and 155. The deposition process can fill both the openings 145 and 155 simultaneously. The optional conductive seed layer can be first deposited in the openings 145 and 155 by a suitable process such as PVD. An optional barrier layer can also be deposited in the openings 145 and 155 before the optional seed layer.

[0045] In Figure 11 [the figure], the excess material of the conductive material 147 can be removed from above the dielectric layer 144 to form the bond pad via 146 and the seal ring extension via 156. Any suitable process can be used to remove the excess material of the conductive material 147, such as a planarization process, such as a CMP process. After the removal process, the upper surfaces of the bond pad via 146 and the seal ring extension via 156 can be flush with the upper surface of the dielectric layer 144.

[0046] Figure 12 Shown are a bond pad 142 and a seal ring extension 152 disposed above the bond pad via 146 and the seal ring extension via 156, respectively. The bond pad 142 and the seal ring extension 152 can be formed using the processes and materials described above with respect to Figures 3 to 6 [the figure], where like reference numerals refer to like elements. As mentioned above, the contents included in the bond pad via 146 and the seal ring extension via 156 can be added to other embodiments below, but are not shown for simplicity.

[0047] Figures 13 to 14Shows die 212 according to some embodiments. Similar features of die 212 are labeled with similar identifiers as used above for die 112, except modified to be led by the number 2. Although die 212 is not shown as having bond pad vias such as Figure 12 bond pad vias of bond pad vias 146, it should be understood that bond pad vias may be present in some embodiments. Figure 13 Shows a schematic top view of wafer 200 according to some embodiments. Wafer 200 includes die 212, and adjacent scribe lines or streets 214 and 216, where streets 214 and 216 separate die 212 from each other. Street 214 has a length direction parallel to the X direction, and street 216 has a length direction parallel to the Y direction, which is perpendicular to the X direction. In each die 212, there may be one or more seal rings, where the outer boundary of the seal ring defines the outer boundary of die 212. Each street 214 is located between and adjacent to two rows of die 212, and each street 216 is located between and adjacent to two columns of die 212. It should be noted that wafer 200 is only by way of example, and the sizes of die 212, streets 214, 216, etc. may vary according to die design.

[0048] In some embodiments, die 212 may be a device similar or identical to die 112, and may have similar dimensions thereto, including the thickness of layers, etc. In some embodiments, die 212 may be different from die 112, and may include logic devices or memory devices such as memory cells including but not limited to static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, magnetoresistive random access memory (MRAM) cells, etc. Die 212 may include other types of devices.

[0049] Figure 14 Shows a cross-sectional view of die 212. As mentioned above, similar features of die 212 compared to die 112 are labeled with similar reference numerals. The processes and materials used to form die 212 may be the same as those used for die 112.

[0050] Figure 15Illustrated is a process of bonding wafer 200 to wafer 100 to bond die 212 to die 112 to form a wafer stack 290. For simplicity, optional bond pad vias 146 and bond pad vias for die 212 are omitted from the view. Although wafer-to-wafer bonding is shown, it should be understood that the bonding can be wafer-to-wafer where two wafers are directly bonded together, chip-to-chip where two singulated chips (or dies) are directly bonded together, or chip-to-wafer where one or more chips (or dies) are directly bonded together, wherein the bonding dielectric layer 138 of one die is fusion bonded to the bonding dielectric layer 238 of another die, the bond pads 142 of die 112 are bonded to the bond pads 242 of die 212, and the seal ring extensions 152 of die 112 are bonded to the seal ring extensions 252 of die 212, without using any eutectic materials such as solder. For example, in wafer-to-wafer bonding, wafer 100 is bonded to wafer 200 by hybrid bonding, wherein die 112 is bonded to die 212 before singulation. In the hybrid bonding of wafers 100 and 200, the bonding dielectric layer 138 is bonded to the bonding dielectric layer 238 by fusion bonding, the metal of bond pads 142 is bonded to the metal of bond pads 242 by metal-to-metal bonding, and the metal of seal ring extensions 152 is bonded to the metal of seal ring extensions 252 by metal-to-metal bonding. Chip-to-chip bonding or chip-to-wafer bonding is performed in a similar manner, except for the method of aligning the chips or the chips and the wafers.

[0051] The bonding process can include pre-bonding and annealing. During pre-bonding, a small pressure can be applied to press wafers 100 and 200 against each other. Pre-bonding can be performed at room temperature (e.g., between about 21 °C and about 25 °C), although higher temperatures can be used. After pre-bonding, the bonding dielectric layers 138 and 238 are bonded to each other. The bonding strength is increased in a subsequent annealing step, wherein the bonded wafers 100 and 200 are annealed at a temperature, for example, between about 300 °C and about 400 °C.

[0052] The annealing can be performed for a time period between about 1 hour and 2 hours. In an exemplary embodiment, as the temperature increases, the OH bonds in the bonding dielectric layer 138 and the bonding dielectric layer 238 break to form strong Si-O-Si bonds, so that wafers 100 and 200 are bonded to each other by fusion bonding (and by van der Waals forces). Additionally, during annealing, the metals (such as copper) in the bond pads 142 and the bond pads 242, and the metals in the seal ring extensions 152 and the seal ring extensions 252 diffuse into each other, thereby also forming metal-to-metal bonding. Thus, the resulting bond between wafers 100 and 200 is a hybrid bond.

[0053] Figure 16a and Figure 16b is Figure 15 an enlarged view of a portion of, as indicated by the dashed box in Figure 15 . In Figure 16a , bonding pads 142 and 242 are shown bonded together in a one-to-one correspondence. Similarly, seal ring extensions 152 and seal ring extensions 252 are also bonded together to form a continuous seal ring through the bonding interface of each of wafers 100 and 200.

[0054] As Figure 16a shown, the bonding does not need to occur in a perfectly aligned manner, and the embodiment advantageously allows a lateral offset d1 between bonding pads 142 and 242 and / or seal ring extensions 152 and 252. The lateral offset d1 is not greater than the minimum bonding pad pitch so as not to interfere with adjacent bonding pads, and is also not greater than half of the minimum bonding pad size to ensure good connectivity between the bonding pads. For example, if the pitch of the bonding pads is 2 μm and the size of the bonding pads is 1 μm, the lateral offset d1 can be between 0 and 0.5 μm. If the bonding pad pitch is 1 μm and the bonding pad size is 2 μm, the lateral offset d1 can be between 0 and 1 μm. The lateral offset d1 also allows for other process variations and thus does not require perfect alignment.

[0055] Figure 16b Similar to Figure 16a the embodiment shown, except that seal ring extensions 252 extend from the same seal ring structure 232, while seal ring extensions 152 extend from different seal ring structures 132A and 132B. This illustrates that the embodiment can flexibly extend the seal ring structures (such as seal ring structures 132 and 232) using different configurations. For example, in some embodiments, some seal ring structures can extend while other seal ring structures do not extend.

[0056] The above-discussed embodiments can be implemented when the die sizes are the same such that the edges of two dies 112 and 212 of wafers 100 and 200 are aligned respectively. Similar processes can be used to provide bonding of two dies of different sizes, for example, aligning at least one seal ring structure 232 of die 212 with seal ring structure 132 of die 112.

[0057] In Figure 17In [the figure], the wafer stack 290 is singulated into packages 295. The packages 295 can be singulated using any suitable cutting technique 292. The cutting technique 292 can include dry etching, wet etching, anisotropic etching, or plasma etching using a suitable etchant. The cutting technique 292 can include a laser making multiple passes to laser dice the packages 295 from each other. The cutting technique 292 can include a mechanical process such as a dicing saw set to cut to a desired depth. Combinations of the cutting techniques 292 discussed above can also be used. Singulation occurs through the non-packaged regions (outside the packaged regions, see, for example Figure 1 the scribe lines 114 and 116 and Figure 13 the scribe lines 214 and 216). The singulation cuts through the processed wafer stack 290 to obtain the packages 295. Due to the seal ring extensions 152 and 252, debris generated during singulation that could propagate to the bonding interfaces or bonding pads 142 and 242 is reduced or eliminated.

[0058] Figure 18 A singulated package 295 with seal ring extensions 152 and 252 is shown. The seal ring extensions 152 and 252 are used to reduce the propagation of debris and prevent moisture and contaminants from seeping along the bonding interface and affecting the bonding of the bonding pads 142 and 242.

[0059] Figure 19 A plan view of the package 295 is illustrated. Various illustrated elements may not actually be visible in the final package, but are illustrated in this view for context purposes. The seal ring extension 152 surrounds the bonding pad 142 (and the bonding pad via 146, if used). The seal ring extension 152 and the seal ring structures 132A and 132B extend around the periphery of the die 112. Similarly, the seal ring extension 252 surrounds the bonding pad 242 (and the corresponding bonding pad via, if used). The seal ring extension 252 and the seal ring structures 232A and 232B extend around the periphery of the die 212. The shape shown is rectangular, but can include any suitable shape and can have rounded corners or dog-ear corners, etc.

[0060] Figures 20 to 25 Various views associated with eutectic seal ring extensions according to some embodiments are shown. Figure 20 The wafer 300 of [the figure] can be formed using processes and materials similar to those discussed above with respect to Figure 3 [the figure], where like reference numerals refer to like elements, except that those beginning with 1 are replaced with those beginning with 3. Although not shown for simplicity, in this embodiment, processes and materials similar to those discussed above can also be used to form those discussed above with respect to Figure 12The bonding pad via 146 shown.

[0061] After forming the openings 139 and 151 (see Figure 3 ), bump materials such as solder or eutectic materials can be formed in the openings 139 and 151 to form bumps 362 above the interconnect 326, and seal ring extensions 364 above the seal ring structure 336, as Figure 20 shown. In some embodiments, a under-bump metallization layer or seed layer can be formed in the openings 139 and 151 before forming the bumps 362 and seal ring extensions 364. The under-bump metallization layer or seed layer can be formed by: forming a photolithography mask layer above the insulating layer 338, forming openings corresponding to the openings 139 and 151 in the photolithography mask layer, and then using a suitable deposition process such as ALD, PVD, or CVD to form the under-bump metallization layer or seed layer in the openings 139 and 151 and above the photolithography mask layer. Then the photolithography mask layer can be removed, thereby removing the unwanted portions of the under-bump metallization layer or seed layer.

[0062] Next, the bumps 362 and seal ring extensions 364 can be formed simultaneously using any suitable process. For example, the bumps 362 and seal ring extensions 364 can be formed by solder printing techniques, plating techniques, board transfer techniques, etc. The materials for the bumps 362 and seal ring extensions 364 can include any suitable eutectic materials, such as solder, high-lead bumps, lead-free bumps, tin-lead eutectic bumps, aluminum-germanium eutectic bumps, etc., or combinations thereof. After deposition, the bumps 362 and seal ring extensions 364 can be reflowed to bond with the seed layer, the under-bump metallization layer, or the metal wires 327 of the interconnect 326.

[0063] In Figure 21 , the wafer 400 can be bonded to the wafer 300 to form a wafer-on-wafer stack 490. According to some embodiments, the wafer 400 can be prepared in a manner similar to the wafer 300, where like reference numerals refer to like elements, except that the 3-lead replacements are replaced with 4-lead. In other embodiments, the wafer 200 can be used. The wafer 400 can be placed on the wafer 300, and the eutectic materials of the bumps 362 (and corresponding bumps 462) are reflowed to form a continuous connection of the merged bumps 466 (see Figure 22a ), and the eutectic materials of the seal ring extensions 364 (and corresponding seal ring extensions 464) are reflowed to form a continuous seal ring extension 468 (see Figure 22a ).

[0064] Figure 22a and Figure 22b is Figure 21An enlarged view of a portion of, as indicated by the dashed box in Figure 21 . In Figure 22a , bumps 362 and 462 are shown engaged together in a one-to-one correspondence to form a merged bump 466. Similarly, seal ring extensions 364 and seal ring extensions 464 are likewise engaged together to form a continuous seal ring extension 468 through the bonding interface of each of wafers 300 and 400.

[0065] Figure 21 , Figure 22a , and Figure 22b It is also shown that, in some embodiments, after bonding, a gap between wafer 300 and wafer 400 may be retained between the two wafers. The gap or void is sealed by seal ring extension 468 to keep contaminants and moisture out of the gap, thus eliminating the need for underfill. Wafers 300 and 400 may be laterally offset by a distance d2, allowing for slight misalignment or other process variations. The lateral offset d2 may not be greater than the minimum bond pad pitch so as not to interfere with adjacent bond pads, and may also not be greater than half of the minimum bond pad size to ensure good connectivity between bond pads. For example, if the pitch of the pads is 2 μm and the size of the bond pads is 1 μm, the lateral offset d2 may be between 0 and 0.5 μm. If the bond pad pitch is 1 μm and the bond pad size is 2 μm, the lateral offset d2 may be between 0 and 1 μm.

[0066] Figure 22b Shows an enlarged view of the dashed portion of Figure 21 according to some embodiments. In Figure 22b , seal ring structures 332A and 332B are joined to a single seal ring structure 432 of wafer 400. The embodiments advantageously provide the ability to flexibly join seal ring structures in one wafer to another wafer through seal ring extensions. Different combinations of configurations can be used to extend different seal ring structures to each other. Moreover, in some embodiments, some seal ring structures may extend without seal ring extensions.

[0067] In Figure 23 , the wafer stack 490 is singulated into packages 495. The packages 495 can be singulated using any suitable dicing technique 292 discussed above.

[0068] Figure 24Illustrated is a singulated package 495 having a seal ring extension 468. The seal ring extension 468 is used to reduce the propagation of debris and prevent moisture and contaminants from infiltrating along the bonding interface and / or between the two wafers, thereby affecting the bonding of bumps 362 and 462. In some embodiments, an underfill material may be used between wafer 300 and wafer 400 after singulation to fill the gap to the first seal ring extension 468.

[0069] Figure 25 A plan view of package 495 is shown. Various illustrated elements may not actually be visible in the final package, but are illustrated in this view for context purposes. The combined seal ring extension 468 surrounds the combined bumps 466 (and the bond pad vias of each wafer, if used). The seal ring extension 468 extends along the periphery of die 312 with seal ring structures 332A and 332B. Similarly, the seal ring extension 468 extends along the periphery of die 412 with seal ring structures 432A and 432B. The shape shown is rectangular, but may include any suitable shape and may have rounded corners or dog-ear corners, etc.

[0070] Figures 26 to 33 An intermediate view of a process for forming an extended seal ring structure 660 extending through a wafer stack is shown according to some embodiments. Figure 26 Illustrated is a wafer stack 690 that includes a wafer 500 that is bonded to a wafer 600. In some embodiments, wafers 500 and 600 each resemble wafer 100, where like reference numerals refer to like elements, except that the 1 leading is replaced with 5 and 6 leading respectively. However, the seal ring structures 532 and 632 do not include seal ring extensions. In such embodiments, wafers 500 and 600 are bonded together using hybrid bonding, such as described above with respect to Figure 15 and dielectric layer 538 is fusion bonded to dielectric layer 638, and bond pad 542 is directly bonded to bond pad 642 by metal-to-metal bonding. In other embodiments, wafers 500 and 600 each resemble wafer 300, and wafer stack 690 is bonded together using bumps (see Figure 32 , discussed below) that are reflowed to effect the bonding. However, in such embodiments, seal ring extensions (such as Figure 20 364) are not included.

[0071] Although two wafers are depicted in wafer stack 690 of Figure 26 , it should be understood that the following description may apply to wafer stacks that include additional wafers (including 3 to 8 or more wafers). Figure 26The wafers therein are shown in a face-to-face bonding configuration. It should also be understood that the following description can also be applied to wafers bonded in a face-to-back bonding configuration. That is, wafer 500 can be flipped such that the vias (not shown) are exposed through substrate 522, and the interconnects formed thereon are then bonded to the front side of wafer 600.

[0072] A lateral offset can be observed between wafers 500 and 600, similar to that described and discussed above with respect to Figure 16a The offset can allow for a margin for bonding wafers 500 and 600 together, and can allow for other process variations, such as variations in bond pads or bump patterns.

[0073] In Figure 27 , the top wafer 600 is thinned to remove the excess portion of substrate 622. The thinning can be implemented using any suitable planarization process (such as grinding process, chemical mechanical polishing process, etching process, etc., or a combination thereof). In some embodiments, the thinning can expose vias formed in the substrate that are connected to interconnect 626. In other embodiments, the vias can be formed to pass through substrate 622 to connect to interconnect 626 after thinning. Such vias can be formed using any suitable process (e.g., a process such as that for forming and filling opening 655, described below) to etch an opening through substrate 622 and deposit a metal fill in the opening.

[0074] After thinning the top wafer 600, opening 655 is etched through wafer 600 and at least partially through wafer 500, including through interconnect 526. If additional wafers are interposed between the top wafer 600 and wafer 500, opening 655 is etched through each of the intermediate wafers. In some embodiments, opening 655 can further extend partially or entirely (e.g., if connected to a carrier (not shown)) through substrate 522. Opening 655 can be formed using any suitable patterning technique. In some embodiments, a mask is formed over substrate 622 and patterned to form an opening therein corresponding to opening 655. Then, the opening in the mask is transferred to each layer of the wafer stack 690 by a dry etching process, such as by reactive ion etching or plasma etching. The mask used can include multiple layers. By thinning the top wafer 600 before forming opening 655, the aspect ratio of opening 655 can be increased.

[0075] Opening 655 includes a trench that travels around the peripheries of die 512 and die 612. As Figure 27As indicated, the opening 655 may be located outside the seal ring structures 532 and 632. In some embodiments, the opening 655 may be located between the seal ring structures 532A and 532B and between the seal ring structures 632A and 632B. In other embodiments, the opening 655 may be located between the seal ring structure 532 and the bonding pad 542 and between the seal ring structure 632 and the bonding pad 642. In some embodiments, combinations of these arrangements may occur.

[0076] In Figure 28 it, an extended seal ring structure 660 is formed by depositing a filling material in the opening 655. In some embodiments, the filling material may be a conductive material, such as those discussed above with respect to the bonding pad vias 146. In other embodiments, the filling material may be an insulating material, such as ceramics, nitrides, or oxides. The selected material may exhibit resistance to mechanical stress and moisture. The extended seal ring structure 660 may be formed by a suitable deposition process, such as by PVD, CVD, or plating techniques. When the material of the extended seal ring structure 660 is a conductive material, a seed layer and / or a barrier layer may be used, such as those discussed above with respect to the bonding pad vias 146. During deposition, the material of the extended seal ring structure 660 may overfill the opening 655, and then a removal process may be implemented to remove the excess portion of the material of the extended seal ring structure 660 and to make the upper surface of the extended seal ring structure 660 flush with the (current) upper surface of the substrate 622. The removal process may be any suitable process, such as a grinding process, a CMP process, an etch-back process, etc., or any combination thereof.

[0077] In Figure 29 it, an optional bonding pad 670 may be added to the top of the extended seal ring structure 660. The optional bonding pad 670 may be formed using processes and materials similar to those discussed above with respect to the pad 142. The bonding pad 670 may be used to electrically ground the extended seal ring structure 660.

[0078] In Figure 30 it, the wafer stack 690 is singulated into packages 695. The packages 695 may be singulated using any suitable dicing technique 292 described above.

[0079] Figure 31 A singulated package 695 with an extended seal ring structure 660 is shown. The extended seal ring structure 660 is used to reduce the spread of debris and to prevent moisture and contaminants from infiltrating along the bonding interface and / or between the two wafers and affecting the bonding of the bonding pads 542 and 642.

[0080] Figure 32Shows the above-mentioned alternative embodiments, where wafers 500 and 600 are similar to wafer 300 and have bumps 562 and 662 respectively. In Figure 33 the singulated package 695 in, the bumps 562 and 662 are connected together to form a continuous connector from wafer 600 to wafer 500 (see Figure 30 ). In some embodiments, such as Figure 32 depicted in, the air gap 696 can be surrounded by an extended seal ring structure 660. As seen in the left view of the extended seal ring structure 660, in such an embodiment, a portion of the extended seal ring structure 660 can laterally extend into the air gap 696 between the dielectric layers 538 and 638. In some embodiments, the extended portion 661 of the extended seal ring structure 660 can extend above the dielectric layer 538. In embodiments where the extended seal ring structure 660 is an insulating material, the extended portion 661 can extend into the air gap 696 and contact the bump 562 and / or the bump 662. In some embodiments, the extended seal ring structure 660 may not significantly laterally extend into the air gap 696. In some embodiments, when making the opening 655 (see Figure 27 ), underfill material can be deposited between wafer 500 and wafer 600. In Figure 32 the embodiment shown, the underfill can fill the gap and surround the connector between wafers 500 and 600. In some embodiments, the underfill material can also serve as the extended seal ring structure 660. In other embodiments, the opening 655 can be modified or completed after applying the underfill material. The extended seal ring structure 660 is used to reduce debris propagation and prevent moisture and contaminants from infiltrating along the bonding interface and / or between the two wafers and affecting the bonding of the bumps 562 and 662.

[0081] Figure 33 Shows the above-mentioned embodiment regarding Figure 29 which includes a bonding pad 670 formed above the extended seal ring structure 660. The bonding pad 670 can be used as a ground point or for other purposes in the subsequently formed package.

[0082] Figure 34A plan view of the package 695 is illustrated. Various illustrated elements may not be visible in the final package, but are illustrated in this view for context purposes. The extended seal ring structure 660 surrounds the combined bond pads 542 and 642 (or bumps 562 and 662, if used). The extended seal ring structure 660 extends around the periphery of the die 512 with the seal ring structures 532A and 532B. Similarly, the extended seal ring structure 660 extends around the periphery of the die 612 with the seal ring structures 632A and 632B. The shape shown is rectangular, but may include any suitable shape and may have rounded corners or dog-ear corners, etc. As mentioned above, although the extended seal ring structure 660 is depicted as surrounding the seal ring structures 532 and 632, in some embodiments, conversely, some or all of the seal ring structure 532 may surround the extended seal ring structure 660.

[0083] Figures 35 to 40 An intermediate view of a process for forming an extended seal ring structure 660 (see Figure 36 ) extending through the wafer stack 690 is shown according to some embodiments. Figure 35 A wafer stack 690 is shown that includes a wafer 500 bonded to a wafer 600. One or more intermediate wafers may be interposed between the wafer 500 and the wafer 600. The wafer stack 690 may be similar to the wafer stack 690 discussed above with respect to Figures 26 to 34 where like reference numerals refer to like elements.

[0084] In Figure 35 , a process and materials similar to those discussed above with respect to Figure 27 are used to thin the substrate of the wafer 600. Next, an opening 655 is formed through the wafer 600 and at least partially through the wafer 500. In Figure 35 , the seal ring structures 532 and 632 are at least partially exposed in the formation of the opening 655. During the formation of the opening 655, the seal ring structure 532 may be retained and suspended in the opening 655, or may be partially removed by the process used to create the opening 655.

[0085] In Figure 36 , a filling material is deposited to form the extended seal ring structure 660. The filling material may use a process and materials similar to those discussed above with respect to Figure 28The processes and materials discussed are similar to those used to deposit the processes and materials. When the fill material is formed in the opening 655, the fill material contacts the seal ring structures 532 and 632, such as 532A and 632A. When the fill material is a conductive material, the extended seal ring structure 660 is electrically connected to the seal ring structures 532 and 632. In some embodiments, these elements can be electrically grounded and thus can be used as a ground point.

[0086] Figure 36 Also shown is the singulation of the wafer stack 690 into the package 695. Singulation can be performed by any suitable singulation process (e.g., the cutting technique 292 discussed above with respect to Figure 30 ).

[0087] In Figure 37 , one embodiment of the package 695 includes bond pads 542 and 642 that are directly bonded to each other by a metal-to-metal bond, and dielectric layers 538 and 638 that are fused to each other. The extended seal ring structure 660 contacts the seal ring structures 532 and 632 and completely penetrates the wafer 600 and at least partially through the wafer 500.

[0088] In Figure 38 , one embodiment of the package 695 includes bumps 562 and 662 that merge together upon reflow. The resulting package 695 can have an air gap 696 between the two dies. The extended seal ring structure 660 seals the air gap 696 to prevent unwanted moisture intrusion, so no underfill is required between the two dies. In some embodiments, a portion 661 of the extended seal ring structure 660 can extend laterally into the air gap 696, as discussed above. In some embodiments, when the opening 655 is fabricated (see Figure 35 ), an underfill material can be deposited between the wafers 500 and 600. In the embodiment shown in Figure 38 , the underfill can fill the gap and surround the connector between the wafers 500 and 600. In some embodiments, the underfill material can also serve as the extended seal ring structure 660. In other embodiments, the opening 655 can be retrofitted or completed after the application of the underfill material.

[0089] In Figure 39 , one embodiment of the package 695 includes an optional bond pad 670 formed above the extended seal ring structure 660. The bond pad 670 can be used as a ground point or for other purposes in a subsequently formed package.

[0090] Figure 40A plan view of a package 695 according to some embodiments is shown. Various illustrated elements may not be visible in the final package, but are illustrated in this view for context purposes. An extended seal ring structure 660 surrounds the combined bond pads 542 and 642 (or bumps 562 and 662, if used). The extended seal ring structure 660 extends around the periphery of die 512 together with seal ring structures 532A and 532B, and contacts one or more of the seal ring structures 532A and 532B. Similarly, the extended seal ring structure 660 extends around the periphery of die 612 together with seal ring structures 632A and 632B, and contacts one or more of the seal ring structures 632A and 632B. The illustrated shape is rectangular, but may include any suitable shape and may have rounded corners or dog-ear corners, etc. Although the extended seal ring structure 660 is depicted as surrounding the seal ring structures 532 and 632, in some embodiments, conversely, part or all of the seal ring structure 532 may surround the extended seal ring structure 660.

[0091] Figure 40 A top view of an optional bond pad 670 formed on the extended seal ring structure 660 according to an embodiment utilizing any of the extended seal ring structures 660 discussed above is also shown. As Figure 40 shown, the bond pad 670 may be a circular pad, a rectangular pad, etc. In some embodiments, the bond pad 670 may extend along the entire length of the extended seal ring structure 660 and form a continuous ring.

[0092] Figures 41 to 47 A combination of features of the previously shown embodiments according to some embodiments is shown. Figure 41 A wafer stack 890 is shown, which includes a wafer 700 bonded to a wafer 800. In some embodiments, each of wafers 700 and 800 is similar to wafer 100, where like reference numerals refer to like elements, except that the 1 leading is replaced with 7 and 8 leading respectively. In addition to seal ring extensions 752 and 852, wafers 700 and 800 also include an extended seal ring structure 860 (see the extended seal ring structure 660 above). The various illustrated elements may be formed using the materials and processes discussed above with respect to their corresponding elements.

[0093] In Figure 42 it, an optional bond pad 870 (see the bond pad 670 above) is formed above the extended seal ring structure 860. In Figure 43In, the extended seal ring structure 860 is formed such that it contacts the seal ring structures 732 and 832 in each of the wafers 700 and 800, respectively. Optional bonding pads 870 may also be included in this embodiment. Both the extended seal ring structure 860 that contacts the seal ring structure 832 and the extended seal ring structure 860 that does not contact the seal ring structure 832 may be included in one embodiment, including being on the same side of the package 895 and may or may not be made of the same material.

[0094] In Figure 44 each of the wafers 700 and 800 corresponds to the wafer 300 discussed above, where like reference numerals refer to like elements, except that the leading 3 is replaced with a leading 6 for the wafer 600 and a leading 7 for the wafer 700. The wafer stack 890 includes a seal ring extension 868, which is made by bonding to the bump 864 of the bump 764. Additionally, the wafer stack 890 includes an extended seal ring structure 860, which may be similar to those discussed above with respect to Figure 32 or Figure 37 . Optional bonding pads 870 are included, but may be omitted. The left extended seal ring structure does not contact the seal ring structures 732 and 832, for example, as discussed above with respect to Figure 32 , but the right extended seal ring structure 860 is shown contacting the seal ring structure 832, for example, as discussed above with respect to Figure 37 . Both the extended seal ring structure 860 that contacts the seal ring structure 832 and the extended seal ring structure 860 that does not contact the seal ring structure 832 may be included in the same embodiment, including being on the same side of the package 895 and may or may not be made of the same material. Figure 44 The embodiment shown also includes a gap 896, which may have a bottom fill deposited therein, for example, as described for the gap 696 above with respect to Figure 32 or Figure 38 .

[0095] In Figure 45 taking the wafer stack 890 of Figure 41 as a representative, the wafer stack 890 is singulated to form the package 895. The singulation process may use a cutting technique 292 to cut the wafer stack 890 into the package 895. The cutting technique 292 may be any of the techniques discussed previously (see, for example, Figure 17 ).

[0096] In Figure 46In [the figure], the package 895 includes an extended seal ring structure 860 in addition to the seal ring extensions 752 and 852. The simultaneous use of the extended seal ring structure 860 and one or more seal ring extensions 752 and 852 can provide enhanced protection against debris propagation at the joint between the bonding pads 742 and 842 (or Figure 44 the bumps 762 and 862), as well as humidity or environmental contamination.

[0097] Figure 47 A plan view of the package 895 according to some embodiments is shown. Various illustrated elements may not be visible in the final package, but are illustrated in this view for context purposes. The extended seal ring structure 860 surrounds the bonding pads 742 and 842 (or the bumps 762 and 862, if used). The extended seal ring structure 860 extends around the periphery of the die 712 side by side with the seal ring structures 732A and 732B. The extended seal ring structure 860 can contact one or more of the seal ring structures 732A and 732B. Similarly, the extended seal ring structure 860 extends around the periphery of the die 812 side by side with the seal ring structures 832A and 832B, and can also contact one or more of the seal ring structures 832A and 832B. The shape shown is rectangular, but can include any suitable shape, and can have rounded corners or dog-ear corners, etc. Although the extended seal ring structure 860 is depicted as surrounding the seal ring structures 732 and 832, in some embodiments, conversely, part or all of the seal ring structure 732 can surround the extended seal ring structure 860.

[0098] The seal ring extensions 752 and 852 surround the bonding pads 742 and 842 respectively, and are formed on the seal ring structures 732 and 832 in each of the wafers 700 and 800.

[0099] Figure 48 and Figure 49 A packaged device is shown that utilizes a package 295 / 495 / 695 / 895 as disclosed herein to connect to another device or structure 905, such as a printed circuit board, a system on an integrated chip package, a chip on wafer on a substrate configuration, or an integrated fan-out package. In Figure 48 [the figure], the package 295 / 495 / 695 / 895 can have a front connector 910 formed thereon, which connects to one or more devices in the package 295 / 495 / 695 / 895. Then, the package 295 / 495 / 695 / 895 can be flipped and bonded to the structure 905 through the connector 910 to form a packaged device 925. In some embodiments, the front connector 910 can electrically connect the extended seal ring structure 860 to the structure 905.

[0100] In Figure 49 , the package 295 / 495 / 695 / 895 can have pads 970 formed on the top surface and connected to one or more devices within the package 295 / 495 / 695 / 895. The package can then be adhered to the structure 905. Wire bonds 960 can be used to connect the pads 970 to pads 965 formed in the structure 905. In some embodiments, wire bonds 960 can be used to electrically connect the extended seal ring structure 860 to the structure 905.

[0101] The seal rings are used to provide structural and mechanical support to resist stresses from warping and peeling. When bonding one wafer to another wafer, each seal ring typically functions separately. Some embodiments of the present disclosure advantageously extend the seal rings of the wafers to the bonding surface and bond the seal ring of one wafer to the seal ring of another wafer when the wafers are bonded together in a wafer-to-wafer bond. The advantages of the extended seal rings are that they provide a strong stress handling ability between the two wafers to resist peeling of the wafers due to warping. The extended seal rings also have the advantage that they can completely seal the bonding interface between the two wafers where the active connectors are bonded together. The risk of humidity and contaminant penetration is greatly reduced, thereby providing a more robust and resilient device with fewer chances of failure. At the same time, since absolute precision is not required, the seal rings can tolerate minor offsets or misalignments, so a cost-saving wafer-to-wafer bonding process can still be used for mass production. Some embodiments of the present disclosure advantageously form an extended seal ring structure after wafer-to-wafer bonding. The extended seal ring structure forms trenches through the upper wafer and through all bonding interfaces and fills the trenches with seal ring material. The extended seal ring structure is used to prevent contaminants and moisture from infiltrating the bonding interface and further enhance the mechanical stability of the wafer stack (and the die stack obtained after singulation) to resist stresses generated by warping. Since the extended seal ring structure is formed after wafer-to-wafer bonding, misalignment is not a problem for the extended seal ring structure. In some embodiments, the extended seal ring structure can be physically and electrically connected to the seal rings of each wafer. Embodiments can also include bonding pads located above the extended seal ring structure, which can be used for grounding.

[0102] One embodiment is an encapsulated device, comprising: a first die, comprising: a first seal ring structure disposed around a periphery of the first die and within a first interconnect of the first die; a first dielectric layer located above the first interconnect; and a first seal ring extension disposed within the first dielectric layer. The first seal ring extension is aligned and physically connected to the first seal ring structure, and the first seal ring extension extends continuously around the periphery of the first die. The encapsulated device further comprises: a second die, comprising: a second dielectric layer disposed below a second interconnect and a second seal ring extension disposed within the second dielectric layer. The second seal ring extension is aligned and physically connected to the first seal ring extension. In one embodiment, the first seal ring extension and the second seal ring extension are physically connected by a direct metal-to-metal bond with no eutectic material formed therebetween. In one embodiment, an air gap between the first die and the second die is sealed by the connected first seal ring extension and second seal ring extension. In one embodiment, the first seal ring extension and the second seal ring extension are offset by a lateral distance. In one embodiment, the encapsulated device may comprise a third seal ring extension that extends through the second die and into the first die, the third seal ring extension surrounding a first connector of the first die and a second connector of the second die. In one embodiment, the third seal ring extension contacts the first seal ring structure and the second seal ring structure. In one embodiment, the encapsulated device may comprise one or more bond pads disposed at a top surface of the third seal ring extension.

[0103] Another embodiment is an encapsulated device, comprising: a first die, comprising a first seal ring around its periphery. The encapsulated device further comprises: a second die, comprising a second seal ring around its periphery. The encapsulated device further comprises: a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring. In one embodiment, the third seal ring is aligned and contacts the first seal ring and the second seal ring. In one embodiment, the third seal ring extends upward through the second die, the second die being located above the first die. In one embodiment, the third seal ring surrounds the first seal ring and the second seal ring. In one embodiment, the encapsulated device may comprise: a fourth seal ring disposed between the first seal ring and the second seal ring, the fourth seal ring spanning the interface between the first die and the second die, the fourth seal ring having an upper surface that contacts a lower surface of the second seal ring and a bottom surface that contacts an upper surface of the first seal ring.

[0104] Another embodiment is a method that includes: bonding a first connector of a first wafer to a second connector of a second wafer. The first wafer may include a first sealing ring; the second wafer may include a second sealing ring. The method further includes forming a third sealing ring around the first and second connectors, the third sealing ring spanning the interface between the first and second wafers. The method further includes singulating the first and second wafers to singulate a first package therefrom. In one embodiment, forming the third sealing ring may include: forming a first trench opening in a first dielectric layer above the first sealing ring, the first trench opening exposing an upper surface of the first sealing ring; and depositing a conductive material in the first trench opening to form a first sealing ring extension; forming a second trench opening in a second dielectric layer above the second sealing ring, the second trench opening exposing an upper surface of the second sealing ring; depositing a conductive material in the second trench opening to form a second sealing ring extension; and bonding the first sealing ring extension to the second sealing ring extension while bonding the first connector of the first wafer to the second connector of the second wafer. In one embodiment, the first sealing ring extension and the second sealing ring extension may include a eutectic material. In one embodiment, the first sealing ring extension and the second sealing ring extension are bonded together using a direct metal-to-metal bond. In one embodiment, forming the third sealing ring may include: thinning the second wafer; and forming a trench through the second wafer that penetrates the first wafer, the trench surrounding the first and second connectors; and filling the trench with a sealing ring material. In one embodiment, the sealing ring material is a conductive material. In one embodiment, the method may further include: forming a bonding pad above the third sealing ring. In one embodiment, the trench exposes the first and second sealing rings, and the sealing ring material electrically and physically connects the first and second sealing rings.

[0105] Embodiments of the present application disclose a packaged device, comprising: a first die, including: a first seal ring structure disposed around the periphery of the first die and in a first interconnect of the first die; a first dielectric layer located above the first interconnect; and a first seal ring extension disposed in the first dielectric layer, the first seal ring extension being aligned with and physically connected to the first seal ring structure, the first seal ring extension continuously extending around the periphery of the first die; and a second die, including: a second dielectric layer disposed below a second interconnect; and a second seal ring extension disposed in the second dielectric layer, the second seal ring extension being aligned with and physically connected to the first seal ring extension. In some embodiments, the first seal ring extension and the second seal ring extension are physically connected by a direct metal-to-metal bond, with no eutectic material formed therebetween. In some embodiments, the air gap between the first die and the second die is sealed by the connected first seal ring extension and second seal ring extension. In some embodiments, the first seal ring extension and the second seal ring extension are offset by a lateral distance. In some embodiments, further comprising: a third seal ring extension extending through the second die and into the first die, the third seal ring extension surrounding a first connector of the first die and a second connector of the second die. In some embodiments, the third seal ring extension contacts the first seal ring structure and the second seal ring structure. In some embodiments, further comprising: one or more bonding pads disposed at the top surface of the third seal ring extension.

[0106] Embodiments of the present application provide a packaged device, comprising: a first die including a first seal ring around the periphery of the first die; a second die including a second seal ring around the periphery of the second die; and a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring. In some embodiments, the third seal ring is aligned with and contacts the first seal ring and the second seal ring. In some embodiments, the third seal ring extends upward through the second die, with the second die located above the first die. In some embodiments, the third seal ring surrounds the first seal ring and the second seal ring. In some embodiments, further comprising: a fourth seal ring between the first seal ring and the second seal ring, the fourth seal ring spanning the interface between the first die and the second die, the fourth seal ring having an upper surface contacting the lower surface of the second seal ring and a bottom surface contacting the upper surface of the first seal ring.

[0107] Embodiments of the present application also provide a method, including: bonding a first connector of a first wafer to a second connector of a second wafer, the first wafer including a first sealing ring and the second wafer including a second sealing ring; forming a third sealing ring around the first connector and the second connector, the third sealing ring spanning an interface between the first wafer and the second wafer; and singulating the first wafer and the second wafer to singulate a first package from the first wafer and the second wafer. In some embodiments, forming the third sealing ring includes: forming a first trench opening in a first dielectric layer above the first sealing ring, the first trench opening exposing an upper surface of the first sealing ring; depositing a conductive material in the first trench opening to form a first sealing ring extension; forming a second trench opening in a second dielectric layer above the second sealing ring, the second trench opening exposing an upper surface of the second sealing ring; depositing the conductive material in the second trench opening to form a second sealing ring extension; and bonding the first sealing ring extension to the second sealing ring extension while bonding the first connector of the first wafer to the second connector of the second wafer. In some embodiments, the first sealing ring extension and the second sealing ring extension include a eutectic material. In some embodiments, the first sealing ring extension and the second sealing ring extension are bonded together using a direct metal-to-metal bond. In some embodiments, forming the third sealing ring includes: thinning the second wafer; forming a trench through the second wafer, the trench penetrating the first wafer, the trench surrounding the first connector and the second connector; and filling the trench with a sealing ring material. In some embodiments, the sealing ring material is a conductive material. In some embodiments, it further includes: forming a bonding pad above the third sealing ring. In some embodiments, the trench exposes the first sealing ring and the second sealing ring, and the sealing ring material electrically and physically connects the first sealing ring and the second sealing ring.

[0108] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An encapsulation device, comprising: A first die, comprising: A first sealing ring structure, disposed around the periphery of the first die and within a first interconnect of the first die; A first dielectric layer, located above the first interconnect; and A first sealing ring extension, disposed within the first dielectric layer, the first sealing ring extension being aligned with and physically connected to the first sealing ring structure, the first sealing ring extension continuously extending around the periphery of the first die; and A second die, comprising: A second sealing ring structure, disposed around the periphery of the second die and within a second interconnect of the second die; A second dielectric layer, disposed below the second interconnect; and A second sealing ring extension, disposed within the second dielectric layer, the second sealing ring extension being aligned with and physically connected to the second sealing ring structure, the second sealing ring extension continuously extending around the periphery of the second die, the second sealing ring extension being aligned with and physically connected to the first sealing ring extension, thereby forming a sealing ring extension, wherein there is a gap between the first die and the second die, and the gap is sealed by the sealing ring extension.

2. The encapsulation device according to claim 1, wherein, the first sealing ring extension and the second sealing ring extension are physically connected by a direct metal-to-metal bond, with no eutectic material formed therebetween.

3. The encapsulation device according to claim 1, wherein, the first sealing ring and the second sealing ring comprise a conductive material.

4. The encapsulation device according to claim 1, wherein, the first sealing ring extension and the second sealing ring extension are offset by a lateral distance.

5. The encapsulation device according to claim 1, further comprising: A third sealing ring extension, extending through the second die and into the first die, the third sealing ring extension surrounding a first connector of the first die and a second connector of the second die.

6. The encapsulation device according to claim 5, wherein, the third sealing ring extension contacts the first sealing ring structure and the second sealing ring structure.

7. The encapsulation device according to claim 5, further comprising: One or more bonding pads, disposed at the top surface of the third sealing ring extension.

8. An encapsulation device, comprising: A first die, comprising a first sealing ring around the periphery of the first die; A second die, comprising a second sealing ring around the periphery of the second die; and A third sealing ring spans an interface between the first die and the second die. The third sealing ring surrounds the interface and seals the interface within the third sealing ring. The third sealing ring is a homogeneous structure extending through the interface between the first die and the second die. A first horizontal line parallel to the interface interfaces with the third sealing ring and the first sealing ring, and a second horizontal line parallel to the interface interfaces with the third sealing ring and the second sealing ring. Wherein, the third sealing ring is aligned with and contacts side portions of the first sealing ring and the second sealing ring.

9. The packaged device according to claim 8, further comprising: One or more bonding pads disposed at a top surface of the third sealing ring.

10. The packaged device according to claim 9, wherein, The third sealing ring extends upward through the second die, and the second die is located above the first die.

11. The packaged device according to claim 8, wherein, The first sealing ring and the second sealing ring comprise a conductive material.

12. The packaged device according to claim 8, further comprising: A fourth sealing ring is between the first sealing ring and the second sealing ring. The fourth sealing ring spans the interface between the first die and the second die. The fourth sealing ring has an upper surface contacting a lower surface of the second sealing ring and a bottom surface contacting an upper surface of the first sealing ring.

13. A method of forming a packaged device, comprising: Bonding a first connector of a first wafer to a second connector of a second wafer. The first wafer includes a first sealing ring and the second wafer includes a second sealing ring; Forming a third sealing ring around the first connector and the second connector. The third sealing ring spans an interface between the first wafer and the second wafer; Forming a trench through the second wafer, the trench penetrating the first wafer. The trench surrounds the first connector and the second connector; Filling the trench with a sealing ring material to form a fourth sealing ring; and and Singulating the first wafer and the second wafer to singulate a first package from the first wafer and the second wafer, wherein, forming the third sealing ring includes: Forming a first trench opening in a first dielectric layer above the first sealing ring. The first trench opening exposes an upper surface of the first sealing ring; Depositing a conductive material in the first trench opening to form a first sealing ring extension; Forming a second trench opening in a second dielectric layer above the second sealing ring. The second trench opening exposes an upper surface of the second sealing ring; Depositing the conductive material in the second trench opening to form a second sealing ring extension; and While bonding the first connector of the first wafer to the second connector of the second wafer, bonding the first sealing ring extension to the second sealing ring extension.

14. The method of forming a packaged device according to claim 13, wherein, The fourth sealing ring contacts the first sealing ring and the second sealing ring.

15. The method of forming a packaged device according to claim 14, wherein, the first sealing ring extension and the second sealing ring extension comprise a eutectic material.

16. The method of forming a packaged device according to claim 14, wherein, the first sealing ring extension and the second sealing ring extension are joined together using a direct metal-to-metal bond.

17. The method of forming a packaged device according to claim 13, wherein, the second wafer is thinned before forming the trench.

18. The method of forming a packaged device according to claim 13, wherein, the sealing ring material is a conductive material.

19. The method of forming a packaged device according to claim 13, further comprising: forming a bonding pad over the third sealing ring.

20. The method of forming a packaged device according to claim 13, wherein, the trench exposes sides of the first sealing ring and the second sealing ring, and the sealing ring material electrically and physically connects the first sealing ring and the second sealing ring.

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