Semiconductor Devices

Abstract

A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack located between the first electrode and the second electrode, the dielectric layer stack including a first antiferroelectric layer, a second antiferroelectric layer and a ferroelectric layer between the first antiferroelectric layer and the second antiferroelectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0059084, filed on May 18, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate generally to a semiconductor device, and more particularly, to an improved semiconductor device including both antiferroelectric and ferroelectric materials. Background Art

[0004] In order to ensure adequate operating characteristics while further scaling down the size of capacitors in semiconductor devices, sufficient capacitance must be maintained. One method of achieving this goal includes increasing the dielectric constant of the dielectric material used in the capacitor. However, known materials compatible with semiconductor processing are limited, so the current limitation is to scale down the size of capacitors in semiconductor devices while maintaining effective capacitance. Summary of the invention

[0005] Embodiments of the present invention are directed to a semiconductor device including a dielectric layer stack having a high dielectric constant. The semiconductor device may include a capacitor.

[0006] According to one embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack located between the first electrode and the second electrode, the dielectric layer stack including a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer arranged between the first antiferroelectric layer and the second antiferroelectric layer.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; and an alternating stack located between the first electrode and the second electrode, the alternating stack including a plurality of dielectric layer stacks and a plurality of leakage blocking layers alternately stacked, wherein each of the plurality of dielectric layer stacks includes a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer arranged between the first antiferroelectric layer and the second antiferroelectric layer.

[0008] These and other features and advantages of the present invention will be understood by one of ordinary skill in the art to which the present invention pertains from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A semiconductor device according to an embodiment of the present invention is shown.

[0010] Figure 2A and Figure 2B The polarization characteristics of ferroelectric and antiferroelectric materials are shown respectively.

[0011] Figure 2C The polarization characteristics of a stack including both ferroelectric and antiferroelectric materials are shown.

[0012] Figures 3 to 8B Semiconductor devices according to other embodiments of the present invention are shown.

[0013] 9A to 9C is a view showing a storage unit.

[0014] FIG. 10A to FIG. 10F is a view showing an application example of a capacitor of a memory cell.

[0015] Fig.11 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0016] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in the various drawings and embodiments of the present invention, the same reference numerals refer to the same parts.

[0017] The drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on a second layer" or "on a substrate", it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0018] It will also be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on the other element, directly connected to or coupled to the other element, or one or more intervening elements may be present. Furthermore, the connection / coupling may not be limited to a physical connection, but may also include a non-physical connection, such as a wireless connection.

[0019] In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0020] When a first element is referred to as being 'over' a second element, it not only refers to a case where the first element is directly formed on the second element but also refers to a case where a third element exists between the first element and the second element.

[0021] It should be understood that the drawings are simplified schematic diagrams of the devices being described and may not include well-known details in order to avoid obscuring aspects of the present invention.

[0022] It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the present invention.

[0023] It should also be noted that like reference numerals denote like elements throughout the various drawings.

[0024] The combination of hafnium oxide (HfO2) and zirconium oxide (ZrO2) can be adjusted to have ferroelectric or antiferroelectric properties. Therefore, it is necessary to control the polarization switching to occur near the operating voltage of volatile memory such as dynamic random access memory (DRAM) and use the maximized dielectric constant in this region.

[0025] When a ferroelectric material is used, the coercive field as an operating voltage may be low, but even when the operating voltage is removed (eg, the operating voltage is 0 V), the polarization does not become 0 and a residual polarization remains. This may limit the use of ferroelectric materials for DRAM.

[0026] When an antiferroelectric material is used, since the coercive field in which polarization switching occurs is relatively large, the coercive field needs to be reduced in order to use DRAM.

[0027] The dielectric material of the capacitor of the DRAM according to an embodiment of the present invention provides a combination of low coercive field (which is a characteristic of ferroelectric materials), no residual polarization (which is a characteristic of antiferroelectric materials), and high dielectric constant during polarization switching operations (which is a common feature of ferroelectric materials and antiferroelectric materials).

[0028] The dielectric constant of ferroelectric materials is maximum near the coercive field. Some researchers are developing memory devices using ferroelectric materials with relatively low coercive fields. However, such devices can be problematic because the polarization does not become 0 at 0V and a remnant polarization remains. Therefore, the use of ferroelectric materials in volatile memories is limited. On the other hand, the polarization of antiferroelectric materials is 0 at 0V, but has a relatively high coercive field, which limits its application in volatile memories.

[0029] In the following embodiments of the present invention, a semiconductor device including a stacked structure is provided, which employs both ferroelectric and antiferroelectric materials. The stacked structure achieves low switching voltage (ie, low coercive field), high capacitance, and no remnant polarization.

[0030] Figure 1 A semiconductor device 100 according to an embodiment of the present invention is shown.

[0031] refer to Figure 1 , the semiconductor device 100 may be part of a memory. The semiconductor device 100 may be part of a volatile memory. The semiconductor device 100 may be part of a DRAM. The semiconductor device 100 may include a DRAM capacitor.

[0032] The semiconductor device 100 may include a first electrode 101, a second electrode 102, and a dielectric layer stack 110 between the first electrode 101 and the second electrode 102. The dielectric layer stack 110 may be in direct contact with the first electrode 101 and the second electrode 102.

[0033] The first electrode 101 may include a metal-containing material. The first electrode 101 may include, for example, a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The first electrode 101 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), niobium nitride (NbN), molybdenum nitride (MoN), or a combination thereof. According to another embodiment of the present invention, the first electrode 101 may include a silicon-containing material. The first electrode 101 may include, for example, silicon, silicon germanium, or a combination thereof. According to another embodiment of the present invention, the first electrode 101 may include a stack of a metal-containing material and a silicon-containing material. The first electrode 101 may also be referred to as a 'bottom electrode' or a storage node.

[0034] The second electrode 102 may include a silicon-containing material, a germanium-containing material, a metal-containing material, or a combination thereof. The second electrode 102 may include, for example, a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The second electrode 102 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO2), silicon (Si), germanium (Ge), germanium silicon (SiGe), or a combination thereof. The second electrode 102 may include a 'Si / SiGe stack' in which germanium silicon is stacked on silicon. In one embodiment, the second electrode 102 may include a 'Ge / SiGe stack' in which germanium silicon is stacked on germanium. In another embodiment, the second electrode 102 may be formed by stacking germanium silicon on a metal nitride. For example, the second electrode 102 may be formed by stacking silicon germanium (SiGe) on titanium nitride (TiN). According to another embodiment of the present invention, the second electrode 102 may include titanium nitride (TiN), silicon germanium (SiGe) and tungsten (W), which are stacked in the order described. According to another embodiment of the present invention, the second electrode 102 may include titanium nitride (TiN), silicon germanium (SiGe) and tungsten nitride (WN), which are stacked in the order described.

[0035] The dielectric layer stack 110 may include at least one high-k material having a high dielectric constant of about 7 or more. The high-k material may have a dielectric constant higher than silicon oxide and silicon nitride. The dielectric layer stack 110 may include at least one ultra-high-k material. The ultra-high-k material may be a material having a dielectric constant higher than the high-k material. The ultra-high-k material may have a high dielectric constant of about 60 or more. The dielectric layer stack 110 may include at least one ferroelectric material and at least one antiferroelectric material.

[0036] The dielectric layer stack 110 may include a multi-layer stack of different dielectric materials. The dielectric layer stack 110 may include a three-layer stack including a first dielectric layer 111, a second dielectric layer 112, and a third dielectric layer 113. The third dielectric layer 113 may be located between the first dielectric layer 111 and the second dielectric layer 112. The first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 may be vertically arranged between the first electrode 101 and the second electrode 102.

[0037] At least one of the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 may be a ferroelectric material FE. For example, the third dielectric layer 113 may be a ferroelectric material FE. The first dielectric layer 111 and the second dielectric layer 112 may be a material different from that of the third dielectric layer 113. The first dielectric layer 111 and the second dielectric layer 112 may be the same material or different materials. At least one of the first dielectric layer 111 and the second dielectric layer 112 may be an antiferroelectric material AFE. Figure 1 In this embodiment, both the first dielectric layer 111 and the second dielectric layer 112 can be antiferroelectric materials AFE1, AFE2.

[0038] The first dielectric layer 111 may include a first antiferroelectric material AFE1, and the second dielectric layer 112 may include, for example, a second antiferroelectric material AFE2. The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be the same antiferroelectric material. Alternatively, the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be different antiferroelectric materials. For example, the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be made of a first hafnium zirconium oxide (HfZrO).

[0039] Other suitable materials for the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3, NaNbO3, or combinations thereof.

[0040] The third dielectric layer 113 may include a ferroelectric material FE. The ferroelectric material FE may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric material FE may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric material FE may include, for example, a second hafnium zirconium oxide (HfZrO).

[0041] Other suitable materials for the ferroelectric material FE may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, and combinations thereof.

[0042] The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may include a first hafnium zirconium oxide, and the third dielectric layer 113 may include, for example, a second hafnium zirconium oxide. The first hafnium zirconium oxide and the second hafnium zirconium oxide may have different hafnium component ratios. The first hafnium zirconium oxide and the second hafnium zirconium oxide may have different zirconium component ratios. The first hafnium zirconium oxide and the second hafnium zirconium oxide may have different hafnium component ratios and zirconium component ratios.

[0043] Figure 1 The dielectric layer stack 110 of the semiconductor device 100 may include a multilayer stack structure of ferroelectric materials and antiferroelectric materials. A low coercive field can be obtained by the ferroelectric material FE, and no remanent polarization (i.e., zero level remanent polarization) can be maintained by the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2.

[0044] exist Figure 1 In the embodiment of the present invention, the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 are formed in direct contact with the first electrode 101 and the second electrode 102, respectively, so that a polarization of '0' can be obtained when no voltage (0V) is applied between the first electrode 101 and the second electrode 102. When the voltage applied between the first electrode 101 and the second electrode 102 is gradually increased, as the ferroelectric material FE first starts to switch, a high dielectric constant can be ensured. Then, when the applied voltage is turned off (i.e., 0V), the polarization becomes '0' again (i.e., no residual polarization), thereby realizing the operation of the volatile memory.

[0045] Since one ferroelectric material FE is located between two antiferroelectric materials AFE1 and AFE2, the dielectric layer stack 110 may be referred to as an "AFE-FE-AFE stack". The dielectric layer stack 110 may have a polarity-voltage characteristic whose hysteresis loop shows two polarization characteristics (AFE type and FE type). The hysteresis loop of the dielectric layer stack 110 may have a nonlinear direct contact point. Here, the polarization of the nonlinear direct contact point may be '0'.

[0046] Figure 2A The polarity-voltage characteristics of ferroelectric materials are described. Figure 2B The polarity-voltage characteristics of an antiferroelectric material are shown. Figure 2C The polarity-voltage characteristics of the AFE-FE-AFE stack are shown.

[0047] refer to Figure 2A , ferroelectric material FE can have high capacitance at low voltage, but remnant polarization (Pr and -Pr) may exist.

[0048] refer to Figure 2B, antiferroelectric material AFE may have no remanent polarization (Pr), but may have low capacitance at low voltage.

[0049] refer to Figure 2C , the AFE-FE-AFE stack can have polarity-voltage characteristics showing two polarization characteristics (AFE type and FE type). The hysteresis loop of the AFE-FE-AFE stack can have ferroelectric polarization (FE type), antiferroelectric polarization (AFE type) and nonlinear direct contact points. Here, when the applied voltage is 0V, the polarization of the nonlinear direct contact point can be '0'. Figure 2B In the antiferroelectric hysteresis loop, the part with polarization '0' can be linear.

[0050] refer to Figure 2C , it can be seen that the AFE-FE-AFE stack has high capacitance at low voltage and a hysteresis loop without remnant polarization.

[0051] Figure 3 A semiconductor device according to another embodiment of the present invention is shown.

[0052] In addition to the dielectric layer stack 120, the constituent elements of the semiconductor device 200 shown in FIG. 2 may be Figure 1 The components of the semiconductor device 100 shown in FIG. 1 are the same. In the following, the description of the first electrode and the second electrode will refer to FIG. Figure 1 The semiconductor device 200 may be part of a memory. The semiconductor device 200 may be part of a volatile memory. The semiconductor device 200 may be part of a DRAM. The semiconductor device 200 may include a DRAM capacitor.

[0053] refer to Figure 3 , the semiconductor device 200 may include a first electrode 101 , a second electrode 102 , and a dielectric layer stack 120 between the first electrode 101 and the second electrode 102 .

[0054] The dielectric layer stack 120 may include different hafnium zirconium oxides stacked on each other. Here, the different hafnium zirconium oxides may have different hafnium component ratios, may have different zirconium component ratios, or may have different hafnium component ratios and zirconium component ratios. The different hafnium zirconium oxides may have different thicknesses. The different hafnium zirconium oxides may have different polarization characteristics. The hafnium zirconium oxide may include Hf x Zr y O(x>0, y>0, and x+y=1).

[0055] According to the ratio of hafnium content (x) to zirconium content (y), hafnium zirconium oxide (Hf x Zr yO) may have ferroelectric properties or antiferroelectric properties. The ferroelectric hafnium zirconium oxide may have a hafnium content (x) of about 0.46 to about 0.75 and a zirconium content (y) of about 0.25 to about 0.54. The antiferroelectric hafnium zirconium oxide may have a hafnium content (x) of about 0.2 to about 0.45 and a zirconium content (y) of about 0.55 to about 0.8.

[0056] The dielectric layer stack 120 may include a first hafnium zirconium oxide (HZO1) 121, a second hafnium zirconium oxide (HZO2) 122, and a third hafnium zirconium oxide (HZO3) 123 between the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122. Reference numerals HZO1, HZO2, and HZO3 may denote HfZO1, HZO2, and HZO3, respectively. x Zr y O.

[0057] The first hafnium zirconium oxide 121 and the third hafnium zirconium oxide 123 may have different hafnium component ratios. The first hafnium zirconium oxide 121 and the third hafnium zirconium oxide 123 may have different zirconium component ratios. The first hafnium zirconium oxide 121 and the third hafnium zirconium oxide 123 may have different hafnium component ratios and different zirconium component ratios. The first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122 may have the same hafnium component ratio and the same zirconium component ratio.

[0058] The first hafnium zirconium oxide 121 may include Hf x Zr y O(x>0, y>0, x=0.46~0.75, y=0.25~0.54, x+y=1). in Hf x Zr y In the ZrO, the hafnium content (x) and the zirconium content (y) may be the same. In one example, the hafnium content (x) may be 0.5, and the zirconium content (y) may be 0.5.

[0059] The second hafnium zirconium oxide 122 may include Hf x Zr y O(x>0, y>0, x=0.46-0.75, y=0.25-0.54, x+y=1). In the second hafnium zirconium oxide 122, the hafnium content (x) and the zirconium content (y) may be the same. For example, the ratio of the hafnium content (x) to the zirconium content (y) may be about 1:1. For example, the hafnium content (x) may be about 0.5, and the zirconium content (y) may be about 0.5.

[0060] The third hafnium zirconium oxide 123 may include Hf x Zr y O(x>0, y>0, x=0.2~0.45, y=0.55~0.8, x+y=1, and y>x). in Hf xZr y In the third hafnium zirconium oxide 123, the hafnium content (x) may be less than the zirconium content (y). For example, the zirconium content (y) may be at least twice the hafnium content (x). For example, the ratio of the zirconium content (y) to the hafnium content (x) may be about 2:1. As an example, the hafnium content (x) may be about 0.3, and the zirconium content (y) may be about 0.7. In this way, the hafnium zirconium oxide having a high zirconium content (y) may be referred to as 'zirconium (Zr)-rich hafnium zirconium oxide' or 'zirconium oxide-rich hafnium zirconium oxide'. The third hafnium zirconium oxide 123 may have a greater zirconium content than the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122.

[0061] Hafnium Zirconium Oxide (Hf x Zr y (O) may have ferroelectric FE characteristics or antiferroelectric AFE characteristics based on the hafnium content (x) and the zirconium content (y). In addition, the critical concentration at which the change between the ferroelectric FE characteristics and the antiferroelectric AFE characteristics appears may be different based on the hafnium content (x) and the zirconium content (y).

[0062] For example, when the hafnium content (x) and zirconium content (y) are the same, Hf 0.5 Zr 0.5 O may have ferroelectric properties.

[0063] When the zirconium content is greater than the hafnium content (i.e., zirconium-rich Hf x Zr y O), such as Hf 0.3 Zr 0.7 O, it can have antiferroelectric AFE characteristics.

[0064] refer to Figure 3 The third hafnium zirconium oxide 123 having ferroelectric properties can be controlled to have a ratio of hafnium content to zirconium content of 1:1, and the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122 having antiferroelectric properties can be controlled to have a ratio of zirconium content to hafnium content such that zirconium is at least 2 times or more of hafnium (for example, y / x is at least equal to 2:1).

[0065] As the dielectric layer 123 is formed by controlling the combination of the zirconium content and the hafnium content in this manner, the polarization-voltage curve may start switching at a low voltage, and the polarization becomes '0' again at '0V', thereby implementing an operation as a volatile memory.

[0066] exist Figure 1 In the embodiment of the present invention, the first dielectric layer 111 and the second dielectric layer 112 are in direct contact with the first electrode 101 and the second electrode 102, respectively. Figure 3 In the embodiment of the present invention, the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122 are in direct contact with the first electrode 101 and the second electrode 102 respectively.

[0067] Figure 4 3 is a view for describing a semiconductor device according to another embodiment of the present invention. In addition to the interface layer 331, Figure 4 The semiconductor device 300 may have Figure 1 The semiconductor device 100 has the same constituent elements. In the following, for a detailed description of the first electrode and the second electrode, reference can be made to Figure 1 and description thereof. The semiconductor device 300 may be part of a memory. The semiconductor device 300 may be part of a volatile memory. The semiconductor device 300 may be part of a DRAM. The semiconductor device 300 may include a DRAM capacitor.

[0068] refer to Figure 4 The semiconductor device 300 may include a first electrode 101, a second electrode 102, and a dielectric layer stack 320 disposed between the first electrode 101 and the second electrode 102. The semiconductor device 300 may further include an interface layer 331 disposed between the second electrode 102 and the dielectric layer stack 320.

[0069] The dielectric layer stack 320 may include a multi-layer stack of different dielectric materials. The dielectric layer stack 320 may have a three-layer stack including a first antiferroelectric layer 321, a second antiferroelectric layer 322, and a ferroelectric layer 323. The ferroelectric layer 323 may be located between the first antiferroelectric layer 321 and the second antiferroelectric layer 322.

[0070] The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may be made of the same antiferroelectric material or different antiferroelectric materials. The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may be made of oxides including hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a ratio of zirconium content to hafnium content of 2:1. Other suitable materials for the first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include PbZrO 3 , PbHfO 3 , PbMgWO 3 , PbZrTiO 3 , BiNaTiO 3 , NaNbO 3 , and combinations thereof.

[0071] The ferroelectric layer 323 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may include hafnium zirconium oxide (HfZrO) having a zirconium content and a hafnium content ratio of 1:1. Other suitable materials for the ferroelectric layer 323 may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, or combinations thereof.

[0072] The interface layer 331 may be used to suppress leakage current of the dielectric layer stack 320. When forming the second electrode 102, the interface layer 331 may be used to protect the dielectric layer stack 320. The interface layer 331 may include a material that is reduced prior to the dielectric layer stack 320 when forming the second electrode 102. The interface layer 331 may be used as a leakage current block having a large effective work function (eWF) and a large conduction band offset (CBO). In addition, the interface layer 331 may not increase the equivalent oxide film thickness T of the dielectric layer stack 320. ox The interface layer 331 may serve as a portion of the second electrode 102 .

[0073] The interface layer 331 may be a material having a large electronegativity. The interface layer 331 may have a Pauling electronegativity greater than that of the dielectric layer stack 320. The interface layer 331 may include a material whose Pauling electronegativity (hereinafter referred to as 'electronegativity') is greater than that of the first antiferroelectric layer 321 and the second antiferroelectric layer 322 and the ferroelectric layer 323. The interface layer 331 may have a sufficiently large electronegativity so that it is hardly oxidized and is easily reduced. Therefore, the interface layer 331 may replace the dielectric layer stack 320 and lose oxygen, so the interface layer 331 may prevent the loss of oxygen from the dielectric layer stack 320.

[0074] The interface layer 331 may include atoms having large electronegativity, for example, metal atoms, silicon atoms, or germanium atoms. The interface layer 331 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

[0075] The interface layer 331 may include, for example, titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof. According to another embodiment of the present invention, the interface layer 331 may include a stack of molybdenum and molybdenum nitride (Mo / MoN) or a stack of tungsten and tungsten nitride (W / WN).

[0076] Figure 5 3 is a diagram illustrating a semiconductor device 301 according to another embodiment of the present invention. In addition to the additional interface layer 332, Figure 5 The constituent elements of the semiconductor device 301 may be Figure 4 The semiconductor device 301 is the same as those of the semiconductor device 300 shown. The semiconductor device 301 may be part of a memory. The semiconductor device 301 may be part of a volatile memory. The semiconductor device 301 may be part of a DRAM. The semiconductor device 301 may include a DRAM capacitor.

[0077] refer to Figure 5 , the semiconductor device 301 may include: a first electrode 101; a second electrode 102; a dielectric layer stack 320 disposed between the first electrode 101 and the second electrode 102; and an interface layer 331 between the second electrode 102 and the dielectric layer stack 320. The semiconductor device 301 may further include an additional interface layer 332 disposed between the first electrode 101 and the dielectric layer stack 320.

[0078] The dielectric layer stack 320 may include a multi-layer stack of different dielectric materials. The dielectric layer stack 320 may include a three-layer stack including a first antiferroelectric layer 321, a second antiferroelectric layer 322, and a ferroelectric layer 323. The ferroelectric layer 323 may be located between the first antiferroelectric layer 321 and the second antiferroelectric layer 322.

[0079] The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may be the same antiferroelectric material or different antiferroelectric materials. The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may be oxides including hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a ratio of zirconium content to hafnium content of approximately 2:1. Other suitable materials for the first antiferroelectric layer 321 and the second antiferroelectric layer 322 may include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3, NaNbO3, and combinations thereof.

[0080] The ferroelectric layer 323 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may include hafnium zirconium oxide (HfZrO) having a zirconium content and a hafnium content ratio of about 1:1. Other suitable materials for the ferroelectric layer 323 may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, and combinations thereof.

[0081] The interface layer 331 and the additional interface layer 332 may be used to suppress leakage current of the dielectric layer stack 320. The interface layer 331 may be used to protect the dielectric layer stack 320 when forming the second electrode 102. The interface layer 331 may include a material that is reduced prior to the dielectric layer stack 320 when forming the second electrode 102. The interface layer 331 and the additional interface layer 332 may be used as a leakage current block having a large effective work function (eWF) and a large conduction band offset (CBO). In addition, the interface layer 331 and the additional interface layer 332 may not increase the equivalent oxide film thickness T of the dielectric layer stack 320. ox The interface layer 331 may serve as a portion of the second electrode 102 .

[0082] The interface layer 331 and the additional interface layer 332 may be the same material. The interface layer 331 and the additional interface layer 332 may have the same thickness. The interface layer 331 and the additional interface layer 332 may be thinner than the first and second antiferroelectric layers 321 and 322 and the ferroelectric layer 323.

[0083] The additional interface layer 332 may be a material having a large electronegativity. The additional interface layer 332 may have a larger Pauling electronegativity than the dielectric layer stack 320. The additional interface layer 332 may include a material having a larger Pauling electronegativity (hereinafter referred to as 'electronegativity') than the first antiferroelectric layer 321 and the second antiferroelectric layer 322 and the ferroelectric layer 323. The additional interface layer 332 may have a sufficiently large electronegativity so that it is hardly oxidized and is easily reduced.

[0084] The interface layer 331 and the additional interface layer 332 may include atoms having large electronegativity, such as metal atoms, silicon atoms, or germanium atoms. The interface layer 331 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

[0085] The interface layer 331 and the additional interface layer 332 may include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof. According to another embodiment of the present invention, the interface layer 331 may include a stack of molybdenum and molybdenum nitride (Mo / MoN) or a stack of tungsten and tungsten nitride (W / WN).

[0086] Figure 6 A semiconductor device 400 according to another embodiment of the present invention is shown. Figure 6 The semiconductor device 400 may be similar to Figure 1 The semiconductor device 100 of FIG. 400 may be part of a memory. The semiconductor device 400 may be part of a volatile memory. The semiconductor device 400 may be part of a DRAM. The semiconductor device 400 may include a DRAM capacitor.

[0087] refer to Figure 6 The semiconductor device 400 may include a first electrode 101, a second electrode 102, and a dielectric layer stack 420 between the first electrode 101 and the second electrode 102. Figure 1 and its description.

[0088] The dielectric layer stack 420 may include at least one antiferroelectric layer and at least one ferroelectric layer. The dielectric layer stack 420 may include a first stack 420A and a second stack 420B. The dielectric layer stack 420 may further include a high bandgap layer 424 disposed between the first stack 420A and the second stack 420B.

[0089] The stack 420A may include a multilayer stack of different dielectric materials. The stack 420A may include a three-layer stack including a first antiferroelectric layer 421, a second antiferroelectric layer 422, and a ferroelectric layer 423. The ferroelectric layer 423 may be located between the first antiferroelectric layer 421 and the second antiferroelectric layer 422. The first antiferroelectric layer 421 and the second antiferroelectric layer 422 may be the same antiferroelectric material or different antiferroelectric materials. The first antiferroelectric layer 421 and the second antiferroelectric layer 422 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 421 and the second antiferroelectric layer 422 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 421 and the second antiferroelectric layer 422 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layer 421 and the second antiferroelectric layer 422 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) with a zirconium content of about 2:1 to hafnium content. Other suitable materials for the first antiferroelectric layer 421 and the second antiferroelectric layer 422 may include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3, NaNbO3 and combinations thereof. The ferroelectric layer 423 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423 may include hafnium zirconium oxide (HfZrO) with a zirconium content of about 1:1 to hafnium content. Other suitable materials for the ferroelectric layer 423 may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, and combinations thereof.

[0090] The second stack 420B may include a multilayer stack of different dielectric materials. The second stack 420B may include a three-layer stack, the stack including a first antiferroelectric layer 421′, a second antiferroelectric layer 422′ and a ferroelectric layer 423′. The ferroelectric layer 423′ may be located between the first antiferroelectric layer 421′ and the second antiferroelectric layer 422′. The first antiferroelectric layer 421′ and the second antiferroelectric layer 422′ may be the same antiferroelectric material or different antiferroelectric materials. The first antiferroelectric layer 421′ and the second antiferroelectric layer 422′ may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 421′ and the second antiferroelectric layer 422′ may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 421′ and the second antiferroelectric layer 422′ may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layer 421′ and the second antiferroelectric layer 422′ may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content of approximately 2:1 to hafnium content. Other suitable materials for the first antiferroelectric layer 421′ and the second antiferroelectric layer 422′ may include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3 or NaNbO3. The ferroelectric layer 423′ may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423′ may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423′ may include hafnium zirconium oxide (HfZrO) having a zirconium content of approximately 1:1 to hafnium content. Other suitable materials for the ferroelectric layer 423' may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, and combinations thereof.

[0091] The height (thickness) of the first stack 420A and the height (thickness) of the second stack 420B may be the same or different. The first stack 420A and the second stack 420B may have the same structure.

[0092] In this embodiment, the first stack 420A and the second stack 420B can each have a three-layer stack structure including two antiferroelectric layers and one ferroelectric layer. The first antiferroelectric layer 421 of the first stack 420A and the first antiferroelectric layer 421′ of the second stack 420B can be made of the same antiferroelectric material or different antiferroelectric materials. The second antiferroelectric layer 422 of the first stack 420A and the second antiferroelectric layer 422′ of the second stack 420B can be made of the same antiferroelectric material or different antiferroelectric materials. The ferroelectric layer 423 of the first stack 420A and the ferroelectric layer 423′ of the second stack 420B can be made of the same ferroelectric material or different ferroelectric materials.

[0093] The first antiferroelectric layers 421 and 421′ and the second antiferroelectric layers 422 and 422′ may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layers 421 and 421′ and the second antiferroelectric layers 422 and 422′ may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content to hafnium content ratio of approximately 2:1. Other suitable materials for the first antiferroelectric layers 421 and 421′ and the second antiferroelectric layers 422 and 422′ may include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3, NaNbO3, and combinations thereof. The ferroelectric layers 423 and 423′ may include hafnium zirconium oxide (HfZrO) having a zirconium content to hafnium content ratio of approximately 1:1. Other suitable materials for the ferroelectric layers 423 and 423' may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, and combinations thereof.

[0094] The high bandgap layer 424 can be used to prevent leakage current of the dielectric layer stack 420. The high bandgap layer 424 may include a high bandgap energy material. The high bandgap layer 424 may have a bandgap energy of about 8.8 eV to about 10.6 eV. The high bandgap layer 424 may include a material with a higher bandgap energy than the first stack 420A and the second stack 420B. The high bandgap layer 424 may include a material with a higher bandgap energy than the first antiferroelectric layer 421 and 421', the second antiferroelectric layer 422 and 422', and the ferroelectric layer 423 and 423'. The high bandgap layer 424 may include a material different from the first stack 420A and the second stack 420B. The high bandgap layer 424 may include a high-k material, but may have a lower dielectric constant than the first stack 420A and the second stack 420B. The high bandgap layer 424 may have a higher dielectric constant than silicon oxide and silicon nitride. The high bandgap layer 424 may include aluminum oxide or beryllium oxide. The high bandgap layer 424 may be thinner than the first stack 420A and the second stack 420B. Since the high bandgap layer 424 has a relatively low dielectric constant compared to the dielectric constants of the first stack 420A and the second stack 420B, the high bandgap layer 424 may be formed very thin to increase capacitance.

[0095] Figure 7 A semiconductor device 401 according to another embodiment of the present invention is shown. Figure 7 The semiconductor device 401 may be similar to Figure 6The semiconductor device 400 may be a part of a memory. The semiconductor device 401 may be a part of a volatile memory. The semiconductor device 401 may be a part of a DRAM. The semiconductor device 401 may include a DRAM capacitor.

[0096] refer to Figure 7 The semiconductor device 401 may include a first electrode 101, a second electrode 102, and a dielectric layer stack 420' between the first electrode 101 and the second electrode 102. Figure 1 and its description.

[0097] The dielectric layer stack 420′ may include at least one antiferroelectric layer and at least one ferroelectric layer. The dielectric layer stack 420′ may include at least one tri-layer stack TL and at least one high bandgap layer HBG. The dielectric layer stack 420′ may be formed by alternately stacking the tri-layer stack TL and the high bandgap layer HBG at least twice or more. Therefore, the dielectric layer stack 420′ may be a stack including a plurality of alternating tri-layer stacks TL and the high bandgap layer HBG. The tri-layer stack TL at the bottom among the tri-layer stack TL may directly contact the first electrode 101, and the tri-layer stack TL at the top among the tri-layer stack TL may directly contact the second electrode 102. The high bandgap layer HBG may not be in direct contact with the first electrode 101 and the second electrode 102. According to another embodiment of the present invention, a high bandgap layer HBG may be added between the top tri-layer stack TL and the second electrode 102.

[0098] The three-layer stack TL may correspond to Figure 6 The first stack 420A or the second stack 420B. The three-layer stack TL may have a structure in which a ferroelectric layer is located between antiferroelectric layers. The high bandgap layer HBG may correspond to Figure 6 A high bandgap layer 424 is provided.

[0099] The three-layer stack TL may include a first antiferroelectric layer AFEL1, a second antiferroelectric layer AFEL2, and a ferroelectric layer FEL disposed between the first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2. The first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 may be made of the same antiferroelectric material or different antiferroelectric materials. The first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 may be made of oxides including hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and a hafnium content ratio of about 2:1. According to another embodiment of the present invention, the first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 can be made of other suitable materials, and the other suitable materials include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3, NaNbO3 and combinations thereof. The ferroelectric layer FEL may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer FEL may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer FEL may include hafnium zirconium oxide (HfZrO) having a ratio of zirconium content to hafnium content of about 1:1. According to another embodiment of the present invention, the ferroelectric layer FEL can be made of other suitable materials, and the other suitable materials include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3 and combinations thereof.

[0100] The high bandgap layer HBG can be used to prevent leakage current of the dielectric layer stack 420'. The high bandgap layer HBG may include a high bandgap energy material. The high bandgap layer HBG may have a bandgap energy of about 8.8 eV to about 10.6 eV. The high bandgap layer HBG may include a material having a higher bandgap energy than the three-layer stack TL. The high bandgap layer HBG may include a material having a higher bandgap energy than the first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL2 and the ferroelectric layer FEL. The high bandgap layer HBG may include a material different from the three-layer stack TL. The high bandgap layer HBG may include a high-k material, but may have a lower dielectric constant than the three-layer stack TL. The high bandgap layer HBG may have a higher dielectric constant than silicon oxide and silicon nitride. The high bandgap layer HBG may include aluminum oxide or beryllium oxide. The high bandgap layer HBG may be thinner than the three-layer stack TL. Since the high bandgap layer HBG has a relatively low dielectric constant compared to the three-layer stack TL, the high bandgap layer HBG may be formed very thin to increase capacitance.

[0101] Fig. 8A and Figure 8B Semiconductor devices according to other embodiments of the present invention are shown. Fig. 8A The semiconductor device 402 and Figure 8B The semiconductor device 403 may be similar to Figure 6 Each of semiconductor devices 402 and 403 may be part of a memory. Each of semiconductor devices 402 and 403 may be part of a volatile memory. Each of semiconductor devices 402 and 403 may be part of a DRAM. Each of semiconductor devices 402 and 403 may include a DRAM capacitor.

[0102] refer to Fig. 8A , the semiconductor device 402 may include: a first electrode 101 ; a second electrode 102 ; a dielectric layer stack 420 between the first electrode 101 and the second electrode 102 ; and an interface layer 431 between the second electrode 102 and the dielectric layer stack 420 .

[0103] The dielectric layer stack 420 may include a first stack 420A, a second stack 420B, and a high bandgap layer 424, which is disposed between the first stack 420A and the second stack 420B. The first stack 420A may include a first antiferroelectric layer 421, a second antiferroelectric layer 422, and a ferroelectric layer 423, which is disposed between the first antiferroelectric layer 421 and the second antiferroelectric layer 422. The second stack 420B may include a first antiferroelectric layer 421′, a second antiferroelectric layer 422′, and a ferroelectric layer 423′, which is disposed between the first antiferroelectric layer 421′ and the second antiferroelectric layer 422′.

[0104] Hereinafter, a detailed description of the first electrode 101 , the second electrode 102 , and the dielectric layer stack 420 will be described with reference to the above-described embodiments of the present invention.

[0105] The interface layer 431 may correspond to Figure 4 The interface layer 331 is formed.

[0106] The interface layer 431 may be located between the second stack 420B and the second electrode 102. The interface layer 431 may be a material having a large electronegativity. The interface layer 431 may have a higher Pauling electronegativity than the dielectric layer stack 420. The interface layer 431 may include a material having a larger electronegativity than the first antiferroelectric layer 421 and 421′, the second antiferroelectric layer 422 and 422′, and the ferroelectric layer 423 and 423′. Therefore, the interface layer 431 may prevent oxygen loss of the dielectric layer stack 420.

[0107] The interface layer 431 may include atoms having large electronegativity, such as metal atoms, silicon atoms, or germanium atoms. The interface layer 431 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

[0108] The interface layer 431 may include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof. According to another embodiment of the present invention, the interface layer 431 may include a stack of molybdenum and molybdenum nitride (Mo / MoN) or a stack of tungsten and tungsten nitride (W / WN).

[0109] In addition to the additional interface layer 432, Figure 8B The semiconductor device 403 may have Fig. 8A The same constituent elements as those of the semiconductor device 402.

[0110] The semiconductor device 403 may include: a first electrode 101; a second electrode 102; a dielectric layer stack 420 disposed between the first electrode 101 and the second electrode 102; an interface layer 431 disposed between the second electrode 102 and the dielectric layer stack 420; and an additional interface layer 432 disposed between the first electrode 101 and the dielectric layer stack 420.

[0111] The additional interface layer 432 and the interface layer 431 may be used to suppress leakage current of the dielectric layer stack 420. The interface layer 431 may be used to protect the dielectric layer stack 420 when forming the second electrode 102. The interface layer 431 may include a material that is reduced prior to the dielectric layer stack 420 when forming the second electrode 102. The interface layer 431 and the additional interface layer 432 may serve as a large leakage current block having a large effective work function (eWF) and a large conduction band offset (CBO). In addition, the interface layer 431 and the additional interface layer 432 may not increase the equivalent oxide film thickness T of the dielectric layer stack 420. ox The interface layer 431 may serve as a portion of the second electrode 102 .

[0112] The interface layer 431 and the additional interface layer 432 may be made of the same material. The interface layer 431 and the additional interface layer 432 may have the same thickness. The interface layer 431 and the additional interface layer 432 may be thinner than the first and second antiferroelectric layers 421 and 422 and the ferroelectric layer 423.

[0113] The additional interface layer 432 may be a material having a large electronegativity. The additional interface layer 432 may have a greater Pauling electronegativity than the dielectric layer stack 420. The additional interface layer 432 may include a material having a greater electronegativity than the first antiferroelectric layers 421 and 421′, the second antiferroelectric layers 422 and 422′, and the ferroelectric layers 423 and 423′.

[0114] The additional interface layer 432 may include atoms with large electronegativity, such as metal atoms, silicon atoms, or germanium atoms. The interface layer 331 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

[0115] The additional interface layer 432 may include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO 2 ), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof.

[0116] According to another embodiment of the present invention, the dielectric layer stack 420 of the semiconductor devices 402 and 403 may be replaced with Figure 7 The dielectric layer stack 420' corresponds to the alternating stack.

[0117] 9A to 9C is a view showing a storage unit. Fig. 9B It is along Fig. 9A A cross-sectional view taken along line AA′. Fig. 9C It is along Fig. 9A A cross-sectional view taken along line BB′.

[0118] The memory cell 500 may include a cell transistor including a buried word line 508, a bit line 514, and a capacitor 600. The capacitor 600 may include a dielectric layer stack, and the dielectric layer stack may include one of the dielectric layer stacks of the above-described embodiments of the present invention.

[0119] The storage unit 500 will now be described in detail.

[0120] An isolation layer 503 and an active area 504 may be formed on the substrate 501. A plurality of active areas 504 may be defined by the isolation layer 503. The substrate 501 may be a material suitable for semiconductor processing. The substrate 501 may include a semiconductor substrate. The substrate 501 may be formed of a silicon-containing material. The substrate 501 may include, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 501 may also include other semiconductor materials, such as germanium. The substrate 501 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The substrate 501 may include a silicon on insulator (SOI) substrate. The isolation layer 503 may be formed in the isolation trench 502 by a shallow trench isolation (STI) process.

[0121] A word line trench 506 may be formed in the substrate 501. The word line trench 506 may be referred to as a gate trench. A gate dielectric layer 507 may be formed on the surface of the word line trench 506. A buried word line 508 partially filling the word line trench 506 may be formed above the gate dielectric layer 507. The buried word line 508 may be referred to as a buried gate electrode. A word line capping layer 509 may be formed above the buried word line 508. The top surface of the buried word line 508 may be located at a level lower than the surface of the substrate 501. The buried word line 508 may be made of a low-resistance metal material. The buried word line 508 may be made of a stack in which titanium nitride and tungsten are sequentially stacked. According to another embodiment of the present invention, the buried word line 508 may be formed only of titanium nitride (only TiN).

[0122] A first impurity region 510 and a second impurity region 511 may be formed in the substrate 501. The first impurity region 510 and the second impurity region 511 may be spaced apart from each other by the word line trench 506. The first impurity region 510 and the second impurity region 511 may be referred to as a first source / drain region and a second source / drain region. The first impurity region 510 and the second impurity region 511 may include N-type impurities such as arsenic (As) or phosphorus (P). Therefore, the buried word line 508 and the first impurity region 510 and the second impurity region 511 may become a cell transistor. The cell transistor may improve the short channel effect by burying the word line 508.

[0123] A bit line contact plug 513 may be formed over the substrate 501. The bit line contact plug 513 may be coupled to the first impurity region 510. The bit line contact plug 513 may be located in the bit line contact hole 512. The bit line contact hole 512 may be formed using a hard mask layer 505. The hard mask layer 505 may be formed over the substrate 501. The bit line contact hole 512 may expose the first impurity region 510. The bottom surface of the bit line contact plug 513 may be lower than the top surface of the substrate 501. The bit line contact plug 513 may be formed of, for example, polysilicon or a metal material. A portion of the bit line contact plug 513 may have a line width smaller than a diameter of the bit line contact hole 512. A bit line 514 may be formed over the bit line contact plug 513. A bit line hard mask 515 may be formed over the bit line 514. The stacked structure of the bit line 514 and the bit line hard mask 515 may be referred to as a bit line structure BL. The bit line 514 may have a line shape extending in a direction crossing the buried word line 508. A portion of the bit line 514 may be coupled to the bit line contact plug 513. The bit line 514 may include a metal material. The bit line hard mask 515 may include a dielectric material.

[0124] The bit line spacer 516 may be formed on the sidewall of the bit line structure BL. The bottom portion of the bit line spacer 516 may extend to be formed on both sides of the bit line contact plug 513. The bit line spacer 516 may include, for example, silicon oxide, silicon nitride, or a combination thereof. According to another embodiment of the present invention, the bit line spacer 516 may include an air gap. For example, it may be a NAN (nitride-air gap-nitride) structure in which the air gap is located between silicon nitrides.

[0125] The storage node contact plug SNC may be formed between adjacent bit line structures BL. The storage node contact plug SNC may be formed in the storage node contact hole 518. The storage node contact plug SNC may be coupled to the second impurity region 511. The storage node contact plug SNC may include a lower plug 519 and an upper plug 521. The storage node contact plug SNC may further include an ohmic contact layer 520 disposed between the lower plug 519 and the upper plug 521. The ohmic contact layer 520 may include a metal silicide. The upper plug 521 may include a metal material, and the lower plug 519 may include a silicon-containing material.

[0126] From the perspective of a direction parallel to the bit line structure BL, a plug isolation layer 517 may be formed between adjacent storage node contact plugs SNC. The plug isolation layer 517 may be formed between adjacent bit line structures BL and may provide a storage node contact hole 518 together with the hard mask layer 505.

[0127] The capacitor 600 may be coupled to the storage node contact plug SNC.

[0128] FIG. 10A to FIG. 10F 601P and 601L may correspond to the first electrode 101 of the above-described embodiment of the present invention, and the upper electrode 602 may correspond to the second electrode 102.

[0129] refer to Fig. 10A , the capacitor 611 may include a lower electrode 601, a dielectric layer stack 603 and an upper electrode 602. The lower electrode 601 may have a cylindrical shape. The dielectric layer stack 603 may correspond to one of the dielectric layer stacks of the above-mentioned embodiment. Therefore, the dielectric layer stack 603 may include a first antiferroelectric layer, a second antiferroelectric layer and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer. The dielectric layer stack 603 may include, for example, two zirconium-rich hafnium zirconium oxide layers and one hafnium zirconium oxide layer. The two zirconium-rich hafnium zirconium oxide layers may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content to hafnium content ratio of about 2:1. One hafnium zirconium oxide layer may include hafnium zirconium oxide having a zirconium content to hafnium content ratio of about 1:1.

[0130] In the following, the FIG. 10B to FIG. 10F in Fig. 10A A detailed description of the overlapping parts of the embodiments.

[0131] refer to Fig. 10B , the capacitor 612 may include a lower electrode 601, a dielectric layer stack 603 and an upper electrode 602, the three of which are formed into a cylindrical shape. The capacitor 612 may also include a support member 600S. The support member 600S may be a structure that supports the outer wall of the lower electrode 601. The support member 600S may include, for example, silicon nitride. According to another embodiment of the present invention, a multi-level support member formed by a plurality of support members 600S may support the lower electrode 601. For example, the multi-level support member may be a two-level support member structure formed by a lower support member and an upper support member. In addition, the multi-level support member may be a three-level support member structure formed by a lower support member, an intermediate support member and an upper support member.

[0132] refer to Fig. 10C and Fig. 10D , the capacitor 613 and the capacitor 614 may include a lower electrode 601P, a dielectric layer stack 603 and an upper electrode 602, wherein the lower electrode has a columnar shape. Fig. 10D The capacitor 614 may also include a support member 600S.

[0133] refer to Fig.10E and Fig.10F, capacitor 615 and capacitor 616 may include a lower electrode 601L, a dielectric layer stack 603 and an upper electrode 602, wherein the lower electrode has a columnar shape ( Fig.10E ) or hybrid pillar-cylinder shape ( Fig.10F ). Fig.10F The capacitor 616 may further include a support member 600S. The lower electrode 601L may be a hybrid structure in which a columnar shape and a cylindrical shape are combined. More specifically, the lower electrode 601L may have a columnar lower portion and a cylindrical upper portion. This columnar and cylindrical hybrid structure may be simply referred to as a hybrid columnar-cylindrical structure. In one embodiment, the support member 600S may be in contact with the columnar shape of the lower electrode 601L.

[0134] The dielectric layer stack according to the above embodiment of the present invention can be applied to the peripheral circuit of DRAM. For example, DRAM may include: a memory cell ( Fig. 9A 500) and a peripheral circuit region including a peripheral transistor. The gate dielectric layer of the peripheral transistor may include one of the dielectric layer stacks of the above-mentioned embodiments of the present invention. For example, the gate dielectric layer of the peripheral transistor may include a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer between the first antiferroelectric layer and the second antiferroelectric layer. The gate dielectric layer of the peripheral transistor may include two zirconium-rich hafnium zirconium oxide layers and one hafnium zirconium oxide layer. The two zirconium-rich hafnium zirconium oxide layers may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content to hafnium content ratio of approximately 2:1. One hafnium zirconium oxide layer may include hafnium zirconium oxide having a zirconium content to hafnium content ratio of approximately 1:1.

[0135] Fig.11 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0136] refer to Fig.11 , the semiconductor device 700 may include a transistor. The semiconductor device 700 may include a semiconductor substrate 701, a gate dielectric layer 710, a gate electrode 720, a source region 740, and a drain region 750. The gate dielectric layer 710 may be formed over the semiconductor substrate 701, and the gate electrode 720 may be formed over the gate dielectric layer 710. The source region 740 and the drain region 750 may be formed in the semiconductor substrate 701.

[0137] The gate dielectric layer 710 may include one of the dielectric layer stacks according to the above-mentioned embodiments of the present invention. In this embodiment, the gate dielectric layer 710 may be a stack of three layers, the stack including a first antiferroelectric layer 711, a second antiferroelectric layer 712 and a ferroelectric layer 713, the ferroelectric layer 713 being disposed between the first antiferroelectric layer 711 and the second antiferroelectric layer 712. The first antiferroelectric layer 711 and the second antiferroelectric layer 712 may be made of the same antiferroelectric material or different antiferroelectric materials. The first antiferroelectric layer 711 and the second antiferroelectric layer 712 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 711 and the second antiferroelectric layer 712 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer 711 and the second antiferroelectric layer 712 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first antiferroelectric layer 711 and the second antiferroelectric layer 712 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) with a zirconium content of about 2:1 to hafnium content. Other suitable materials for the first antiferroelectric layer 711 and the second antiferroelectric layer 712 may include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3, NaNbO3 and combinations thereof. The ferroelectric layer 713 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 713 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 713 may include hafnium zirconium oxide (HfZrO) with a zirconium content of about 1:1 to hafnium content. Other suitable materials for the ferroelectric layer 713 may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, and combinations thereof.

[0138] The gate electrode 720 may be a metal gate electrode including a metal-based material, such as tungsten, aluminum, tungsten nitride, titanium nitride, titanium, or a combination thereof.

[0139] The source region 740 and the drain region 750 may include impurities of the same conductivity type. The source region 740 and the drain region 750 may include N-type impurities or P-type impurities. The N-type impurities may include, for example, phosphorus or arsenic, and the P-type impurities may include boron or indium.

[0140] According to another embodiment of the present invention, a thin interface layer may be further formed between the gate dielectric layer 710 and the semiconductor substrate 701. The thin interface layer may include, for example, silicon oxide or silicon oxynitride.

[0141] According to another embodiment of the present invention, the gate dielectric layer 710 may be applied to a gate dielectric layer of a fin-shaped FET.

[0142] The dielectric layer stack according to the above-mentioned embodiment of the present invention can be applied to a metal-insulator-metal (MIM) capacitor. For example, a MIM capacitor may include a first metal electrode, a second metal electrode, and a dielectric layer stack formed between the first metal electrode and the second metal electrode. The dielectric layer stack of the MIM capacitor may include one of the dielectric layer stacks of the above-mentioned embodiment of the present invention. For example, the dielectric layer stack may include a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer.

[0143] The dielectric layer stack according to the above-mentioned embodiment of the present invention can be applied to embedded DRAM. For example, the embedded DRAM may include a logic circuit and a capacitor, and the capacitor of the embedded DRAM may include a lower electrode, a dielectric layer stack and an upper electrode. The dielectric layer stack of the capacitor of the embedded DRAM may include one of the dielectric layer stacks of the above-mentioned embodiment of the present invention. For example, the dielectric layer stack may include a first antiferroelectric layer, a second antiferroelectric layer and a ferroelectric layer arranged between the first antiferroelectric layer and the second antiferroelectric layer.

[0144] The dielectric layer stack according to the above-mentioned embodiment of the present invention can be applied to 3D NAND (three-dimensional NAND). For example, 3D NAND may include a dielectric layer stack, which includes: a pillar-type channel layer; a word line, which surrounds the pillar-type channel layer; and a tunnel dielectric layer, which is between the pillar-type channel layer and the word line. At least the tunnel dielectric layer in the dielectric layer stack of the 3D NAND may include at least one of the first antiferroelectric layer, the second antiferroelectric layer and the ferroelectric layer of the above-mentioned embodiment of the present invention.

[0145] According to an embodiment of the present invention, the switching voltage, capacitance and polarization of the dielectric layer stack can be controlled by controlling the composition ratio between the ferroelectric material and the antiferroelectric material. Therefore, a volatile memory can be realized.

[0146] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A semiconductor device, comprising: a first electrode; a second electrode; as well as a dielectric layer stack located between the first electrode and the second electrode, wherein the dielectric layer stack comprises: First stack; a second laminate; and A high bandgap layer is disposed between the first stack and the second stack, wherein each of the first stack and the second stack includes a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer.

2. The semiconductor device according to claim 1, wherein The first antiferroelectric layer, the ferroelectric layer, and the second antiferroelectric layer are vertically arranged between the first electrode and the second electrode.

3. The semiconductor device according to claim 1, wherein The first antiferroelectric layer and the second antiferroelectric layer include the same antiferroelectric material or different antiferroelectric materials.

4. The semiconductor device according to claim 1, wherein: The first antiferroelectric layer, the second antiferroelectric layer, and the ferroelectric layer include an oxide containing hafnium, zirconium, and oxygen.

5. The semiconductor device according to claim 1, wherein The first antiferroelectric layer and the second antiferroelectric layer include antiferroelectric hafnium zirconium oxide, and the ferroelectric layer includes ferroelectric hafnium zirconium oxide.

6. The semiconductor device according to claim 1, wherein The first antiferroelectric layer and the second antiferroelectric layer include hafnium zirconium oxide having a zirconium content greater than a hafnium content.

7. The semiconductor device according to claim 1, wherein The ferroelectric layer includes a hafnium zirconium oxide having the same hafnium content as the zirconium content.

8. The semiconductor device according to claim 1, wherein Each of the first antiferroelectric layer, the second antiferroelectric layer, and the ferroelectric layer includes hafnium zirconium oxide, and The zirconium content of the first antiferroelectric layer and the second antiferroelectric layer is at least twice the hafnium content, and The ratio of hafnium content to zirconium content in the ferroelectric layer is 1:

1.

9. The semiconductor device according to claim 1, wherein: The first antiferroelectric layer and the second antiferroelectric layer include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3 or NaNbO3.

10. The semiconductor device according to claim 1, wherein The ferroelectric layer includes BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3 or BaSrTiO3.

11. The semiconductor device according to claim 1, further comprising: an interface layer disposed between the dielectric layer stack and the second electrode; as well as An additional interface layer is disposed between the first electrode and the dielectric layer stack.

12. The semiconductor device according to claim 11, wherein The interfacial layer includes a material that is reduced prior to the dielectric layer stack.

13. The semiconductor device according to claim 11, wherein The interface layer and the additional interface layer include a material having a greater electronegativity than the first and second antiferroelectric layers and the ferroelectric layer.

14. The semiconductor device according to claim 11, wherein The interface layer and the additional interface layer include titanium oxide, tantalum oxide, niobium oxide or tin oxide.

15. A semiconductor device comprising: a first electrode; a second electrode; as well as an alternating stack, which contacts the first electrode and the second electrode, the alternating stack comprising a plurality of dielectric layers and a plurality of leakage blocking layers that are alternately and vertically stacked, Each of the multiple dielectric layer stacks includes a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer arranged between the first antiferroelectric layer and the second antiferroelectric layer, and the leakage blocking layer is in contact with two of the dielectric layer stacks formed above and below the leakage blocking layer.

16. The semiconductor device according to claim 15, wherein: The first antiferroelectric layer, the ferroelectric layer, and the second antiferroelectric layer are vertically arranged between the first electrode and the second electrode.

17. The semiconductor device according to claim 15, wherein: The first antiferroelectric layer and the second antiferroelectric layer include antiferroelectric hafnium zirconium oxide, and the ferroelectric layer includes ferroelectric hafnium zirconium oxide.

18. The semiconductor device according to claim 15, wherein: The first antiferroelectric layer and the second antiferroelectric layer include hafnium zirconium oxide having a zirconium content greater than a hafnium content.

19. The semiconductor device according to claim 15, wherein: The ferroelectric layer includes a hafnium zirconium oxide having the same hafnium content as the zirconium content.

20. The semiconductor device according to claim 15, wherein The first antiferroelectric layer and the second antiferroelectric layer include PbZrO3, PbHfO3, PbMgWO3, PbZrTiO3, BiNaTiO3 or NaNbO3.

21. The semiconductor device of claim 15, wherein the ferroelectric layer comprises BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3 or BaSrTiO3.

22. The semiconductor device according to claim 15, further comprising: an interface layer disposed between the second electrode and the alternating stack; as well as An additional interface layer is disposed between the first electrode and the alternating stack.

23. The semiconductor device according to claim 22, wherein: The interfacial layer includes a material that is reduced prior to the dielectric layer stack.

24. The semiconductor device according to claim 22, wherein: The interface layer and the additional interface layer include a material having a greater electronegativity than the first and second antiferroelectric layers and the ferroelectric layer.

25. The semiconductor device according to claim 22, wherein: The interface layer and the additional interface layer include titanium oxide, tantalum oxide, niobium oxide or tin oxide.

26. The semiconductor device according to claim 15, wherein The first electrode includes a cylindrical shape, a columnar shape, or a mixed cylindrical shape.

27. The semiconductor device according to claim 15, further comprising: A support member is used to support the first electrode.

28. The semiconductor device according to claim 15, further comprising: a semiconductor substrate comprising a first doped region and a second doped region; a word line buried in the semiconductor substrate between the first doped region and the second doped region; a bit line formed above the word line and coupled to the first doped region; as well as a storage node contact plug coupled to the second doped region, Wherein, the first electrode is electrically connected to the storage node contact plug.

29. The semiconductor device according to claim 15, wherein: The first electrode, the alternating stack and the second electrode form a dynamic random access memory (DRAM) capacitor.

Images