Microelectronic device including decoupling capacitor, and related apparatus, electronic system and method

Abstract

The present application relates to microelectronic devices including decoupling capacitors, and related devices, electronic systems, and methods. A microelectronic device includes: a die including a front side and a back side opposite the front side; one or more components of an integrated circuit system within a base material of the die and between the front side and the back side of the die; and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors include a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further includes a first conductive via including a conductive material extending through the base material, the first conductive via being electrically connected to the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device. Related devices including a decoupling capacitor in the back side, as well as related electronic systems and methods are also described.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application Ser. No. 16 / 876,362, filed May 18, 2020, for “Microelectronic Devices Including Decoupling Capacitors, and Related Apparatuses, Electronic Systems, and Methods.” Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to microelectronic devices and apparatuses including one or more decoupling capacitors in their backsides, and to related electronic systems and methods of forming the microelectronic devices and apparatuses. Background Art

[0004] Microelectronic device designers often desire to increase the integration or density of features (e.g., components) within a microelectronic device (e.g., a semiconductor device) by reducing the size of individual features and by reducing the separation distance between adjacent features. Furthermore, microelectronic device designers often desire to design architectures that are not only compact but also provide performance advantages and simplify the design. Reducing the size and spacing of microelectronic device features places increasing demands on methods for forming microelectronic device features.

[0005] A relatively common microelectronic device is a memory device, which may include a memory array having a plurality of memory cells arranged in a grid pattern on the active surface of the device. One type of memory cell is a dynamic random access memory (DRAM) device, which is a volatile memory device that can lose its stored state over time unless the DRAM device is periodically refreshed by an external power source. In the simplest design configuration, a DRAM cell includes an access device (e.g., a transistor) and a storage device (e.g., a capacitor). Modern applications of memory devices may utilize a large number of DRAM unit cells arranged in an array of rows and columns. The DRAM cells can be electrically accessed via digit lines and word lines arranged along the rows and columns of the array. High data reliability, high-speed memory access, reduced chip size, and reduced power consumption are desirable performance attributes of DRAM devices. In a DRAM device, power lines provide power from an external power source to the components of the DRAM device (e.g., transistors, capacitors, etc.). The power lines are typically arranged as metal layers throughout the DRAM device.

[0006] A microelectronic device may include a decoupling capacitor configured to store local charge during switching of a logic load of the microelectronic device in order to control voltage variations and ensure the power integrity of the microelectronic device. However, the decoupling capacitor in the microelectronic device may consume a significant amount of useful active surface area on the microelectronic device die that could otherwise be used to improve the feature density (e.g., memory density) of the microelectronic device. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes: a die including a front side and a back side opposite the front side; one or more components of an integrated circuit system within a base material of the die and between the front side and the back side of the die; and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors each include a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further includes a first conductive via including a conductive material extending through the base material, the first conductive via being in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device.

[0008] In other embodiments, a device includes: an active circuit system adjacent to a base material; a decoupling capacitor in a back side of a die, the decoupling capacitor comprising a dielectric material between a first electrode and a second electrode; a first conductive via extending through the base material and electrically communicating with a front side of the die and the first electrode of the decoupling capacitor; and a second conductive via extending through the base material and electrically communicating with the front side of the die and the second electrode of the decoupling capacitor.

[0009] In yet other embodiments, a method of forming a microelectronic device includes forming a die including a front side and a back side opposite the front side, active circuitry located between the front side and the back side; forming a recess in a semiconductive material from the back side of the die to expose a portion of a first conductive via; forming a dielectric material within the recess; and forming a decoupling capacitor within the recess. Forming the decoupling capacitor includes forming an opening in the dielectric material to expose a portion of the first conductive via; forming a conductive material in electrical communication with the portion of the first conductive via; forming another dielectric material adjacent to the conductive material; and forming another conductive material adjacent to the another dielectric material and in electrical communication with a second conductive via.

[0010] In another embodiment, an electronic system includes: a processor device operatively coupled to an input device and an output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: an active area comprising a semiconductive material between a front side and a back side of a die; a decoupling capacitor in the back side of the die, the decoupling capacitor comprising a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode; a first conductive via extending through the semiconductive material and electrically communicating with the first electrode of the decoupling capacitor and the front side of the die; a redistribution line in electrical communication with the second electrode of the decoupling capacitor; and a second conductive via in electrical communication with the redistribution line and the front side of the die. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a simplified cross-sectional view of a microelectronic device according to an embodiment of the present disclosure;

[0012] Figure 1B is a simplified cross-sectional view of a microelectronic device according to an embodiment of the present disclosure;

[0013] Figures 2A to 2E For the purpose of explaining the embodiments of the present disclosure Figure 1A A simplified cross-sectional view of a microelectronic device structure of a microelectronic device method;

[0014] Figures 3A to 3E A simplified cross-sectional view of a microelectronic device structure illustrating a method of forming a microelectronic device including a decoupling capacitor according to an embodiment of the present disclosure;

[0015] Figures 4A to 4E A simplified cross-sectional view of a microelectronic device structure illustrating a method of forming a microelectronic device according to other embodiments of the present disclosure;

[0016] Figure 5 is a simplified cross-sectional view of a microelectronic device including a decoupling capacitor on the back side of a die according to an embodiment of the present disclosure;

[0017] Figure 6 is a block diagram of an electronic system according to an embodiment of the present disclosure;

[0018] Figure 7 is a processor-based system according to an embodiment of the present disclosure; and

[0019] Figure 8 is a simplified schematic perspective view of a microelectronic assembly including a host device in the form of a processor and a plurality of microelectronic devices mounted to an interposer according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The illustrations included herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations used to describe the embodiments herein. Elements and features that are common between the figures may retain the same numerical designations, but for ease of description below, the reference numerals begin with the number of the figure in which the element is introduced or most fully described.

[0021] The following description provides specific details, such as material type, material thickness, and processing conditions, in order to provide a full description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without adopting these specific details. In fact, the embodiments can be practiced in combination with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device, such as a DRAM memory device), an equipment, or an electronic system, or a complete microelectronic device, device, or electronic system including one or more decoupling capacitors on its back side. The structure described below does not form a complete microelectronic device, device, or electronic system. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions for forming a complete microelectronic device, device, or electronic system from the structure can be performed by conventional techniques.

[0022] The materials described herein can be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the material can be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material can be selected by one of ordinary skill in the art. Unless the context indicates otherwise, material removal can be achieved by any suitable technique, including but not limited to etching, grinding planarization (e.g., chemical-mechanical planarization), or other known methods.

[0023] As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" refer to a principal plane of a substrate (e.g., a base material, a base structure, a base configuration, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the principal plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of a substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0024] As used herein, the term "substantially" with respect to a given parameter, attribute, or condition means and encompasses the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is met to a degree of deviation (e.g., within an acceptable tolerance). By way of example, depending on the particular parameter, attribute, or condition that is substantially met, the parameter, attribute, or condition may be met by at least 90.0%, by at least 95.0%, by at least 99.0%, by at least 99.9%, or even by 100.0%.

[0025] As used herein, "about" or "approximately" with reference to a numerical value of a particular parameter includes the numerical value, and the degree of deviation from the numerical value that one of ordinary skill in the art would understand is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with reference to a numerical value may include additional numerical values ​​that are within 90.0% to 110.0% of the numerical value, such as within 95.0% to 105.0% of the numerical value, within 97.5% to 102.5% of the numerical value, within 99.0% to 101.0% of the numerical value, within 99.5% to 100.5% of the numerical value, or within 99.9% to 100.1% of the numerical value.

[0026] As used herein, spatially relative terms such as "below," "beneath," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," and similar spatially relative terms may be used to conveniently describe the relationship of one element or feature to another, as illustrated in the drawings. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the drawings. For example, if the material in the drawings were reversed, an element described as being "below," "beneath," "under," or "on the bottom" of another element or feature would be oriented "above" or "on the top" of the other element or feature. Thus, the term "below" can encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.), and the spatially relative descriptors used herein may be interpreted accordingly.

[0027] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory in the form of DRAM, NAND, etc., but also, by way of example only, means and includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device that combines logic and memory, or a graphics processing unit (GPU) that incorporates memory.

[0028] As used herein, the term "decoupling capacitor" means and includes a capacitor configured to decouple one part of a circuit (electrical network) from another part. For example, noise caused by other circuit elements (e.g., a power supply, an output, one or more memory devices, a memory array, or other components) can pass through (e.g., be shunted through) a decoupling capacitor, thereby reducing the impact of other circuit elements on the circuit (e.g., noise caused by them). A decoupling capacitor can be configured to store charge during the switching of a logic load of an associated logic device (e.g., a memory device) to control voltage changes and provide constant power to a microelectronic device. As a non-limiting example, a decoupling capacitor can be configured to suppress voltage surges that could otherwise damage other parts of the circuit. The terms "bypass capacitor" and "buffer capacitor" can be used interchangeably with "decoupling capacitor."

[0029] According to embodiments described herein, a microelectronic device includes a die including a front side (i.e., an active surface) and a back side opposite the front side. The die may include active circuitry between the front side and the back side. For example, the die may include front-end-of-line (FEOL) structures, such as various components of the active circuitry. The FEOL structures may include one or more of capacitors, transistors, electrodes, diodes, memory cells, resistors, metal structures, conductive lines (e.g., access lines, digit lines, word lines), and other components. In some embodiments, some components of the active circuitry are formed within or adjacent to a semiconducting material, while other components of the active circuitry are formed within or adjacent to an insulating material. The front side of the die may further include back-end-of-line (BEOL) structures above and adjacent to the FEOL structures. The BEOL structures may include various metal lines and redistribution lines for routing one or more electrical paths from the FEOL structures to the front side of the die.

[0030] The backside of the die may include one or more decoupling capacitors. The decoupling capacitors may include a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The first electrode may be electrically coupled to a first conductive via (e.g., a through-silicon via (TSV), a through-substrate via) extending through at least a portion of the die. The first conductive via may be electrically coupled to the front side. The second electrode may be electrically coupled to a second conductive via extending through at least a portion of the die. The second conductive via may be electrically connected to the front side of the die. Thus, the decoupling capacitors may be located within or near the backside of the die and may be electrically coupled to terminals on the front side of the die. In some embodiments, at least one of the first and second conductive vias is laterally offset from a corresponding one of the first and second electrodes by a redistribution line. Forming the decoupling capacitors in the backside of the die may facilitate providing the decoupling capacitors to the microelectronic device without substantially reducing the area on the active surface of the die available for various features of the die (e.g., memory devices). Additionally, because the decoupling capacitors are formed on the backside of the die (rather than the frontside, e.g., within or near the active circuitry area), the decoupling capacitors can be formed under less expensive processing conditions without requiring the tight tolerances of structures formed on the frontside of the die. Because the decoupling capacitors are fabricated separately from (e.g., decoupled from) the frontside processing, their fabrication may not directly impact the fabrication of the active circuitry, and the entire backside of the die may be available for the decoupling capacitors. Furthermore, forming the decoupling capacitors on the backside of the die may not increase the thickness of the frontside of the die, which would reduce the available thickness of the semiconducting material (e.g., silicon) of the die and reduce the impedance and strength of the die due to the corresponding reduction in bulk semiconducting material. Furthermore, forming the decoupling capacitors on the backside of the die may allow the die to be maintained at a minimum thickness suitable for mobile applications, which require a reduced height in terms of form factor parameters.

[0031] Figure 1A 1 is a simplified cross-sectional view of a microelectronic device 100 according to an embodiment of the present disclosure. The microelectronic device 100 may include a volatile or nonvolatile memory device (e.g., a semiconductor memory device). For example, the microelectronic device 100 may include dynamic random access memory (DRAM), magnetic random access memory (MRAM), static random access memory (SRAM), NAND flash memory, 3D memory (e.g., 3D DRAM, 3D SRAM) including stacked memory dies in the form of a high bandwidth memory (HBM) configuration such as DRAM, or another known memory type. However, the present disclosure is not limited thereto and the microelectronic device 100 may include other forms of memory devices.

[0032] The microelectronic device 100 may include a die 105 including a front side 101 and a back side 103 opposite the front side 101. In some embodiments, the microelectronic device 100 may also be referred to herein as a die. As will be described herein, during fabrication of the microelectronic device 100, various components thereof may be fabricated on the front side 101 and other components and structures may be fabricated on the back side 103.

[0033] Microelectronic device 100 includes front-end-of-the-line (FEOL) structures 110, including substrate material 106. FEOL structures 110 may include, for example, active circuitry such as one or more of capacitors, transistors, electrodes, diodes, memory cells, resistors, metal structures, conductive lines (access lines, digit lines, word lines), and other structures. In some embodiments, FEOL structures 110 include a memory array region.

[0034] The base material 106 may include the active surface 104. The base material 106 may include, for example, a semiconducting material including one or more of a semiconductor substrate, a base semiconductor material on a support structure, or a semiconductor substrate with one or more layers, structures, or regions formed thereon. The base material 106 may be a conventional silicon substrate or other bulk substrate including a layer of a semiconducting material. As used herein, the term "bulk substrate" refers to and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The base material 106 may be doped or undoped or may include one or more doped regions and one or more undoped regions.

[0035] In some embodiments, the base material 106 may include an electrically insulating structure 108, such as a shallow trench isolation (STI) structure therein. The electrically insulating structure 108 may be formed of, for example, silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbonoxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof. In some embodiments, the electrically insulating structure 108 includes silicon dioxide.

[0036] refer to Figure 1A, the FEOL structure 110 may include a transistor 112 overlying a base material 106 and within a dielectric material 114. The transistor 112 may include, for example, a gate dielectric material 116 adjacent to the base material 106 and spanning between a source region (not shown) and a drain region (not shown) of the base material 106; and a gate electrode 118 adjacent to the gate dielectric material 116. An insulating cap or sidewall spacer 120 may be positioned adjacent to the gate dielectric material 116 and the gate electrode 118. Although Figure 1A Transistor 112 is illustrated above base material 106, but in some embodiments, FEOL structure 110 may include transistor 112 recessed into base material 106. In some such embodiments, transistor 112 may be buried and isolated from base material 106 by, for example, gate dielectric material 116.

[0037] The conductive contact (e.g., conductive plug) 122 may form an electrical connection between the conductive pillar 124 and the base material 106. The conductive contact 122 may be formed of and include a conductive material (e.g., conductive material) such as a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); an alloy (e.g., Co-based alloy, Fe-based alloy, The conductive contact 122 may be a conductive contact material comprising one or more of: a Ni alloy, an Fe and Ni alloy, a Co and Ni alloy, an Fe and Co alloy, an Co, Ni and Fe alloy, an Al alloy, a Cu alloy, a magnesium (Mg) alloy, a Ti alloy, steel, mild steel, stainless steel); a conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)); a conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), or a combination thereof. In some embodiments, the conductive contact 122 is formed of and includes tungsten.

[0038] The conductive pillars 124 can be formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive contacts 122. In some embodiments, the conductive pillars 124 include tungsten. In other embodiments, the conductive pillars 124 include copper.

[0039] In some embodiments, the conductive posts 124 may form electrical contacts to the capacitors (which may be located in addition to Figure 1A), which is operably coupled to transistor 112 and is configured and arranged to store charge representing a logic state of the memory cell, as in a DRAM device.

[0040] The FEOL structure 110 may further include conductive traces 126 configured to reroute (eg, redistribute) signals from the various conductive materials.

[0041] Continue to refer Figure 1A , a back-end of line (BEOL) structure 130 may be positioned adjacent to and above the FEOL structure 110 proximate the front side 101 of the die 105. The BEOL structure 130 may include a number of dielectric and conductive materials selectively positioned and configured to form routing elements (e.g., lines, traces, pads, vias) positioned on a side of the FEOL structure 110 opposite the substrate material 106. As a specific non-limiting example, the BEOL structure 130 may include one or more metallization structures (e.g., metallization materials) M1, M2, M3, M4, M5, M6, M7, each of which includes one or more conductive structures (e.g., conductive plugs, conductive landing pads, conductive bonding pads, conductive posts, conductive contacts) 132 positioned within a dielectric material 134. In some embodiments, at least some of the conductive structures 132 may be in electrical communication with the conductive posts 124. The conductive structures 132 may facilitate lateral (lateral) transmission of signals or power. Figure 1A left and right) routing in the view of ; and Figure 1A The page spans the BEOL structure 130 and / or vertically (in Figure 1A 1 and 2) through the BEOL structure 130.

[0042] One or more conductive elements 136, for example in the form of copper pillars capped with solder, can be located on the front side 101 of the microelectronic device 100. The conductive elements 136 can be in electrical communication with at least some of the conductive structures 132. In some embodiments, the conductive elements 136 can comprise terminals of a capacitor structure 150 within the back side 103 of the die 105, as will be described herein. The capacitor structure 150 can comprise, for example, a decoupling capacitor and can be referred to herein as a decoupling capacitor.

[0043] Continue to refer Figure 1A, the microelectronic device 100 can include one or more decoupling capacitors 150 located on the back side 103 of the die 105. The decoupling capacitors 150 can be electrically isolated from the base material 106, for example, by an insulating material configured as a liner material 148. The insulating liner material 148 can include one or more dielectric materials, such as silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbonoxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof. In some embodiments, the insulating liner material 148 includes silicon dioxide.

[0044] The decoupling capacitor 150 can be electrically connected to a conductive via (eg, through silicon via (TSV), through substrate via) that is electrically coupled to the front side 101 of the microelectronic device 100. Figure 1A A single decoupling capacitor 150 is illustrated on the back side 103 , but the disclosure is not limited thereto. It should be understood that the back side 103 may include any number of decoupling capacitors 150 .

[0045] The decoupling capacitor 150 may include, for example, a first electrode 152, a dielectric material 154 adjacent to the first electrode 152, and a second electrode 156 adjacent to the dielectric material 154. The dielectric material 154 may be directly between the first electrode 152 and the second electrode 156.

[0046] The first electrode 152 and the second electrode 156 may each independently include a conductive material. For example, the first electrode 152 and the second electrode 156 may be independently formed of and include metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys, The first electrode 152 and the second electrode 156 may be a conductive material or a combination thereof. ...

[0047] The dielectric material 154 may be formed from and include one or more of silicon dioxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide (Al2O3), yttrium oxide (Y2O3), scandium oxide (Sc2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium silicate (ZrSiO4), hafnium silicate (HfSiO4), yttrium orthoaluminate (also known as yttrium aluminum perovskite; YAlO3), hafnium aluminum oxide (HfAlO3), lanthanum aluminate (LaAlO3), or hafnium silicon oxynitride (HfSiON). In some embodiments, the dielectric material 154 is formed from and includes silicon dioxide.

[0048] The first electrode 152 can be in electrical communication with the front side 101 of the microelectronic device 100 by means of a first conductive via 160. In some embodiments, the first conductive via 160 is in direct contact with the first electrode 152. The first conductive via 160 can include a conductive material 162 extending through the microelectronic device 100, for example, through the dielectric material 114. In some embodiments, the first conductive via 160 extends through the FEOL structure 110. Figure 1AThe conductive material 162 is illustrated as terminating at the BEOL structure 130, but it should be understood that the BEOL structure 130 may include a conductive structure 132 in electrical communication with the conductive material 162 for providing electrical communication between the conductive material 162 of the first conductive via 160 and the front side 101 of the microelectronic device 100. For example, the conductive structure 132 in electrical communication with the first conductive via 160 may be connected to the front side 101 of the microelectronic device 100. Figure 1A Other conductive structures 132 not shown in the cross-sectional view of FIG. 1 are in electrical communication with the front side 101. As an example, the conductive path between the first conductive via 160 and the front side 101 can be routed to a plurality of redistribution lines or redistribution structures other than the first conductive via 160. Figure 1A In some embodiments, first conductive via 160 is in electrical communication with front side 101 via conductive trace 126 and one or more conductive structures 132 .

[0049] Barrier material 164 may be adjacent to conductive material 162 and dielectric material 165 may be adjacent to barrier material 164. Barrier material 164 may be formulated and configured to prevent material (e.g., atoms) of conductive material 162 from diffusing from (e.g., away from) conductive material 162. Barrier material 164 may be formed of, for example, and include one or more of titanium nitride, tantalum nitride, titanium zirconium nitride, tungsten nitride, or another material. Dielectric material 165 may be formed of, for example, and include one or more of silicon dioxide, silicon nitride, silicon oxynitride, or another material.

[0050] The second electrode 156 can be in electrical communication with a redistribution line (RDL) 166 on the back side 103 of the microelectronic device 100. The redistribution line 166 can be formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive material 162. In some embodiments, the redistribution line 166 is formed of and includes copper. In other embodiments, the redistribution line 166 is formed of and includes tungsten.

[0051] Redistribution line 166 can be in electrical communication with a second conductive via 170. Second conductive via 170 can be formed of and include materials as described with reference to first conductive via 160. Second conductive via 170 can be in electrical communication with backside 103 and frontside 101 of microelectronic device 100. For example, second conductive via 170 can extend through dielectric material 114 and can be in electrical communication with frontside 101 via conductive structure 132, conductive trace 126, or a combination of conductive trace 126 and conductive structure 132. In some embodiments, second conductive via 170 extends through FEOL structure 110. In some embodiments, second conductive via 170 is in electrical communication with conductive element 136, which can include a terminal of decoupling capacitor 150.

[0052] In some embodiments, the second electrode 156 can be laterally offset from the second conductive via 170. The redistribution line 166 can be configured to redistribute (reroute) electrical signals from the front side 101 via the second conductive via 170 to the second electrode 156, which can be located at a different lateral location on the back side 103 than the terminal on the front side 101.

[0053] In some embodiments, the first conductive via 160 can be connected to the first terminal ( Figure 1A 10 and 11. The first and second terminals may be in electrical communication with each other (e.g., not shown in the cross-section of FIG. 10 ) and the second conductive via 170 may be in electrical communication with a second terminal (e.g., conductive element 136) on the front side 101. The first and second terminals may, in turn, be in electrical communication with various components or power supplies of the microelectronic device 100. By way of non-limiting example, one of the first and second terminals may be in electrical communication with electrical ground and the other of the first and second terminals may be in electrical communication with one or more components of the active circuitry (e.g., one or more of the capacitors in the FEOL structure 110). In some such embodiments, the decoupling capacitor 150 may be configured to store charge during switching of a logic load of the active circuitry (e.g., a memory device) of the microelectronic device 100 and may control voltage variations of the microelectronic device 100 and contribute to a constant power supply to the microelectronic device 100 and its components. In other embodiments, one of the first and second terminals may be in electrical communication with a positive supply voltage (e.g., V DD voltage) and the other of the first terminal and the second terminal can be connected to a second supply voltage (eg, V SS In some embodiments, decoupling capacitor 150 can be configured to electrically isolate transistor 112 from adjacent active circuitry (e.g., adjacent transistor 112, an adjacent power supply, or an adjacent conductive line electrically connected to adjacent active circuitry (e.g., adjacent transistor 112) or a power supply).

[0054] The dielectric material 172 can be adjacent to the redistribution line 166 and can electrically isolate the redistribution line 166 from other components of the microelectronic device 100. The dielectric material 172 can include one or more of silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbonoxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or combinations thereof. In some embodiments, the dielectric material 172 includes silicon dioxide.

[0055] Thus, the microelectronic device 100 can include one or more decoupling capacitors 150 located on the backside 103 of the microelectronic device 100. Because the decoupling capacitors 150 are located on the backside 103, the decoupling capacitors 150 can occupy more area of ​​the die 105 than in conventional microelectronic devices where the decoupling capacitors are formed in the FEOL structure or frontside of the microelectronic device. Additionally, because the decoupling capacitors 150 are formed in the backside 103, the decoupling capacitors 150 can be manufactured using less expensive and less complex processing methods than conventional decoupling capacitors formed in the frontside because the backside 103 may not include components that are as closely spaced as the frontside. Additionally, in some embodiments, a larger portion (e.g., substantially the entire portion) of the backside 103 can be used to form the decoupling capacitors 150 therein, compared to only a smaller portion of the frontside 101. Furthermore, because the decoupling capacitors 150 are formed in the backside 103 of the die 105 , the decoupling capacitors 150 do not directly impact the formation of active circuitry, such as in the FEOL structure 110 .

[0056] The decoupling capacitor 150 can be formed in the base material 106 without increasing the thickness (in Figure 1A In other words, the decoupling capacitors 150 do not thin the base material 106, which would otherwise reduce the impedance of the microelectronic device 100, thereby reducing the performance of the microelectronic device 100. Because the thickness of the base material 106 is not thinned by the presence of the decoupling capacitors 150, the microelectronic device 100 may not exhibit a reduction in die fracture strength.

[0057] In some embodiments, one or both of the first conductive via 160 and the second conductive via 170 can be in electrical communication with the front side 101 via a conductive trace (eg, conductive trace 126). Figure 1B In some embodiments, the second conductive via 170 can be in electrical communication with the front side 101 via the conductive trace 126. In some embodiments, the conductive trace 126 can route the signal from the second conductive via 170 to be laterally offset from the second conductive via 170 near the back side 103 on the front side 101 (e.g., at Figure 1B left and right in the view).

[0058] Figures 2A to 2E For the purpose of explaining the embodiments of the present disclosure Figure 1A A simplified cross-sectional view of a microelectronic device structure 200 of a method of a microelectronic device 100 is shown. Figure 2A The microelectronic device structure 200 includes a FEOL structure 110 including a substrate material 106. The FEOL structure 110 may be similar to the one described above with reference to Figure 1A and Figure 1BThe FEOL structures described are substantially the same.As described above, in some embodiments, one of the first conductive via 160 and the second conductive via 170 can be in electrical communication with the conductive trace 126.

[0059] Active circuitry may be formed within and adjacent to the base material 106. For example, one or more of capacitors, transistors (e.g., transistor 112), electrodes, diodes, memory cells, resistors, metal structures, conductive lines (access lines, digit lines, word lines), redistribution lines, and other component circuitry may be formed within and adjacent to the base material 106. The active circuitry may be formed by conventional techniques and procedures.

[0060] In some embodiments, the first conductive via 160 and the second conductive via 170 may be formed by a so-called "via-first" process, in which the first conductive via 160 and the second conductive via 170 are formed before the formation of active circuitry in the FEOL structure 110. In other embodiments, the first conductive via 160 and the second conductive via 170 may be formed by a so-called "via-middle" process, in which the first conductive via 160 and the second conductive via 170 are formed after the formation of active circuitry but before the formation of the BEOL structure 130. In still other embodiments, the first conductive via 160 and the second conductive via 170 are formed by a so-called "via-last" process, in which the first conductive via 160 and the second conductive via 170 are formed after or during the formation of the BEOL structure 130. In some embodiments, the first conductive via 160 and the second conductive via 170 are formed before the microelectronic device structure 200 is flipped over and processing actions are performed on the backside 103 of the microelectronic device structure 200.

[0061] refer to Figure 2B After forming the substrate material 106 and the FEOL structure 110, the BEOL structure 130 may be formed adjacent to the FEOL structure 110. The BEOL structure 130 may be similar to the one described above with reference to FIG. Figure 1A and Figure 1BThe BEOL structure 130 is substantially the same as described. For example, the BEOL structure 130 can be formed by forming a first metallization structure M1 adjacent to (e.g., above) the FEOL structure 110. For example, the first metallization structure M1 can be formed by forming a dielectric material 134 above the FEOL structure 110, forming an opening in the dielectric material 134, and forming a conductive structure 132 in the opening. A desired number of metallization structures M2, M3, M4, M5, M6, and M7 can be similarly formed adjacent to (e.g., above) the first metallization structure M1 and adjacent to the FEOL structure 110 to form the BEOL structure 130 and route electrical pathways to desired locations within the microelectronic device structure 200. The metallization structures M1, M2, M3, M4, M5, M6, and M7 can be formed using conventional techniques. After forming the desired number of metallization structures M1 , M2 , M3 , M4 , M5 , M6 , M7 , conductive balls 136 or other conductive structures may be formed on the exposed surface of the microelectronic device structure 200 .

[0062] refer to Figure 2C After forming the BEOL structure 130, the back side 103 may be processed. Figure 2C Show relative to Figure 2B Inverted (e.g., flipped) microelectronic device structure 200. In some embodiments, a portion of substrate material 106 can be removed (e.g., thinned), for example, by chemical mechanical planarization (CMP). In some embodiments, removing a portion of substrate material 106 can expose at least a portion of second conductive via 170. For example, surface 202 of second conductive via 170 can be exposed after exposing backside 103 to a CMP process.

[0063] A recess 204 may be formed in the base material 106 to expose a portion of the first conductive via 160. By way of non-limiting example, a mask material (e.g., a photomask) may be formed over the base material 106 and an opening (corresponding to the location of the recess 204) may be formed in the mask material. The recess 204 may be formed through the mask material, such as by photolithography.

[0064] After forming the recess 204, an insulating liner material 148 may be formed in the recess 204. The insulating liner material 148 may be formed by one or more of spin coating, blanket coating, CVD, ALD, plasma-enhanced ALD, PVD, PECVD, or LPCVD. After forming the insulating liner material 148, at least a portion of the insulating liner material 148 may be removed to expose the conductive material 162 of the first conductive via 160.

[0065] refer to Figure 2D, a conductive material may be formed and patterned within the recess 204 to form the first electrode 152. By way of non-limiting example, the conductive material may be formed by one or more of coating, blanket coating, CVD, ALD, plasma-enhanced ALD, PVD, PECVD, or LPCVD. After forming the conductive material, portions of the conductive material above the surface of the base material 106 may be removed (e.g., by CMP) to form the first electrode 152. The first electrode 152 may include a surface extending along the sidewalls of the insulating liner material 148 within the recess 204.

[0066] After forming the first electrode 152, a dielectric material 254 may be formed within the recess 204 and over the base material 106. The dielectric material 254 may include the dielectric material 154 ( Figure 1A , Figure 1B ). In some embodiments, dielectric material 254 includes silicon dioxide. Dielectric material 254 can be formed by one or more of coating, blanket coating, CVD, ALD, plasma-enhanced ALD, PVD, PECVD, or LPCVD.

[0067] refer to Figure 2E After forming the dielectric material 254, a conductive material may be formed in the recess 204 ( Figure 2D ) to form the second electrode 156. The conductive material can be formed by one or more of coating, blanket coating, CVD, ALD, plasma-enhanced ALD, PVD, PECVD, or LPCVD. In other embodiments, the second electrode 156 is formed by electrochemical deposition (ECD) or electrochemical deposition plating. The formation of the second electrode 156 can form the decoupling capacitor 150 in the back side 103 of the microelectronic device structure 200.

[0068] After forming the second electrode 156, a conductive material may be formed to electrically communicate with the second electrode 156 and the first conductive via 160 to form a redistribution line 166 ( Figure 1A , Figure 1B In some embodiments, a masking material can be formed over the microelectronic device structure 200 and patterned to include openings at locations corresponding to the locations of the redistribution lines 166 .

[0069] After forming the mask material, portions of the dielectric material 254 exposed through the mask material may be removed. For example, the dielectric material 254 may be removed by exposing portions of the dielectric material 254 to one or more of hydrofluoric acid or a dry etchant, such as sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), oxygen, trifluoromethane (also known as trifluoromethane (fluoroform); CHF3), hexafluoroethane (C2F6), perfluoropropane (C3F8), or perfluorocyclopentene (also known as octafluorocyclopentene; C5F8).

[0070] After forming the redistribution line 166, the dielectric material 172 ( Figure 1A , Figure 1B ) may be formed over the base material 106 and the redistribution line 166 of the microelectronic device structure 200 to form Figure 1A The dielectric material 172 may be formed by one or more of coating, blanket coating, CVD, ALD, plasma enhanced ALD, PVD, PECVD, or LPCVD. In some embodiments, the dielectric material 172 has the same material composition as the dielectric material 254 and is formed by one or more of the following methods: Figure 1A It should be understood that in other embodiments, dielectric material 172 and dielectric material 254 may comprise different material compositions.

[0071] although Figure 1A 、 Figure 1B and Figures 2A to 2E While the present disclosure has been described and illustrated as including the decoupling capacitor 150 having a particular configuration, the present disclosure is not limited thereto. Figures 3A to 3E A simplified cross-sectional view of a microelectronic device structure 300 illustrating a method of forming a microelectronic device including a decoupling capacitor according to an embodiment of the present disclosure.

[0072] Figure 3A FIG is a simplified cross-sectional view of the microelectronic device structure 300. The microelectronic device structure 300 is similar to the microelectronic device structure 300 described above. Figure 2C The described microelectronic device structure 200 can be formed in substantially the same manner and can be substantially the same. For example, after forming the FEOL structure 110 adjacent to the substrate material 106, the BEOL structure 130 can be formed adjacent to the FEOL structure 110, and the microelectronic device structure 300 can be flipped over. After flipping the microelectronic device structure 300, the recess 204 can be formed in the substrate material 106 and the insulating liner material 148 can be formed within the recess 204, as described above with reference to FIG. Figure 2C described.

[0073] refer to Figure 3AAfter forming the insulating lining material 148 in the recess 204, the conductive material 312 may be formed in the recess 204 ( Figure 2C ). The conductive material 312 may include one or more conductive materials, such as the first electrode 152 ( Figure 1A , Figure 1B ) . Conductive material 312 may substantially completely fill recess 204. In some embodiments, conductive material 312 is formed of and includes copper. In other embodiments, conductive material 312 is formed of and includes tungsten. The exposed surface of microelectronic device structure 300 may be exposed to a CMP process to substantially planarize conductive material 312. In some embodiments, the exposed surface of conductive material 312 may be substantially coplanar with the exposed surface of base material 106.

[0074] refer to Figure 3B , portions of conductive material 312 may be removed to form first electrode 352 comprising fingers 314 of conductive material 312 separated by gaps 316. For example, first electrode 352 may be formed by forming a masking material over microelectronic device structure 300. Openings may be formed through the masking material at locations corresponding to gaps 316 to expose conductive material 312 through the openings in the masking material. Exposed portions of conductive material 312 may be removed through the openings in the masking material to form gaps 316. After gaps 316 are formed, the masking material may be removed.

[0075] refer to Figure 3C , dielectric material 354 may be formed over first electrode 352. In some embodiments, dielectric material 354 is conformally formed over first electrode 352 and may not completely fill gap 316. Dielectric material 354 may be formed by one or more of coating, blanket coating, CVD, ALD, plasma-enhanced ALD, PVD, PECVD, or LPCVD. In some embodiments, dielectric material 354 is formed by ALD. In other embodiments, dielectric material 354 is formed by CVD. In some embodiments, dielectric material 354 is formed over an exposed surface of substrate material 106.

[0076] The dielectric material 354 may include the dielectric material 154 ( Figure 1A , Figure 1B ) In some embodiments, dielectric material 354 includes silicon dioxide.

[0077] refer to Figure 3D After forming the dielectric material 354, the second electrode 356 may be formed in the gap 316 ( Figure 3C) and formed over the dielectric material 354 to form the decoupling capacitor 350. The second electrode 356 may include the second electrode 156 ( Figure 1A , Figure 1B ) One or more of the conductive materials described. The second electrode 356 may substantially fill the gap 316 ( Figure 3C ) and may include fingers 318. In some embodiments, first electrode 352 and second electrode 356 may include so-called "interdigitated electrodes," each including portions (e.g., fingers 314, 318) located between adjacent portions of the other electrode (e.g., fingers 314, 318) and separated by dielectric material 354. In some embodiments, second electrode 356 includes copper. In other embodiments, second electrode 356 includes tungsten.

[0078] refer to Figure 3E After forming the second electrode 356, an opening can be formed in the dielectric material 354 above the second conductive via 170 to expose the conductive material 162. After exposing the conductive material 162, a redistribution line 166 can be formed above the second electrode 356 and extend between the conductive material 162 of the second conductive via 170 and the second electrode 356. After forming the redistribution line 166, a dielectric material 360 can be formed over the microelectronic device structure 300 to form the microelectronic device 300'. The dielectric material 360 can include, for example, one or more of silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, a nitride material, an oxynitride (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), and a dielectric carbonoxynitride material (e.g., silicon carbon oxynitride (SiOCN)). In some embodiments, the dielectric material 360 includes silicon dioxide.

[0079] Figures 4A to 4E is a simplified cross-sectional view of a microelectronic device structure 400 illustrating methods of forming a microelectronic device according to other embodiments of the present disclosure. Figure 4A FIG. 4 is a simplified cross-sectional view of a microelectronic device structure 400. The microelectronic device structure 400 is similar to the microelectronic device structure 400 described above. Figure 2C The described microelectronic device structure 200 can be formed in substantially the same manner and can be substantially the same, except for the recess 204 ( Figure 2C) may not be formed except in the backside 103 of the microelectronic device structure 400. For example, after forming the FEOL structure 110 adjacent to the base material 106 and forming the BEOL structure 130 adjacent to the FEOL structure 110, the microelectronic device structure 400 can be flipped over. After flipping the microelectronic device structure 400, a portion of the base material 106 can be removed (e.g., thinned) to expose the conductive material 162 of each of the first conductive via 160 and the second conductive via 170.

[0080] refer to Figure 4B After exposing the first conductive via 160 and the second conductive via 170, electrical contacts can be individually formed to each of the first conductive via 160 and the second conductive via 170. In some embodiments, a dielectric material 402 is formed over the base material 106 and an opening is formed through the dielectric material 402 to expose the conductive material 162 of the second conductive via 170. In some embodiments, the dielectric material 402 is adjacent to (e.g., overlying) the conductive material 162 of the first conductive via 160.

[0081] A conductive material may be formed in the opening in the dielectric material 402 to form a first electrode 452. The first electrode 452 may include the conductive material described above with reference to the first electrode 152 ( Figure 1A , Figure 1B )One or more of the conductive materials described.

[0082] refer to Figure 4C , the dielectric material 454 may be formed above the first electrode 452. The dielectric material 454 may have a greater length (in Figure 4C ). The dielectric material 454 may include the above-referenced dielectric material 154 ( Figure 1A , Figure 1B ) One or more of the materials described.

[0083] After forming the dielectric material 454, the conductive material 162 of the first conductive via 160 may be exposed, for example, by removing a portion of the dielectric material 402 adjacent to the first conductive via 160. Figure 4D , a conductive material may be formed over the dielectric material 454 and patterned to form a second electrode 456 and a redistribution line 466. The second electrode 456 may include the second electrode 156 ( Figure 1A , Figure 1B ) One or more of the materials described.

[0084] First electrode 452, dielectric material 454, and second electrode 456 may form decoupling capacitor 450. Decoupling capacitor 450 may be referred to as a so-called "plate capacitor." First electrode 452 may be in electrical communication with front side 101 via second conductive via 170 and conductive structure 132 of BEOL structure 130. Second electrode 456 may be in electrical communication with front side 101 via first conductive via 160 and conductive structure 132 of BEOL structure 130.

[0085] refer to Figure 4E A dielectric material 172 may be formed over the second electrode 456 to electrically isolate the decoupling capacitor 450 from other components and form the microelectronic device 400 ′.

[0086] Although the microelectronic devices 100, 300', 400' have been described and illustrated as including a single decoupling capacitor (e.g., decoupling capacitors 150, 350, 450) on the back side 103, the present disclosure is not limited thereto. In other embodiments, the microelectronic device may include more than one decoupling capacitor (e.g., a plurality of decoupling capacitors) on the back side 103. Figure 5 FIG. 5 is a simplified cross-sectional view of a microelectronic device 500 including a plurality of decoupling capacitors 150 on the back side 103 of the die 105 according to an embodiment of the present disclosure. Figure 1A The decoupling capacitors 150 described may be substantially the same. Figure 5 A plurality of decoupling capacitors 150 are illustrated, but the microelectronic device 100, 300', 400' may include two or more decoupling capacitors 150, 350, 450. In other embodiments, at least one of the decoupling capacitors 150 may be connected to a Figure 1A or Figure 1B The decoupling capacitors 150 are substantially identical and at least one other of the decoupling capacitors 150 may be substantially identical to the decoupling capacitors 150. Figure 3D Decoupling capacitors of 350 or Figure 4E The decoupling capacitor 450 is substantially the same. The capacitor structures 150, 350, 450 can be as described above with reference to Figure 1A 、 Figure 1B 、 Figure 3E and Figure 4E The capacitor structure 150 is formed as described.

[0087] although Figure 5 Only two decoupling capacitors 150 are illustrated, but it is understood that the back side 103 of the die 105 may include any number (eg, three, four, ten, fifty, one hundred, one thousand) of decoupling capacitors 150 .

[0088] Each of the decoupling capacitors 150 may be in electrical communication with the front side 101, as described above with reference to FIG. Figure 1A and Figure 1BIn some embodiments, at least one of the decoupling capacitors 150 may be electrically connected to the front side 101 via the conductive structure 502. For example, the conductive structure 502 may be located at a different Figure 5 In other embodiments, the conductive structure 502 is in electrical communication with the front side 101 via conductive vias located in substantially the same plane.

[0089] In some embodiments, one of the electrodes of the decoupling capacitors 150 (e.g., the second electrode 156) can be in electrical communication with the same redistribution line 166. In other words, the redistribution line 166 can be common between more than one of the decoupling capacitors 150. However, in other embodiments, at least one of the decoupling capacitors 150 (e.g., each of the decoupling capacitors 150) can be electrically isolated from the other decoupling capacitors 150 and may not share, for example, a redistribution line 166 with any other of the decoupling capacitors 150.

[0090] Thus, in at least some embodiments, a microelectronic device includes: a die including a front side and a back side opposite the front side; one or more components of an integrated circuit system within a base material of the die and between the front side and the back side of the die; and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors each include a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further includes a first conductive via including a conductive material extending through the base material, the first conductive via being in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device.

[0091] Thus, in at least some embodiments, a device includes: an active circuit system adjacent to a substrate material; a decoupling capacitor in a back side of a die, the decoupling capacitor comprising a dielectric material between a first electrode and a second electrode; a first conductive via extending through the substrate material and electrically communicating with a front side of the die and the first electrode of the decoupling capacitor; and a second conductive via extending through the substrate material and electrically communicating with the front side of the die and the second electrode of the decoupling capacitor.

[0092] Thus, in at least some embodiments, a method of forming a microelectronic device includes forming a die comprising a front side and a back side opposite the front side, active circuitry located between the front side and the back side; forming a recess in a semiconductive material from the back side of the die to expose a portion of a first conductive via; forming a dielectric material within the recess; and forming a decoupling capacitor within the recess. Forming the decoupling capacitor includes forming an opening in the dielectric material to expose a portion of the first conductive via; forming a conductive material in electrical communication with the portion of the first conductive via; forming another dielectric material adjacent to the conductive material; and forming another conductive material adjacent to the another dielectric material and in electrical communication with a second conductive via.

[0093] Microelectronic devices including microelectronic devices (e.g., microelectronic devices 100, 300', 400', 500) and microelectronic device structures (e.g., microelectronic device structures 200, 300, 400) including decoupling capacitors (e.g., decoupling capacitors 150, 350, 450) according to embodiments of the present disclosure may be used in embodiments of electronic systems of the present disclosure. For example, Figure 6 6 is a block diagram of an electronic system 603 according to an embodiment of the present disclosure. The electronic system 603 may include, for example, a computer or computer hardware component, a server or other network connection hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 603 includes at least one memory device 605. The memory device 605 may include, for example, an embodiment of a microelectronic device structure previously described herein (e.g., as previously described with reference to FIG. 1 ) including a decoupling capacitor (e.g., decoupling capacitors 150, 350, 450). Figures 2A to 5 One of the described microelectronic devices 100 , 300 ′, 400 ′, 500 or microelectronic device structures 200 , 300 , 400 ).

[0094] The electronic system 603 may further include at least one electronic signal processing device 607 (often referred to as a "microprocessor"). The electronic signal processing device 607 may optionally include an embodiment of a microelectronic device or microelectronic device structure previously described herein (e.g., previously described with reference to Figure 1A 、 Figure 1B 、 Figures 2A to 5The electronic system 603 may further include one or more input devices 609 for inputting information into the electronic system 603 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 603 may further include one or more output devices 611 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 609 and the output device 611 may include a single touch screen device that can be used to both input information into the electronic system 603 and output visual information to the user. The input device 609 and the output device 611 may be in electrical communication with one or more of the memory device 605 and the electronic signal processor device 607.

[0095] refer to Figure 7 , depicting a processor-based system 700. The processor-based system 700 may include various microelectronic devices and microelectronic device structures fabricated according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of the microelectronic devices 100, 300', 400', 500 or microelectronic device structures 200, 300, 400). The processor-based system 700 may be any of a variety of types, such as a computer, a pager, a cellular telephone, a personal assistant, a control circuit, or other electronic device. The processor-based system 700 may include one or more processors 702 (e.g., microprocessors) to control system functions and processing requests in the processor-based system 700. The processor 702 and other subcomponents of the processor-based system 700 may include microelectronic devices and microelectronic device structures fabricated according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of the microelectronic devices 100, 300', 400', 500 or microelectronic device structures 200, 300, 400).

[0096] The processor-based system 700 may include a power source 704 in operable communication with the processor 702. For example, if the processor-based system 700 is a portable system, the power source 704 may include one or more of a fuel cell, a power purification device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power source 704 may also include an AC adapter; thus, the processor-based system 700 may be plugged into a wall outlet. For example, the power source 704 may also include a DC adapter, so that the processor-based system 700 may be plugged into a vehicle cigarette lighter or vehicle power port.

[0097] Various other devices may be coupled to processor 702 depending on the functions performed by processor-based system 700. For example, a user interface 706 may be coupled to processor 702. User interface 706 may include input devices such as buttons, switches, a keyboard, a light pen, a mouse, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, or a combination thereof. A display 708 may also be coupled to processor 702. Display 708 may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projection, an audio display, or a combination thereof. Furthermore, an RF subsystem / baseband processor 710 may also be coupled to processor 702. RF subsystem / baseband processor 710 may include an antenna coupled to an RF receiver and to an RF transmitter (not shown). A communication port 712 or more communication ports 712 may also be coupled to processor 702. The communication port 712 may be adapted to couple to one or more peripheral devices 714, such as a modem, printer, computer, scanner, or camera, or to a network, such as a local area network, a remote local area network, an intranet, the Internet, or the like.

[0098] The processor 702 can control the processor-based system 700 by executing software programs stored in the memory. For example, the software programs may include an operating system, database software, drawing software, word processing software, media editing software, or media playback software. The memory is operably coupled to the processor 702 to store and facilitate the execution of various programs. For example, the processor 702 may be coupled to a system memory 716, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory 716 may include volatile memory, non-volatile memory, or a combination thereof. The system memory 716 is typically large so that it can store dynamically loaded applications and data. In some embodiments, system memory 716 may include semiconductor devices such as the microelectronic devices and microelectronic device structures described above (eg, microelectronic devices 100, 300', 400', 500 and microelectronic device structures 200, 300, 400), or combinations thereof.

[0099] Processor 702 may also be coupled to nonvolatile memory 718, which does not necessarily imply that system memory 716 is volatile. Nonvolatile memory 718 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 716. The size of nonvolatile memory 718 is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Furthermore, for example, nonvolatile memory 718 may include mass storage such as disk drive memory, such as a hybrid drive including resistive memory, or other types of nonvolatile solid-state memory. Nonvolatile memory 718 may include microelectronic devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic devices 100, 500 and microelectronic device structures 200, 300, 400), or combinations thereof.

[0100] Thus, in at least some embodiments, an electronic system includes: a processor device operatively coupled to an input device and an output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: an active area comprising a semiconductive material between a front side and a back side of a die; a decoupling capacitor in the back side of the die, the decoupling capacitor comprising a first electrode, a second electrode, and a dielectric material between the first and second electrodes; a first conductive via extending through the semiconductive material and electrically communicating with the first electrode of the decoupling capacitor and the front side of the die; a redistribution line in electrical communication with the second electrode of the decoupling capacitor; and a second conductive via in electrical communication with the redistribution line and the front side of the die.

[0101] Figure 8 is a simplified schematic perspective view of a microelectronic assembly 800 according to an embodiment of the present disclosure, including a host device in the form of a processor 802 and a plurality of microelectronic devices 804a-804d (collectively referred to herein as reference 804) mounted to an interposer 806 comprising semiconductor material (eg, silicon).

[0102] The processor 802 may be any of a number of configurations of a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a controller), or a system on a chip (SoC), or some other form of host device. The microelectronic device 804 of the plurality of microelectronic devices 804 may include the microelectronic device described above with reference to FIG. Figures 1A to 5One or more of the described microelectronic devices 100, 500 or microelectronic device structures 200, 300, 400. The microelectronic devices 804 may be of the same or different forms; and any of the memory devices may be a single die or a stack of interconnected memory dies.

[0103] The processor 802 can exchange information with one or more of the microelectronic devices 804 using signals communicated via signal paths formed at least partially within the interposer 806. In some embodiments, the interposer 806 is coupled to an external structure, such as a package substrate, a motherboard, etc., to form a larger system (e.g., the processor-based system 700). Figure 7 )) part.

[0104] Additional non-limiting example embodiments of the present disclosure are described below.

[0105] Embodiment 1: A microelectronic device comprises: a die including a front side and a back side opposite the front side; one or more components of an integrated circuit system within a base material of the die and between the front side and the back side of the die; and one or more decoupling capacitors within the back side of the die, each of the one or more decoupling capacitors comprising: a first electrode; a second electrode; and a dielectric material between the first electrode and the second electrode; and a first conductive via comprising a conductive material extending through the base material, the first conductive via being electrically connected to the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device.

[0106] Embodiment 2: The microelectronic device of Embodiment 1, further comprising a second conductive via in electrical communication with the second electrodes of the one or more capacitors and the front side of the microelectronic device.

[0107] Embodiment 3: The microelectronic device of Embodiment 2, wherein the second conductive via is in electrical communication with the second electrode via a redistribution line.

[0108] Embodiment 4: The microelectronic device of Embodiment 2 or Embodiment 3, wherein the second conductive via is laterally offset from the second electrode.

[0109] Embodiment 5: The microelectronic device of any one of embodiments 1 to 4, wherein the dielectric material comprises silicon dioxide.

[0110] Embodiment 6: The microelectronic device of any one of embodiments 1 to 5, wherein the first conductive via is in direct contact with the first electrode.

[0111] Embodiment 7: The microelectronic device of any one of embodiments 1 to 6, wherein the first conductive via extends through a memory array region of the microelectronic device.

[0112] Embodiment 8: The microelectronic device of any one of Embodiments 1 to 7, wherein the first electrode and the second electrode comprise interdigitated electrodes.

[0113] Embodiment 9: The microelectronic device of any one of Embodiments 1 to 8, wherein the first electrode includes sidewalls extending in a substantially perpendicular direction relative to the major surface of the base material.

[0114] Embodiment 10: A device comprising: an active circuit system adjacent to a substrate material; a decoupling capacitor in a back side of a tube core, the decoupling capacitor comprising a dielectric material between a first electrode and a second electrode; a first conductive via extending through the substrate material and electrically connected to a front side of the tube core and the first electrode of the decoupling capacitor; and a second conductive via extending through the substrate material and electrically connected to the front side of the tube core and the second electrode of the decoupling capacitor.

[0115] Embodiment 11: The apparatus of Embodiment 10, wherein the first conductive via is directly adjacent to and in contact with the first electrode.

[0116] Embodiment 12: The apparatus of Embodiment 10 or Embodiment 11, further comprising a redistribution line extending between the second conductive via and the second electrode.

[0117] Embodiment 13: The apparatus of Embodiment 12, further comprising another decoupling capacitor in the back side of the die, the another decoupling capacitor comprising another electrode in electrical communication with the redistribution line.

[0118] Embodiment 14: The apparatus of any one of Embodiments 10 to 13, wherein the first conductive via and the second conductive via comprise copper.

[0119] Embodiment 15: The apparatus of any one of Embodiments 10 to 14, wherein the first electrode includes portions separated from each other by the dielectric material and portions of the second electrode.

[0120] Embodiment 16: The apparatus of any one of Embodiments 10 to 15, wherein the first conductive via is in electrical communication with the front side of the die via a conductive structure in a metallization layer of the die.

[0121] Embodiment 17: The apparatus of any one of embodiments 10 to 16, wherein the first electrode and the second electrode are substantially planar.

[0122] Embodiment 18: The apparatus of any one of Embodiments 10 to 17, wherein the first conductive via is electrically connected to a voltage source.

[0123] Example 19: A method of forming a microelectronic device, the method comprising: forming a tube core including a front side and a back side opposite to the front side, and an active circuit system located between the front side and the back side; forming a recess in a semi-conductive material from the back side of the tube core to expose a portion of a first conductive via; forming a dielectric material in the recess; and forming a decoupling capacitor in the recess, forming the decoupling capacitor comprising: forming an opening in the dielectric material to expose a portion of the first conductive via; forming a conductive material electrically connected to the portion of the first conductive via; forming another dielectric material adjacent to the conductive material; and forming another conductive material adjacent to the another dielectric material and electrically connected to a second conductive via.

[0124] Embodiment 20: The method of Embodiment 19, wherein forming another conductive material adjacent to the another dielectric material and in electrical communication with the second conductive via comprises forming a redistribution line in electrical communication with the second conductive via and the second electrode.

[0125] Embodiment 21: The method of Embodiment 19 or Embodiment 20, wherein forming another conductive material comprises forming the another conductive material to be laterally offset from the second conductive via.

[0126] Embodiment 22: The method of any one of Embodiments 19 to 21, wherein forming a conductive material in electrical communication with the portion of the first conductive via comprises forming the conductive material to include portions separated from each other by gaps.

[0127] Embodiment 23: The method of any one of Embodiments 19 to 22, further comprising forming at least one of the first conductive via and the second conductive via to extend through the active circuitry.

[0128] Embodiment 24: An electronic system comprises: a processor device operably coupled to an input device and an output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device, the microelectronic device comprising: an active area comprising a semiconductive material between a front side and a back side of a die; a decoupling capacitor in the back side of the die, the decoupling capacitor comprising a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode; a first conductive via extending through the semiconductive material and electrically connected to the first electrode of the decoupling capacitor and the front side of the die; a redistribution line electrically connected to the second electrode of the decoupling capacitor; and a second conductive via electrically connected to the redistribution line and the front side of the die.

[0129] Although certain illustrative embodiments have been described in conjunction with the drawings, those skilled in the art will recognize and appreciate that the embodiments encompassed by the present disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure (such as those claimed herein, including legal equivalents). Additionally, features from one disclosed embodiment may be combined with features from another disclosed embodiment and still be encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device comprising: a die comprising a front side and a back side opposite the front side; one or more components of an integrated circuit system between the front side and the back side of the die; as well as one or more decoupling capacitors within a substrate material on the backside of the die, the substrate material comprising a semiconductor material, the one or more decoupling capacitors each comprising a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode, the dielectric material comprising: vertically extending portions, each vertically extending portion being between a sidewall of the first electrode and an additional sidewall of the second electrode; and at least one lateral extension portion between a lateral surface of the first electrode and a lateral surface of the second electrode, the at least one lateral extension portion connecting the vertical extension portion; a first conductive via comprising a conductive material extending through the base material, the first conductive via being in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device; a redistribution line in direct contact with the second electrode of the one or more decoupling capacitors; and a second conductive via in direct contact with a redistribution line and in electrical communication with the second electrodes of the one or more decoupling capacitors via the redistribution line, the second conductive via extending through the entire vertical thickness of the base material, the second conductive via being in electrical communication with the front side of the microelectronic device; 2 . The microelectronic device of claim 1 , wherein the second conductive via is laterally offset from the second electrode. The microelectronic device of claim 1 , wherein the dielectric material comprises silicon dioxide. The microelectronic device of claim 1 , wherein the first conductive via is in direct contact with the first electrode.

5. The microelectronic device of any one of claims 1 to 4, wherein the first conductive via extends through a memory array region of the microelectronic device.

6. The microelectronic device of any one of claims 1 to 4, wherein the first electrode and the second electrode comprise interdigitated electrodes.

7. A microelectronic device as claimed in any one of claims 1 to 4, wherein the first electrode comprises sidewalls extending in a substantially vertical direction relative to the major surface of the base material.

8. A device comprising: active circuitry adjacent to a substrate material comprising a semiconductor material; a decoupling capacitor in the base material on the backside of the die, the decoupling capacitor comprising a dielectric material between a first electrode and a second electrode, the dielectric material comprising: vertically extending portions, each vertically extending portion being between a sidewall of the first electrode and an additional sidewall of the second electrode; and at least one lateral extension portion between a lateral surface of the first electrode and a lateral surface of the second electrode, the at least one lateral extension portion connecting the vertical extension portion; a first conductive via extending through the base material and in electrical communication with the front side of the die and the first electrode of the decoupling capacitor; a second conductive via extending through the entire vertical thickness of the base material and in electrical communication with the front side of the die; and a redistribution line in direct contact with the second electrode of the decoupling capacitor and the second conductive via, the redistribution line extending between the second conductive via and the second electrode of the decoupling capacitor, The second conductive via is electrically connected to the second electrode of the decoupling capacitor via the redistribution line.

9. The apparatus of claim 8, wherein the first conductive via is directly adjacent to and in contact with the first electrode of the decoupling capacitor.

10. The apparatus of claim 8, further comprising another decoupling capacitor in the back side of the die, the another decoupling capacitor comprising another electrode in electrical communication with the redistribution line.

11. The apparatus of claim 8, wherein the first conductive via and the second conductive via comprise copper.

12. The apparatus of any one of claims 8 to 11, wherein the first electrode of the decoupling capacitor includes portions separated from each other by the dielectric material and portions of the second electrode of the decoupling capacitor.

13. The apparatus of any one of claims 8 to 11, wherein the first conductive via is in electrical communication with the front side of the die via a conductive structure in a metallization layer of the die.

14. The apparatus of any one of claims 8 to 11, wherein the first electrode and the second electrode are substantially planar.

15. The apparatus of any one of claims 8 to 11, wherein the first conductive via is electrically connected to a voltage source.

16. A method of forming a microelectronic device, the method comprising: forming a die comprising a front side and a back side opposite the front side; forming active circuitry between the front side and the back side of the die, the active circuitry adjacent to a base material of the die, the base material comprising at least one semiconductor substrate; forming a first conductive via extending through the base material; forming a second conductive via extending through the entire vertical thickness of the base material, the second conductive via being laterally offset from the first conductive via; forming a recess in a semiconductive material from the back side of the die to expose a portion of the first conductive via; forming a dielectric material within the recess; as well as forming a decoupling capacitor in the recess, wherein forming the decoupling capacitor comprises: forming an opening in the dielectric material to expose a portion of the first conductive via; forming a conductive material in electrical communication with the portion of the first conductive via to form a first electrode of the decoupling capacitor; forming another dielectric material adjacent to the conductive material; and forming another conductive material adjacent to the another dielectric material to form a second electrode of the decoupling capacitor, the another dielectric material comprising: vertically extending portions, each vertically extending portion being between a sidewall of the first electrode and an additional sidewall of the second electrode; and at least one lateral extension between a lateral surface of the first electrode and a lateral surface of the second electrode, the at least one lateral extension connecting the vertical extension; and forming a redistribution line, the redistribution line being in direct contact with the second conductive via and the second electrode of the decoupling capacitor, the redistribution line extending between the second conductive via and the second electrode of the decoupling capacitor, wherein the first conductive via is in electrical communication with the first electrode of the decoupling capacitor and the front side of the die; and The second conductive via is in electrical communication with the second electrode of the decoupling capacitor via the redistribution line and in electrical communication with the front side of the die. 17 . The method of claim 16 , wherein forming another conductive material comprises forming the another conductive material to be laterally offset from the second conductive via.

18. The method of any one of claims 16 or 17, wherein forming the conductive material in electrical communication with the portion of the first conductive via comprises forming the conductive material to include portions separated from each other by gaps.

19. The method according to any one of claims 16 or 17, wherein: forming the first conductive via comprises forming a first conductive via extending through the base material and the active circuitry, or forming the second conductive via includes forming a second conductive via extending through the base material and the active circuitry, or Both of the above.

20. An electronic system comprising: a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising at least one microelectronic device, the microelectronic device comprising: an active region comprising semiconducting material between the front and back sides of the die; a decoupling capacitor in a base material on the back side of the die, the base material comprising at least one semiconductor substrate, the decoupling capacitor comprising a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode, the dielectric material comprising: vertically extending portions, each vertically extending portion being between a sidewall of the first electrode and an additional sidewall of the second electrode; and at least one lateral extension portion between a lateral surface of the first electrode and a lateral surface of the second electrode, the at least one lateral extension portion connecting the vertical extension portion; a first conductive via extending through the semiconductive material and in electrical communication with the first electrode of the decoupling capacitor and the front side of the die; a redistribution line directly contacting the second electrode of the decoupling capacitor; and A second conductive via extends through the entire vertical thickness of the base material, the second conductive via being in electrical communication with the second electrode of the decoupling capacitor via the redistribution line and with the front side of the die.

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