Transistor gate structure and method for forming the same

Abstract

The present disclosure relates to transistor gate structures and methods for forming the same. In one embodiment, a device includes: an isolation region; a nanostructure protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructure, the gate structure having a bottom surface in contact with the isolation region, the bottom surface of the gate structure extending a first distance away from the nanostructure, the gate structure having a sidewall set at a second distance from the nanostructure, the first distance being less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

Description

Technical Field

[0001] The present disclosure generally relates to transistor gate structures and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials over a semiconductor substrate and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: an isolation region; a nanostructure protruding higher than a top surface of the isolation region; a gate structure wrapped around the nanostructure, the gate structure having a bottom surface in contact with the isolation region, the bottom surface of the gate structure extending a first distance away from the nanostructure, the gate structure having a sidewall set to be a second distance from the nanostructure, the first distance being less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: an isolation region; a semiconductor fin protruding higher than a top surface of the isolation region; a nanostructure located above the semiconductor fin; a gate structure wrapped around the nanostructure; and a hybrid fin on a sidewall of the gate structure, the hybrid fin being set at a first distance from the semiconductor fin, the hybrid fin being set at a second distance from the nanostructure, and the second distance being greater than the first distance.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: depositing a dummy gate layer over an isolation region and alternating first and second nanostructures, the first nanostructures and the second nanostructures protruding above a top surface of the isolation region; patterning the dummy gate layer to form a dummy gate on a sidewall of the first nanostructure, a sidewall of the second nanostructure, and a top surface of the isolation region; forming a protective layer on an upper portion of the dummy gate; trimming a lower portion of the dummy gate while the protective layer covers an upper portion of the dummy gate; and replacing the dummy gate and the first nanostructure with a metal gate, which is wrapped around the second nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It is worth noting that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 Examples of nanostructured transistors / FETs are shown in accordance with some embodiments.

[0009] Figure 2-22C is a diagram of an intermediate stage in the fabrication of a nanostructure transistor / FET according to some embodiments.

[0010] Figure 23A-23C is a diagram of a nanostructure transistor / FET according to various embodiments.

[0011] Figure 24A-24C is a diagram of a nanostructure transistor / FET according to various embodiments.

[0012] Figure 25A-Figure 25C is a diagram of a nanostructure transistor / FET according to various embodiments.

[0013] Figure 26A-26C Detailed views of nanostructured transistors / FETs, respectively.

[0014] Figure 27A-Figure 27D is a diagram of an intermediate stage in the fabrication of a nanostructure transistor / FET according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] According to various embodiments, a dummy gate having a small footing profile is formed around the semiconductor fin and the nanostructure surrounded by the hybrid fin. The dummy gate is removed in a replacement gate process. Forming the dummy gate having a small footing profile can increase the processing window of subsequent operations, such as a replacement gate process and / or an epitaxial growth process of source / drain regions.

[0018] Embodiments are described in the specific context of a die including nanostructure transistors / FETs. However, various embodiments may be applied to dies including other types of transistors / FETs (e.g., fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanostructure transistors / FETs.

[0019] Figure 1 Examples of nanostructure transistors / FETs (eg, nanowire FETs, nanosheet FETs, etc.) are shown in accordance with some embodiments. Figure 1 3D view, in which some features of nanostructure transistor / FET are omitted for clarity of illustration. The nanostructure transistor / FET may be a nanosheet field effect transistor (NSFET), a nanowire field effect transistor (NWFET), a gate all around field effect transistor (GAAFET), etc.

[0020] The nanostructure transistor / FET includes a nanostructure 66 (e.g., a nanosheet, a nanowire, etc.) on a semiconductor fin 62 on a substrate 50 (e.g., a semiconductor substrate), and the nanostructure 66 is used as a channel region of the nanostructure transistor / FET. The nanostructure 66 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. Isolation regions 72 such as shallow trench isolation (STI) regions are disposed between adjacent semiconductor fins 62, and these semiconductor fins 62 may protrude from between adjacent isolation regions 72 to be higher than these isolation regions 72. Although the isolation regions 72 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer only to a semiconductor substrate or to a combination of a semiconductor substrate and an isolation region. In addition, although the bottom of the semiconductor fin 62 is shown as being separated from the substrate 50, the bottom of the semiconductor fin 62 may be a single continuous material with the substrate 50. In this context, the semiconductor fin 62 refers to a portion extending from between adjacent isolation regions 72 to be higher than these isolation regions 72.

[0021] The gate structure 130 is located above the top surface of the semiconductor fin 62 and along the top surface, sidewalls, and bottom surface of the nanostructure 66. The epitaxial source / drain regions 108 are disposed on the semiconductor fin 62 on the opposite side of the gate structure 130. The epitaxial source / drain regions 108 can be shared between the various semiconductor fins 62. For example, adjacent epitaxial source / drain regions 108 can be electrically connected (e.g., by coupling the epitaxial source / drain regions 108 to the same source / drain contact).

[0022] The hybrid fin 82 is disposed over the isolation region 72 and between adjacent epitaxial source / drain regions 108. The hybrid fin 82 blocks epitaxial growth to prevent agglomeration of some epitaxial source / drain regions 108 during epitaxial growth. For example, the hybrid fin 82 may be formed at a cell boundary to separate the epitaxial source / drain regions 108 of adjacent cells.

[0023] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section AA' is along the longitudinal axis of the semiconductor fin 62 and in the direction of current flow, for example, between the epitaxial source / drain regions 108 of the nanostructure transistor / FET. Cross section BB' is along the longitudinal axis of the gate structure 130 and in a direction, for example, perpendicular to the direction of current flow, between the epitaxial source / drain regions 108 of the nanostructure transistor / FET. Cross section CC' is parallel to cross section BB' and extends through the epitaxial source / drain regions 108 of the nanostructure transistor / FET. For clarity, subsequent figures refer to these reference cross sections.

[0024] Figure 2-22Cis a diagram of an intermediate stage in the fabrication of a nanostructure transistor / FET according to some embodiments. Figure 2 , Figure 3 and Figure 4 is a three-dimensional view. Figure 5A , Fig. 6A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A is along with Figure 1 A cross-sectional view similar to the cross-sectional view shown in reference section AA'. Figure 5B , Figure 6B , Figures 7A-9C , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B and Fig. 22B is along with Figure 1 A cross-sectional view similar to the cross-sectional view shown in reference section BB'. Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C and Fig. 22C is along with Figure 1 A cross-sectional view similar to the cross-sectional view shown in reference cross-section CC'.

[0025] exist Figure 2In the present invention, a substrate 50 for forming a nanostructure transistor / FET is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type impurities or n-type impurities) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; combinations thereof, etc.

[0026] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type nanostructure transistor / FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type nanostructure transistor / FET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0027] The substrate 50 may be lightly doped with p-type impurities or n-type impurities. An anti-punch-through (APT) implant may be performed on the upper portion of the substrate 50 to form an APT region. During the APT implant, impurities may be implanted in the substrate 50. The impurities may have a conductivity type opposite to the conductivity type of the source / drain regions that will be subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain region in the nanostructure transistor / FET. The APT region may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region is between 10 and 10 nm. 18 cm -3 Up to 10 19 cm -3 within the range.

[0028] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. These semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be understood that the multilayer stack 52 can include any number of first semiconductor layers 54 and second semiconductor layers 56. For example, the multilayer stack 52 can include one to ten layers of each of the first semiconductor layers 54 and the second semiconductor layers 56.

[0029] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed and the second semiconductor layer 56 is patterned to form a channel region for a nanostructure transistor / FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that is removed in subsequent processing to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity relative to etching of the second semiconductor layer 56, such as silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type devices and p-type devices, such as silicon.

[0030] In another embodiment (not separately shown), the first semiconductor layer 54 is patterned to form a channel region for a nanostructure transistor / FET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 is patterned to form a channel region for a nanostructure transistor / FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 can be a material suitable for a p-type device, such as silicon germanium (e.g., Si x Ge 1-x , where x can be in the range of 0 to 1), pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. The second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, for example, silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. The etching of the first semiconductor material and the second semiconductor material relative to each other can have a high etching selectivity, so that the first semiconductor layer 54 can be removed without removing the second semiconductor layer 56 in the n-type region 50N, and the second semiconductor layer 56 can be removed without removing the first semiconductor layer 54 in the p-type region 50P.

[0031] Each layer of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc. Each layer can have a small thickness, for example, a thickness in the range of about 5nm to about 30nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or a dummy layer) and the second semiconductor layer 56 is patterned to form a channel region for a nanostructure transistor / FET in both the n-type region 50N and the p-type region 50p, the first semiconductor layer 54 can have a first thickness and the second semiconductor layer 56 can have a second thickness, wherein the second thickness is about 30% to about 60% less than the first thickness. Forming the second semiconductor layer 56 to have a smaller thickness allows the channel region to be formed at a greater density.

[0032] exist Figure 3 , trenches are patterned in substrate 50 and multilayer stack 52 to form semiconductor fins 62, nanostructures 64, and nanostructures 66. Semiconductor fins 62 are semiconductor strips patterned in substrate 50. Nanostructures 64 and nanostructures 66 include remaining portions of first semiconductor layer 54 and second semiconductor layer 56, respectively. The trenches may be patterned by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

[0033] The semiconductor fins 62 and nanostructures 64, 66 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the semiconductor fins 62 and nanostructures 64, 66, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines photolithography and a self-aligned process, allowing the creation of patterns having, for example, a pitch that is less than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on top of a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used as a mask 58 to pattern the semiconductor fins 62 and nanostructures 64, 66. In some embodiments, the mask 58 (or other layer) may remain on the nanostructures 64, 66.

[0034] The semiconductor fins 62 and nanostructures 64, 66 may each have a width in the range of 8 nm to 40 nm. In the illustrated embodiment, the semiconductor fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, the semiconductor fins 62 and nanostructures 64, 66 in one region (e.g., the n-type region 50N) may be wider or narrower than the semiconductor fins 62 and nanostructures 64, 66 in another region (e.g., the p-type region 50P).

[0035] exist Figure 4 In the embodiment, STI regions 72 are formed above substrate 50 and between adjacent semiconductor fins 62. STI regions 72 are disposed around at least a portion of semiconductor fins 62 such that at least a portion of nanostructures 64, 66 protrude from between adjacent STI regions 72. In the illustrated embodiment, the top surface of STI regions 72 is lower than the top surface of semiconductor fins 62. In some embodiments, the top surface of STI regions 72 is higher than or coplanar with the top surface of semiconductor fins 62 (within process variation).

[0036] The STI region 72 may be formed by any suitable method. For example, an insulating material may be formed over the substrate 50 and the nanostructures 64, 66 and between adjacent semiconductor fins 62. The insulating material may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), etc., or a combination thereof, and may be formed by a chemical vapor deposition (CVD) process (e.g., high density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or a combination thereof). Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed so that excess insulating material covers the nanostructures 64, 66. Although the STI regions 72 are each shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, the semiconductor fins 62, and the nanostructures 64, 66. Thereafter, an insulating material such as described above may be formed over the liner. A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 64 and 66. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be used. In embodiments where the mask 58 remains on the nanostructures 64 and 66, the planarization process may expose the mask 58 or remove the mask 58. After the planarization process, the top surface of the insulating material and the top surface of the mask 58 (if present) or the top surface of the nanostructures 64 and 66 are coplanar (within the process variation range). Therefore, the top surface of the mask 58 (if present) or the top surface of the nanostructures 64 and 66 is exposed through the insulating material. In the illustrated embodiment, the mask 58 remains on the nanostructures 64 and 66. The insulating material is then recessed to form the STI region 72. The insulating material is recessed so that at least a portion of the nanostructures 64 and 66 protrude from between adjacent portions of the insulating material. In addition, the top surface of the STI region 72 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish), or a combination thereof. In the illustrated embodiment, the top surface of the STI region 72 is a concave surface, so that some portions of the STI region 72 extend upward along the sidewalls of the semiconductor fin 62. The top surface of the STI region 72 can be formed to be flat, convex, and / or concave by appropriate etching. The insulating material can be recessed using any acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., the etching process selectively etches the insulating material of the STI region 72 at a faster rate than etching the material of the semiconductor fin 62 and the nanostructures 64, 66). For example, the oxide removal can be performed using dilute hydrofluoric acid (dHF).

[0037] The processes previously described are merely one example of how the semiconductor fins 62 and nanostructures 64, 66 may be formed. In some embodiments, the semiconductor fins 62 and / or nanostructures 64, 66 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes relative to the dielectric layer to form the semiconductor fins 62 and / or nanostructures 64, 66. The epitaxial structure may include alternating semiconductor materials previously described, for example, a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and / or subsequent implantation, but in-situ doping and implantation doping may also be used together.

[0038] In addition, appropriate wells (not shown separately) may be formed in the nanostructures 64, 66, the semiconductor fins 62, and / or the substrate 50. The conductivity type of the well may be opposite to the conductivity type of the source / drain regions that will be subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0039] In embodiments with different well types, a mask such as a photoresist (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the semiconductor fins 62, nanostructures 64, 66, and STI regions 72 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., which is implanted into the region at a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist may be removed, for example, by any acceptable ashing process.

[0040] After or before the implantation of the p-type region 50P, a mask such as a photoresist (not shown separately) is formed over the semiconductor fins 62, nanostructures 64, 66, and STI regions 72 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., which is implanted into the region, and its concentration is about 10 13 cm -3 Up to 10 14 cm -3 After implantation, the photoresist may be removed, for example, by any acceptable ashing process.

[0041] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments of epitaxially growing epitaxial structures for semiconductor fins 62 and / or nanostructures 64, 66, the grown material may be doped in-situ during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0042] Figure 5A-Figure 22C Various additional steps in the fabrication of example devices are shown. Figure 5A-Figure 22C Features in either the n-type region 50N and the p-type region 50P are shown. For example, the structure shown can be applicable to both the n-type region 50N and the p-type region 50P. The differences in the structure of the n-type region 50N and the p-type region 50P, if any, are described in the text corresponding to each figure. As will be described in more detail later, the hybrid fin 82 will be formed between the semiconductor fins 62. Figure 5A-Figure 22C Two semiconductor fins 62 and some portions of the hybrid fin 82 and the STI region 72 disposed between the two semiconductor fins 62 in the corresponding cross section are each shown.

[0043] exist Figure 5A-Figure 5BIn the embodiment, the dummy gate layer 74 is conformally formed over the mask 58 (if present), the semiconductor fins 62, the nanostructures 64, 66, and the STI region 72. The dummy gate layer 74 may be formed of a semiconductor material (e.g., a semiconductor material selected from the candidate semiconductor materials of the substrate 50), which may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc. For example, the dummy gate layer 74 may be formed of silicon or silicon germanium. The dummy gate layer 74 may be formed over the STI region 72 to have a thickness T 1 , which is in the range of 1 nm to 100 nm. The thickness of the dummy gate layer 74 determines the size of the replacement gate structure of the nanostructure transistor / FET.

[0044] exist Figure 6A-6B In the embodiment shown, the dummy gate layer 74 is patterned to form a dummy gate 76 around the mask 58 (if present), the semiconductor fin 62 and the nanostructures 64, 66. The dummy gate 76 is disposed above the STI region 72. The dummy gate layer 74 has some portions (thereby forming the dummy gate 76) left on the sidewalls of the mask 58 (if present), the semiconductor fin 62 and the nanostructures 64, 66 after being patterned. The dummy gate 76 covers the sidewalls of the nanostructures 64, 66 that will be exposed in subsequent processing to form the channel region. The dummy gate 76 is used as a temporary spacer during processing and will be removed later to expose the sidewalls of some portions of the nanostructure 66 that will serve as the channel region of the nanostructure transistor / FET. Specifically, in the embodiment shown, the dummy gate 76 and the nanostructure 64 will be removed later and replaced with a gate structure wrapped around the nanostructure 66. The dummy gate 76 is formed of a material having a high etch selectivity relative to the etching of the material of the nanostructure 66. The dummy gate 76 may be formed of the same semiconductor material as the nanostructure 64 , or may be formed of a different material.

[0045] As will be described in more detail later, the dummy gates 76 are formed so that they have a small footing profile. The footing profile of the dummy gates 76 refers to the shape and size of the portion of the dummy gates 76 that extends along the top surface of the STI region 72. Forming the dummy gates 76 with a small footing profile refers to forming the dummy gates 76 such that the portion of the dummy gates 76 on the top surface of the STI region 72 does not flare out outward along the concave surface of the STI region 72. Thus, the bottom surface of the dummy gates 76 extends a first distance D away from the nanostructures 64, 66. 1 , and the outer sidewall of the dummy gate 76 is set to be a second distance D from the nanostructures 64 and 662 , and the first distance D 1 Less than or equal to (eg, not greater than) the second distance D 2 The first distance D 1 is measured below the top surface of semiconductor fin 62, and the second distance D 2 is measured between the top surface of the semiconductor fin 62 and the bottom surface of the bottom nanostructure 66. The first distance D 1 and the second distance D 2 The size of will be described in more detail later. Forming the dummy gate 76 with a small footing profile increases the process window for subsequent operations (eg, a replacement gate process and / or an epitaxial growth process of source / drain regions).

[0046] Figures 7A-9C is a view of an intermediate stage in patterning a dummy gate 76 having a small footing profile according to some embodiments. The dummy gate 76 is formed to have a small footing profile by patterning the dummy gate layer 74 using multiple etching processes. Specifically, a first etching process is performed to initially pattern the dummy gate layer 74 into the dummy gate 76 (see Figure 7A-7B A protective layer 80 is formed along the upper portion 76U of the dummy gate 76 (see Figure 7A-7B ), and the lower portion 76L of the dummy gate 76 is still exposed by the protective layer 80. Then, a second etching process is performed to trim the lower portion 76L of the dummy gate 76 while leaving the upper portion 76U of the dummy gate 76 covered by the protective layer 80 (see Figure 8A-8C ). The trimming of the lower portion 76L of the dummy gate 76 reduces the footing profile of the dummy gate 76 by reducing the width of the lower portion 76L of the dummy gate 76. The protective layer 80 may be optionally removed (see Figure 9A-9C ).

[0047] exist Figure 7A-7B In the process, a first etching process is performed to remove the dummy gate layer 74 (see Figure 5A-Figure 5B ) is initially patterned as a dummy gate 76. The first etching process may be dry etching, wet etching, etc. or a combination thereof. The first etching process may be anisotropic. The portion of the dummy gate layer 74 located above the mask 58 (if present) or the nanostructures 64, 66 is removed by the first etching process.

[0048] The areal density of the nanostructures 64, 66 determines the outcome of the first etching process, for example by affecting the load during the first etching process. The dummy gates 76 along the nanostructures 64, 66 in the sparse regions may be patterned such that the STI regions 72 between the nanostructures 64, 66 are exposed, as shown in FIG. Fig. 7AThe dummy gates 76 along the nanostructures 64, 66 in the dense region may be patterned such that the STI regions 72 between the nanostructures 64, 66 are covered, as shown in FIG. Figure 7B In some embodiments, the critical dimension (CD) between the nanostructures 64 and 66 is in the range of 2 nm to 2000 nm, wherein the sparse region refers to a region where the CD is close to the lower limit of the range, and the dense region refers to a region where the CD is close to the upper limit of the range. The same substrate 50 may have a sparse region and a dense region, so that the first etching process forms a plurality of nanostructures 64 and 66 on the same substrate 50. Fig. 7A and Figure 7B structure.

[0049] The first etching process forms a dummy gate 76 having a large footing profile. Forming the dummy gate 76 having a large footing profile refers to forming the dummy gate 76 such that a portion of the dummy gate 76 on the top surface of the STI region 72 is flared outward along the concave surface of the STI region 72. In other words, the distances at which the sidewalls of the dummy gate 76 are spaced apart increase in a direction extending from the top of the dummy gate 76 to the bottom of the dummy gate 76. Fig. 7A When the dummy gate 76 is patterned so that the STI region 72 between the nanostructures 64 and 66 is exposed, the first distance D 1 Greater than the second distance D 2 In this embodiment, the portion of the dummy gate layer 74 located above the STI region 72 is removed. Figure 7B , when the dummy gate 76 is patterned so that the STI region 72 between the nanostructures 64, 66 is covered, the dummy gate 76 extends across the concave surface of the STI region 72. In this embodiment, the portion of the dummy gate layer 74 located above the STI region 72 is thinned. Therefore, the thickness T of the dummy gate 76 located above the STI region 72 is 1.33mm / s. 1 After the first etching process, the dummy gate layer 74 located on the STI region 72 may have a thickness T 2 , which is in the range of 0.3nm to 20nm, and has a thickness of T 2 Less than thickness T 1 .

[0050] In addition, the protective layer 80 is formed along the upper portion 76U of the dummy gate 76 and is located above the mask 58 (if present) or the nanostructures 64, 66. In this embodiment, the protective layer 80 is not formed along the lower portion 76L of the dummy gate 76, so that the lower portion 76L of the dummy gate 76 is exposed and can be subsequently trimmed. The protective layer 80 is also not formed along the portion of the dummy gate 76 that covers the top surface of the STI region 72 (see Figure 7B), so that these portions of the dummy gate 76 are exposed and can be subsequently removed during trimming. In this context, the upper portions 76U of the dummy gates 76 refer to portions having straight sidewalls spaced at a constant distance and having a rounded top surface, and the lower portions 76L of the dummy gates 76 refer to portions that are flared outward along the STI region 72. In some embodiments, the lower portion 76L of each dummy gate 76 is disposed below the bottom surface 64B of the nanostructure(s) 64 / 66 that are adjacent to the dummy gate 76 and disposed closest to (and above) the STI region 72. In some embodiments, the upper portion 76U of each dummy gate 76 is disposed above the bottom surface 64B of the nanostructure(s) 64 / 66.

[0051] In this embodiment, the protective layer 80 is a byproduct layer 80B generated by the first etching process used to pattern the dummy gate layer 74. The byproduct layer 80B is formed by including a passivating gas in the etchant used during the first etching process. The passivating gas controls the selectivity of the first etching process and promotes the generation of etching byproducts, thereby leaving the byproduct layer 80B after the first etching process. The byproduct layer 80B may have a to The byproduct layer 80B may have a thickness within a range of . The upper thickness of the byproduct layer 80B in the direction along the sidewall of the dummy gate 76 may be greater than the lower thickness, so that the byproduct layer 80B has an inverted trapezoidal profile shape. The byproduct layer 80B having such a thickness and shape is formed to protect the upper portion 76U of the dummy gate 76 when the lower portion 76L of the dummy gate 76 is subsequently trimmed. Forming the byproduct layer 80B without such a thickness or shape may fail to protect the upper portion 76U of the dummy gate 76 when the lower portion 76L of the dummy gate 76 is subsequently trimmed.

[0052] In some embodiments, the first etching process is a dry etching process performed using a gas source including a main etching gas and a passivation gas. The main etching gas may be Cl 2 , HBr, CF 4 , CHF 3 , CH 2 F 2 , CH 3 F.C 4 F 6 , BCl 3 , SF 6 , H 2 The passivation gas can be N 2 , O 2 , CO 2 、SO 2 , CO, CH 4 、SiCl4 etc. In some embodiments, the gas source further comprises a rare gas, such as Ar, He, Ne, etc. A plasma is generated during the first etching process. In some embodiments, the first etching process is implemented cyclically. For example, the first etching process may include cycling between dispensing a main etching gas and dispensing a passivation gas. The etching cycle may be repeated up to 50 times. In some embodiments, the process conditions of the first etching process include: a pressure in the range of 1mTorr to 800mTorr; a plasma source power in the range of 10W to 3000W (configured to control the ratio of ions to radicals); a plasma bias power in the range of 0W to 3000W (configured to control the etching direction (e.g., isotropic etching or anisotropic etching)); and a gas source flow rate in the range of 1sccm to 5000sccm. Performing the first etching process with parameters within these ranges allows the byproduct layer 80B to be formed to have a desired thickness and shape (described previously).

[0053] The composition of the byproduct layer 80B depends on the passivation gas used in the first etching process. Continuing with the example that the dummy gate layer 74 is formed of silicon or silicon germanium: the byproduct layer 80B may be formed when an oxygen-based passivation gas (e.g., O 2 , CO 2 、SO 2 , CO, etc.); the byproduct layer 80B may be a byproduct of SiO or SiGeO formed when a nitrogen-based passivation gas (e.g., N 2 and the byproduct layer 80B may be a byproduct of SiN or SiGeN formed by using a sulfur-based passivation gas (e.g., SO 2 In some embodiments, a plurality of passivation gases may be used in the first etching process. For example, an oxygen-based passivation gas, a nitrogen-based passivation gas, and a sulfur-based passivation gas (e.g., SO 2 and N 2 ), and the byproduct layer 80B may be SiGeS x O y N z By-product.

[0054] exist Figure 8A-8CIn the embodiment, a second etching process is performed to trim the lower portion 76L of the dummy gate 76 while the upper portion 76U of the dummy gate 76 is covered by the protective layer 80. The second etching process can be a wet etching, and the second etching process reduces the footing profile of the dummy gate 76 by reducing the width of the lower portion 76L of the dummy gate 76. Specifically, the second etching process laterally etches the lower portion 76L of the dummy gate 76 until the dummy gate 76 has a small footing profile. The second etching process can have a greater lateral etching rate than the first etching process, and can have a lower vertical etching rate than the first etching process, which allows the second etching process to serve as a trimming process. In an embodiment where the dummy gate 76 covers the STI region 72 located between the nanostructures 64, 66 (see Figure 7B ), the second etching process also exposes the top surface of the STI region 72. The protection layer 80 acts as an etch stop layer during the second etching process to protect the upper portion 76U of the dummy gate 76 so that they are not trimmed during the second etching process. In other words, the lower portion 76L of the dummy gate 76 is etched during the second etching process, and the upper portion 76U of the dummy gate 76 is not etched during the second etching process (or at least is etched less than the lower portion 76L of the dummy gate 76). In some embodiments, after the second etching process, the first distance D 1 Equal to the second distance D 2 ,like Fig. 8A In some embodiments, after the second etching process, the first distance D 1 Less than the second distance D 2 ,like Figure 8B and Figure 8C shown.

[0055] In some embodiments, the second etching process is a wet clean performed using a primary etching chemistry and an auxiliary etching chemistry in a solvent. The primary etching chemistry may be HF, F 2 Etc. The auxiliary etching chemicals can be O 3 , H 2 SO 4 , HCl, HBr, etc. The solvent can be deionized (DI) water, alcohol, acetone, etc.

[0056] Fig. 8A The structure of can be obtained by: Fig. 7AThe second etching process is performed on the structure of the dummy gate 76, for example, the dummy gate 76 is patterned so that the STI region 72 between the nanostructures 64 and 66 is exposed, and then the lower portion 76L of the dummy gate 76 is trimmed. For example, the second etching process can be controlled (for example, by adjusting the plasma bias power) so that the second etching process etches in a lateral direction substantially parallel to the main surface of the substrate 50. In this embodiment, the sidewalls of the lower portion 76L of the dummy gate 76 are spaced apart at a constant distance in a direction extending from the top of the dummy gate 76 to the bottom of the dummy gate 76. Therefore, the sidewalls of the lower portion 76L of the dummy gate 76 are substantially perpendicular to the main surface of the substrate 50.

[0057] Figure 8B The structure of can be obtained by: Fig. 7A The second etching process is performed on the structure of the substrate 50, for example, the dummy gate 76 is patterned so that the STI region 72 between the nanostructures 64 and 66 is exposed, and then the lower portion 76L of the dummy gate 76 is trimmed. For example, the second etching process can be controlled (for example, by adjusting the plasma bias power) so that the second etching process etches in a lateral direction substantially parallel to the main surface of the substrate 50. Compared to Fig. 8A The dummy gate 76 in the embodiment of Figure 8B The dummy gates 76 in the embodiment of FIG. 5 may be etched more so that they are flared inwardly along the STI region 72. In this embodiment, the distance at which the sidewalls of the lower portion 76L of the dummy gate 76 are spaced apart decreases linearly in the extending direction from the top of the dummy gate 76 to the bottom of the dummy gate 76. Therefore, the sidewalls of the lower portion 76L of the dummy gate 76 form an acute angle with a plane parallel to the main surface of the substrate 50.

[0058] Figure 8C The structure of can be obtained by: Figure 7B The second etching process is performed on the structure of the dummy gate 76, for example, the dummy gate 76 is patterned so that the STI region 72 between the nanostructures 64 and 66 is covered, and then the lower portion 76L of the dummy gate 76 is trimmed so that the STI region 72 is exposed. For example, the second etching process can be controlled (for example, by adjusting the plasma bias power) so that the second etching process etches in a diagonal direction that forms an acute angle with a plane parallel to the main surface of the substrate 50. In this embodiment, the distance between the sidewalls of the lower portion 76L of the dummy gate 76 decreases nonlinearly in a direction extending from the top of the dummy gate 76 to the bottom of the dummy gate 76, and then also increases nonlinearly in this direction. When the dummy gate 76 has a portion covering the STI region 72 (see Figure 7B), etching these parts can reduce the lateral etching of the second etching process. Therefore, the sidewall of the lower portion 76L of the dummy gate 76 may include a sidewall recess 76R. The bottom of the sidewall recess 76R is set to be a third distance D from the nanostructures 64, 66. 3 , where the third distance D 3 Less than the second distance D 2 and the first distance D 1 The third distance D 3 The second distance D is measured 2 The first distance D is measured between the point 1 Measured between points.

[0059] exist Figure 9A-9C In some embodiments, the protective layer 80 is removed by a wet cleaning process performed after trimming the lower portion 76L of the dummy gate 76. In some embodiments, the protective layer 80 is removed by a second etching process to trim the lower portion 76L of the dummy gate 76. In other embodiments (described later), the protective layer 80 is not removed but remains in the final device.

[0060] Figures 10A-22C It is for Fig.9A In addition, in the embodiment shown, the protective layer 80 is removed. It should be understood that the protective layer 80 can be used. Figure 8A-8C or Figure 9B-Figure 9C A similar process is performed using the embodiments of the present invention.

[0061] exist Figure 10A-10CIn the embodiment of the present invention, the hybrid fin layer 78 is conformally formed over the mask 58 (if present), the semiconductor fin 62, the nanostructures 64, 66, and the dummy gate 76. The hybrid fin layer 78 is formed of one or more dielectric materials having high etch selectivity relative to the etching of the semiconductor fin 62, the nanostructures 64, 66, and the dummy gate 76. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, silicon carbon nitride, metal-based dielectric materials, combinations thereof, and the like, which may be formed by conformal deposition processes such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), and the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, the hybrid fin layer 78 is formed of a low-k dielectric material (e.g., a dielectric material having a k value less than about 3.5), such as fluorosilicate glass (FSG). The hybrid fin layer 78 fills the remaining area between the semiconductor fin 62 and the nanostructures 64, 66 that is not filled by the dummy gate 76, and the hybrid fin layer 78 may be formed on the mask 58 (if present) or the top surface of the nanostructures 64, 66. In some embodiments, the hybrid fin layer 78 includes a plurality of sub-layers, such as a liner layer 78A and a filler layer 78B, which may be formed of different materials.

[0062] exist Figure 11A-11C In the process, a removal process is performed to remove excess portions of the material(s) of the hybrid fin layer 78, which are located above the top surface of the mask 58 (if present) or the nanostructures 64, 66, thereby forming the hybrid fin 82. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The hybrid fin layer 78 has portions remaining in the region between the semiconductor fin 62 and the nanostructures 64, 66 after being planarized (thereby forming the hybrid fin 82). After the planarization process, the top surfaces of the hybrid fin 82, the dummy gate 76, and the mask 58 (if present) or the nanostructures 64, 66 are coplanar (within process variation).

[0063] In embodiments where the mask 58 remains on the nanostructures 64, 66, the removal process may expose the mask 58 or remove the mask 58. Additionally, in some embodiments, the mask 58 is removed by a separate process performed after the removal process. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the mask 58. The etching may be anisotropic. In some embodiments where the mask 58 is removed, the removal process may also (or may not) recess the dummy gate 76.

[0064] exist Figure 12A-12CIn the embodiment of the present invention, a dummy gate layer 84 is formed on the hybrid fin 82, the dummy gate 76 and the mask 58 (if present) or the nanostructures 64, 66. The dummy gate layer 84 can be deposited and then planarized, for example, by CMP. The dummy gate layer 84 can be formed of a conductive material or a non-conductive material, such as amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 84 can also be formed of a semiconductor material (e.g., a semiconductor material selected from the candidate semiconductor materials of the substrate 50), which can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The dummy gate layer 84 can be formed of (one or more) materials having a high etch selectivity relative to etching of an insulating material (e.g., the hybrid fin 82). A mask layer 86 may be deposited over the dummy gate layer 84. The mask layer 86 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 84 and a single mask layer 86 are formed across the n-type region 50N and the p-type region 50P.

[0065] exist Figure 13A-13C In the embodiment of the present invention, the mask layer 86 is patterned using acceptable photolithography and etching techniques to form a mask 96. The pattern of the mask 96 is then transferred to the dummy gate layer 84 by any acceptable etching technique to form a dummy gate 94. The dummy gate 94 covers the top surface of the nanostructures 64, 66 that will be exposed in subsequent processing to form a channel region. The pattern of the mask 96 can be used to physically separate adjacent dummy gates 94. The dummy gate 94 can also have a length direction that is substantially perpendicular to the length direction of the semiconductor fin 62 (within the process variation range). Optionally, the mask 96 can be removed after patterning, for example by any acceptable etching technique.

[0066] Dummy gate 76 and dummy gate 94 extend together along the portion of nanostructure 66 that will be patterned to form channel region 68. A subsequently formed gate structure will replace dummy gate 76 and dummy gate 94. Forming dummy gate 94 over dummy gate 76 allows a subsequently formed gate structure to have a greater height.

[0067] As described above, the dummy gate 94 may be formed of a semiconductor material. In such embodiments, the nanostructure 64, the dummy gate 76, and the dummy gate 94 are each formed of a semiconductor material. In some embodiments, the nanostructure 64 and the dummy gate 76 are formed of a first semiconductor material (e.g., silicon germanium) and the dummy gate 94 is formed of a second semiconductor material (e.g., silicon), so that during the replacement gate process, the dummy gate 94 may be removed in a first etching step, and the nanostructure 64 and the dummy gate 76 may be removed together in a second etching step. When the nanostructure 64 and the dummy gate 76 are formed of silicon germanium: the nanostructure 64 and the dummy gate 76 may have similar germanium concentrations, the nanostructure 64 may have a greater germanium concentration than the dummy gate 76, or the dummy gate 76 may have a similar germanium concentration as the nanostructure 64. In some embodiments, nanostructure 64 is formed of a first semiconductor material (e.g., silicon germanium) and dummy gate 76 and dummy gate 94 are formed of a second semiconductor material (e.g., silicon), such that during a replacement gate process, dummy gate 76 and dummy gate 94 can be removed together in a first etching step and nanostructure 64 can be removed in a second etching step.

[0068] In addition, a gate spacer 98 is formed on the mask 58 (if present) or the nanostructures 64, 66 and on the exposed sidewalls of the mask 96 (if present) and the dummy gate 94. The gate spacer 98 can be formed by conformally depositing one or more dielectric materials and then etching the (one or more) dielectric materials. Acceptable dielectric materials may include: silicon oxide, silicon nitride, silicon oxynitride, carbon nitride silicon oxynitride, etc., which can be formed by a conformal deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. Any acceptable etching process (e.g., dry etching, wet etching, etc., or a combination thereof) can be performed to pattern the (one or more) dielectric materials. The etching can be anisotropic. After being etched, some portions of the (one or more) dielectric materials remain on the sidewalls of the dummy gate 94 (thereby forming the gate spacer 98). After etching, the gate spacers 98 may have straight sidewalls (as shown) or may have curved sidewalls (not separately shown).

[0069] In addition, implantation may be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments having different device types, similar to the implantation for the well described previously, a mask such as a photoresist (not shown separately) may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of the appropriate type (e.g., p-type) may be implanted into the semiconductor fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist (not shown separately) may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of the appropriate type (e.g., n-type) may be implanted into the semiconductor fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities described previously, and the p-type impurity may be any of the p-type impurities described previously. During the implantation, the channel region 68 remains covered by the dummy gate 94 so that the channel region 68 remains substantially free of the impurities implanted to form the LDD region. The LDD region may have a 15 cm -3 Up to 10 19 cm -3 Annealing can be used to repair implantation damage and activate the implanted impurities.

[0070] Note that the previous disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, additional spacers may be formed and removed, etc. Furthermore, different structures and steps may be used to form n-type devices and p-type devices.

[0071] exist Figure 14A-Figure 14C, source / drain recesses 104 are formed in mask 58 (if present), nanostructures 64, 66, and dummy gate 76. In the embodiment shown, source / drain recesses 104 extend through nanostructures 64, 66 and into semiconductor fin 62. Source / drain recesses 104 may also extend into substrate 50. In various embodiments, source / drain recesses 104 may extend to the top surface of substrate 50 without etching substrate 50; semiconductor fin 62 may be etched such that the bottom surface of source / drain recesses 104 is disposed below the top surface of STI region 72; and so on. Source / drain recesses 104 may be formed by etching nanostructures 64, 66 and dummy gate 76 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the source / drain recesses 104, the gate spacers 98 and the dummy gates 94 collectively mask portions of the semiconductor fins 62 and / or the nanostructures 64, 66. A single etching process may be used to etch each nanostructure 64, 66, or multiple etching processes may be used to etch the nanostructures 64, 66. A timed etching process may be used to stop etching the source / drain recesses 104 after the source / drain recesses 104 reach a desired depth. In some embodiments, during the formation of the source / drain recesses 104, portions of the STI regions 72 adjacent to the hybrid fins 82 may also be etched.

[0072] Because the dummy gates 76 have a small footer profile, they can be removed more easily without the remnants of the dummy gates 76 remaining on the top surface of the STI region 72. Therefore, more area can be used for the source / drain regions, and the source / drain regions can be formed without the remnants of the dummy gates 76 beneath them. Therefore, etching of the subsequently formed source / drain regions during the replacement gate process can be avoided, thereby improving manufacturing yield.

[0073] Optionally, internal spacers 106 are formed on the sidewalls of the mask 58 (if present) and the remaining portions of the nanostructure 64 (e.g., on those sidewalls exposed by the source / drain recess 104). As will be described in more detail later, source / drain regions will be subsequently formed in the source / drain recess 104, and the nanostructure 64 will subsequently be replaced by a corresponding gate structure. The internal spacers 106 act as isolation features between the subsequently formed source / drain regions and the subsequently formed gate structures. In addition, the internal spacers 106 can be used to substantially prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for subsequently removing the nanostructure 64).

[0074] As an example for forming internal spacers 106, source / drain recesses 104 can be expanded laterally. Specifically, portions of the sidewalls of nanostructures 64 exposed by source / drain recesses 104 can be recessed. Although the sidewalls of nanostructures 64 are shown as straight, these sidewalls can be concave or convex. The sidewalls can be recessed by any acceptable etching process, such as a process that is selective to nanostructures 64 (e.g., selectively etches the material of nanostructures 64 at a faster rate than etching the material of nanostructures 66). The etching can be isotropic. For example, when nanostructures 66 are formed of silicon and nanostructures 64 are formed of silicon germanium, the etching process can be using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. 4 OH) and the like. In another embodiment, the etching process may be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process may be performed continuously to form both the source / drain recess 104 and the sidewall of the nanostructure 64. An internal spacer 106 is then formed on the recessed sidewall of the nanostructure 64. The internal spacer 106 may be formed by conformally forming an insulating material and then etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low-k dielectric material. The insulating material may be deposited by a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as RIE, NBE, etc. Although the outer sidewalls of the inner spacer 106 are shown as being flush with the sidewalls of the gate spacer 98, the outer sidewalls of the inner spacer 106 may extend beyond the sidewalls of the gate spacer 98 or be recessed relative to the sidewalls of the gate spacer 98. In other words, the inner spacer 106 may partially fill, completely fill, or overfill the sidewall recess. In addition, although the sidewalls of the inner spacer 106 are shown as being straight, the sidewalls of the inner spacer 106 may be concave or convex. Portions of the sidewalls of the mask 58 (if present) may also be recessed, and the inner spacer 106 may also be formed on the recessed sidewalls of the mask 58.

[0075] exist Figure 15A-Figure 15C, epitaxial source / drain regions 108 are formed in source / drain recesses 104. Epitaxial source / drain regions 108 are formed in source / drain recesses 104 so that each dummy gate 94 (and corresponding channel region 68) is disposed between adjacent pairs of corresponding epitaxial source / drain regions 108. In some embodiments, gate spacers 98 and internal spacers 106 are used to separate epitaxial source / drain regions 108 from dummy gates 94 and nanostructures 64, respectively, by appropriate lateral distances so that epitaxial source / drain regions 108 do not short circuit with subsequently formed gates of the resulting nanostructure transistor / FET. The material of the epitaxial source / drain regions 108 may be selected to impart stress in the corresponding channel regions 68, thereby improving performance.

[0076] The epitaxial source / drain region 108 in the n-type region 50N may be formed by masking the p-type region 50P. The epitaxial source / drain region 108 in the n-type region 50N is then epitaxially grown in the source / drain recess 104 in the n-type region 50N. The epitaxial source / drain region 108 may include any acceptable material suitable for an n-type device. For example, if the nanostructure 66 is silicon, the epitaxial source / drain region 108 in the n-type region 50N may include a material that applies tensile strain to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 108 in the n-type region 50N may be referred to as an "n-type source / drain region". The epitaxial source / drain region 108 in the n-type region 50N may have a surface that protrudes from the corresponding surfaces of the semiconductor fin 62 and the nanostructures 64, 66, and may have a small facet.

[0077] The epitaxial source / drain region 108 in the p-type region 50P may be formed by masking the n-type region 50N. The epitaxial source / drain region 108 in the p-type region 50P is then epitaxially grown in the source / drain recess 104 in the p-type region 50P. The epitaxial source / drain region 108 may include any acceptable material suitable for a p-type device. For example, if the nanostructure 66 is silicon, the epitaxial source / drain region 108 in the p-type region 50P may include a material that applies compressive strain to the channel region 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 108 in the p-type region 50P may be referred to as a "p-type source / drain region". The epitaxial source / drain region 108 in the p-type region 50P may have a surface that protrudes from the corresponding surfaces of the semiconductor fin 62 and the nanostructures 64, 66, and may have a small facet.

[0078] The epitaxial source / drain regions 108, nanostructures 64, 66, and / or semiconductor fins 62 may be implanted with impurities to form source / drain regions, similar to the process previously described for forming LDD regions, and then annealed. The impurity concentration of the source / drain regions may be between 10 19 cm -3 Up to 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the previously described impurities. In some embodiments, the epitaxial source / drain regions 108 may be doped in-situ during growth.

[0079] The epitaxial source / drain region 108 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 108 may each include a liner layer 108A, a main layer 108B, and a finishing layer 108C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 108. Each of the liner layer 108A, the main layer 108B, and the finishing layer 108C may be formed of a different semiconductor material and may be doped to have different impurity concentrations. In some embodiments, the liner layer 108A may have a lower impurity concentration than the main layer 108B, and the finishing layer 108C may have a higher impurity concentration than the liner layer 108A and a lower impurity concentration than the main layer 108B. In embodiments where epitaxial source / drain regions 108 include three layers of semiconductor material, liner layer 108A may be grown in source / drain recesses 104 , main layer 108B may be grown on liner layer 108A, and finishing layer 108C may be grown on main layer 108B.

[0080] As a result of the epitaxial process used to form epitaxial source / drain regions 108, the top surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of semiconductor fins 62 and nanostructures 64, 66. However, hybrid fins 82 prevent lateral epitaxial growth. Fig. 15CAs shown, adjacent epitaxial source / drain regions 108 remain separated after the epitaxial process is completed. The epitaxial source / drain regions 108 contact the sidewalls of the hybrid fins 82. In the illustrated embodiment, the epitaxial source / drain regions 108 are grown such that the top surfaces of the epitaxial source / drain regions 108 are disposed below the top surfaces of the hybrid fins 82. In various embodiments, the top surfaces of the epitaxial source / drain regions 108 are disposed above the top surfaces of the hybrid fins 82; portions of the top surfaces of the epitaxial source / drain regions 108 are disposed above and below the top surfaces of the hybrid fins 82, etc. In addition, in the illustrated embodiment, the epitaxial source / drain regions 108 are grown such that the top surfaces of the epitaxial source / drain regions 108 are coplanar with the top surfaces of the nanostructures 64, 66. In another embodiment, the epitaxial source / drain regions 108 are grown such that the top surfaces of the epitaxial source / drain regions 108 are disposed above the top surfaces of the nanostructures 64, 66.

[0081] exist Figure 16A-16C In the embodiment of the present invention, a first interlayer dielectric (ILD) 114 is deposited over the epitaxial source / drain regions 108, the gate spacers 98, the mask 96 (if present), or the dummy gate 94. The first ILD 114 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0082] In some embodiments, a contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the epitaxial source / drain regions 108, the gate spacers 98, and the mask 96 (if present) or the dummy gate 94. The CESL 112 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a high etch selectivity with respect to the etching of the first ILD 114. The CESL 112 may be formed by any suitable method, such as CVD, ALD, etc.

[0083] exist Figure 17A-17CIn the embodiment shown, a removal process is performed to make the top surface of the first ILD 114 flush with the top surface of the mask 96 (if present) or the dummy gate 94. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process may also remove the mask 96 on the dummy gate 94, and the portion of the gate spacer 98 along the sidewall of the mask 96. After the planarization process, the top surfaces of the gate spacer 98, the first ILD 114, the CESL 112, and the mask 96 (if present) or the dummy gate 94 are coplanar (within the process variation range). Therefore, the top surface of the mask 96 (if present) or the dummy gate 94 is exposed through the first ILD 114. In the embodiment shown, the mask 96 remains, and the planarization process makes the top surface of the first ILD 114 flush with the top surface of the mask 96.

[0084] exist Figures 18A-18C In the embodiment of the present invention, the mask 96 (if present) and the dummy gate 94 are removed in an etching process, thereby forming recesses 116. In some embodiments, the dummy gate 94 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 94 at a faster rate than etching the first ILD 114 or the gate spacer 98. Each recess 116 exposes and / or overlies some portion of the channel region 68. Some portions of the nanostructures 66 that serve as the channel region 68 are disposed between adjacent pairs of the epitaxial source / drain regions 108.

[0085] The remaining portions of the nanostructures 64 are then removed to enlarge the recesses 116, thereby forming openings 118 in the areas between the nanostructures 66. The remaining portions of the dummy gates 76 are also removed to enlarge the recesses 116, thereby forming openings 120 in the areas between the semiconductor fins 62 and the hybrid fins 82. The remaining portions of the nanostructures 64 and the dummy gates 76 may be removed by any acceptable etching process that selectively etches the material(s) of the nanostructures 64 and the dummy gates 76 at a faster rate than the material of the nanostructures 66 is etched. The etching may be isotropic. For example, when the nanostructures 64 and the dummy gates 76 are formed of silicon germanium and the nanostructures 66 are formed of silicon, the etching process may be using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or tetramethylammonium hydroxide (TMAH). 4 The mask 58 (if present) may also be removed. In some embodiments, a trimming process (not separately shown) is performed to reduce the thickness of the exposed portion of the nanostructure 66.

[0086] Because the dummy gates 76 have a small footing profile, they can be removed more easily without the residue of the dummy gates 76 remaining on the top surface of the STI regions 72. Therefore, more area can be used for the replacement gate, and the formation of voids in the replacement gate can be avoided, thereby improving device performance. In addition, as described above, the epitaxial source / drain regions 108 are formed so that there are no residues of the dummy gates 76 below them. Therefore, etching below the epitaxial source / drain regions 108 during the formation of the recesses 116 can be avoided, thereby reducing the risk of damaging the epitaxial source / drain regions 108.

[0087] exist Figure 19A-Figure 19C In the embodiment, a gate dielectric layer 124 is formed in the recess 116. A gate electrode layer 126 is formed on the gate dielectric layer 124. The gate dielectric layer 124 and the gate electrode layer 126 are layers for replacing the gate, and each wraps around all (e.g., four) sides of the nanostructure 66. Therefore, the gate dielectric layer 124 and the gate electrode layer 126 are formed in the opening 118 and the opening 120 (see Fig.18B )middle.

[0088] The gate dielectric layer 124 is disposed on the sidewalls and / or top surfaces of the semiconductor fins 62; on the top surfaces, sidewalls, and bottom surfaces of the nanostructures 66; on the sidewalls of the gate spacers 98 and the inner spacers 106; and on the top surfaces and sidewalls of the hybrid fins 82. The gate dielectric layer 124 may also be formed on the top surface of the first ILD 114 and the top surface of the gate spacers 98. The gate dielectric layer 124 may include an oxide (e.g., silicon oxide or a metal oxide), a silicate (e.g., a metal silicate), combinations thereof, multilayers thereof, and the like. The gate dielectric layer 124 may include a high-k dielectric material (e.g., a dielectric material having a k value greater than approximately 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Figure 19A-Figure 19C A single gate dielectric layer 124 is shown in FIG. 1 , but the gate dielectric layer 124 may include any number of interfacial layers and any number of main layers.

[0089] The gate electrode layer 126 may include a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, etc. Figure 19A-Figure 19C A single gate electrode layer 126 is shown in FIG. 1 , but the gate electrode layer 126 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesion layers, and filler materials.

[0090] The formation of the gate dielectric layer 124 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 124 in each region is formed of the same material, and the formation of the gate electrode layer 126 may occur simultaneously, such that the gate electrode layer 126 in each region is formed of the same material. In some embodiments, the gate dielectric layer 124 in each region may be formed by a different process, such that the gate dielectric layer 124 may be a different material and / or have a different number of layers, and / or the gate electrode layer 126 in each region may be formed by a different process, such that the gate electrode layer 126 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0091] exist Figure 20A-20C 114 and the gate spacer 98, thereby forming the gate structure 130. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. The gate dielectric layer 124 has some portions remaining in the recess 116 after being planarized (thereby forming a gate dielectric for the gate structure 130). The gate electrode layer 126 has some portions remaining in the recess 116 after being planarized (thereby forming a gate electrode for the gate structure 130). The top surfaces of the following items are coplanar (within process variations): gate spacer 98; CESL 112; first ILD 114; and gate structure 130. Gate structure 130 is a replacement gate for the resulting nanostructure transistor / FET and may be referred to as a "metal gate". The gate structures 130 each extend along a top surface, sidewalls, and bottom surface of the channel region 68 of the nanostructure 66 .

[0092] Some gate structures 130 are cap gate structures 130C. Cap gate structures 130C are non-functional structures disposed on the ends of semiconductor fins 62 and over STI regions 72 between semiconductor fins 62. Fig. 20A In the cross section of FIG. 8 , the capping gate structure 130C is disposed between the hybrid fin 82 and the semiconductor fin 62 .

[0093] Gate structure 130 fills the area previously occupied by nanostructure 64, dummy gate 76, and dummy gate 94. After their formation, gate structure 130 has the same outline shape as dummy gate 76. The outline shape of gate structure 130 will be described in more detail later.

[0094] In some embodiments, the isolation region 132 is formed to extend through some of the gate structures 130. The isolation region 132 is formed to divide (or "cut") the gate structure 130 into a plurality of gate structures 130. The isolation region 132 may be formed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by a deposition process such as CVD, ALD, etc. As an example for forming the isolation region 132, an opening may be patterned in the desired gate structure 130. Any acceptable etching process (e.g., dry etching, wet etching, etc., or a combination thereof) may be performed to pattern the opening. The etching may be anisotropic. One or more layers of dielectric material may be deposited in the opening. A removal process may be performed to remove excess portions of the dielectric material that are located above the top surface of the gate structure 130, thereby forming the isolation region 132.

[0095] exist Figure 21A-Figure 21C In the embodiment of the present invention, the second ILD 136 is deposited over the gate spacer 98, the CESL 112, the first ILD 114, and the gate structure 130. In some embodiments, the second ILD 136 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 136 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0096] In some embodiments, an etch stop layer (ESL) 134 is formed between the second ILD 136 and the gate spacers 98, CESL 112, first ILD 114, and gate structure 130. ESL 134 may include a dielectric material having a high etch selectivity with respect to etching the second ILD 136, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0097] exist Figure 22A-22C , a gate contact 142 and a source / drain contact 144 are formed to contact the gate structure 130 and the epitaxial source / drain region 108, respectively. The gate contact 142 is physically and electrically coupled to the gate structure 130. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 108.

[0098] As an example for forming a gate contact 142 and a source / drain contact 144, an opening for a gate contact 142 is formed through the second ILD 136 and the ESL 134, and an opening for a source / drain contact 144 is formed through the second ILD 136, the ESL 134, the first ILD 114, and the CESL 112. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, or nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 136. The remaining liner and conductive material form a gate contact 142 and a source / drain contact 144 in the opening. The gate contact 142 and the source / drain contact 144 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 142 and the source / drain contact 144 may be formed in different cross sections, which may avoid shorting of the contacts.

[0099] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain regions 108 and the source / drain contacts 144. The metal-semiconductor alloy region 146 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanium region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 146 may be formed before the material(s) of the source / drain contacts 144 by depositing a metal in the openings of the source / drain contacts 144 and then performing a thermal annealing process. The metal can be any metal that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain region 108 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process such as a wet clean can be performed to remove any residual metal from the opening of the source / drain contact 144 (e.g., from the surface of the metal-semiconductor alloy region 146). Then, the material(s) of the source / drain contact 144 can be formed on the metal-semiconductor alloy region 146.

[0100] Figure 23A-23C is a diagram of a nanostructure transistor / FET according to various embodiments. Fig.23A , Fig. 23B and Fig.23C They are shown in Fig.9A , Fig. 9B and Fig. 9C The gate structure 130 obtained after performing the replacement gate process in the embodiment of FIG. As described above, the gate structure 130 has the same contour shape as the dummy gate 76. Specifically, the portion of the gate structure 130 on the top surface of the STI region 72 does not flare outward along the concave surface of the STI region 72.

[0101] exist Fig.23A In the embodiment of the present invention, after the replacement gate process, the bottom surface of the gate structure 130 extends to a first distance D away from the nanostructure 66. 1 , and the outer sidewall of the gate structure 130 is set to be a second distance D from the nanostructure 66 2 , where the first distance D 1 Equal to the second distance D 2 In addition, the hybrid fin 82 is disposed at a first distance D from the semiconductor fin 62. 1 , and is set to be a second distance D from the nanostructure 66 2 In this embodiment, the sidewalls of the lower portion of the gate structure 130 are spaced apart by a constant width. 1 and distance D 2 Each may be in the range of 0.5 nm to 30 nm.

[0102] exist Fig. 23B In the embodiment of the present invention, after the replacement gate process, the bottom surface of the gate structure 130 extends to a first distance D away from the nanostructure 66. 1 , and the outer sidewall of the gate structure 130 is set to be a second distance D from the nanostructure 66 2 , where the first distance D 1 Less than the second distance D 2 In addition, the hybrid fin 82 is disposed at a first distance D from the semiconductor fin 62. 1 , and is set to be a second distance D from the nanostructure 66 2 In this embodiment, the distance between the sidewalls of the lower portion of the gate structure 130 decreases linearly in a direction extending from the top of the gate structure 130 to the bottom of the gate structure 130. The distance D 1 and distance D 2 Each may be in the range of 0.5 nm to 30 nm.

[0103] exist Fig.23C In the embodiment of FIG. 1 , after the replacement gate process, the bottom surface of the gate structure 130 extends away from the nanostructure 66 by a first distance D 1, and the outer sidewall of the gate structure 130 is set to be a second distance D from the nanostructure 66 2 , where the first distance D 1 Less than the second distance D 2 In addition, the hybrid fin 82 is disposed at a first distance D from the semiconductor fin 62. 1 , and is set to be a second distance D from the nanostructure 66 2 In this embodiment, the distance at which the sidewalls of the lower portion of the gate structure 130 are spaced apart decreases nonlinearly in a direction extending from the top of the gate structure 130 to the bottom of the gate structure 130, and then increases nonlinearly in that direction as well. The sidewalls of those portions of the gate structure 130 include sidewall recesses 130R. The hybrid fin 82 extends into the sidewall recesses 130R of the gate structure 130. The bottom of the sidewall recesses 130R is disposed at a third distance D from the nanostructure 66. 3 , where the third distance D 3 Less than the second distance D 2 and the first distance D 1 . Distance D 1 , distance D 2 , and distance D 3 Each may be in the range of 0.5 nm to 30 nm.

[0104] Figure 24A-24C is a diagram of a nanostructure transistor / FET according to various embodiments. These embodiments are similar to Figure 23A-23C , except that the protective layer 80 is not removed and remains in the final device. The protective layer 80 extends along the portion of the sidewall of the gate structure 130 adjacent to the nanostructure 66. In these embodiments, the protective layer 80 has a constant width. The protective layer 80 contacts the upper portion of the sidewall of the gate structure 130. The height H of the protective layer 80 is 0 can be in the range of 1 nm to 300 nm, and the width W 0 The height H of the lower portion of the sidewall of the gate structure 130 not covered by the protection layer 80 is in the range of 0.3 nm to 15 nm. 1 It can be in the range of 0nm to 300nm.

[0105] Figure 25A-Figure 25C is a diagram of a nanostructure transistor / FET according to various embodiments. These embodiments are similar to Figure 24A-Figure 24C The embodiment is different in that the protective layer 80 has a width that decreases in a direction extending from the top of the protective layer 80 to the bottom of the protective layer 80.

[0106] Figure 26A-26C They are Figure 23A-23C Detailed view of region 50R in FIG. Fig.26A , the sidewall of the lower portion of the gate structure 130 is substantially perpendicular to a plane parallel to the main surface of the substrate 50. For example, the angle θ between the sidewall of the gate structure 130 and the top surface of the STI region 72 is 1 It can be in the range of 80 to 100 degrees. Fig.26B , the sidewall of the lower portion of the gate structure 130 forms an acute angle with a plane parallel to the main surface of the substrate 50. For example, the angle θ between the sidewall of the gate structure 130 and the top surface of the STI region 72 is 2 It can be in the range of 30 degrees to 85 degrees. Fig.26C , the surface of the gate structure 130 defining the sidewall recess 130R forms several angles. Specifically, the surface of the gate structure 130 defining the sidewall recess 130R forms an angle θ with the top surface of the STI region 72. 3 , and forms an angle θ with a plane parallel to the main surface of the substrate 50 4 Angle θ 3 and angle θ 4 They may each be in the range of 95 to 150 degrees.

[0107] Figure 27A-Figure 27D is a diagram of an intermediate stage in the patterning of a dummy gate 76 having a small footing profile according to some other embodiments. Figures 7A-9C In a manner similar to that described above, by patterning the dummy gate layer 74 using multiple etching processes, the dummy gate 76 is formed to have a small footing profile. In this embodiment, different types of protective layers 80 are used. Specifically, the protective layer 80 is a passivation layer 80P. The passivation layer 80P can be formed by a separate process before or after the initial patterning of the dummy gate layer 74. Advantageously, the passivation layer 80P can be formed to have a more uniform thickness than the byproduct layer 80B. In addition, the passivation gas can be omitted from the first etching process for initially patterning the dummy gate 76.

[0108] The passivation layer 80P may be formed by a surface modification process or a deposition process. Generally, the surface modification process is easier to control to reduce damage to the dummy gate 76, and the deposition process is easier to control the thickness of the resulting passivation layer 80P. The surface modification process may be a plasma modification process, a chemical modification process, etc. In some embodiments, the thickness of the passivation layer 80P is about 1000 nm. to within the range.

[0109] In an embodiment using a plasma modification process, forming the passivation layer 80P may include exposing the structure to a passivation gas while generating plasma. The passivation gas may be CH 4 、SiCl 4 、N2 , O 2 , CO 2 、SO 2 , CO, etc. In some embodiments, a rare gas such as Ar, He, Ne, or a combination thereof may be used. In some embodiments, the process conditions of the plasma modification process include: a pressure in the range of 1mTorr to 10Torr; a plasma source power in the range of 10W to 3000W (configured to control the ratio of ions to radicals); a plasma bias power in the range of 0W to 3000W (configured to control the plasma direction); and a gas source flow rate in the range of 1sccm to 5000sccm. The composition of the passivation layer 80P formed by the plasma modification process depends on the passivation gas used. Continuing with the example that the dummy gate layer 74 is formed of silicon or silicon germanium: when an oxygen-based passivation gas (e.g., O 2 , CO 2 、SO 2 , CO, etc.), the passivation layer 80P may be formed of SiO or SiGeO; when a nitrogen-based passivation gas (e.g., N 2 When a sulfur-based passivation gas (e.g., SO 2 When the passivation layer 80P is formed of SiS or SiGeS, the passivation layer 80P may be formed of SiS or SiGeS. In some embodiments, a plurality of passivation gases may be used in the plasma modification process. For example, a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas, and a sulfur-based passivation gas (e.g., SO 2 and N 2 ), and the passivation layer 80P may be made of SiGeS x O y N z form.

[0110] In an embodiment using a chemical modification process, forming the passivation layer 80P may include exposing the structure to a passivation solution without generating a plasma. The passivation solution may include a primary passivation chemical and an auxiliary passivation chemical in a solvent. The primary passivation chemical may be a 3 , CO 2 etc. The auxiliary passivation chemicals can be H 2 SO 4 NH 3 The solvent may be deionized (DI) water, alcohol, acetone, etc.

[0111] In an embodiment using a deposition process, forming the passivation layer 80P may include PECVD, CVD, ALD, PVD, or a growth process suitable for depositing dielectric materials. The passivation layer 80P may be made of, for example, SiN, SiON, SiCON, SiC, SiOC, SiO 2 The dielectric material is formed.

[0112] In some embodiments, before patterning the dummy gate layer 74, a passivation layer 80P is formed on the dummy gate layer 74, such as Fig.27A As shown. After forming the passivation layer 80P, the dummy gate layer 74 and the passivation layer 80P can be patterned simultaneously to form a dummy gate 76 with a small footing profile. For example, an etching process can be performed to etch both the dummy gate layer 74 and the passivation layer 80P. The etching process can be controlled (for example, by adjusting the plasma bias power) so that it etches in a lateral direction substantially parallel to the main surface of the substrate 50. Portions of the passivation layer 80P can be removed by the etching process to expose the lower portion of the dummy gate layer 74, and the lateral direction of the etching process causes the dummy gate layer 74 to be etched to form a dummy gate 76 with a small footing profile. In some embodiments, portions of the dummy gate 76 may extend over the mask 58 (if present) and the nanostructures 64, 66. These portions of the dummy gate 76 may be removed in a subsequent process, for example, a removal process is performed to remove portions of the hybrid fin layer 78 that are located above the mask 58 (if present) and the nanostructures 64, 66 (see Figure 11A-11C ).

[0113] In some embodiments, the passivation layer 80P is formed after the initial patterning of the dummy gate layer 74 but before the trimming of the dummy gate 76 so that the STI region 72 is covered, as shown in FIG. Fig.27B After forming the passivation layer 80P, the dummy gate 76 can be trimmed while the dummy gate 76 is covered by the passivation layer 80P to form a dummy gate 76 with a small footing profile, thereby obtaining Figure 8C For example, an etching process may be performed to etch both the dummy gate 76 and the passivation layer 80P. The etching process may be controlled (e.g., by adjusting the plasma bias power) so that it etches in a lateral direction substantially parallel to the main surface of the substrate 50. Some portions of the passivation layer 80P may be removed by the etching process (to form Figure 7B The lateral direction of the etching process causes the lower portion of the dummy gate 76 to be etched to form a dummy gate 76 having a small footing profile (thereby forming a Figure 8C structure).

[0114] In some embodiments, the passivation layer 80P is formed after the initial patterning of the dummy gate layer 74 but before the trimming of the dummy gate 76 so that the STI region 72 is exposed, such as Fig.27C and Fig.27D In some embodiments where the passivation layer 80P is formed by a surface modification process, the passivation layer 80P may be selectively formed on the mask 58 (if present) and the dummy gate 76 but not on the STI region 72, as shown. Fig.27C In some embodiments where the passivation layer 80P is formed by a deposition process, the passivation layer 80P may be conformally formed on the mask 58 (if present), the dummy gate 76, and the STI region 72, as shown. Fig.27D After forming the passivation layer 80P, the dummy gate 76 can be trimmed while the dummy gate 76 is covered by the passivation layer 80P to form a dummy gate 76 with a small footing profile, thereby obtaining Fig. 8A or Figure 8B For example, an etching process may be performed to etch both the dummy gate 76 and the passivation layer 80P. The etching process may be controlled (e.g., by adjusting the plasma bias power) so that it etches in a diagonal direction that forms an acute angle with a plane parallel to the main surface of the substrate 50. The diagonal direction of the etching process results in etching through the passivation layer 80P at the lower portion of the dummy gate 76 (thereby forming Fig. 7A ), and then etching the lower portion of the dummy gate 76 to form a dummy gate 76 having a small footing profile (thereby forming Fig. 8A or Figure 8B structure).

[0115] As described above, the same substrate 50 may have sparse regions and dense regions. In such an embodiment, the passivation layer 80P may have different thicknesses in different regions. As a result, dummy gates 76 having different footing profiles may be formed from the same initial structure. For example, dummy gates 76 may be formed in dense regions and sparse regions. Fig.27A A passivation layer 80P may be formed over these structures, and then a dummy gate 76 is patterned, wherein Fig. 8A or Figure 8B The structure produces dense areas, while Figure 8C The structure produces sparse areas.

[0116] Embodiments can achieve advantages. Forming a dummy gate 76 with a small footing profile increases the processing window for subsequent operations, such as a replacement gate process and / or an epitaxial growth process of the source / drain region. Specifically, there may be no residue of the dummy gate 76 below the epitaxial source / drain region 108, thereby avoiding damage to the epitaxial source / drain region 108 when removing the dummy gate 76 in the replacement gate process. In addition, the dummy gate 76 with a small footing profile can be more easily removed in the replacement gate process, and voids can be avoided in the replacement gate, thereby improving device performance.

[0117] In one embodiment, a device includes: an isolation region; a nanostructure protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructure, the gate structure having a bottom surface in contact with the isolation region, the bottom surface of the gate structure extending to a first distance away from the nanostructure, the gate structure having a sidewall set to a second distance from the nanostructure, the first distance being less than or equal to the second distance; and a hybrid fin located on the sidewall of the gate structure. In some embodiments of the device, the first distance is less than the second distance. In some embodiments of the device, the hybrid fin extends into a sidewall recess of the gate structure. In some embodiments of the device, the first distance is equal to the second distance. In some embodiments of the device, the first distance and the second distance are each in the range of 0.5 nm to 30 nm. In some embodiments, the device also includes: a protective layer disposed between the hybrid fin and the gate structure, the protective layer covering an upper portion of the sidewall of the gate structure, and a lower portion of the sidewall of the gate structure is not covered by the protective layer.

[0118] In one embodiment, a device includes: an isolation region; a semiconductor fin protruding above a top surface of the isolation region; a nanostructure located above the semiconductor fin; a gate structure wrapped around the nanostructure; and a hybrid fin on a sidewall of the gate structure, the hybrid fin being disposed at a first distance from the semiconductor fin, the hybrid fin being disposed at a second distance from the nanostructure, the second distance being greater than the first distance. In some embodiments, the device further includes: a protective layer located between the hybrid fin and the gate structure, the protective layer extending along a portion of the sidewall of the gate structure adjacent to the nanostructure. In some embodiments of the device, the protective layer includes SiGeS x O y N z In some embodiments of the device, the protective layer includes a dielectric material. In some embodiments of the device, a portion of the hybrid fin extends into the sidewall recess of the gate structure, the portion of the hybrid fin being disposed at a third distance from the semiconductor fin, the third distance being less than the first distance and the second distance.

[0119] In one embodiment, a method includes: depositing a dummy gate layer over an isolation region and alternating first and second nanostructures, the first and second nanostructures protruding above a top surface of the isolation region; patterning the dummy gate layer to form a dummy gate on a sidewall of the first nanostructure, a sidewall of the second nanostructure, and a top surface of the isolation region; forming a protective layer on an upper portion of the dummy gate; trimming a lower portion of the dummy gate while the protective layer covers the upper portion of the dummy gate; and replacing the dummy gate and the first nanostructure with a metal gate, the metal gate wrapped around the second nanostructure. In some embodiments of the method, the protective layer is a byproduct layer formed during patterning of the dummy gate layer, and patterning the dummy gate layer includes etching the dummy gate layer using a gas source, the gas source including a primary etching gas and a passivation gas. In some embodiments of the method, the dummy gate layer and the first nanostructure include silicon or silicon germanium; and the passivation gas is a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas, and a sulfur-based passivation gas. In some embodiments of the method, the protective layer is a passivation layer formed after patterning the dummy gate layer, and forming the protective layer includes exposing the dummy gate to a passivation gas while generating plasma. In some embodiments of the method, the protective layer is a passivation layer formed after patterning the dummy gate layer, and forming the protective layer includes exposing the dummy gate to a passivation solution without generating plasma. In some embodiments of the method, the protective layer is a passivation layer formed after patterning the dummy gate layer, and forming the protective layer includes depositing a dielectric material on the dummy gate. In some embodiments of the method, the dummy gate has a sidewall and has a bottom surface in contact with the isolation region, the sidewall of the dummy gate is set to a first distance from the second nanostructure, and trimming the lower portion of the dummy gate includes: etching the lower portion of the dummy gate until the bottom surface of the dummy gate extends to a second distance away from the second nanostructure, the second distance being less than the first distance. In some embodiments of the method, the dummy gate has a sidewall and has a bottom surface in contact with the isolation region, the sidewall of the dummy gate is disposed a first distance from the second nanostructure, and trimming the lower portion of the dummy gate includes etching the lower portion of the dummy gate until the bottom surface of the dummy gate extends a second distance away from the second nanostructure, the second distance being equal to the first distance. In some embodiments of the method, etching the lower portion of the dummy gate forms a sidewall recess in the lower portion of the dummy gate.

[0120] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0121] Example 1. A semiconductor device comprising:

[0122] Isolation area;

[0123] a nanostructure protruding above a top surface of the isolation region;

[0124] a gate structure wrapped around the nanostructure, the gate structure having a bottom surface in contact with the isolation region, the bottom surface of the gate structure extending a first distance away from the nanostructure, the gate structure having a sidewall disposed a second distance from the nanostructure, the first distance being less than or equal to the second distance; and

[0125] A hybrid fin is provided on a sidewall of the gate structure.

[0126] Example 2. The device of Example 1, wherein the first distance is less than the second distance.

[0127] Example 3. The device of Example 2, wherein the hybrid fin extends into a sidewall recess of the gate structure.

[0128] Example 4. The device of Example 1, wherein the first distance is equal to the second distance.

[0129] Example 5. The device of Example 1, wherein the first distance and the second distance are each in the range of 0.5 nm to 30 nm.

[0130] Example 6. The device of Example 1, further comprising:

[0131] A protection layer is disposed between the hybrid fin and the gate structure, wherein the protection layer covers an upper portion of a side wall of the gate structure, and a lower portion of the side wall of the gate structure is not covered by the protection layer.

[0132] Example 7. A semiconductor device comprising:

[0133] Isolation area;

[0134] a semiconductor fin protruding above a top surface of the isolation region;

[0135] a nanostructure located on the semiconductor fin;

[0136] a gate structure wrapped around the nanostructure; and

[0137] A hybrid fin on a sidewall of the gate structure is arranged at a first distance from the semiconductor fin, and the hybrid fin is arranged at a second distance from the nanostructure, wherein the second distance is greater than the first distance.

[0138] Example 8. The device of Example 7, further comprising:

[0139] A protection layer is located between the hybrid fin and the gate structure, and the protection layer extends along a portion of a sidewall of the gate structure adjacent to the nanostructure.

[0140] Example 9. The device of Example 8, wherein the protective layer comprises SiGeS x O y N z .

[0141] Example 10. The device of Example 8, wherein the protective layer comprises a dielectric material.

[0142] Example 11. The device of Example 7, wherein a portion of the hybrid fin extends into a sidewall recess of the gate structure, the portion of the hybrid fin being disposed a third distance from the semiconductor fin, the third distance being less than the first distance and the second distance.

[0143] Example 12. A method for forming a semiconductor device, comprising:

[0144] depositing a dummy gate layer over the isolation region and the alternating first and second nanostructures, the first and second nanostructures protruding above a top surface of the isolation region;

[0145] Patterning the dummy gate layer to form a dummy gate on a sidewall of the first nanostructure, a sidewall of the second nanostructure, and a top surface of the isolation region;

[0146] forming a protective layer on an upper portion of the dummy gate;

[0147] trimming a lower portion of the dummy gate while the protection layer covers an upper portion of the dummy gate; and

[0148] The dummy gate and the first nanostructure are replaced with a metal gate, and the metal gate is wrapped around the second nanostructure.

[0149] Example 13. A method according to Example 12, wherein the protective layer is a byproduct layer formed during patterning of the dummy gate layer, and patterning the dummy gate layer includes etching the dummy gate layer using a gas source, the gas source including a main etching gas and a passivation gas.

[0150] Example 14. The method of Example 13, wherein the dummy gate layer and the first nanostructure include silicon or silicon germanium; and the passivation gas is a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas, and a sulfur-based passivation gas.

[0151] Example 15. The method of Example 12, wherein the protective layer is a passivation layer formed after patterning the dummy gate layer, and forming the protective layer includes exposing the dummy gate to a passivation gas while generating plasma.

[0152] Example 16. The method of Example 12, wherein the protective layer is a passivation layer formed after patterning the dummy gate layer, and forming the protective layer includes exposing the dummy gate to a passivation solution without generating plasma.

[0153] Example 17. The method of Example 12, wherein the protective layer is a passivation layer formed after patterning the dummy gate layer, and forming the protective layer includes depositing a dielectric material on the dummy gate.

[0154] Example 18. The method of Example 12, wherein the dummy gate has a sidewall and has a bottom surface in contact with the isolation region, the sidewall of the dummy gate is disposed at a first distance from the second nanostructure, and trimming a lower portion of the dummy gate comprises:

[0155] The lower portion of the dummy gate is etched until a bottom surface of the dummy gate extends to a second distance away from the second nanostructure, and the second distance is smaller than the first distance.

[0156] Example 19. The method of Example 12, wherein the dummy gate has a sidewall and has a bottom surface in contact with the isolation region, the sidewall of the dummy gate is disposed at a first distance from the second nanostructure, and trimming a lower portion of the dummy gate comprises:

[0157] The lower portion of the dummy gate is etched until a bottom surface of the dummy gate extends to a second distance away from the second nanostructure, and the second distance is equal to the first distance.

[0158] Example 20. The method of Example 12, wherein etching the lower portion of the dummy gate forms a sidewall recess in the lower portion of the dummy gate.

Claims

1. A semiconductor device, comprising: Isolation area; a nanostructure protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructure, the gate structure having a bottom surface in contact with the isolation region, the bottom surface of the gate structure extending a first distance away from the nanostructure, the gate structure having a sidewall disposed a second distance from the nanostructure, the first distance being less than or equal to the second distance; as well as a hybrid fin on a sidewall of the gate structure, wherein the hybrid fin is formed of a dielectric material, The semiconductor device further includes: a protection layer disposed between the hybrid fin and the gate structure, wherein the protection layer covers an upper portion of a side wall of the gate structure, and a lower portion of the side wall of the gate structure is not covered by the protection layer.

2. The device according to claim 1, wherein The first distance is smaller than the second distance.

3. The device according to claim 2, wherein The hybrid fin extends into a sidewall recess of the gate structure.

4. The device according to claim 1, wherein The first distance is equal to the second distance.

5. The device according to claim 1, wherein The first distance and the second distance are each in the range of 0.5 nm to 30 nm.

6. A semiconductor device comprising: Isolation area; a semiconductor fin protruding above a top surface of the isolation region; a nanostructure located on the semiconductor fin; a gate structure wrapped around the nanostructure; as well as a hybrid fin on a sidewall of the gate structure, the hybrid fin being disposed at a first distance from the semiconductor fin, the hybrid fin being disposed at a second distance from the nanostructure, the second distance being greater than the first distance, wherein the hybrid fin is formed of a dielectric material, The semiconductor device further comprises: a protection layer located between the hybrid fin and the gate structure, wherein the protection layer extends along a portion of a side wall of the gate structure adjacent to the nanostructure.

7. The device according to claim 6, wherein The protective layer includes SiGeS x O y N z .

8. The device according to claim 6, wherein The protection layer includes a dielectric material.

9. The device according to claim 6, wherein A portion of the hybrid fin extends into the sidewall recess of the gate structure, and the portion of the hybrid fin is disposed a third distance from the semiconductor fin, the third distance being less than the first distance and the second distance.

10. A method for forming a semiconductor device, comprising: depositing a dummy gate layer over the isolation region and the alternating first and second nanostructures, the first and second nanostructures protruding above a top surface of the isolation region; Patterning the dummy gate layer to form a dummy gate on a sidewall of the first nanostructure, a sidewall of the second nanostructure, and a top surface of the isolation region; forming a protective layer on an upper portion of the dummy gate; While the protection layer covers the upper portion of the dummy gate, trimming the lower portion of the dummy gate; as well as The dummy gate and the first nanostructure are replaced with a metal gate, wherein the metal gate is wrapped around the second nanostructure, The dummy gate has a sidewall and a bottom surface in contact with the isolation region, the sidewall of the dummy gate is set to be a first distance from the second nanostructure, and trimming the lower portion of the dummy gate includes: The lower portion of the dummy gate is etched until a bottom surface of the dummy gate extends to a second distance away from the second nanostructure, and the second distance is smaller than the first distance.

11. The method according to claim 10, wherein: The protection layer is a byproduct layer formed during patterning of the dummy gate layer, and patterning the dummy gate layer includes etching the dummy gate layer using a gas source including a main etching gas and a passivation gas.

12. The method according to claim 11, wherein: The dummy gate layer and the first nanostructure include silicon or silicon germanium; and the passivation gas is a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas, and a sulfur-based passivation gas.

13. The method according to claim 10, wherein: The protection layer is a passivation layer formed after the dummy gate layer is patterned, and forming the protection layer includes exposing the dummy gate to a passivation gas while generating plasma.

14. The method according to claim 10, wherein: The protection layer is a passivation layer formed after the dummy gate layer is patterned, and forming the protection layer includes exposing the dummy gate to a passivation solution without generating plasma.

15. The method according to claim 10, wherein: The protection layer is a passivation layer formed after the dummy gate layer is patterned, and forming the protection layer includes depositing a dielectric material on the dummy gate.

16. The method according to claim 10, wherein: The dummy gate has a sidewall and has a bottom surface in contact with the isolation region, the sidewall of the dummy gate is disposed at a first distance from the second nanostructure, and trimming a lower portion of the dummy gate includes: The lower portion of the dummy gate is etched until a bottom surface of the dummy gate extends to a second distance away from the second nanostructure, and the second distance is equal to the first distance.

17. The method according to claim 10, wherein: Etching a lower portion of the dummy gate forms a sidewall recess in the lower portion of the dummy gate.

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