Capacitive sensing device and method for sensing capacitance

Abstract

The embodiments of the present application provide a capacitive sensing device and a method for sensing capacitance. The capacitive sensing device includes: a capacitive sensor, which is suitable for sensing a conductive object approaching it; a switch group, which is suitable for alternately coupling the capacitive sensor to a first predetermined voltage and a reference capacitor; a reference capacitor, which is suitable for sharing charge with the capacitive sensor when sensing a conductive object; a comparator, which has a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the reference capacitor, the second input terminal is coupled to the reference voltage, and the output terminal is coupled to a charge balancing circuit and a counter; the charge balancing circuit is coupled to the reference capacitor and is suitable for charging or discharging the reference capacitor when sensing a conductive object; a counter, which is suitable for counting and obtaining a count value based on the first or second logic level output by the comparator. The technical solution of the embodiments of the present application is conducive to improving the sensing sensitivity and avoiding the increase in power consumption due to the increase in the sensing cycle.

Description

Technical Field

[0001] The present invention relates to the field of proximity sensing, and in particular to a capacitive sensing device and a method for sensing capacitance. Background Art

[0002] Capacitive sensing devices are increasingly being used in electronic devices such as personal computers, multimedia players, game consoles, consumer electronics, and mobile communication devices.

[0003] Taking the existing patent document with the invention name of "Capacitive proximity detection using Δ / Σ conversion" (patent authorization number CN105379120B, hereinafter referred to as "Patent Document 1") as an example, the patent document describes a specific implementation scheme of capacitive proximity detection. However, this scheme has three disadvantages. The first disadvantage is that during the entire capacitive sensing process, the charging circuit selectively charges and discharges the holding capacitor according to the output result of the comparator. This method is equivalent to increasing the capacitance value of the capacitive sensor, which is not conducive to improving the sensing sensitivity; the second disadvantage is that the switch coupled to the capacitive sensor is controlled by the output signal of the comparator, which in principle makes the formula for measuring the final count value of the capacitance value of the capacitive sensor complicated, which is not conducive to the automatic adjustment of the sensing sensitivity in practical applications; the third disadvantage is that the improvement of the sensing sensitivity is based on the increase of the measurement time period, which increases the power consumption of the sensing process.

[0004] Existing capacitive sensing devices need to be improved in aspects such as power consumption and sensing sensitivity. Summary of the invention

[0005] The technical problem solved by the present invention is that the existing capacitive sensing devices need to be improved in terms of power consumption and sensing sensitivity.

[0006] To solve the above technical problems, an embodiment of the present invention provides a capacitive sensing device, including: a capacitive sensor, which is suitable for sensing a conductive object approaching it; a switch group, which is suitable for alternately coupling the capacitive sensor to a first predetermined voltage and a reference capacitor; a reference capacitor, which is suitable for sharing charge with the capacitive sensor when sensing a conductive object; a comparator, which has a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the reference capacitor, the second input terminal is coupled to the reference voltage, and the output terminal is coupled to a charge balancing circuit and a counter; the charge balancing circuit is coupled to the reference capacitor and is suitable for charging or discharging the reference capacitor when sensing a conductive object; and a counter, which is suitable for counting and obtaining a count value based on a first logic level or a second logic level output by the comparator.

[0007] Optionally, the first end of the capacitive sensor is grounded, the first end of the reference capacitor is grounded, and the switch group includes a first switch and a second switch, wherein the first switch is coupled between the second end of the capacitive sensor and a first predetermined voltage, and the second switch is coupled between the second end of the capacitive sensor and the second end of the reference capacitor.

[0008] Optionally, any one of the first logic level and the second logic level is a high level or a low level.

[0009] Optionally, the charge balancing circuit is adapted to charge or discharge the reference capacitor to maintain the voltage of the reference capacitor near a reference voltage.

[0010] Optionally, the first predetermined voltage is at a low level and the charge balancing circuit is adapted to charge the reference capacitor when sensing a conductive object, or the first predetermined voltage is at a high level and the charge balancing circuit is adapted to discharge the reference capacitor when sensing a conductive object.

[0011] Optionally, the charge balancing circuit includes a first power supply, a second power supply, a first control switch and a second control switch, the first power supply and the second power supply are coupled to a reference capacitor through the first control switch and the second control switch, respectively, and the output end of the comparator is coupled to the first control switch and the second control switch to selectively close and open the reference capacitor, thereby alternately charging or discharging the reference capacitor through the first power supply and the second power supply.

[0012] Optionally, when the first predetermined voltage is at a low level, the first power supply and the second power supply are respectively coupled to a high level to alternately charge the reference capacitor; when the first predetermined voltage is at a high level, the first power supply and the second power supply are both coupled to a low level to alternately discharge the reference capacitor.

[0013] Optionally, the first power source and the second power source are respectively a first current source and a second current source.

[0014] Optionally, the first power source and the second power source are respectively a first voltage source and a second voltage source.

[0015] Optionally, the charge balancing circuit further includes a first resistor and a second resistor, the first voltage source is coupled to the first control switch via the first resistor, and the second voltage source is coupled to the second control switch via the second resistor.

[0016] Optionally, the first control switch includes a first AND gate and a third switch, the second control switch includes a second AND gate and a fourth switch, the first input terminal of the first AND gate and the first input terminal of the second AND gate are both coupled to the output terminal of the comparator, the second input terminal of the first AND gate and the second input terminal of the second AND gate are both coupled to the clock signal, the third switch is coupled between the output terminal of the first AND gate and the second terminal of the reference capacitor, and the fourth switch is coupled between the output terminal of the second AND gate and the second terminal of the reference capacitor.

[0017] Optionally, the charge balancing circuit further includes a first capacitor and a second capacitor, wherein a first end of the first capacitor is coupled to the third switch and a second end is coupled to the ground, and a first end of the second capacitor is coupled to the fourth switch and a second end is coupled to the ground.

[0018] Optionally, the first power source and the second power source are respectively a third current source and a third voltage source.

[0019] Optionally, the charge balancing circuit further includes a third resistor, and the third voltage source is coupled to the second control switch via the third resistor.

[0020] Optionally, the capacitive sensing device includes a timing unit, and the output end of the comparator is respectively coupled to the charge balancing circuit and the counter through the timing unit.

[0021] Optionally, the capacitive sensing device includes a timer coupled to the counter and adapted to determine a sensing period and output a timing signal to the counter, wherein the counter is adapted to count within the sensing period to obtain a final count value based on the first logic level or the second logic level and the timing signal.

[0022] Optionally, the capacitive sensing device comprises a control unit coupled to the timer, adapted to output an enable signal or a disable signal to the timer, and receive a timing signal.

[0023] An embodiment of the present invention also provides a method for sensing capacitance, comprising: a, alternately coupling a capacitive sensor to a first predetermined voltage and a reference capacitor; b, comparing the voltage of the reference capacitor with the reference voltage and outputting a first logic level or a second logic level; c, counting a counter based on the first logic level or the second logic level to obtain a count value and charging or discharging the reference capacitor.

[0024] Optionally, step c includes charging or discharging the reference capacitor based on the first logic level or the second logic level to maintain the voltage of the reference capacitor near the reference voltage.

[0025] Optionally, steps a, b and c are executed cyclically within a sensing period determined by a timer, and a final count value is obtained.

[0026] Optionally, the first predetermined voltage is a low level, and step a includes charging the capacitive sensor through the reference capacitor to adjust the voltage of the reference capacitor.

[0027] Optionally, the method includes charging the capacitive sensor via a reference capacitor and charging the reference capacitor via a charge balancing circuit to adjust the voltage of the reference capacitor.

[0028] Optionally, the charge balancing circuit includes a first power supply and a second power supply, and the first power supply and the second power supply charge the reference capacitor alternately based on a first logic level and a second logic level, respectively.

[0029] Optionally, the first predetermined voltage is a high level, and step a includes adjusting the voltage of the reference capacitor by charging the reference capacitor through a capacitive sensor.

[0030] Optionally, the voltage of the reference capacitor is adjusted by charging the reference capacitor through the capacitive sensor and discharging the reference capacitor through the charge balancing circuit.

[0031] Optionally, the charge balancing circuit includes a first power supply and a second power supply, and the first power supply and the second power supply discharge the reference capacitor alternately based on a first logic level and a second logic level, respectively.

[0032] Compared with the prior art, the technical solution of the embodiment of the present invention has beneficial effects. For example, in the entire capacitance sensing process, for each capacitive sensing device with a specific circuit structure in the embodiment of the present invention, the charge balancing circuit continuously charges or discharges the reference capacitor according to the output result of the comparator, rather than selectively charging and discharging the reference capacitor, which is conducive to improving the sensing sensitivity; the switch group in the embodiment of the present invention is not controlled by the logic level output by the comparator, so that the relationship between the count value of the capacitance value of the capacitive sensor is relatively simple, and is conducive to the automatic adjustment of the sensing sensitivity in practical applications, thereby avoiding the increase in power consumption due to the increase in the sensing cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the overall structure of a capacitive sensing device according to an embodiment of the present invention;

[0034] Figure 2 is a schematic diagram of a specific structure of a capacitive sensing device according to an embodiment of the present invention;

[0035] Figure 3 is a schematic structural diagram of a capacitive sensing device in a first embodiment of the present invention;

[0036] Figure 4 is a schematic structural diagram of a capacitive sensing device in a second embodiment of the present invention;

[0037] Figure 5 is a schematic structural diagram of a capacitive sensing device in a third embodiment of the present invention;

[0038] Figure 6 is a schematic structural diagram of a capacitive sensing device in a fourth embodiment of the present invention;

[0039] Figure 7 is a schematic structural diagram of a capacitive sensing device in a fifth embodiment of the present invention;

[0040] Figure 8is a structural schematic diagram of a capacitive sensing device in a sixth embodiment of the present invention;

[0041] Fig. 9 is a schematic structural diagram of a capacitive sensing device in a seventh embodiment of the present invention;

[0042] Fig.10 is a schematic structural diagram of a capacitive sensing device in an eighth embodiment of the present invention;

[0043] Fig.11 is a flow chart of a method for sensing capacitance according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figure 1 is a schematic diagram of the overall structure of a capacitive sensing device according to an embodiment of the present invention, Figure 2 It is a schematic diagram of the specific structure of the capacitive sensing device according to an embodiment of the present invention.

[0046] like Figure 1 As shown, the capacitive sensing device 100 includes a capacitive sensor 101 , a switch group 102 , a reference capacitor 103 , a comparator 104 , a charge balancing circuit 105 and a counter 106 .

[0047] The capacitive sensing device 100 may be disposed in an electronic device to sense user operations as a part of a user interface.

[0048] The capacitive sensor 101 can be arranged in a specific area of ​​the capacitive sensing device 100, which is suitable for sensing a conductive object (such as a human finger) approaching it. The change in the capacitance value of the capacitive sensor 101 can be sensed by the circuit inside the capacitive sensing device 100 to determine whether a conductive object is approaching, wherein the capacitance value to be sensed of the capacitive sensor 101 is Figures 1 to 10 Marked as C X .

[0049] In one embodiment, a first terminal of the capacitive sensor 101 is grounded.

[0050] The switch group 102 is adapted to alternately couple the capacitive sensor 101 to the first predetermined voltage 107 and the reference capacitor 103 ( Figures 1 to 10 Marked as C R ), wherein the reference capacitor 103 is suitable for sharing charge with the capacitive sensor 101 when sensing a conductive object.

[0051] In one embodiment, a first terminal of the reference capacitor 103 is grounded.

[0052] The switch group 102 may have a first terminal, a second terminal and a third terminal. The first terminal of the switch group 102 may be coupled to the second terminal of the capacitive sensor 101 , the second terminal of the switch group 102 may be coupled to the first predetermined voltage 107 , and the third terminal of the switch group 102 may be coupled to the second terminal of the reference capacitor 103 .

[0053] The switch group 102 can perform a first operation, that is, coupling its first end to the second end of the capacitive sensor 101, coupling the second end to the first predetermined voltage 107, and disconnecting the third end from the second end of the reference capacitor 103, so that the capacitive sensor 101 is coupled to the first predetermined voltage 107 and disconnected from the reference capacitor 103; the switch group 102 can also perform a second operation, that is, coupling its first end to the second end of the capacitive sensor 101, disconnecting the second end from the first predetermined voltage 107, and coupling the third end to the second end of the reference capacitor 103, so that the capacitive sensor 101 is coupled to the reference capacitor 103 and disconnected from the first predetermined voltage 107. The switch group 102 can alternately perform the first operation and the second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage 107 and the reference capacitor 103.

[0054] In one embodiment, the switch group 102 has a fourth terminal coupled to the clock 123 ; the switch group 102 receives a control signal from the clock 123 to alternately perform the first operation and the second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage 107 and the reference capacitor 103 .

[0055] In another embodiment, the switch group 102 includes a first switch 113 ( Figures 2 to 10 Marked as ) and the second switch 114 ( Figures 2 to 10 Marked as ), the first switch 113 is coupled between the second end of the capacitive sensor 101 and the first predetermined voltage 107, and the second switch 114 is coupled between the second end of the capacitive sensor 101 and the second end of the reference capacitor 103. The first switch 113 and the second switch 114 can operate in a two-phase non-overlapping phase mode, and they and the capacitive sensor 101 form a switched capacitor circuit.

[0056] The first predetermined voltage 107 can be a low level, such as ground; or a high level, such as a working voltage (V DD ).

[0057] The reference capacitor 103 is suitable for sharing charge with the capacitive sensor 101 when sensing a conductive object. "Sharing charge" means that if the first predetermined voltage 107 is at a low level, the reference capacitor 103 charges the capacitive sensor 101 when the switch group 102 performs the second operation (and the first predetermined voltage 107 discharges the capacitive sensor 101 when the switch group 102 performs the first operation); if the first predetermined voltage 107 is at a high level, the reference capacitor 103 discharges the capacitive sensor 101 when the switch group 102 performs the second operation (and the first predetermined voltage 107 charges the capacitive sensor 101 when the switch group 102 performs the first operation).

[0058] In the embodiments of the present invention, "charging" means that one element receives charge (positive charge and / or negative charge) transferred from another element, and "discharging" means that one element releases charge (positive charge and / or negative charge) to another element; "one element charges another element" means that another element receives charge (positive charge and / or negative charge) transferred from one element, and "one element discharges another element" means that another element releases charge (positive charge and / or negative charge) to one element.

[0059] In a specific implementation, if the first predetermined voltage 107 is at a low level, the charge balancing circuit 105 is suitable for charging the reference capacitor 103 when sensing a conductive object; if the first predetermined voltage is at a high level, the charge balancing circuit 105 is suitable for discharging the reference capacitor 103 when sensing a conductive object.

[0060] The capacitance of the reference capacitor 103 may be greater than the capacitance of the capacitive sensor 101 , so that when the switch group 102 performs the second operation, the voltage of the reference capacitor 103 caused by the coupling between the capacitive sensor 101 and the reference capacitor 103 does not change significantly.

[0061] The comparator 104 has a first input terminal 108, a second input terminal 109 and an output terminal 110. The first input terminal 108 is coupled to the reference capacitor 103, and the second input terminal 109 is coupled to the reference voltage 111 ( Figures 1 to 10 Marked as V REF ), the output terminal 110 is coupled to the charge balancing circuit 105 and the counter 106.

[0062] In one embodiment, a first terminal of the reference capacitor 103 is grounded, and a second terminal of the reference capacitor 103 is coupled to a first input terminal 108 of the comparator 104 .

[0063] The comparator 104 can compare the voltage of the reference capacitor 103 with the reference voltage 111. For example, when the voltage value of the reference capacitor 103 is lower than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a first logic level; when the voltage value of the reference capacitor 103 is higher than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a second logic level; wherein the first logic level is a high level and the second logic level is a low level, or the first logic level is a low level and the second logic level is a high level.

[0064] The charge balancing circuit 105 is coupled to the reference capacitor 103, and is suitable for charging or discharging the reference capacitor 103 when sensing a conductive object, wherein “the charge balancing circuit 105 charges the reference capacitor 103” means that the reference capacitor 103 receives the charge transferred from the charge balancing circuit 105, and “the charge balancing circuit 105 discharges the reference capacitor 103” means that the reference capacitor 103 releases the charge to the charge balancing circuit 105.

[0065] In one embodiment, a first terminal of the reference capacitor 103 is grounded, and a second terminal of the reference capacitor 103 is coupled to the charge balancing circuit 105 .

[0066] In another embodiment, the charge balancing circuit 105 is suitable for charging or discharging the reference capacitor 103 to maintain the voltage value of the reference capacitor 103 near the voltage value of the reference voltage 111, for example, maintaining the voltage value of the reference capacitor 103 between 70% and 130% of the voltage value of the reference voltage 111.

[0067] In a specific implementation, the charge balancing circuit 105 includes a first power supply 119, a second power supply 120, a first control switch 121, and a second control switch 122. The first power supply 119 and the second power supply 120 are respectively coupled to the reference capacitor 103 (e.g., Figure 2 The output terminal 110 of the comparator 104 is coupled to the first control switch 121 and the second control switch 122 to selectively close and open the comparator 104, thereby alternately charging the reference capacitor 103 through the first power supply 119 and the second power supply 120, or alternately discharging the reference capacitor 103 through the first power supply 119 and the second power supply 120.

[0068] For example, when the output terminal 110 of the comparator 104 outputs a first logic level, the first control switch 121 is closed and the second control switch 122 is opened, so that only the first power supply 119 charges or discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs a second logic level, the first control switch 121 is opened and the second control switch 122 is closed, so that only the second power supply 119 charges or discharges the reference capacitor 103.

[0069] For another example, when the output terminal 110 of the comparator 104 outputs a first logic level, the first control switch 121 is opened and the second control switch 122 is closed, so that only the second power supply 119 charges or discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs a second logic level, the first control switch 121 is closed and the second control switch 122 is opened, so that only the first power supply 119 charges or discharges the reference capacitor 103.

[0070] In a specific implementation, the first power source 119 and the second power source 120 are respectively coupled to a second predetermined voltage ( Figure 2 V1, ) and a third predetermined voltage ( Figure 2 If the first predetermined voltage 107 is at a low level, the second predetermined voltage and the third predetermined voltage are both at a high level and alternately charge the reference capacitor 103; if the first predetermined voltage 107 is at a high level, the second predetermined voltage and the third predetermined voltage are both at a low level (for example, both are coupled to ground) and alternately discharge the reference capacitor 103.

[0071] In an embodiment of the present invention, the first power supply 119 and the second power supply 120 are used to provide a determined current or a determined voltage, therefore, either of the first power supply 119 and the second power supply 120 can be a current source or a voltage source; when the above-mentioned "determined current" or "determined voltage" is zero, the first power supply 119 or the second power supply 120 can be considered as "ground" or the first power supply 119 or the second power supply 120 can be considered as coupled to the "ground".

[0072] The counter 106 is coupled to the output terminal 110 of the comparator 104 , and is adapted to count based on the logic level output by the comparator 104 to obtain a count value.

[0073] For example, when the counter 106 receives a first logic level through its enable terminal, the count value of the counter 106 performs an accumulated counting operation (e.g., the count value increases by one after receiving the first logic level once); when the counter 106 receives a second logic level through its enable terminal, the count value of the counter 106 is maintained.

[0074] For another example, when the counter 106 receives a first logic level through its enable terminal, the count value of the counter 106 is maintained; when the counter 106 receives a second logic level through its enable terminal, the count value of the counter 106 performs an accumulated counting operation (e.g., the count value increases by one when the second logic level is received once).

[0075] The count value (eg, the final count value obtained in one sensing cycle) may be output via the output terminal 112 of the counter 106 .

[0076] The capacitive sensing device 100 may include a filter coupled to the output terminal 112 of the counter 106 to filter the count value output by the counter 106 .

[0077] The capacitive sensing device 100 may include a timing unit 115, and the output terminal 110 of the comparator 104 is respectively coupled to the charge balancing circuit 105 and the counter 106 through the timing unit 115. Figures 2 to 10 As shown, the input end of the timing unit 115 is coupled to the output end 110 of the comparator 104, and the output end is coupled to the charge balancing circuit 105 and the counter 106 respectively. The first logic level or the second logic level output by the comparator 104 is synchronized by the timing unit 115 and then provided to the charge balancing circuit 105 and the counter 106 respectively, so that the charge balancing circuit 105 can charge or discharge the reference capacitor 103 in a precise cycle, and the counter 106 can count accurately.

[0078] The capacitive sensing device 100 may include a timer 116, which is coupled to the counter 106 to output a timing signal thereto; the timer 116 is adapted to determine a sensing period, during which the counter 106 counts. Specifically, the output terminal 110 of the comparator 104 (which may be coupled to the timing unit 115) and the output terminal of the timer 116 are respectively coupled to two input terminals of an AND gate 117, and the output terminal of the AND gate 117 is coupled to an enable terminal of the counter 106, so that the counter 106 counts within the sensing period based on the first logic level output by the comparator 104 and the timing signal output by the timer 116, and a final count value can be obtained at the end of the sensing period.

[0079] The capacitive sensing device 100 may include a control unit 118, which is coupled to the timer 116 and outputs an enable signal or a disable signal to the latter, and receives a timing signal output by the latter. Specifically, the input end of the control unit 118 is coupled to the output end of the timer 116 to receive the timing signal output by the latter; the output end of the control unit 118 is coupled to the enable end of the timer 116 to output an enable signal or a disable signal to the latter, wherein the enable signal is a signal to enable the timer 116 to work, and the disable signal is a signal to disable the timer 116 to work. The control unit 118 controls the start and end of the sensing process by controlling the enable or disable of the timer 116.

[0080] The final count value obtained in one sensing cycle or the final digital value obtained after filtering can be used to measure the capacitance value of the capacitive sensor 101 .

[0081] The following describes it in conjunction with specific embodiments.

[0082] Figure 3 Schematic diagram of the structure of a capacitive sensing device in the first embodiment of the present invention.

[0083] like Figure 3 As shown, the first predetermined voltage is a low level (grounded); in the charge balancing circuit 105, the first power supply and the second power supply are respectively a current source 201 ( Figure 3 ) and current source 202 ( Figure 3 The current source 201 is coupled to a predetermined voltage ( Figure 3 Marked as V DD1 ), the current source 202 is coupled to a predetermined voltage ( Figure 3 Marked as V DD2 ), the first control switch and the second control switch are switch 203 and switch 204 respectively.

[0084] When the capacitive sensing device 200 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group and alternately perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 charges the capacitive sensor 101.

[0085] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 203 is closed and the switch 204 is opened, so that the current source 201 charges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 203 is opened and the switch 204 is closed, so that the current source 202 charges the reference capacitor 103.

[0086] Figure 4 Schematic diagram of the structure of a capacitive sensing device in a second embodiment of the present invention.

[0087] like Figure 4 As shown, the first predetermined voltage is a high level (working voltage V DD ); In the charge balancing circuit 105, the first power source and the second power source are respectively a current source 301 and a current source 302, and the current source 301 ( Figure 4 ) and current source 302 ( Figure 4 Both are coupled to the ground, and the first control switch and the second control switch are switch 303 and switch 304 respectively.

[0088] When the capacitive sensing device 300 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group and alternately perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 discharges the capacitive sensor 101.

[0089] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 303 is closed and the switch 304 is opened, so that the current source 301 discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 303 is opened and the switch 304 is closed, so that the current source 302 discharges the reference capacitor 103.

[0090] Figure 3 and Figure 4 The first and second embodiments shown involve two current sources. In the first embodiment, the final count value C1 obtained in a sensing cycle is used to measure the capacitance value of the capacitive sensor 101, which can be calculated by the following formula (1), and the sensing sensitivity S1 can be calculated by the following formula (2); in the second embodiment, the final count value C2 obtained in a sensing cycle is used to measure the capacitance value of the capacitive sensor 101, which can be calculated by the following formula (3), and the sensing sensitivity S2 can be calculated by the following formula (4):

[0091]

[0092]

[0093]

[0094]

[0095] Where N is the number of bits of the timer 116, V REF is the voltage value of the reference voltage 111, F is the frequency of the switch group 102, C X The capacitance value to be sensed of the capacitive sensor 101 , I1 and I2 are the currents of the first power supply and the second power supply (they are both current sources in the first and second embodiments), and VDD is the operating voltage.

[0096] From formulas (1) and (3), it can be seen that the final count values ​​C1 and C2 are both related to the capacitance value to be sensed C X It can be seen from formulas (2) and (4) that the sensitivities S1 and S2 can be adjusted by adjusting parameters such as I1 and I2 respectively.

[0097] Compared with Patent Document 1, the first and second embodiments have at least four technical advantages.

[0098] First, the charging circuit in patent document 1 selectively charges and discharges the holding capacitor according to the output result of the comparator; in contrast, the first and second embodiments of the present invention only charge or discharge the reference capacitor 103 through the charge balancing circuit 105, which is beneficial to improve the sensing sensitivity.

[0099] Second, the switch coupled to the capacitive sensor in Patent Document 1 is controlled by the comparator output signal, which makes the formula for measuring the final count value of the capacitance value of the capacitive sensor complicated. In contrast, the switch group coupled to the capacitive sensor in the first and second embodiments of the present invention is not controlled by the comparator output signal, which makes the formula for measuring the final count value of the capacitance value of the capacitive sensor relatively simple, as shown in formulas (1) and (3).

[0100] Third, the improvement in sensitivity in Patent Document 1 is based on the increase in the measurement time period, which increases the power consumption of the sensing process; in contrast, in the first and second embodiments of the present invention, as shown in formulas (2) and (4), the number of bits of the timer does not need to be adjusted (i.e., the sensing period is not increased), but the sensitivity can be improved by flexibly adjusting the voltage value of the reference voltage, the frequency of the switch group, and the current value of the current source, while avoiding the increase in power consumption due to the increase in the sensing period.

[0101] Fourth, compared with patent document 1, under the condition of the same sensing period, in the first and second embodiments of the present invention, as shown in formulas (2) and (4), the sensitivity can be further improved by adjusting the currents I1 and I2 of the first power supply and the second power supply, so that smaller changes in the capacitance value of the capacitive sensor can be sensed.

[0102] In the first and second embodiments of the present invention, as shown in formulas (2) and (4), the current values ​​of the two current sources can be flexibly adjusted. Compared with only providing one current source for adjustment, the former not only has higher sensitivity, but also does not overflow.

[0103] Specifically, in the scheme of using a current source for adjustment, the capacitive sensing device only uses a current source to charge or discharge the reference capacitor, and the other circuit structures are the same as the first or second embodiment, so that scheme 1 and scheme 2 can be formed respectively. In scheme 1, the final count value C3 obtained in a sensing cycle can be calculated by the following formula (5), and the sensing sensitivity S3 can be calculated by the following formula (6); in scheme 2, the final count value C4 obtained in a sensing cycle can be calculated by the following formula (7), and the sensing sensitivity S4 can be calculated by the following formula (8):

[0104]

[0105]

[0106]

[0107]

[0108] Where N is the number of bits of the timer, V REF is the voltage value of the reference voltage, F is the frequency of the switch group, C X The capacitance value to be sensed of the capacitive sensor, I1 is the current of the current source.

[0109] Compared with solutions one and two, the first and second embodiments have at least two technical advantages.

[0110] First, for solutions 1 and 2, if the current I1 is adjusted to X, the calculated sensitivity S2 is A; for embodiments 1 and 2, the currents I1 and I2 are adjusted to X and 0.5X respectively, and the calculated sensitivity S1 is 2 A. It can be seen that in embodiments 1 and 2, the sensitivity is improved.

[0111] Second, for schemes one and two, if the output value accounts for 70% when the current I1 is X, when the current I1 is adjusted to 0.5X, the output value accounts for more than 1 (70%*2=140%), and an overflow occurs; for embodiments one and two, when the current I1 is X and I2 is 0.5X, the output value accounts for less than 1 (70%*2-1=40%), and no overflow occurs.

[0112] Figure 5 is a schematic structural diagram of a capacitive sensing device in a third embodiment of the present invention.

[0113] like Figure 5 As shown, the first predetermined voltage is a low level (grounded); in the charge balancing circuit 105, the first power supply and the second power supply are respectively a voltage source 401 ( Figure 5 Marked as V DD3 ) and voltage source 402 ( Figure 5 Marked as V DD4 ), the first control switch and the second control switch are switch 403 and switch 404 respectively.

[0114] In the third embodiment, the charge balancing circuit 105 may include a resistor 405 ( Figure 5 R1) and resistor 406 ( Figure 5 The voltage source 401 is coupled to the switch 403 via the resistor 405 , and the voltage source 402 is coupled to the switch 404 via the resistor 406 .

[0115] The sensing sensitivity may be adjusted by adjusting the resistance of the resistor 405 and / or the resistor 406 .

[0116] When the capacitive sensing device 400 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group and alternately perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 charges the capacitive sensor 101.

[0117] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 403 is closed and the switch 404 is opened, so that the voltage source 401 charges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 403 is opened and the switch 404 is closed, so that the voltage source 402 charges the reference capacitor 103.

[0118] Figure 6 4 is a schematic diagram of the structure of a capacitive sensing device in a fourth embodiment of the present invention.

[0119] like Figure 6 As shown, the first predetermined voltage is a high level (working voltage V DD ); In the charge balancing circuit 105, the first power source and the second power source are voltage sources (not shown) both coupled to ground, and the first control switch and the second control switch are switch 503 and switch 504 respectively.

[0120] In the fourth embodiment, the charge balancing circuit 105 may include a resistor 501 ( Figure 6 Marked as R3) and resistor 502 ( Figure 6 The voltage source is coupled to the switch 503 through the resistor 501 , and the voltage source is coupled to the switch 504 through the resistor 502 .

[0121] The sensing sensitivity may be adjusted by adjusting the resistance of the resistor 501 and / or the resistor 502 .

[0122] When the capacitive sensing device 500 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group and alternately perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 discharges the capacitive sensor 101.

[0123] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 503 is closed and the switch 504 is opened, so that the first power supply discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 303 is opened and the switch 304 is closed, so that the second power supply discharges the reference capacitor 103.

[0124] Figure 5 and Figure 6 The third and fourth embodiments shown involve two voltage sources. In the third embodiment, I1 and I2 in equations (1) and (2) are replaced by (V A -V REF ) / R A and (V B -V REF ) / R B And we get formulas (9) and (10), where V A and V B are the voltages of the two voltage sources, R A and R Bare resistors coupled to two voltage sources, respectively. The final count value C5 and sensitivity S5 obtained in one sensing cycle can be calculated based on formulas (9) and (10), respectively. In the fourth embodiment, I1 and I2 in formulas (3) and (4) are replaced by V REF / R A and V REF / R B Then we get formulas (11) and (12), where R A and R B are resistances coupled to ground respectively. The final count value C6 and sensitivity S6 obtained in one sensing cycle can be calculated based on formulas (11) and (12) respectively.

[0125] Similar to the first and second embodiments, the third and fourth embodiments have at least four technical advantages compared to Patent Document 1.

[0126] In the scheme of using one voltage source for regulation, the capacitive sensing device only uses one voltage source to charge or discharge the reference capacitor and the other circuit structures are the same as those of the third or fourth embodiment, thereby forming scheme three and scheme four respectively.

[0127] Similar to the first and second embodiments, the third and fourth embodiments have at least two technical advantages compared with solutions three and four, respectively.

[0128] Figure 7 is a schematic structural diagram of a capacitive sensing device in a fifth embodiment of the present invention.

[0129] like Figure 7 As shown, the first predetermined voltage is a low level (grounded); in the charge balancing circuit 105, the first power supply and the second power supply are respectively a voltage source 601 ( Figure 7 Marked as V DD5 ) and voltage source 602 ( Figure 7 Marked as V DD6 ), the first control switch includes an AND gate 603 and a switch 605, and the second control switch includes an AND gate 604 and a switch 606, wherein the switch 605 and the switch 606 are both switch groups consisting of two sub-switches, and the two sub-switches in the switch 605 and the two sub-switches in the switch 606 both operate in two-phase non-overlapping phases.

[0130] The first input terminal of AND gate 603 and the first input terminal of AND gate 604 are both coupled to the output terminal 110 of comparator 104, the second input terminal of AND gate 603 is coupled to the first clock signal (which is used to control the switching frequency of switch 605), and the second input terminal of AND gate 604 is coupled to the second clock signal (which is used to control the switching frequency of switch 606); switch 605 is coupled between the output terminal of AND gate 603 and the second terminal of reference capacitor 103, and switch 606 is coupled between the output terminal of AND gate 604 and the second terminal of reference capacitor 103.

[0131] In the fifth embodiment, the charge balancing circuit 105 may include a capacitor 607 ( Figure 7 Marked as C D1 ) and capacitor 608( Figure 7 Marked as C D2 ), the first end of capacitor 607 is coupled to the ground, and the second end is coupled to switch 605, so that the reference capacitor 103 can be selectively coupled by closing or opening the switch 605, and the first end of capacitor 608 is coupled to the ground, and the second end is coupled to switch 606, so that the reference capacitor 103 can be selectively coupled by closing or opening the switch 606.

[0132] When the capacitive sensing device 600 senses the capacitance value of the capacitive sensor 101, the capacitor 607 and the switch 605 form an equivalent resistor, and the capacitor 608 and the switch 606 form an equivalent resistor, thereby controllably charging the reference capacitor 103. The sensing sensitivity can be adjusted by adjusting the capacitance values ​​of the capacitors 607 and 608 and the switching frequencies of the switches 605 and 606.

[0133] When the capacitive sensing device 600 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 alternately provide output levels to respectively perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 charges the capacitive sensor 101.

[0134] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the AND gate 603 has an output and the AND gate 604 has no output, so that the voltage source 601 charges the capacitor 607 in the first phase, and the capacitor 607 charges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the AND gate 603 has no output and the AND gate 604 has an output, so that the voltage source 602 charges the capacitor 608 in the first phase, and the capacitor 608 charges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately.

[0135] Figure 8 Schematic diagram of the structure of a capacitive sensing device in a sixth embodiment of the present invention.

[0136] like Figure 8 As shown, the first predetermined voltage is a high level (working voltage V DD ); In the charge balancing circuit 105, the first power supply and the second power supply are voltage sources (not shown) both coupled to ground, the first control switch includes an AND gate 701 and a switch 703, and the second control switch includes an AND gate 702 and a switch 704, wherein the switch 703 and the switch 704 are both switch groups consisting of two sub-switches, and the two sub-switches in the switch 703 and the two sub-switches in the switch 704 both operate in two non-overlapping phases.

[0137] The first input terminal of the AND gate 701 and the first input terminal of the AND gate 702 are both coupled to the output terminal 110 of the comparator 104, the second input terminal of the AND gate 701 is coupled to the third clock signal (which is used to control the switching frequency of the switch 703), and the second input terminal of the AND gate 702 is coupled to the fourth clock signal (which is used to control the switching frequency of the switch 704); the switch 703 is coupled between the output terminal of the AND gate 701 and the second terminal of the reference capacitor 103, and the switch 704 is coupled between the output terminal of the AND gate 702 and the second terminal of the reference capacitor 103.

[0138] In the sixth embodiment, the charge balancing circuit 105 may include a capacitor 705 ( Figure 8 Marked as C D3 ) and capacitor 706( Figure 8 Marked as C D4 ), the first end of capacitor 705 is coupled to the ground, and the second end is coupled to switch 703, so that the reference capacitor 103 can be selectively coupled by closing or opening the switch 703, and the first end of capacitor 706 is coupled to the ground, and the second end is coupled to switch 704, so that the reference capacitor 103 can be selectively coupled by closing or opening the switch 704.

[0139] When the capacitive sensing device 700 senses the capacitance value of the capacitive sensor 101, the capacitor 705 and the switch 703 form an equivalent resistor, and the capacitor 706 and the switch 704 form an equivalent resistor, thereby controllably discharging the reference capacitor 103. The sensing sensitivity can be adjusted by adjusting the capacitance values ​​of the capacitors 705 and 706 and the switching frequencies of the switches 703 and 704.

[0140] When the capacitive sensing device 700 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 alternately provide output levels to respectively perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 discharges the capacitive sensor 101.

[0141] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the AND gate 701 has an output and the AND gate 702 has no output, so that the ground discharges the capacitor 705 in the first phase, and the capacitor 705 discharges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the AND gate 701 has no output and the AND gate 702 has an output, so that the ground discharges the capacitor 706 in the first phase, and the capacitor 706 discharges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately.

[0142] Figure 7 and Figure 8 The fifth and sixth embodiments shown involve two voltage sources. In the fifth embodiment, R in equations (9) and (10) is replaced by A and R B Replace with 1 / F respectively A C A and 1 / F B C B Then we get formulas (13) and (14), where F A and F B are the frequencies of the two switch groups coupled to the two voltage sources, C A and C B are the capacitance values ​​coupled to the two switch groups, respectively. The final count value C7 and sensitivity S7 obtained in one sensing cycle can be calculated based on formulas (13) and (14), respectively. In the sixth embodiment, R in formulas (11) and (12) is replaced by A and R B Replace with 1 / F respectively A CA and 1 / F B C B Then we get formulas (15) and (16), where F A and F B are the frequencies of the two switch groups coupled to the two voltage sources, C A and C B are the capacitance values ​​coupled to the two switch groups respectively. The final count value C8 and sensitivity S8 obtained in one sensing cycle can be calculated based on formulas (15) and (16) respectively.

[0143] Similar to the first and second embodiments, the fifth and sixth embodiments have at least four technical advantages compared to Patent Document 1.

[0144] In the scheme of using one voltage source for regulation, the capacitive sensing device only uses one voltage source to charge or discharge the reference capacitor and the other circuit structures are the same as those of the fifth or sixth embodiment, thereby forming scheme five and scheme six respectively.

[0145] Similar to the first and second embodiments, the fifth and sixth embodiments have at least two technical advantages compared with solutions five and six.

[0146] Fig. 9 is a schematic structural diagram of a capacitive sensing device in a seventh embodiment of the present invention.

[0147] like Fig. 9 As shown, the first predetermined voltage is a low level (grounded); in the charge balancing circuit 105, the first power supply and the second power supply are respectively a current source 801 ( Fig. 9 ) and voltage source 802 ( Fig. 9 Marked as V DD8 ), the current source 801 is coupled to a predetermined voltage ( Fig. 9 Marked as V DD7 ), the first control switch and the second control switch are switch 803 and switch 804 respectively.

[0148] In the seventh embodiment, the charge balancing circuit 105 may include a resistor 805 ( Fig. 9 The voltage source 802 is coupled to the switch 804 via the resistor 805 ).

[0149] The sensing sensitivity can be adjusted by adjusting the resistance of the resistor 805 and the current of the current source 801 .

[0150] When the capacitive sensing device 800 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group and alternately perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 charges the capacitive sensor 101.

[0151] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 803 is closed and the switch 804 is opened, so that the current source 801 charges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 803 is opened and the switch 804 is closed, so that the voltage source 802 charges the reference capacitor 103.

[0152] Fig.10 Schematic diagram of the structure of a capacitive sensing device in an eighth embodiment of the present invention.

[0153] like Fig.10 As shown, the first predetermined voltage is a high level (working voltage V DD ); In the charge balancing circuit 105, the first power source and the second power source are both ground-coupled current sources 901 ( Fig.10 The first control switch is switch 903 and the second control switch is switch 904, respectively.

[0154] In the eighth embodiment, the charge balancing circuit 105 may include a resistor 902 ( Fig.10 The voltage source is coupled to the switch 904 via the resistor 902 ).

[0155] The sensing sensitivity can be adjusted by adjusting the resistance of the resistor 902 and the current of the current source 901 .

[0156] When the capacitive sensing device 900 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group and alternately perform a first operation and a second operation, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitor 103. When the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitor 103 discharges the capacitive sensor 101.

[0157] When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 903 is closed and the switch 904 is opened, so that the current source discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 903 is opened and the switch 904 is closed, so that the voltage source discharges the reference capacitor 103.

[0158] Fig. 9 and Fig.10 The seventh and eighth embodiments shown involve a current source and a voltage source. In the seventh embodiment, I2 in equations (1) and (2) is replaced by (V C -V REF ) / R C And we get formulas (17) and (18), where V C is the voltage of the voltage source, R C is a resistor coupled to a voltage source, and the final count value C9 and sensitivity S9 obtained in one sensing cycle can be calculated based on formulas (17) and (18), respectively. In the eighth embodiment, I2 in formulas (3) and (4) is replaced by V REF / R C Then we get formulas (19) and (20), where R C is a resistor coupled to ground. The final count value C10 and sensitivity S10 obtained in one sensing cycle can be calculated based on formulas (19) and (20), respectively.

[0159] Similar to the first and second embodiments, the seventh and eighth embodiments have at least four technical advantages compared to Patent Document 1.

[0160] In the scheme with only one voltage source or one current source for adjustment, the capacitive sensing device only uses one voltage source or one current source to charge or discharge the reference capacitor and the other circuit structures are the same as the seventh or eighth embodiment, thereby forming scheme seven and scheme eight respectively.

[0161] Similar to the first and second embodiments, the seventh and eighth embodiments have at least two technical advantages compared with solutions seven and eight, respectively.

[0162] Fig.11 1 is a flow chart of a method for sensing capacitance according to an embodiment of the present invention. The method 1000 comprises the following steps:

[0163] Step S1010: alternately coupling the capacitive sensor to a first predetermined voltage and a reference capacitor;

[0164] Step S1020: Compare the voltage of the reference capacitor with the reference voltage and output a first logic level or a second logic level;

[0165] Step S1030: enabling the counter to count based on the first logic level or the second logic level to obtain a count value and charging or discharging the reference capacitor.

[0166] During the execution of step S1010 , as described above, the first operation and the second operation may be alternately performed by the switch group 102 , so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage 107 and the reference capacitor 103 .

[0167] During the execution of step S1020, as described above, the voltage of the reference capacitor 103 may be compared with the reference voltage 111 by the comparator 104. For example, when the voltage value of the reference capacitor 103 is lower than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a first logic level; when the voltage value of the reference capacitor 103 is higher than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a second logic level; wherein the first logic level is a high level and the second logic level is a low level, or the first logic level is a low level and the second logic level is a high level.

[0168] In step S1030, as described above, the reference capacitor 103 may be charged or discharged by the charge balancing circuit 105 to maintain the voltage of the reference capacitor 103 near the reference voltage 111. For example, the voltage of the reference capacitor 103 is maintained between 70% and 130% of the voltage of the reference voltage 111.

[0169] In a specific implementation, steps S1010 , S1020 and S1030 are cyclically executed within a sensing period determined by a timer, and a final count value is obtained.

[0170] In a specific implementation, the first predetermined voltage is a low level, and step S1010 includes charging the capacitive sensor through the reference capacitor to adjust the voltage of the reference capacitor.

[0171] In a specific implementation, the capacitive sensor is charged by a reference capacitor and a charge balancing circuit is used to charge the reference capacitor to adjust the voltage of the reference capacitor.

[0172] In a specific implementation, the charge balancing circuit includes a first power supply and a second power supply, and the first power supply and the second power supply charge the reference capacitor alternately based on a first logic level and a second logic level, respectively.

[0173] In a specific implementation, the first predetermined voltage is a high level, and step S1010 includes charging the reference capacitor through the capacitive sensor to adjust the voltage of the reference capacitor.

[0174] In a specific implementation, the voltage of the reference capacitor is adjusted by charging the reference capacitor through the capacitive sensor and discharging the reference capacitor through the charge balancing circuit.

[0175] In a specific implementation, the charge balancing circuit includes a first power supply and a second power supply, and the first power supply and the second power supply discharge the reference capacitor alternately based on a first logic level and a second logic level, respectively.

[0176] For the specific principles and implementations of the method 1000 for sensing capacitance, please refer to the above-mentioned Figures 1 to 10 The relevant description about the capacitive sensing device will not be repeated here.

[0177] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A capacitive sensing device, characterized in that: include: A capacitive sensor adapted to sense a conductive object in proximity thereto; a switch group adapted to alternately couple the capacitive sensor to a first predetermined voltage and a reference capacitance; the reference capacitor being adapted to share charge with the capacitive sensor when sensing the conductive object; A comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the reference capacitor, the second input terminal is coupled to a reference voltage, and the output terminal is coupled to a charge balancing circuit and a counter; The charge balancing circuit is coupled to the reference capacitor and is suitable for charging or discharging the reference capacitor when sensing the conductive object; the charge balancing circuit comprises a first power supply, a second power supply, a first control switch and a second control switch, the first power supply and the second power supply are coupled to the reference capacitor through the first control switch and the second control switch respectively; when the first predetermined voltage is at a low level, the first power supply and the second power supply are respectively coupled to a high level to charge the reference capacitor alternately, and when the first predetermined voltage is at a high level, the first power supply and the second power supply are both coupled to a low level to discharge the reference capacitor alternately; The counter is adapted to count and obtain a count value based on the first logic level or the second logic level output by the comparator.

2. The capacitive sensing device according to claim 1, characterized in that The first end of the capacitive sensor is grounded, the first end of the reference capacitor is grounded, and the switch group includes a first switch and a second switch, wherein the first switch is coupled between the second end of the capacitive sensor and the first predetermined voltage, and the second switch is coupled between the second end of the capacitive sensor and the second end of the reference capacitor.

3. The capacitive sensing device according to claim 1, characterized in that: Either the first logic level and the second logic level is a high level or a low level.

4. The capacitive sensing device according to claim 1, characterized in that: The charge balancing circuit is adapted to charge or discharge the reference capacitor to maintain a voltage of the reference capacitor close to the reference voltage.

5. The capacitive sensing device according to claim 1, characterized in that: The first power source and the second power source are respectively a first current source and a second current source.

6. The capacitive sensing device according to claim 1, characterized in that: The first power source and the second power source are respectively a first voltage source and a second voltage source.

7. The capacitive sensing device according to claim 6, characterized in that: The charge balancing circuit further includes a first resistor and a second resistor. The first voltage source is coupled to the first control switch via the first resistor, and the second voltage source is coupled to the second control switch via the second resistor.

8. The capacitive sensing device according to claim 6, characterized in that: The first control switch includes a first AND gate and a third switch, the second control switch includes a second AND gate and a fourth switch, the first input terminal of the first AND gate and the first input terminal of the second AND gate are both coupled to the output terminal of the comparator, the second input terminal of the first AND gate and the second input terminal of the second AND gate are both coupled to a clock signal, the third switch is coupled between the output terminal of the first AND gate and the second terminal of the reference capacitor, and the fourth switch is coupled between the output terminal of the second AND gate and the second terminal of the reference capacitor.

9. The capacitive sensing device according to claim 8, characterized in that: The charge balancing circuit further includes a first capacitor and a second capacitor. The first end of the first capacitor is coupled to the third switch and the second end is coupled to the ground. The first end of the second capacitor is coupled to the fourth switch and the second end is coupled to the ground.

10. The capacitive sensing device according to claim 1, characterized in that: The first power source and the second power source are respectively a third current source and a third voltage source.

11. The capacitive sensing device according to claim 10, characterized in that: The charge balancing circuit further includes a third resistor, and the third voltage source is coupled to the second control switch through the third resistor.

12. The capacitive sensing device according to any one of claims 1 to 11, characterized in that: A timing unit is included, and the output end of the comparator is respectively coupled to a charge balancing circuit and a counter through the timing unit.

13. The capacitive sensing device according to any one of claims 1 to 11, characterized in that: A timer is included, which is coupled to the counter and is suitable for determining a sensing period and outputting a timing signal to the counter. The counter is suitable for counting within the sensing period to obtain a final count value based on the first logic level or the second logic level and the timing signal.

14. The capacitive sensing device according to claim 13, characterized in that A control unit is included, which is coupled to the timer and is suitable for outputting an enable signal or a disable signal to the timer and receiving the timing signal.

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