Oscillator calibration method, module, chip and electronic device

Abstract

The embodiment of the present application provides an oscillator calibration method, including: counting a third clock signal of an external device to obtain a first count value, counting a scan signal of the oscillation module to obtain a second count value, so as to obtain a first cycle ratio; comparing the first cycle ratio with a pre-stored reference cycle ratio, and confirming whether the first clock signal has a frequency deviation according to the comparison result; and if the first clock signal has a frequency deviation, adjusting the frequency division coefficient of the oscillation module so that the oscillation module divides the first clock signal according to the adjusted frequency division coefficient, thereby obtaining a calibrated second clock signal. The embodiment of the present application also provides a calibration module, a chip, and an electronic device. In this way, the oscillator calibration method, module, chip, and electronic device provided in the embodiment of the present application can accurately calibrate the clock signal frequency of the oscillation module.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an oscillator calibration method, module, chip and electronic device. Background Art

[0002] With the rapid development of the consumer electronics industry, the application of oscillator clock (OSC) signals has become more and more widespread. The oscillation clock signal is generated by an oscillator and can be used for oscillation module timing, counting, signal synchronization, etc., thereby controlling the orderly and stable operation between system units, enabling all signals within the system to be input and output synchronously to ensure accurate information.

[0003] However, in the actual production process, the stability of the oscillator is easily affected by the process environment. The main influencing factors include temperature, humidity, crystal doping, power supply voltage stability, ionization degree, etc. The combined effect of many factors leads to different specifications of the oscillators produced, and the OSC clock frequency has obvious deviations (frequency deviation). In actual application scenarios, OSC oscillation modules with built-in frequency deviation problems will have serious problems such as unstable operation, failure of synchronization between devices, and errors in oscillation module calculations. Summary of the invention

[0004] In view of the above problems, it is necessary to provide an oscillator calibration method, module, chip and electronic device to accurately calibrate the clock signal frequency of the crystal oscillator.

[0005] According to a first aspect of an embodiment of the present application, there is provided an oscillator calibration method for calibrating a first clock signal output by an oscillation module including a crystal oscillator to obtain a calibrated second clock signal. The oscillator calibration method includes:

[0006] Counting a third clock signal of the external device to obtain a first count value, and counting a scan signal of the oscillation module to obtain a second count value, so as to obtain a first cycle ratio, wherein the first cycle ratio is a ratio of the first count value to the second count value;

[0007] comparing the first cycle ratio with a pre-stored reference cycle ratio, and determining whether the first clock signal has a frequency deviation according to the comparison result; and

[0008] If the first clock signal has a frequency deviation, the frequency division coefficient of the oscillation module is adjusted so that the oscillation module divides the frequency of the first clock signal according to the adjusted frequency division coefficient, thereby obtaining the calibrated second clock signal.

[0009] In a possible implementation manner, counting the third clock signal of the external device includes:

[0010] Counting is performed within M cycles of the third clock signal at the frequency of the fourth clock signal.

[0011] In a possible implementation manner, counting the scanning signal of the oscillation module includes:

[0012] Counting is performed within N periods of the scanning signal of the oscillation module at the frequency of the fourth clock signal.

[0013] In a possible implementation, adjusting the frequency division coefficient of the oscillation module includes: after detecting that the first clock signal has a frequency deviation, adjusting the frequency division coefficient of the oscillation module to a product of a ratio of a first period ratio to a reference period ratio and an original frequency division coefficient.

[0014] A second aspect of an embodiment of the present application provides a calibration module for calibrating a first clock signal output by an oscillation module including a crystal oscillator, the calibration module comprising:

[0015] an acquisition unit, configured to count a third clock signal of an external device to obtain a first count value, and count a scan signal of the oscillation module to obtain a second count value, so as to obtain a first cycle ratio, wherein the first cycle ratio is a ratio of the first count value to the second count value;

[0016] a comparing unit, configured to compare the first cycle ratio with a reference cycle ratio, and determine whether the first clock signal has a frequency deviation according to the comparison result; and

[0017] The calibration unit is used to adjust the frequency division coefficient of the oscillation module when the first clock signal has a frequency deviation, so that the oscillation module divides the first clock signal according to the adjusted frequency division coefficient, thereby obtaining the calibrated second clock signal.

[0018] In a possible implementation manner, counting the third clock signal of the external device includes: the acquisition unit counting within M cycles of the third clock signal at a frequency of a fourth clock signal.

[0019] In a possible implementation manner, counting the scanning signal of the oscillation module includes: the acquisition unit counting within N periods of the scanning signal of the oscillation module at a frequency of a fourth clock signal.

[0020] In a possible implementation manner, adjusting the frequency division coefficient of the oscillation module includes: adjusting the frequency division coefficient of the oscillation module to a product of a ratio of a first period ratio to a reference period ratio and an original frequency division coefficient.

[0021] A third aspect of an embodiment of the present application provides a chip, wherein the chip integrates at least two sub-chips, wherein one sub-chip integrates an oscillation module, and the other sub-chip integrates a calibration module as described in any one of the above items.

[0022] A fourth aspect of an embodiment of the present application provides an electronic device, including:

[0023] Memory for storing computer programs;

[0024] A processor is used to execute the computer program stored in the memory. When the computer program is executed, the processor is used to execute any one of the oscillator calibration methods described above.

[0025] Therefore, the oscillator calibration method, module, chip and electronic device provided in the embodiments of the present application can accurately calibrate the clock signal frequency of the oscillation module. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 An application scenario diagram of a calibration module provided for one embodiment of the present application.

[0027] Figure 2 A functional block diagram of a calibration module provided for one embodiment of the present application.

[0028] Figure 3 A flowchart of an oscillator calibration method provided by one embodiment of the present application.

[0029] Figure 4 A schematic diagram of the structure of an electronic device provided for one embodiment of the present application.

[0030] Main component symbols

[0031] Calibration module 100

[0032] Oscillator module 200

[0033] External device 300

[0034] Electronic equipment 400

[0035] Acquisition unit 101

[0036] Comparison unit 103

[0037] Calibration unit 105

[0038] Oscillator 201

[0039] Divider 202

[0040] Scanner 203

[0041] Memory 401

[0042] Processor 402

[0043] Communication Bus 403

[0044] Communication interface 404

[0045] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0046] In the embodiments of the present application, the words "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. For example, the first application, the second application, etc. are used to distinguish different applications, rather than to describe a specific order of applications. The features defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0047] See also Figure 1 , Figure 1 FIG. 1 is a diagram showing an application scenario of a calibration module 100 provided in one embodiment of the present application. Figure 1 As shown, the calibration module 100 is connected to the oscillation module 200 and the external device 300, and is used to calibrate the clock signal frequency of the oscillation module 200 according to the clock signal of the external device 300. The oscillation module 200 is connected to the external device 300, and is used to obtain the clock signal frequency of the external device 300.

[0048] In some embodiments, the oscillation module 200 can be arranged in an electronic device including a touch panel (TouchPad, TP), and the oscillation module 200 can be an analog front end (AFE) module, which includes an oscillator, a frequency divider, a scanner, etc. Among them, the oscillator is an electronic component that converts direct current power into alternating current with a certain frequency. Optionally, the oscillator is a crystal oscillator, which is used to provide a stable first clock signal for the oscillation module 200, and the frequency ratio of the first clock signal to the clock signal of the calibration module 100 is fixed under normal circumstances. The frequency divider is used to divide the first clock signal according to the frequency division coefficient, and output a second clock signal of different frequencies for use by other units such as a scanner. Specifically, the second clock signal frequency F2 = F1 / x, where F1 is the first clock signal output by the oscillator, x is the frequency division coefficient, and the frequency division coefficient can be specified by the frequency divider. For example, if the frequency of the first clock signal is 72MHz and the operating frequency of the scanner is 360kHz, the frequency divider can define a frequency division factor of 200, and the frequency divider divides the 72MHz first clock signal into a 360kHz second clock signal and outputs it to the scanner. The scanner is used to scan the touch panel of the electronic device, and the frequency of the scanning signal is the same as the frequency of the second clock signal.

[0049] In some embodiments, the frequency of the first clock signal may change or drift due to differences in oscillator aging, manufacturing process, etc., as well as the temperature, humidity, crystal doping inside it, power supply voltage stability, ionization degree, etc., thereby deviating from the set natural frequency and causing frequency deviation. It can be understood that when the frequency of the first clock signal changes, if the frequency division coefficient remains unchanged, the frequency of the clock signal output by the divider will also deviate, resulting in other units that receive the deviated frequency may not work properly. Therefore, it is necessary to detect and calibrate the frequency of the first clock signal output by the oscillator.

[0050] In some embodiments, the external device 300 generates a third clock signal for reference by the calibration module 100. It can be understood that if the first clock signal has no frequency deviation, its frequency and the frequency of the third clock signal can be relatively fixed, and the frequency of the second clock signal after frequency division is relatively stable, and the calibration module 100 does not need to perform calibration, and each unit can work normally. If the calibration module 100 detects that the frequency of the second clock signal has a frequency deviation, the oscillator in the oscillation module 200 can be calibrated according to the second clock signal and the third clock signal.

[0051] See also Figure 2 , Figure 2 FIG. 1 is a functional block diagram of a calibration module 100 provided in one embodiment of the present application.

[0052] In this embodiment, the calibration module 100 may include a plurality of functional units composed of program code segments. The program code of each program segment in the calibration module 100 may be stored in a memory and executed by at least one processor to perform a data processing function.

[0053] In this embodiment, the calibration module 100 can be divided into a plurality of functional units according to the functions it performs. The functional units can include: an acquisition unit 101, a comparison unit 103, and a calibration unit 105. The calibration module 100 is connected to an oscillation module 200, and the oscillation module 200 includes an oscillator 201, a frequency divider 202, and a scanner 203.

[0054] The acquisition unit 101 is used to acquire a first cycle ratio.

[0055] In this embodiment, the first cycle ratio Y1 is the ratio of N cycles of the third clock signal generated by the external device 300 to M cycles of the scanning signal of the scanner 203 in the oscillation module 200. Wherein, M and N are both positive integers. Specifically, the acquisition unit 101 can acquire the third clock signal from the external device 300, and count the third clock signal at the frequency of the fourth clock signal provided by the clock source (not shown in the figure) inside the calibration module 100 within N cycles of the third clock signal to obtain a first count value COUNT1, and at the same time count the scanning signal of the scanner 203 at the frequency of the fourth clock signal within M cycles of the scanning signal of the scanner 203 to obtain a second count value COUNT2. It can be understood that the first cycle ratio Y1 satisfies the following formula:

[0056]

[0057] The comparison unit 103 is used to compare the first cycle ratio with a reference cycle ratio, and determine whether the second clock signal has a frequency deviation according to the comparison result, and further determine whether the first clock signal has a frequency deviation.

[0058] In this embodiment, the reference cycle ratio is the ratio of N (N is a positive integer) cycles of the third clock signal generated by the external device 300 to M (M is a positive integer) cycles of the scanning signal of the scanner 203 in the oscillation module 200 when the second clock signal does not have a frequency deviation. It can be understood that the reference cycle ratio YS satisfies the following formula:

[0059]

[0060] Among them, COUNT3 is the third count value obtained by the calibration module 100 counting the third clock signal at the frequency of the fourth clock signal provided by the clock source inside the calibration module 100 (not shown in the figure) within N cycles of the third clock signal, and COUNT4 is the fourth count value obtained by the calibration module 100 counting the scanning signal of the scanner 203 at the frequency of the fourth clock signal within M cycles of the scanning signal of the scanner 203.

[0061] In some embodiments, when the second clock signal has no frequency deviation, the calibration module 100 may perform a large number of sampling counts on the third clock signal and the scanning signal, and obtain the reference cycle ratio after averaging or other operations.

[0062] The comparison unit 103 can determine whether the second clock signal has a frequency deviation by comparing the first cycle ratio with the reference cycle ratio. Specifically, if the frequency of the third clock signal has not changed, and if the first cycle ratio is not equal to the reference cycle ratio, it can be understood that at this time, the scanning signal has a frequency deviation, and the second clock signal also has a frequency deviation. Since the frequency division coefficient has not changed, it can be deduced that the first clock signal has a frequency deviation. Otherwise, the first clock signal has no frequency deviation.

[0063] If the value of the reference period ratio is greater than the value of the first period ratio, it can be understood that the period of the scanning signal becomes smaller and its frequency becomes larger, which means that the first clock signal has a frequency deviation and the frequency deviation is large.

[0064] If the value of the reference period ratio is smaller than the value of the first period ratio, it can be understood that the period of the scanning signal becomes longer and its frequency becomes smaller, which means that the first clock signal has a frequency deviation and the frequency is small.

[0065] The calibration unit 105 is used to calculate a new frequency division coefficient when the first clock signal has a frequency deviation, and adjust the frequency division coefficient of the oscillation module according to the new frequency division coefficient.

[0066] In this embodiment, if the first clock signal has a frequency deviation, the calibration unit 105 can adjust the frequency division coefficient of the oscillation module. Specifically, according to formula (1) and formula (2), the ratio of the reference period ratio YS to the first period ratio Y1 satisfies the following formula:

[0067]

[0068] It can be understood that since the period and frequency of the signal are reciprocals of each other, assuming that the frequency of the calibrated first clock signal is F1, the frequency of the calibrated second clock signal is F2, the frequency of the third clock signal is F3, the frequency of the fourth clock signal is F4, and the frequency of the uncalibrated second clock signal is F, the following formula can be derived:

[0069]

[0070]

[0071] According to formula (4) and formula (5), the following formula can be derived:

[0072]

[0073] According to formula (6), it can be understood that F satisfies the following formula:

[0074]

[0075] It can be understood that at this time, the uncalibrated first clock signal frequency F5 satisfies the following formula:

[0076] F5=x×F (8)

[0077] According to formula (8), the processing unit 104 can obtain a new frequency division coefficient y, where y satisfies the following formula:

[0078]

[0079] Combining formula (7) and formula (8), we can know that

[0080] In this embodiment, if a frequency deviation of the second clock signal is detected, the calibration unit 105 specifies a new frequency division coefficient y to the frequency divider 202 of the oscillation module 200. The frequency divider 202 can re-divide the first clock signal according to the new frequency division coefficient y and calibrate the second clock signal to ensure that the scanner 203 operates normally.

[0081] In this way, the calibration module 100 provided in an embodiment of the present application can determine whether the second clock signal frequency has a frequency deviation by comparing the first cycle ratio and the reference cycle ratio, thereby accurately calibrating the second clock signal frequency of the oscillation module by calculating a new division coefficient.

[0082] See also Figure 3 , Figure 3 FIG. 1 is an oscillator calibration method provided by an embodiment of the present application. Figure 3 As shown, the oscillator is applied to the calibration module 100, and the calibration method includes the following steps:

[0083] Step S1: Obtain a first cycle ratio.

[0084] In this embodiment, the first cycle ratio Y1 is the ratio of N cycles of the third clock signal generated by the external device 300 to M cycles of the scanning signal of the scanner 203 in the oscillation module 200. Wherein, M and N are both positive integers. Specifically, the calibration module 100 can obtain the third clock signal from the external device 300, and count the third clock signal at the frequency of the fourth clock signal provided by the clock source (not shown) inside the calibration module 100 within N cycles of the third clock signal to obtain a first count value COUNT1, and at the same time count the scanning signal of the scanner 203 at the frequency of the fourth clock signal within M cycles of the scanning signal of the scanner 203 to obtain a second count value COUNT2. It can be understood that the first cycle ratio Y1 satisfies formula (1).

[0085] Step S2: Compare the first cycle ratio with a reference cycle ratio, and determine whether the first and second clock signals have frequency deviation according to the comparison result.

[0086] In this embodiment, the reference cycle ratio is the ratio of N (N is a positive integer) cycles of the third clock signal generated by the external device 300 to M (M is a positive integer) cycles of the scanning signal of the scanner 203 in the oscillation module 200 when the second clock signal does not have a frequency deviation. It can be understood that the reference cycle ratio YS satisfies formula (2).

[0087] Among them, COUNT3 is the third count value obtained by the calibration module 100 counting the third clock signal at the frequency of the fourth clock signal provided by the clock source inside the calibration module 100 (not shown in the figure) within N cycles of the third clock signal, and COUNT4 is the fourth count value obtained by the calibration module 100 counting the scanning signal of the scanner 203 at the frequency of the fourth clock signal within M cycles of the scanning signal of the scanner 203.

[0088] In some embodiments, when there is no frequency deviation in the first and second clock signals, the calibration module 100 may perform a large number of sampling counts on the third clock signal and the scanning signal, and obtain a reference cycle ratio after averaging or other operations.

[0089] The calibration module 100 can determine whether the first clock signal has a frequency deviation by comparing the first cycle ratio with the reference cycle ratio. Specifically, if the frequency of the third clock signal has not changed, and if the first cycle ratio is not equal to the reference cycle ratio, it can be understood that at this time, the scanning signal has a frequency deviation, and the second clock signal also has a frequency deviation. Since the frequency division coefficient has not changed, it can be deduced that the first clock signal has a frequency deviation. Otherwise, the first clock signal has no frequency deviation, and step S4 is executed.

[0090] If the value of the reference period ratio is greater than the value of the first period ratio, it can be understood that the period of the scanning signal becomes smaller and its frequency becomes larger, which means that the first clock signal has a frequency deviation and the frequency deviation is large.

[0091] If the value of the reference period ratio is smaller than the value of the first period ratio, it can be understood that the period of the scanning signal becomes longer and its frequency becomes smaller, which means that the first clock signal has a frequency deviation and the frequency is small.

[0092] Step S3: adjusting the frequency division coefficient of the oscillation module.

[0093] In this embodiment, if the first clock signal has a frequency deviation, the calibration module 100 can calculate the frequency deviation range of the first clock signal according to the first cycle ratio and the reference cycle ratio, and calculate a new frequency division coefficient y according to the frequency deviation range. Specifically, according to formula (1) to formula (9), it can be obtained that:

[0094] In this embodiment, the calibration module 100 may specify a new frequency division coefficient y to the frequency divider 202 of the oscillation module 200 , and the frequency divider 202 may re-divide the frequency of the first clock signal according to the new frequency division coefficient y.

[0095] Step S4: Scanning according to the calibrated second clock signal.

[0096] In this embodiment, after the frequency divider 202 divides the first clock signal into a calibrated second clock signal using the frequency division coefficient y, the scanner 203 uses the calibrated second clock signal frequency as its operating frequency to scan the touch panel.

[0097] By using the calibration module and oscillator calibration method provided in the embodiments of the present application, it is possible to determine whether the frequency of the oscillator clock signal has a frequency deviation by comparing the first period ratio with the second period ratio, thereby accurately calibrating the clock signal frequency of the oscillation module by calculating a new division coefficient.

[0098] An embodiment of the present application also provides a chip, which integrates at least a first sub-chip and a second sub-chip, wherein the first sub-chip may include an oscillation module 200, and the second sub-chip may include a calibration module 100. It can be understood that the calibration module 100 in the second sub-chip can calibrate the first clock signal output by the crystal oscillator of the oscillation module 200 in the first sub-chip according to the above-mentioned oscillator calibration method to obtain a calibrated second clock signal.

[0099] In some embodiments, the first sub-chip may be an AFE chip, and the second sub-chip may be an MCU chip.

[0100] See also Figure 4 , Figure 4Shown is an electronic device 400 provided by one embodiment of the present application.

[0101] In a preferred embodiment of the present application, the electronic device 400 includes a memory 401 , at least one processor 402 , at least one communication bus 403 and a communication interface 404 .

[0102] Those skilled in the art should understand that Figure 4 The structure of the electronic device 400 shown does not constitute a limitation of the embodiments of the present application, and can be either a bus structure or a star structure. The electronic device 400 can also include more or less other hardware or software than shown in the figure, or a different component arrangement.

[0103] In some embodiments, the electronic device 400 is an electronic device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application-specific integrated circuits, programmable gate arrays, digital processors, and embedded devices. The electronic device 400 may also include client devices, which include but are not limited to any electronic product that can interact with a client through a keyboard, mouse, remote control, touchpad, or voice-controlled device, such as a personal computer, tablet computer, smart phone, digital camera, etc.

[0104] It should be noted that the electronic device 400 is only an example, and other existing or future electronic products that are suitable for the present application should also be included in the protection scope of the present application and included here by reference.

[0105] In some embodiments, the memory 401 is used to store program codes and various data, and to achieve high-speed and automatic access to programs or data during the operation of the electronic device 400. The memory 401 includes a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0106] In some embodiments, the at least one processor 402 may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The at least one processor 402 is the control core (Control Unit) of the electronic device 400, and uses various interfaces and lines to connect various components of the entire electronic device 400, and executes various functions of the electronic device 400 and processes data by running or executing programs or units stored in the memory 401, and calling data stored in the memory 401.

[0107] In some embodiments, the at least one communication bus 403 is configured to implement connection and communication between the memory 401 and the at least one processor 402, etc.

[0108] In some embodiments, the communication interface 404 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

[0109] Although not shown, the electronic device 400 may also include a power source (such as a battery) for supplying power to various components. Optionally, the power source may be logically connected to the at least one processor 402 through a power management device, so that the power management device can manage charging, discharging, and power consumption management. The power source may also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 400 may also include a variety of sensors, Bluetooth units, etc., which will not be described in detail here.

[0110] It should be understood that the embodiment is for illustration only and the scope of the patent application is not limited by this structure.

[0111] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, electronic device, or network device, etc.) or a processor to execute part of the method described in each embodiment of the present application.

[0112] In a further embodiment, in combination Figure 2 The at least one processor 402 can execute the operating device of the electronic device 400 and various installed application programs (such as the calibration module 100), program codes, etc., for example, the above-mentioned various units.

[0113] The memory 401 stores program codes, and the at least one processor 402 can call the program codes stored in the memory 401 to execute related functions. For example, Figure 2 The various units described in the embodiment are program codes stored in the memory 401 and are executed by the at least one processor 402, thereby realizing the functions of the various units to achieve the purpose of oscillator calibration.

[0114] In one embodiment of the present application, the memory 401 stores a plurality of instructions, and the plurality of instructions are executed by the at least one processor 402 to implement the function of oscillator calibration.

[0115] Specifically, the specific implementation method of the at least one processor 402 for the above instructions can refer to Figure 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation.

[0117] Furthermore, the computer-readable storage medium may be non-volatile or volatile.

[0118] Furthermore, the computer-readable storage medium mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function, etc.; the data storage area can store data created according to the use of the blockchain node, etc.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0121] Those skilled in the art should recognize that the above embodiments are only used to illustrate the present application and are not intended to be limiting of the present application. As long as they are within the spirit and scope of the present application, appropriate changes and modifications to the above embodiments are within the scope of protection claimed in the present application.

Claims

1. An oscillator calibration method, for calibrating a first clock signal output by an oscillation module including a crystal oscillator to obtain a calibrated second clock signal, characterized in that: The oscillator calibration method comprises: Counting a third clock signal of the external device to obtain a first count value, and counting a scan signal of the oscillation module to obtain a second count value, so as to obtain a first cycle ratio, wherein the first cycle ratio is a ratio of the first count value to the second count value; comparing the first cycle ratio with a pre-stored reference cycle ratio, and determining whether the first clock signal has a frequency deviation according to the comparison result; and If the first clock signal has a frequency deviation, the frequency division coefficient of the oscillation module is adjusted to the product of the ratio of the first period ratio to the reference period ratio and the original frequency division coefficient, so that the oscillation module divides the first clock signal according to the adjusted frequency division coefficient, thereby obtaining the calibrated second clock signal; The reference cycle ratio is a ratio of N cycles of the third clock signal to M cycles of the scanning signal when the second clock signal has no frequency deviation.

2. The oscillator calibration method according to claim 1, characterized in that: The counting of the third clock signal of the external device comprises: Counting is performed within M cycles of the third clock signal at a frequency of a fourth clock signal; wherein the fourth clock signal is a clock signal output by a clock source inside the calibration module.

3. The oscillator calibration method according to claim 2, characterized in that: The counting of the scanning signal of the oscillation module comprises: Counting is performed within N periods of the scanning signal of the oscillation module at the frequency of the fourth clock signal.

4. A calibration module, for calibrating a first clock signal output by an oscillation module including a crystal oscillator, characterized in that: The calibration module comprises: an acquisition unit, configured to count a third clock signal of an external device to obtain a first count value, and count a scan signal of the oscillation module to obtain a second count value, so as to obtain a first cycle ratio, wherein the first cycle ratio is a ratio of the first count value to the second count value; a comparing unit, configured to compare the first cycle ratio with a reference cycle ratio, and determine whether the first clock signal has a frequency deviation according to the comparison result; and a calibration unit, configured to adjust the frequency division coefficient of the oscillation module to the product of the ratio of the first period ratio to the reference period ratio and the original frequency division coefficient when the first clock signal has a frequency deviation, so that the oscillation module divides the first clock signal according to the adjusted frequency division coefficient, thereby obtaining a calibrated second clock signal; The reference cycle ratio is a ratio of N cycles of the third clock signal to M cycles of the scanning signal when the second clock signal has no frequency deviation.

5. The calibration module according to claim 4, characterized in that: The counting of the third clock signal of the external device comprises: the acquiring unit counting within M cycles of the third clock signal at the frequency of the fourth clock signal; The fourth clock signal is a clock signal output by an internal clock source of the calibration module.

6. The calibration module according to claim 4, characterized in that: The counting of the scanning signal of the oscillation module comprises: the acquisition unit counting within N periods of the scanning signal of the oscillation module at the frequency of the fourth clock signal.

7. A chip, characterized in that: The chip integrates at least two sub-chips, wherein one sub-chip integrates an oscillation module, and the other sub-chip integrates a calibration module as described in any one of claims 4-6.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program stored in the memory, wherein when the computer program is executed, the processor is configured to execute the oscillator calibration method according to any one of claims 1 to 3.

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