A monitoring system for precision DME ground navigation equipment

Abstract

The present invention proposes a monitoring system for a precision DME ground navigation device, comprising: the control module comprises: a DSP chip, an RTC clock chip, a multi-channel DA sampling unit, a reset chip, a JTAG download interface, and a CAN bus, wherein the RTC clock chip, the multi-channel DA sampling unit, the reset chip, and the JTAG download interface respectively communicate with the DSP chip in a two-way manner; the signal processing module comprises: an FPGA processor, a first AD sampling unit, a second AD sampling unit, a DA conversion unit, a FLASH chip, and a buzzer, wherein the first AD sampling unit, the second AD sampling unit, the FLASH chip, and the DSP chip respectively communicate with the FPGA processor in a two-way manner, the input end of the DA conversion unit is connected to the output end of the FPGA processor, and the output end of the FPGA processor is connected to the input end of the buzzer.

Description

Technical Field

[0001] The present invention relates to the technical field of DME ground navigation, and in particular to a monitoring system for precision DME ground navigation equipment. Background Art

[0002] In recent years, with the increasing number of airport navigation equipment at home and abroad, the requirements for equipment are getting higher and higher. At present, the monitoring system design of DME / P equipment is outdated, built with integrated circuits of several decades, and there is no localization, which makes debugging difficult. In addition, the functions are very limited, the speed response is slow, there is a lack of protection design, and it is easy to be interfered. Now there is an urgent need for a new monitoring system with localization and more optimized functions, good self-detection ability and special test ability. In addition, it must have requirements such as technological advancement, working stability, and performance reliability. Summary of the invention

[0003] The object of the present invention is to solve at least one of the technical drawbacks.

[0004] To this end, the purpose of the present invention is to provide a monitoring system for precision DME ground navigation equipment.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a monitoring system for precision DME ground navigation equipment, including: a control module and a signal processing module, wherein:

[0006] The control module includes: a DSP chip, an RTC clock chip, a multi-channel DA sampling unit, a reset chip, a JTAG download interface, and a CAN bus, wherein the RTC clock chip, the multi-channel DA sampling unit, the reset chip, and the JTAG download interface communicate with the DSP chip bidirectionally respectively, the DSP chip is connected to the FPGA processor, the FLASH chip, the FRAM chip, the CAN controller, and the serial port controller through the bus, the CAN controller is further bidirectionally connected to the CAN transformer, and the CAN transformer is further bidirectionally connected to the communication interface unit; the serial port controller is further bidirectionally connected to the RS232 transformer and the RS422 transformer;

[0007] The signal processing module includes: an FPGA processor, a first AD sampling unit, a second AD sampling unit, a DA conversion unit, a FLASH chip, and a buzzer, wherein the first AD sampling unit, the second AD sampling unit, the FLASH chip, and the DSP chip respectively communicate with the FPGA processor in a two-way manner, the input end of the DA conversion unit is connected to the output end of the FPGA processor, the output end of the FPGA processor is connected to the input end of the buzzer, the output end of the FPGA processor is further connected to the external inquiry unit through an SPI bus, the output end of the inquiry unit is further connected to the input end of the second AD sampling unit, the output end of the FPGA processor is connected to the output level conversion unit to output an IO signal, and the input end of the FPGA processor is connected to the input level conversion unit to input an IO signal.

[0008] Furthermore, the DSP chip is connected to the RTC clock chip via the I2C bus, and is connected to the multi-channel DA sampling unit via the SPI bus.

[0009] Furthermore, the DSP chip receives the timing interrupt signal of the FPGA chip, reads each monitoring parameter through the data bus, address bus and read, write and chip select control lines, and the monitoring parameters and the alarm thresholds of each parameter enter the alarm threshold comparison module, and outputs the main alarm signal and the auxiliary alarm signal to the communication interface unit; at the same time, the alarm threshold comparison module outputs the alarm warning to the alarm record storage, and the communication corresponding module receives CAN data. When querying, the monitoring parameters output by the communication module with the signal processing part and the alarm record read from the alarm record storage module are newly packaged and then recovered through the CAN interface. When setting, the setting parameters parsed by the protocol are transmitted to the communication module with the signal processing part, and then the parameters are set to the FPGA chip through the data bus, address bus and read, write and chip select control lines.

[0010] Furthermore, the outside of the DSP chip is connected to the FPGA of the signal processing part through a 32-bit data bus and a 16-bit address bus interface for data transmission; a 4M×8bit Flash chip is connected to the DSP through the bus to store related programs; a 4M×16bit FRAM chip is connected to the DSP through the bus to store parameters, data, alarm records and other information that need to be saved when the power is off; the DSP chip is connected to the CAN controller through the bus, and the CAN controller chip is connected to the communication interface unit through a transformer to communicate through the CAN bus; the DSP chip is connected to the serial port controller through the bus, and the two serial ports output by the serial port controller chip are used as debugging serial ports and backup after passing through RS232 serial port transformer and RS422 serial port transformer respectively.

[0011] Furthermore, the FPGA chip processing part inquires about the detection and enters the FPGA chip after AD sampling, passes through the cache FIFO to obtain the delayed detection signal, passes through the peak detection module to obtain the peak value and half-peak value, and then enters the comparator to obtain the half-amplitude pulse mark signal.

[0012] Further, the half-amplitude pulse mark signal and the transmission detection signal enter the waveform calculation module together to obtain the transmission peak value, transmission pulse interval, transmission pulse width, partial rise time, rise time, fall time, and transmission half-amplitude, and are transmitted to the communication module with the control part to be read by the control part; the cold and hot standby signals, the main / standby machine switching signal, the manual / automatic signal, and the test state enter the mode discrimination module to obtain the IA / FA inquiry switch signal, and enter the response processing module together with the previously generated inquiry half-amplitude and transmission half-amplitude to obtain the IA response delay, IA response efficiency, FA response delay, and FA response efficiency, respectively.

[0013] Furthermore, the IA / FA inquiry switch signal and the current working mode XYWZ enter the mode discrimination module to obtain the inquiry frequency and inquiry interval information that should be maintained at present. The GOLD code sequence generator generates a random code according to the inquiry frequency and the random code trigger signal output by the variable divider, and sends it to the variable divider module together with the inquiry interval to obtain a frequency-shaking Gaussian inquiry trigger signal. The signal passes through the Gaussian signal output type judgment module together with the device type to generate a frequency-shaking inquiry Gaussian inquiry signal under the current device type and an inquiry switch signal synchronized with the Gaussian, which are sent to the inquiry unit for use.

[0014] Furthermore, the attenuation value and the test status enter the multi-channel SPI attenuation setting module to obtain the SPI attenuation control signal with three clocks and data multiplexed, which is used by the inquiry unit; the channel number and the test status enter the SPI frequency setting module to generate the frequency setting SPI signals under different test states, which are used by the inquiry unit.

[0015] Furthermore, the FPGA chip adopts an FPGA chip of model EP4CE55F23I7, which is an industrial-grade wide-temperature microcontroller.

[0016] Furthermore, the RTC clock chip is connected to the DSP chip through the I2C interface. This time information is configured and called by the DSP, and a timestamp is recorded when an alarm occurs in the device. The DSP chip is connected to the serial multi-channel DA sampling unit through the SPI interface to output the DC level to the interrogation unit to provide it with the electrical adjustment voltage parameters.

[0017] The monitoring system for the precision DME ground navigation equipment according to the embodiment of the present invention solves the problems of outdated design, very limited functions, slow response, lack of protection design, etc., and according to unit design requirements, the hardware functions are software-based, thereby providing a new monitoring system for DME / P ranging navigation equipment.

[0018] The monitoring system of the present invention has a dual-unit configuration, and has the functions of information collection, signal processing, information transmission, and information storage. The beneficial effect produced by the present invention is to provide an effective implementation scheme for the localized DME / P monitoring system, which has good scalability, clear functional division of labor, fast communication speed, multiple interfaces, and good operating effect, and provides a key monitoring system for the intact operation of the whole machine. The cost of this system is controllable, and the selected devices are all stable and reliable industrial-grade devices on the market, which will not affect the procurement cycle and production cycle. After the successful development of the system, it was not only quickly applied to DME / P equipment, but the design architecture mode of this monitoring system was also applied to miniaturized microwave equipment and TACAN equipment. The versatility of the design has been greatly improved, adapted to environmental requirements, and has also been applied in some complex environments, and has stable operation.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] Figure 1 A hardware block diagram of the control part of the monitoring system of the precision DME ground navigation equipment according to an embodiment of the present invention;

[0022] Figure 2 A hardware block diagram of a signal processing and computing part of a monitoring system according to an embodiment of the present invention;

[0023] Figure 3 A monitoring logic flow chart of a monitoring system for a precision DME ground navigation device according to an embodiment of the present invention;

[0024] Figure 4 A circuit diagram of an FPGA chip according to an embodiment of the present invention;

[0025] Figure 5 A circuit diagram of a DSP chip according to an embodiment of the present invention;

[0026] Figure 6 A circuit diagram of an AD sampling unit according to an embodiment of the present invention;

[0027] Figure 7 FIG. 4 is a circuit diagram of a DA sampling unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0029] The present invention relates to the design and implementation of a monitoring system for precision distance measuring equipment (hereinafter referred to as DME / P). The system uses advanced design ideas and concepts, dual CPU design, real-time monitoring of important signals of the equipment, real-time decoding, measurement, calculation of important technical parameters, and sends the monitoring results to the communication interface unit. It is applied to DME / P ground equipment.

[0030] like Figure 1 As shown, the monitoring system of the precision DME ground navigation equipment of the embodiment of the present invention includes: a control module and a signal processing module.

[0031] Specifically, the control module includes: a DSP chip, an RTC clock chip, a multi-channel DA sampling unit, a reset chip, a JTAG download interface, and a CAN bus. The RTC clock chip, the multi-channel DA sampling unit, the reset chip, and the JTAG download interface communicate with the DSP chip bidirectionally respectively. The DSP chip is connected to the FPGA processor, the FLASH chip, the FRAM chip, the CAN controller, and the serial port controller through the bus. The CAN controller is further bidirectionally connected to the CAN transformer, and the CAN transformer is further bidirectionally connected to the communication interface unit; the serial port controller is further bidirectionally connected to the RS232 transformer and the RS422 transformer. Figure 7 FIG. 4 is a circuit diagram of a DA sampling unit according to an embodiment of the present invention.

[0032] The signal processing module includes: an FPGA processor, a first AD sampling unit, a second AD sampling unit, a DA conversion unit, a FLASH chip, and a buzzer, wherein the first AD sampling unit, the second AD sampling unit, the FLASH chip, and the DSP chip respectively communicate with the FPGA processor in a two-way manner, the input end of the DA conversion unit is connected to the output end of the FPGA processor, the output end of the FPGA processor is connected to the input end of the buzzer, the output end of the FPGA processor is further connected to an external inquiry unit through an SPI bus, the output end of the inquiry unit is further connected to the input end of the second AD sampling unit, the output end of the FPGA processor is connected to the output level conversion unit to output an IO signal, and the input end of the FPGA processor is connected to the input level conversion unit to input an IO signal. Figure 6 FIG. 4 is a circuit diagram of an AD sampling unit according to an embodiment of the present invention.

[0033] Reference Figure 1 The control part adopts a TI C6000 series DSP chip, which is an industrial-grade wide-temperature microcontroller, a 32-bit high-speed floating-point DSP, and a maximum clock frequency of 300MHz. Figure 5 The circuit diagram of the DSP chip according to the embodiment of the present invention. The DSP is connected to the FPGA of the signal processing part through a 32-bit data bus and a 16-bit address bus interface for data transmission; the 4M×8bit Flash chip is connected to the DSP through the bus to store related programs; the 4M×16bit FRAM chip is connected to the DSP through the bus to store parameters, data, alarm records and other information that need to be saved when the power is off; the DSP is connected to the CAN controller through the bus, and the CAN controller chip is connected to the communication interface unit through a transformer, and the system communicates through the CAN bus; the DSP is connected to the serial port controller through the bus, and the two serial ports output by the serial port controller chip are used as debugging serial ports and backup after passing through the RS232 serial port transformer and the RS422 serial port transformer respectively; the RTC clock chip ISL1208 is connected to the DSP through the I2C interface, and this time information is configured and called by the DSP, and the timestamp is recorded when the device alarms; the DSP is connected to the serial multi-channel DA sampling unit through the SPI interface to output the DC level to the inquiry unit to provide it with the electric adjustment voltage parameters; the system uses the MAX708SESA chip and peripheral circuits as the reset circuit.

[0034] Reference Figure 2 The signal processing calculation part adopts Intel's The IV series FPGA chip EP4CE55F23I7 is an industrial-grade wide-temperature microcontroller with 56k LEs resources, 4 PLLs, 484 pins, and 324 GPIOs, which is suitable for our design. The FPGA is connected to the DSP of the control part through a 32-bit data bus and a 16-bit address bus interface for data transmission. The 64M Flash chip is connected to the FPGA through a serial interface to store related programs. The buzzer and its circuit are connected to the FPGA through GPIO for audio output of the identification code. The dual-channel AD sampling chip is connected to the FPGA through GPIO to input the sampling data of the interrogation detection signal and the transmission detection signal into the FPGA for subsequent signal processing. The FPGA is connected to the voltage conversion chip through GPIO to convert the 3.3V LVTTL level into the 5V standard for transmission between boards, and also converts the 5V standard input signal into the 3.3V LVTTL level to enter the FPGA. The FPGA is connected to the DA conversion chip through GPIO to output the frequency-jittered interrogation signal, which is used as the modulation signal of the interrogation unit. The FPGA is connected to the interrogation unit through two SPI interfaces, one of which is multiplexed to control the interrogation signal attenuators of the three interrogation units, and the other SPI interface is used to set the 63MHz of the interrogation unit. Figure 4 is a circuit diagram of an FPGA chip according to an embodiment of the present invention.

[0035] Reference Figure 3, a monitoring system design and implementation method for precision DME ground navigation equipment includes two parts, FPGA signal processing part and DSP control part. In the FPGA signal processing part, the inquiry detection enters the FPGA after AD sampling, and passes through the cache FIFO to obtain the delayed detection signal, passes through the peak detection module to obtain the peak value and half peak value, and then enters the comparator to obtain the 50% half-amplitude pulse mark signal; this signal enters the waveform calculation module together with the inquiry detection signal to obtain the inquiry peak value, inquiry pulse interval, and inquiry half-amplitude, and is transmitted to the communication module with the control part to be read by the control part. After the transmission detection enters the FPGA after AD sampling, it passes through the cache FIFO to obtain the delayed detection signal, passes through the peak detection module to obtain the peak value and half peak value, and then enters the comparator to obtain the 50% half-amplitude pulse mark signal; this signal enters the waveform calculation module together with the transmission detection signal to obtain the transmission peak value, transmission pulse interval, transmission pulse width, partial rise time, rise time, fall time, and transmission half-amplitude, and is transmitted to the communication module with the control part to be read by the control part. The hot / cold standby signal, the master / standby switch signal, the manual / automatic signal, and the test state enter the mode discrimination module, and obtain the IA / FA inquiry switch signal. Together with the previously generated inquiry half-width and transmission half-width, they enter the response processing module, and obtain the IA response delay, IA response efficiency, FA response delay, and FA response efficiency, respectively, and are also transmitted to the control part communication module to be read by the control part. The control part communication module generates a timing interrupt signal and outputs it to the control part; when the control part reads the parameters according to the protocol, the control part communication module transmits the received measurement parameter data of each module to the control part through the 32-bit data bus, 16-bit address bus, and read, write, and chip select control lines; at the same time, the control part communication module responds to the parameter settings of the control part and sends it to each module for use. The IA / FA inquiry switch signal and the current working mode XYWZ enter the mode discrimination module to obtain the inquiry frequency and inquiry interval information that should be maintained. The GOLD code sequence generator generates a random code based on the inquiry frequency and the random code trigger signal output by the variable divider, and sends it to the variable divider module together with the inquiry interval to obtain a frequency-shaking Gaussian inquiry trigger signal. Together with the device type, it passes through the Gaussian signal output type judgment module to generate a frequency-shaking inquiry Gaussian inquiry signal under the current device type and an inquiry switch signal synchronized with the Gaussian, which are sent to the inquiry unit for use. The attenuation value and test status enter the multi-channel SPI attenuation setting module to obtain a three-channel clock and data multiplexed SPI attenuation control signal for use in the inquiry unit. The channel number and test status enter the SPI frequency setting module to generate frequency-setting SPI signals under different test states for use in the inquiry unit.

[0036] The communication module with the signal processing part of the DSP control part receives the timing interrupt signal of the FPGA signal processing part, and then reads each monitoring parameter through the 32-bit data bus, 16-bit address bus and read, write and chip select control lines. The monitoring parameters and the alarm thresholds of each parameter enter the alarm threshold comparison module, and output the main alarm signal and auxiliary alarm signal to the communication interface unit; at the same time, the alarm threshold comparison module outputs the alarm record to the alarm record storage. The communication response module receives CAN data. When querying, it packages the monitoring parameters output by the communication module with the signal processing part and the alarm records read from the alarm record storage module, and then sends them back through the CAN interface; when setting, the setting parameters parsed by the protocol are transmitted to the communication module with the signal processing part, and then the parameters are set to the FPGA signal processing part through the 32-bit data bus, 16-bit address bus and read, write and chip select control lines.

[0037] The system of the present invention constructs a dual CPU architecture of FPGA+DSP, and performs software development by function. The control part responds to the parameter instruction setting and query of the communication interface, and transmits the parameters required for signal processing to the FPGA through the bus, and stores the working parameters and alarm threshold information that need to be saved when the power is off externally; the control part responds to the interruption transmitted by the FPGA, and then reads the parameters monitored by the signal processing, and compares them with the alarm threshold, distinguishes the main and auxiliary alarms for the signals that still alarm after exceeding the alarm delay, and gives the main and auxiliary alarm signals; at the same time, the control part also needs to store the alarm information in the alarm record, and upload the alarm record when the communication interface queries this information. The signal processing part performs peak detection processing, waveform discrimination and index calculation on the inquiry detection signal and the transmission detection signal sampled by the AD, respectively. After detecting the inquiry detection signal in the current working mode, after the fixed delay in different modes, it starts to search for the response signal in the transmission detection signal, and records the response delay and response efficiency; at the same time, after the response signal in the transmission detection signal disappears, there should be a corresponding program to clear the current value. The signal processing part needs to identify and calculate the waveform indicators of the transmission detection signal, including the rise time, partial rise time, fall time, pulse width, pulse interval and other waveform information; at the same time, it is also necessary to identify the identification signal and the identification code according to the timing information of the signal in the transmission detection, and solve the identification information such as the dot signal time, dash signal time, dot dash interval, letter interval, etc. When the transmitter is turned on, the identification signal needs to be ANDed with the transmission detection, and the width is processed and output to the buzzer for identification sound output. The signal processing part also needs to monitor the transmission frequency of the whole machine according to the frequency signal input by GPIO. The signal processing part needs to generate a frequency-jittering Gaussian steep front interrogation signal, and switch the mode of generating the signal in different working modes, such as cold standby, hot standby, XYWZ mode, and IA / FA mode, and then output it to the interrogation unit through DA. At the same time, the signal processing part also needs to provide the interrogation unit with a frequency setting signal, an attenuation setting signal, and a switch control signal. At the same time, the signal processing part also has a self-test function, and sends the working status to the communication interface unit through the I / O port.

[0038] The monitoring system for the precision DME ground navigation equipment according to the embodiment of the present invention solves the problems of outdated design, very limited functions, slow response, lack of protection design, etc., and according to unit design requirements, the hardware functions are software-based, thereby providing a new monitoring system for DME / P ranging navigation equipment.

[0039] The monitoring system of the present invention has a dual-unit configuration, and has the functions of information collection, signal processing, information transmission, and information storage. The beneficial effect produced by the present invention is to provide an effective implementation scheme for the localized DME / P monitoring system, which has good scalability, clear functional division of labor, fast communication speed, multiple interfaces, and good operating effect, and provides a key monitoring system for the intact operation of the whole machine. The cost of this system is controllable, and the selected devices are all stable and reliable industrial-grade devices on the market, which will not affect the procurement cycle and production cycle. After the successful development of the system, it was not only quickly applied to DME / P equipment, but the design architecture mode of this monitoring system was also applied to miniaturized microwave equipment and TACAN equipment. The versatility of the design has been greatly improved, adapted to environmental requirements, and has also been applied in some complex environments, and has stable operation.

[0040] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0041] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. Those skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A monitoring system for precision DME ground navigation equipment, characterized in that: include: control module and signal processing module, wherein, The control module includes: a DSP chip, an RTC clock chip, a multi-channel DA sampling unit, a reset chip, a JTAG download interface, and a CAN bus, wherein the RTC clock chip, the multi-channel DA sampling unit, the reset chip, and the JTAG download interface communicate with the DSP chip bidirectionally respectively, the DSP chip is connected to the FPGA processor, the FLASH chip, the FRAM chip, the CAN controller, and the serial port controller through the bus, the CAN controller is further bidirectionally connected to the CAN transformer, the CAN transformer is further bidirectionally connected to the communication interface unit; the serial port controller is further bidirectionally connected to the RS232 transformer and the RS422 transformer; The signal processing module includes: an FPGA processor, a first AD sampling unit, a second AD sampling unit, a DA conversion unit, a FLASH chip, and a buzzer, wherein the first AD sampling unit, the second AD sampling unit, the FLASH chip, and the DSP chip respectively communicate with the FPGA processor in a two-way manner, the input end of the DA conversion unit is connected to the output end of the FPGA processor, the output end of the FPGA processor is connected to the input end of the buzzer, the output end of the FPGA processor is further connected to an external interrogation unit through an SPI bus, the output end of the interrogation unit is further connected to the input end of the second AD sampling unit, the output end of the FPGA processor is connected to an output level conversion unit to output an IO signal, and the input end of the FPGA processor is connected to an input level conversion unit to input an IO signal; In the FPGA signal processing part, the inquiry detection enters the FPGA after AD sampling, and passes through the cache FIFO to obtain the delayed detection signal, passes through the peak detection module to obtain the peak value and half-peak value, and then enters the comparator to obtain the 50% half-amplitude pulse mark signal; this signal enters the waveform calculation module together with the inquiry detection signal to obtain the inquiry peak value, inquiry pulse interval, and inquiry half-amplitude, and is transmitted to the control part communication module to be read by the control part; the transmission detection enters the FPGA after AD sampling, and passes through the cache FIFO to obtain the delayed detection signal, passes through the peak detection module to obtain the peak value and half-peak value, and then enters the comparator to obtain the 50% half-amplitude pulse mark signal. Half-amplitude pulse mark signal; this signal enters the waveform calculation module together with the transmission detection signal to obtain the transmission peak value, transmission pulse interval, transmission pulse width, partial rise time, rise time, fall time, and transmission half-amplitude, and is transmitted to the control part communication module to be read by the control part; the cold and hot standby signals, the main / standby machine switching signal, the manual / automatic signal, and the test state enter the mode judgment module to obtain the IA / FA inquiry switch signal, and enter the response processing module together with the previously generated inquiry half-amplitude and transmission half-amplitude to obtain the IA response delay, IA response efficiency, FA response delay, and FA response efficiency respectively, and are also transmitted to the control part communication module The control part is to be read; the control part communication module generates a timing interrupt signal and outputs it to the control part; when the control part reads the parameters according to the protocol, the control part communication module transmits the received measurement parameter data of each module to the control part through the 32-bit data bus, 16-bit address bus and read, write and chip select control lines; at the same time, the control part communication module responds to the parameter setting of the control part and sends it to each module for use; the IA / FA inquiry switch signal and the current working mode XYWZ enter the mode discrimination module to obtain the inquiry frequency and inquiry interval information that should be maintained at present, and the GOLD code sequence generator is based on the inquiry frequency and available The random code trigger signal output by the variable frequency divider generates a random code, which is sent to the variable frequency divider module together with the inquiry interval to obtain a frequency-jittering Gaussian inquiry trigger signal, which passes through the Gaussian signal output type judgment module together with the device type to generate a frequency-jittering inquiry Gaussian inquiry signal under the current device type and an inquiry switch signal synchronized with the Gaussian, which are sent to the inquiry unit for use; the attenuation value and the test state enter the multi-channel SPI attenuation setting module to obtain a three-channel clock and data multiplexed SPI attenuation control signal, which is used by the inquiry unit; the channel number and the test state enter the SPI frequency setting module to generate frequency setting SPI signals under different test states, which are used by the inquiry unit; The DSP control part communicates with the signal processing part, receives the timing interrupt signal of the FPGA signal processing part, and then reads each monitoring parameter through the 32-bit data bus, 16-bit address bus and read, write and chip select control lines. The monitoring parameters and the alarm thresholds of each parameter enter the alarm threshold comparison module, and output the main alarm signal and the auxiliary alarm signal to the communication interface unit; at the same time, the alarm threshold comparison module outputs the alarm record to the alarm record storage; the communication response module receives CAN data, and when querying, it packages the monitoring parameters output by the communication module with the signal processing part, the alarm record read from the alarm record storage module and other information, and then sends it back through the CAN interface; when setting, the setting parameters parsed by the protocol are transmitted to the communication module with the signal processing part, and then the parameters are set to the FPGA signal processing part through the 32-bit data bus, 16-bit address bus and read, write and chip select control lines.

2. The monitoring system for precision DME ground navigation equipment according to claim 1, characterized in that: The DSP chip is connected to the RTC clock chip via the I2C bus, and is connected to the multi-channel DA sampling unit via the SPI bus.

3. The monitoring system for the precision DME ground navigation equipment according to claim 2, characterized in that: The outside of the DSP chip is connected to the FPGA of the signal processing part through a 32-bit data bus and a 16-bit address bus interface for data transmission; a 4M×8bit Flash chip is connected to the DSP through the bus to store related programs; a 4M×16bit FRAM chip is connected to the DSP through the bus to store parameters, data, alarm records and other information that need to be saved when the power is off; the DSP chip is connected to the CAN controller through the bus, and the CAN controller chip is connected to the communication interface unit through a transformer to communicate through the CAN bus; the DSP chip is connected to the serial port controller through the bus, and the two serial ports output by the serial port controller chip are used as debugging serial ports and backup after passing through RS232 serial port transformer and RS422 serial port transformer respectively.

4. The monitoring system for the precision DME ground navigation equipment according to claim 1, characterized in that: The FPGA processor uses an FPGA chip of model EP4CE55F23I7, which is an industrial-grade wide-temperature microcontroller.

5. The monitoring system for the precision DME ground navigation equipment according to claim 1, characterized in that: The RTC clock chip is connected to the DSP chip through the I2C interface. This time information is configured and called by the DSP, and the timestamp is recorded when an alarm occurs in the device. The DSP chip is connected to the serial multi-channel DA sampling unit through the SPI interface to output the DC level to the interrogation unit to provide it with the electrical adjustment voltage parameters.

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