A design method for parameterized customized transistor layout and chip layout structure

Abstract

The present invention provides a design method for parameterized customized transistor layout, which includes designing the minimum transistor layout unit according to the basic structure of the transistor; determining the gate width and the number of gate contact holes according to the channel length, determining the number of active area contact holes according to the channel width, replicating the pattern according to the number of parallel units and determining the replication distance; determining the gate contact hole design rules according to the gate contact hole design parameters; determining the active area contact hole design rules according to the active area contact hole design parameters; and generating a customized layout structure. The present invention has flexibility and ease of use, can meet the customized layout requirements, and can realize multi-parameter adjustable.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a design method for parameterized customized transistor layout and a chip layout structure applied to the method. Background Art

[0002] In the process of IC back-end analog circuit layout design, transistors are the most commonly used basic devices, and transistor layout design is the basic layout unit. The adjustable parameter transistor layout unit in the design package provided by the IC manufacturer can only simply set some basic parameters such as the channel length and channel width of the transistor. After adjusting these simple parameters, it is impossible to customize the layout unit according to the layout position. This greatly reduces the efficiency of layout design. Therefore, a flexible, concise, and multi-parameter adjustable transistor layout design unit is urgently needed for layout design.

[0003] Currently, the closest existing technology on the market: the design package provided by the integrated circuit manufacturer has a basic adjustable parameter transistor layout unit, which has the following disadvantages:

[0004] 1. Only simple functions can be realized, there are too few adjustable parameters, and the area is not optimal.

[0005] 2. The layout of the layout design is not taken into consideration, so the versatility is poor.

[0006] 3. The adjustable parameter unit does not remove the layers that can be produced through post-calculation. There are too many visual layers, which can easily cause visual fatigue to layout designers. Summary of the invention

[0007] The main purpose of the present invention is to provide a flexible and concise design method for parameterized customized transistor layout with adjustable multiple parameters.

[0008] Another object of the present invention is to provide a chip layout structure.

[0009] In order to achieve the above main purpose, the present invention provides a method for designing a parameterized customized transistor layout, including designing a minimum transistor layout unit according to the basic structure of the transistor; determining the gate width and the number of gate contact holes according to the channel length, determining the number of active area contact holes according to the channel width, copying the pattern according to the number of parallel units and determining the copy distance; determining the gate contact hole design rules according to the gate contact hole design parameters; determining the active area contact hole design rules according to the active area contact hole design parameters; and generating a customized layout structure.

[0010] In a further solution, before generating the customized layout structure, the following is also performed: determining the transistor application type according to other customized parameters, and adding a corresponding marking layer.

[0011] In a further scheme, all necessary design levels are determined according to the basic structure of the transistor, and the design levels that can be generated by later calculations are removed; wherein the basic structure includes a source terminal, a drain terminal and a gate terminal, and according to the symmetry of the CMOS transistor, the source terminal and the drain terminal are uniformly designed as an active area, and the gate terminal is designed as a gate area.

[0012] In a further solution, the design of the minimum transistor layout unit specifically includes: determining the maximum number of contact holes in the gate region according to the channel length; and determining the maximum number of contact holes in the active region according to the channel width.

[0013] In a further solution, the gate contact hole design parameters include: determining whether to drill a contact hole on the gate; determining whether the gate contact hole is drilled at the upper or lower end of the gate; determining whether the covering metal extension direction of the gate contact hole is vertical or horizontal; the number of gate contact holes deleted; the distance the gate contact hole moves horizontally; and the distance the gate polysilicon extends upward.

[0014] In a further solution, the active area contact hole design parameters include: determining whether to drill contact holes in the active area; determining whether to cover the active area contact holes with wide metal; the number of active area contact holes to be deleted; and the vertical movement distance of the active area contact holes.

[0015] In a further solution, the other customized parameters include: determining whether there is a transistor device type marking layer; determining whether there is a transistor capacitor marking layer; and determining whether to add a well marking layer.

[0016] In a further embodiment, the generating of the customized layout structure includes: adding a plurality of gate contact hole design parameters and active area contact hole design parameters, and automatically calculating the layout unit meeting the customized requirements according to the design rules.

[0017] In order to achieve the above another objective, the present invention provides a chip layout structure, including at least one transistor layout structure, and the transistor layout structure is manufactured using the above-mentioned design method of a parameterized customized transistor layout.

[0018] It can be seen that the present invention adds multiple gate contact hole design parameters and active area contact hole design parameters, and automatically calculates a layout style that meets the customized requirements according to the rules. The generated transistor layout unit has both flexibility and ease of use, meeting the customized layout requirements.

[0019] Furthermore, according to the actual possible application types of the transistor, an optional marking layer can be added to realize the multi-occasion use of the layout unit.

[0020] In addition, removing the layers that can be generated by post-calculations makes the layout units concise and clear, which can reduce the visual fatigue of layout designers and improve layout design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a flow chart of an embodiment of a design method for parameterized customized transistor layout of the present invention.

[0022] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] See also Figure 1 A method for designing a parameterized customized transistor layout of the present invention specifically includes the following steps when generating a customized transistor layout unit according to the basic structure of the transistor and the parameterized selection conditions:

[0025] First, execute step S1, design the minimum transistor layout unit according to the basic structure of the transistor. According to the basic structure of the transistor, all necessary design levels are determined, and the design levels that can be generated by later calculations are removed; the basic structure includes a source terminal, a drain terminal and a gate terminal, and according to the symmetry of the CMOS transistor, the source terminal and the drain terminal are uniformly designed as an active area, and the gate terminal is designed as a gate area.

[0026] The necessary design layers of this embodiment include active injection areas PDIFF and NDIFF, gate polysilicon poly, contact holes contact, and first metal layer two lines Metal1; the design layers that can be generated by later calculations include P+ injection, N+ injection, high-voltage device identification layer, etc.

[0027] In the above step S1, designing the minimum transistor layout unit specifically includes: determining the maximum number of contact holes in the gate region according to the channel length; and determining the maximum number of contact holes in the active region according to the channel width.

[0028] Next, step S2 is performed to determine the gate width and the number of gate contact holes according to the channel length, determine the number of active area contact holes according to the channel width, replicate the pattern according to the number of parallel units and determine the replication distance.

[0029] Then, step S3 is performed to determine the gate contact hole design rule according to the gate contact hole design parameter.

[0030] Next, step S4 is performed to determine the active area contact hole design rules according to the active area contact hole design parameters.

[0031] In the above step S2, the channel length is defined as parameter l, the number of gate contact holes is parameter poly_contact = (l-contact boundary distance) / contact_step, the channel width is parameter w, the number of active area contact holes is parameter diff_contact = (w-contact boundary distance) / contact_step, the number of parallel units is parameter m, and the replication distance is parameter space = m*graphic step.

[0032] In the above step S3, the gate contact hole design parameters include: determining whether to drill a contact hole on the gate; determining whether the gate contact hole is drilled at the upper end or the lower end of the gate; determining whether the covering metal extension direction of the gate contact hole is vertical or horizontal; the number of gate contact holes to be deleted; the distance the gate contact hole moves horizontally; and the distance the gate polysilicon extends upward.

[0033] Specifically, if the physical connection of the gate is directly connected through polysilicon, there is no need to drill a contact hole; if the physical connection of the gate is through metal connection, a contact hole needs to be drilled; the drilling position is determined according to whether the metal connection is accessed from the top or the bottom; the number of deletions is determined according to the wiring density near the gate, and when the wiring density is high, if deleting a contact hole can allow one more Metal1, then a contact hole is deleted, provided that at least one contact hole is retained on the gate itself; based on the judgment condition for deletion of the gate contact hole, on the premise that the gate position will not be moved out of the horizontal direction, if moving x um can just allow Metal1 to have one more connection line, then the moving distance is x.

[0034] In the above step S4, the active area contact hole design parameters include: determining whether to drill contact holes in the active area; determining whether to cover the active area contact holes with wide metal; the number of active area contact holes to be deleted; and the vertical movement distance of the active area contact holes.

[0035] Specifically, if the active area is directly next to the active area of ​​another device, there is no need to drill a contact hole; if the active area is connected through metal, a contact hole needs to be drilled; if covering the wide metal will not cause a design rule violation, the wide metal is covered on the active area contact hole, otherwise the wide metal is not covered; the number of contact holes to be deleted in the active area is determined according to the routing density of the active area. When the routing density is high, if deleting a contact hole can allow one more Metal1 to be routed, then a contact hole is deleted, provided that at least one contact hole is retained in the active area itself; based on the judgment conditions for deleting the active area contact holes, on the premise that the active area position will not be moved out of the vertical direction, if moving y um can just allow Metal1 to have one more connection line, then the moving distance is y.

[0036] Finally, step S5 is executed to generate a customized layout structure, wherein generating a customized layout structure specifically includes: adding multiple gate contact hole design parameters and active area contact hole design parameters, and automatically calculating layout units that meet the customization requirements according to design rules.

[0037] In this embodiment, before generating the customized layout structure, the following steps are further performed: determining the transistor application type according to other customized parameters, and adding a corresponding marking layer.

[0038] The above other customized parameters include: determining whether there is a transistor device type marking layer; determining whether there is a transistor capacitor marking layer; and determining whether to add a well marking layer.

[0039] Therefore, the present invention can automatically calculate the gate contact hole layout design that meets the customized requirements based on the channel length and the customized gate contact hole design parameters; automatically calculate the source and drain contact hole layout design that meets the customized requirements based on the channel width and the customized active area contact hole design parameters; according to the basic structure of the transistor and the actual application type, a special marking layer can be optionally added to realize the use as a transistor layout for different types.

[0040] In practical applications, the present invention determines all necessary design levels, including source, drain and gate, based on the basic structure of the transistor. At the same time, the levels that can be generated by later calculations are removed. According to the symmetry of CMOS transistors, the source and drain are symmetrical in structure and are uniformly designed as active areas.

[0041] Then, all the adjustable parameters used are determined, which include basic parameters and customized parameters. The basic parameters include channel length, channel width and the number of parallel units. The customized parameters include the following:

[0042] a. Gate contact hole design parameters: whether to drill a contact hole on the gate, whether the gate contact hole is drilled at the top or bottom of the gate, whether the metal covering the gate contact hole extends vertically or horizontally, the number of gate contact holes to be deleted, the distance the gate contact hole moves horizontally, and the distance the gate polysilicon extends upward.

[0043] b. Active area contact hole design parameters: whether to drill contact holes in the active area, whether to cover the contact holes with wide metal, the number of contact holes to be deleted, and the vertical movement distance of the contact holes.

[0044] c. Other special customized parameters: whether there is a transistor device type marking layer, whether there is a transistor capacitor marking layer, and whether a well marking layer is added.

[0045] Preferably, in this embodiment, when forming the active area, a photolithography process is used to define the active area contact hole area; the interlayer film and field oxide layer in the active area contact hole area are etched; and self-aligned source injection is performed with adhesive to form the source area.

[0046] Preferably, in this embodiment, when forming the gate region, a photolithography process is used to define the gate contact hole region; the interlayer film and the field oxide layer in the gate contact hole region are etched; self-aligned silicon etching is performed; a front metal layer is deposited and photolithographically etched to form a gate and a source.

[0047] This embodiment also provides a chip layout structure, including at least one transistor layout structure, and the transistor layout structure is manufactured using the above-mentioned parameterized customized transistor layout design method.

[0048] It can be seen that the present invention adds multiple gate contact hole design parameters and active area contact hole design parameters, and automatically calculates a layout style that meets the customized requirements according to the rules. The generated transistor layout unit has both flexibility and ease of use, meeting the customized layout requirements.

[0049] Furthermore, according to the actual possible application types of the transistor, an optional marking layer can be added to realize the multi-occasion use of the layout unit.

[0050] In addition, removing the layers that can be generated by post-calculations makes the layout units concise and clear, which can reduce the visual fatigue of layout designers and improve layout design efficiency.

[0051] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto, and any non-substantial modifications made to the present invention using this concept also fall within the protection scope of the present invention.

Claims

1. A method for designing a parameterized customized transistor layout, characterized in that: include: Design the minimum transistor layout unit based on the basic structure of the transistor; Determine the gate width and the number of gate contact holes according to the channel length, determine the number of active area contact holes according to the channel width, replicate the pattern and determine the replication distance according to the number of parallel units; Determining a gate contact hole design rule according to the gate contact hole design parameters; Determining active area contact hole design rules according to active area contact hole design parameters; Generate customized layout structure; The gate contact hole design parameters include: determining whether to drill a contact hole on the gate; determining whether the gate contact hole is drilled at the upper end or the lower end of the gate; determining whether the metal covering the gate contact hole extends vertically or horizontally; the number of gate contact holes to be deleted; the distance the gate contact hole moves horizontally; the distance the gate polysilicon extends upward; Specifically, if the physical connection of the gate is directly connected through polysilicon, there is no need to drill a contact hole; if the physical connection of the gate is through metal connection, a contact hole needs to be drilled; the drilling position is determined according to whether the metal connection is connected from the top or the bottom; the number of deletions is determined according to the routing density near the gate. When the routing density is high, if deleting a contact hole can allow one more Metal1 to be routed, then a contact hole is deleted, provided that at least one contact hole is retained on the gate itself; based on the deletion judgment condition of the gate contact hole, under the premise that the gate position will not be moved out of the horizontal direction, if moving x um can just allow Metal1 to have one more connection line, then the moving distance is x; The design parameters of the active area contact holes include: determining whether to drill contact holes in the active area; determining whether to cover the contact holes in the active area with wide metal; the number of contact holes deleted in the active area; the vertical movement distance of the contact holes in the active area; Specifically, if the active area is directly next to the active area of ​​another device, there is no need to drill a contact hole; if the active area is connected through metal, a contact hole needs to be drilled; if covering the wide metal will not cause a design rule violation, the wide metal is covered on the active area contact hole, otherwise the wide metal is not covered; the number of contact holes to be deleted in the active area is determined according to the routing density of the active area. When the routing density is high, if deleting a contact hole can allow one more Metal1 to be routed, then a contact hole is deleted, provided that at least one contact hole is retained in the active area itself; based on the judgment conditions for deleting the active area contact holes, on the premise that the active area position will not be moved out of the vertical direction, if moving y um can just allow Metal1 to have one more connection line, then the moving distance is y.

2. The method for designing a parameterized customized transistor layout according to claim 1, characterized in that: Before generating the customized layout structure, the following is also performed: determining the transistor application type according to other customized parameters, and adding a corresponding marking layer.

3. The method for designing a parameterized customized transistor layout according to claim 1, characterized in that: According to the basic structure of transistor, all necessary design levels are determined, and the design levels that can be generated by later calculations are removed; The basic structure includes a source terminal, a drain terminal and a gate terminal. According to the symmetry of the CMOS transistor, the source terminal and the drain terminal are uniformly designed as an active region, and the gate terminal is designed as a gate region.

4. The method for designing a parameterized customized transistor layout according to claim 1, characterized in that: The design of the minimum transistor layout unit specifically includes: determining the maximum number of contact holes in the gate region according to the channel length; and determining the maximum number of contact holes in the active region according to the channel width.

5. The method for designing a parameterized customized transistor layout according to claim 1, characterized in that: The gate contact hole design parameters include: determining whether to drill a contact hole on the gate; determining whether the gate contact hole is drilled at the upper end or the lower end of the gate; determining whether the covering metal extension direction of the gate contact hole is vertical or horizontal; the number of gate contact holes to be deleted; the distance the gate contact hole moves horizontally; and the distance the gate polysilicon extends upward.

6. The method for designing a parameterized customized transistor layout according to claim 1, characterized in that: The active area contact hole design parameters include: determining whether to drill contact holes in the active area; determining whether to cover wide metal on the active area contact holes; the number of active area contact holes deleted; and the vertical movement distance of the active area contact holes.

7. The method for designing a parameterized customized transistor layout according to claim 2, characterized in that: The other customized parameters include: determining whether there is a transistor device type marking layer; determining whether there is a transistor capacitor marking layer; and determining whether to add a well marking layer.

8. The method for designing a parameterized customized transistor layout according to any one of claims 1 to 7, characterized in that: The generating of the customized layout structure includes: adding a plurality of gate contact hole design parameters and active area contact hole design parameters, and automatically calculating a layout unit that meets the customized requirements according to the design rules.

9. A chip layout structure, characterized in that: It comprises at least one transistor layout structure, which is manufactured by using a design method for a parameterized customized transistor layout as claimed in any one of claims 1 to 8.

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