Semiconductor device including vertical wire bonds

Abstract

A semiconductor device includes vertical columns of wire bonds on contact fingers of a substrate of the device. Semiconductor die are mounted on the substrate and electrically coupled to the substrate so that groups of semiconductor die can have bond wires extending to the same contact fingers on the substrate. By bonding these wires to the contact fingers in vertical columns rather than separate, side-by-side wire bonds on the contact fingers, the area of ​​the contact fingers can be reduced.

Description

Technical Field

[0001] The present application relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical wire bond. Background Art

[0002] Strong growth in demand for portable consumer electronics has driven the need for large-capacity storage devices. Nonvolatile semiconductor memory devices, such as flash memory storage cards, have become widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, as well as their high reliability and large capacity, have made such memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs, and cellular phones.

[0003] Although many packaging configurations are known, flash memory semiconductor devices can generally be manufactured as a system in package (SIP) or a multi-chip module (MCM), in which multiple semiconductor die are mounted and interconnected to the upper surface of a small footprint substrate. The substrate can generally include a rigid, dielectric base having a conductive layer etched on one or both sides. The semiconductor die in the die stack are typically electrically connected to the substrate so that multiple bonding wires extend from the stack and are connected to each other side by side at separate, discrete locations on a single contact finger on the substrate. It is known to form these side-by-side wire bonds in a single row of separate locations on separate contact fingers. It is also known to form these wire bonds in an array of separate, side-by-side locations on separate contact fingers, such as, for example, two rows of wire bonds.

[0004] Whether a single row or array of wire bonds, forming separate, side-by-side wire bonds requires a contact finger area large enough to accommodate each individual bond. Given the ever-present drive to increase the storage capacity of a semiconductor package for a given form factor, it is desirable to minimize the size of the semiconductor die in the package. Contact fingers with separate wire bonds take up valuable space in the package that could otherwise be used to increase the size of the die in the package. Summary of the invention

[0005] In one example, the technology is directed to a semiconductor substrate comprising: a first surface; and a plurality of contact fingers formed in the first surface, each of the plurality of contact fingers being configured to receive a plurality of wire bonds while having an area smaller than that required to accommodate two or more side-by-side wire bonds.

[0006] In other examples, the technology relates to a semiconductor device comprising: a substrate comprising: a first surface, and a plurality of contact fingers formed in the first surface; a plurality of semiconductor die; and a plurality of bonding wires coupled to the plurality of semiconductor die, a bonding wire from each of the plurality of semiconductor die bonded to a single contact finger of the plurality of contact fingers, the plurality of bonding wires bonded to the single contact finger in a vertical column.

[0007] In another example, the present technology relates to a semiconductor device, comprising: a substrate, comprising: a first surface, and a plurality of contact fingers formed in the first surface, the contact fingers in the plurality of contact fingers having a length between 50μm and 70μm and a width between 50μm and 70μm; a group of at least two semiconductor die, each group including one or more semiconductor die; and an electrical coupling mechanism for electrically coupling the semiconductor die from each group to a single contact finger. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 The present invention is a flowchart of an overall manufacturing process of a substrate and a semiconductor device using the substrate according to an embodiment of the present technology.

[0009] Figure 2 is a side view of a substrate of a semiconductor device at a first step in a manufacturing process according to an embodiment of the present technology.

[0010] Figure 3 yes Figure 2 A top view of a substrate.

[0011] Figure 4 is a side view of a substrate of a semiconductor device at a second step in a manufacturing process according to an embodiment of the present technology.

[0012] Figure 5 yes Figure 4 A three-dimensional view of the substrate.

[0013] Figure 6 is a side view of several semiconductor dies mounted on a substrate in accordance with an embodiment of the present technology.

[0014] Figure 7 yes Figure 6 An enlarged partial view of a corner of a substrate showing a wire bonding tool forming solder bumps on contact fingers of the substrate.

[0015] Figure 8 yes Figure 6 A three-dimensional diagram of a semiconductor die and substrate.

[0016] Fig. 9 is a side view of several semiconductor dies mounted on a substrate in accordance with an embodiment of the present technology.

[0017] Fig.10 yes Fig. 9 A three-dimensional diagram of a semiconductor die and substrate.

[0018] Fig.11 is a side view of several semiconductor dies mounted on a substrate in accordance with an embodiment of the present technology.

[0019] Fig.12 yes Fig.11 A three-dimensional diagram of a semiconductor die and substrate.

[0020] Fig.13 is a side view of several semiconductor dies mounted on a substrate in accordance with an embodiment of the present technology.

[0021] Fig.14 yes Fig.13 A three-dimensional diagram of a semiconductor die and substrate.

[0022] Fig.15 is a side view of several semiconductor dies mounted on a substrate in accordance with an embodiment of the present technology.

[0023] Fig.16 yes Fig.15 A three-dimensional diagram of a semiconductor die and substrate.

[0024] Fig.17 is a side view of several semiconductor dies mounted on a substrate in accordance with an embodiment of the present technology.

[0025] Fig.18 yes Fig.17 A three-dimensional diagram of a semiconductor die and substrate.

[0026] Fig.19 is an enlarged photograph of several vertically formed wire bonds according to an embodiment of the present technology.

[0027] Fig. 20 is a side view of several semiconductor die mounted on a substrate according to an alternative embodiment of the present technology.

[0028] Fig.21 is a side view of a completed semiconductor device according to an embodiment of the present technology.

[0029] Fig. 22 is a stereoscopic view of several substrates including contact fingers and dummy contact fingers on a substrate panel according to other embodiments of the present technology.

[0030] Fig.23 is a side view of several semiconductor die mounted on a substrate according to an alternative embodiment of the present technology.

[0031] Fig.24 yes Fig.23A three-dimensional diagram of a semiconductor die and substrate.

[0032] Fig.25 yes Fig.23 An enlarged side view of the semiconductor die and substrate shown in FIG.

[0033] Fig.26 yes Fig.23 An enlarged side view of the semiconductor die and substrate shown in FIG. 1 also includes solder balls embedded in the bond wires.

[0034] Fig. 27 is based on Fig.23 An enlarged side view of a semiconductor die and substrate that is an alternative to the approach shown in FIG.

[0035] Fig.28 yes Fig.23 An enlarged side view of the semiconductor die and substrate shown in FIG. 1 also includes a pair of solder balls embedded in the bond wires.

[0036] Fig.29 is an enlarged side view of a semiconductor die and substrate according to other embodiments of the present technology.

[0037] Fig.30 yes Fig.29 , also including solder bumps on top of solder balls. DETAILED DESCRIPTION

[0038] The present technology will now be described with reference to the accompanying drawings, which in an embodiment relates to a semiconductor device including vertical columns of wire bonds on substrate contact fingers of the device. Building the wire bonds vertically on the substrate contact fingers allows the contact fingers to be made smaller, thereby freeing up space in the device for larger semiconductor die, via fences and / or other components. In general, the semiconductor die are mounted on a substrate and electrically coupled to the substrate so that groups of semiconductor die can have bond wires extending to the same contact fingers on the substrate. By bonding these wires to the contact fingers in vertical columns, rather than separate, side-by-side wire bonds on the contact fingers, the area of ​​the contact fingers can be reduced.

[0039] It should be understood that the present technology can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and will fully convey the technology to those skilled in the art. In fact, the present technology is intended to cover the substitution, modification and equivalence of these embodiments, which are included in the scope and spirit of the technology as defined in the appended claims. In addition, in the following detailed description of the present technology, many specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be clear to those of ordinary skill in the art that the present technology can be practiced without such specific details.

[0040] As may be used herein, the terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" are for exemplary and illustrative purposes only and are not meant to limit the description of the present technology, as the referenced items can be interchanged in position and orientation. Likewise, as used herein, the terms "substantially", "approximately" and / or "about" mean that a specified dimension or parameter can vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ±2.5% of a given dimension.

[0041] Now refer to Figure 1 Flowchart and Figures 2 to 21 The top view, side view and perspective view of the first embodiment of the present technology are explained. Although the figures show a single semiconductor device 150 or a portion thereof, it should be understood that the device 150 can be batch processed with multiple other semiconductor devices on a substrate panel to achieve economies of scale. The number of rows and columns of devices 150 on the substrate panel can vary.

[0042] The substrate panel for manufacturing semiconductor device 150 begins with a plurality of substrates 100 (again, Figure 2-21 1. One such substrate is shown in FIG. 1. Substrate 100 may be a variety of chip carrier media, including a printed circuit board (PCB), a lead frame, or a tape automated bonding (TAB) tape. In the case where substrate 100 is a PCB, the substrate may be formed from a core 102, such as Figure 2 . The core 102 may be formed of various dielectric materials, such as polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), etc. The core may have a thickness between 40 micrometers (μm) and 200 μm, although the thickness of the core may vary outside of this range in alternative embodiments. The core 102 may be ceramic or organic in alternative embodiments.

[0043] At step 200, conductive layers 104 and 105 may be formed on the exposed planar surface of dielectric core 102, such as Figure 2 and Figure 3, respectively. Conductive layers 104, 105 may be formed of copper or copper alloy, plated copper or copper alloy, Alloy 42 (42Fe / 58Ni), copper-plated steel, or other metals and materials suitable for use on the substrate panel. Conductive layers 104, 105 may have a thickness of approximately 8 μm to 40 μm, although the thickness of the layer may vary outside of this range in alternative embodiments.

[0044] At step 202, a conductive pattern of vias, pins and / or pads is formed in and through the substrate 100. The substrate 100 may be drilled to define through vias 106, which are subsequently plated and / or filled with a conductive metal. Then a conductive pattern of electrical traces 108 and contact pads or fingers 110 may be formed on the top and / or bottom major planar surfaces 112, 114 of the substrate 100. Figure 3 An example of a conductive pattern including traces 108 and contact fingers 110 formed on a first major planar surface 112 of a substrate 100 is shown.

[0045] The patterns of vias 106, traces 108, and contact fingers 110 shown in the figures are examples only, and substrate 100 may include more or fewer vias, traces, and / or contact fingers in other embodiments, and they may be in different locations in other embodiments. The conductive patterns on the top and / or bottom surfaces of substrate 100 may be formed by various known processes, including, for example, various photolithography processes.

[0046] Reference again Figure 1 , the substrate 100 may then be inspected at step 204. This step may include automated optical inspection (AOI). Once inspected, a solder resist mask 118 may be applied to the upper and / or lower surface of the substrate and etched at step 206, such as, for example, at Figure 3 , Figure 4 and Figure 5 The top view, side view and stereogram are shown respectively. Figure 4 and Figure 5 As can be seen in FIG. 1 , the solder mask may be etched at the contact fingers 110 to create a structure that may be referred to as a window around each contact finger 110. In an embodiment, the window (and the contact finger 110 exposed through the window) may have a length and / or width of 50 μm to 70 μm, such as, for example, 55 μm. In an embodiment, the contact finger exposed through the solder mask may be square, but the contact finger may be rectangular (length greater than width), circular, or oval in other embodiments.

[0047] After applying the solder mask, the contact fingers 110 and any other etched areas to be soldered on the conductive pattern can be plated in a known electroplating or thin film deposition process, such as Ni / Au, Alloy 42, etc., in step 208. The substrate 100 can then be subjected to a run test in step 210 to ensure that the substrate 100 is functioning properly. In step 212, the substrate can be visually inspected, including, for example, automated visual inspection (AVI) and final visual inspection (FVI), to check for contamination, scratches, and discoloration. One or more of the above steps can be omitted or performed in a different order in other embodiments.

[0048] The above-described substrate 100 may have a thickness ranging between 0.05 mm and 0.3 mm, although the substrate 100 may have other thicknesses in other embodiments. In the above-described embodiment, the substrate 100 is a two-layer substrate (two conductive layers sandwiched on a dielectric layer). In other embodiments, the substrate 100 may include more layers, such as, for example, a four-layer substrate (four conductive layers interspersed around three dielectric layers).

[0049] Assuming that the substrate 100 passes the inspection, the passive component 120 ( Figure 4 and Figure 5 ) may then be attached to substrate 100 at step 214. The one or more passive components may include, for example, one or more capacitors, resistors, and / or inductors, although other components are also contemplated. Passive components 120 are shown as examples only, and the number, type, and location may vary in other embodiments.

[0050] At step 218, the controller die 122 may then be attached to a substrate such as, for example, via a die attach film (DAF) layer on the underside of the controller die 122. Figure 4 and Figure 5 1. The controller die 122 may be, for example, an ASIC semiconductor chip, but may be other types of semiconductor die in other embodiments. In one such other embodiment, the die 122 may be, for example, an AI (artificial intelligence) semiconductor chip for implementing an artificial intelligence process (explained below) for data stored on a memory die.

[0051] The controller die 122 can be electrically coupled to the substrate 100 using bonding wires 124, although other methods, such as flip chip bonding, can be used. The number of bonding wires 124 is shown as an example only, and there may be more bonding wires in other embodiments. The bonding wires may extend away from one side, two sides (as shown), three sides, or all four sides of the controller die 122 in other embodiments.

[0052] At step 220, a first set of one or more semiconductor die 125 may be mounted on the substrate 100, such as Figure 6 and Figure 7 125 . Although four semiconductor die are shown in the first group (and subsequent groups discussed below), it should be understood that each of the groups of semiconductor die 125 may include other numbers of semiconductor die, including, for example, 1, 2, 8, 16, and 32 semiconductor die. In other embodiments, there may be other numbers of die in each group. Semiconductor die 125 may be, for example, a memory die, such as a 2D NAND flash memory or a 3D BiCS (bit cost scaling), V-NAND or other 3D flash memory, but other types of die 125 may be used. These other types of semiconductor die include, but are not limited to, controller die such as ASIC, or RAM such as SDRAM, DDR SDRAM, LPDDR, and GDDR.

[0053] The first group (plurality) of semiconductor die 125 can be spaced above the surface 112 of the substrate 100 by spacers 126 to leave space for the controller die 122 and any wire bonds 124. The specific arrangement of the spacers 126 can vary in different embodiments. The die 125 can include a DAF layer to attach to each other and to the upper surface of the spacers 126. As an example, the DAF layer on the semiconductor die 125 and the controller die 122 can be cured to a B stage to initially attach the die to each other, to the substrate and to the spacers, and then cured to a final C stage to permanently attach the die 122, 125 within the semiconductor device 150.

[0054] Where multiple semiconductor die 125 are included in a group, the semiconductor die 125 may be stacked one above the other in various configurations. In one example, the die stacks are in an offset step configuration to form, for example, Figure 6 and Figure 7 In such a configuration, the bond pads on each semiconductor die in the die stack remain exposed and accessible for wire bonding.

[0055] At step 224, the semiconductor die 125 in the first group may be electrically interconnected to each other and to the contact fingers 110 of the substrate 100. According to aspects of the present technique, wire bonds from a group of multiple semiconductor die 125 are bonded to a single contact finger using a row of wire bonds vertically constructed on the contact finger. In the first step of the process, ball bumps 130 may be deposited on the contact fingers 110, such as Figure 6-8 Specific reference Figure 8, using heat pressure (e.g., at 150° C.) and / or ultrasonic energy (e.g., at 120 kHz), the wire bonding blade 132 can melt and deposit discrete amounts of metal onto the contact fingers 110, and then flatten the balls and form ball bumps 130 that adhere to the contact fingers 110. The ball bumps 130 can be formed of gold, but can be formed of other materials, including copper, silver, aluminum, and alloys such as palladium-silver. The first ball bumps 130 deposited on the contact fingers 110 can provide a bonding surface (on top of the ball bumps), for example, above the solder mask window.

[0056] Next, a first set of semiconductor die 125 in the first group (e.g., on the left edge) may be wire bonded to each other and to contact fingers 110 having ball bumps 130 on substrate 100. In an embodiment, the wire bonds may be formed using a so-called ball stitch on bump or stand-off stitch technique. In this technique, as shown in FIG. Fig. 9 and Fig.10 As shown, the wire bonding blade 132 can form a ball on the first die bonding pad of the bottom-most die (e.g., on pad 125a on the left side of the first die 125). The blade can then release the wire and form a stitch bond on top of the corresponding ball bump 130 on the contact finger 110a, thereby forming a bonding wire 134. The blade can break the wire, move up and form a ball on the first die bonding pad of the second die in the stack (e.g., on pad 125b of the second die 125). The blade can then release the wire and form a stitch bond on top of the wire bond formed on pad 125a, thereby forming the next bonding wire 134.

[0057] The process continues upward in the die stack, connecting all corresponding die bond pads of the die 125 in the stack that have the same function. The process is then repeated across the die stack, depositing ball bumps 130 on the contact fingers, and then bonding corresponding die bond pads upward in the stack, until the contact fingers 110 and bond pads of all the dies are bonded to each other, as shown in FIG. Fig.10 It should be understood that the bonding wires 134 may be bonded to the ball bumps 130 by other bonding techniques to electrically connect the corresponding die bonding pads to each other and to the substrate 100 .

[0058] The above process of steps 220 and 224 can be repeated to add and electrically connect additional groups of die to the semiconductor device 150. According to aspects of the present technique, each electrical coupling between a new group of die on the substrate 100 and the contact fingers 110 is formed directly on top of the previously formed electrical coupling, so that the wire bonds on the contact fingers 110 are built vertically upward in a single file column. This concept will be discussed below with respect to Figure 11-18More detailed explanation.

[0059] Fig.11 and Fig.12 The side view and perspective view of FIG. 1 show a second group of semiconductor die mounted on top of the first group. The die of the second group can have the same step offset as the first group, with the leading edges of the bottom-most die in the first and second groups aligned with each other in the reference plane R. A wire embedded film (WEF) layer 136 can be applied between adjacent groups of die to allow space for bonding wires 134 to leave the top die in the group below.

[0060] The second ball bump 130 may also be applied directly on top of the existing stitch bond and ball bump 130 on each contact finger 110. The second ball bump 130 may be applied in the same manner as the first ball bump 130. Referring now to Fig.13 and Fig.14 , bonding wires 140 may then be formed as described above with respect to bonding wires 134 to electrically couple the second group of semiconductor die 125 to each other and to substrate 100. The bonding wires 140 extending from the bottommost die of the second group may be stitch bonded directly onto the top of the second ball bumps 130.

[0061] Fig.15 and Fig.16 1 is a side view and a perspective view showing another (third) group of semiconductor die 125 mounted on top of the second group. The third group of die is provided with the same step offset, and the bottommost die in each of the three groups has a front edge aligned with the reference plane R. The third group of die can be separated from the second group of die by the WEF layer 136.

[0062] The third ball bump 130 may also be applied directly on top of the existing stitch bonds and ball bumps 130 on each contact finger 110. The third ball bump 130 may be applied in the same manner as the first and second ball bumps 130. Bond wires 142 may then be formed as described above to electrically couple the third group of semiconductor die 125 to each other and to the substrate 100. The bond wires 142 extending from the bottommost die of the third group may be stitch bonded directly on top of the third ball bump 130.

[0063] Fig.17 and Fig.18 1 is a side view and a perspective view showing another (fourth) group of semiconductor die 125 mounted on top of the third group. The fourth group of die is provided with the same step offset, and the bottommost die in each of the four groups has a front edge aligned with the reference plane R. The fourth group of die can be separated from the third group of die by the WEF layer 136.

[0064] Fourth ball bumps 130 may also be applied in a vertical column directly on top of the existing stitch bonds and ball bumps 130 on each contact finger 110. The fourth ball bumps 130 may be applied in the same manner as the first, second, and third ball bumps 130. Bond wires 144 may then be formed as described above to electrically couple the fourth group of semiconductor die 125 to each other and to the substrate 100. Bond wires 144 extending from the bottom-most die of the fourth group may be stitch bonded directly on top of the fourth ball bumps 130.

[0065] For example Fig.17 and Fig.18 As shown in , multiple connections from groups of different semiconductor die 125 to corresponding contact fingers 110 are constructed in a single vertical column, thereby minimizing the total footprint of the wire bonds on the contact fingers 110. In an embodiment, the total footprint of the wire bonds may be the area of ​​a single ball bond, which in an embodiment may have a diameter of 50 μm to 55 μm, such as, for example, 52.4 μm. Thus, as described above, the size of the contact fingers 110 may be reduced relative to conventional contact fingers, where each bond wire has its own separate, side-by-side connection on a single contact finger. As an example, providing a 55 μm x 55 μm contact finger provides a 26% reduction in length and a 33% reduction in area relative to conventional contact fingers. As another example, providing a 55 μm x 55 μm contact finger provides an 80% reduction in length and an 80% reduction in area relative to a conventional contact finger having four discrete wire bonds in a straight line.

[0066] A feature of the present technology is to minimize the area of ​​a contact finger that receives multiple wire bonds, where the wire bonds may include ball bumps and pin bonds. As mentioned, a ball bump may have a footprint diameter of 55 μm, resulting in an area of ​​2376 μm. A contact finger on which multiple such ball bumps may be formed may have a length and width of 55 μm, resulting in an area of ​​3025 μm. Thus, the present technology allows for multiple ball bumps on a single contact finger, where the total area of ​​the contact finger is greater than a single ball bump by less than 27.3% of the area of ​​the single ball bump, or less than 28% of the area of ​​the single ball bump.

[0067] Such contact fingers are smaller than previously known contact fingers that receive multiple wire bonds. For example, a conventional contact finger that receives two wire bonds must have an area at least twice that of the wire bonds because those wire bonds are typically formed side by side with each other on the contact finger. Reducing the area of ​​the contact finger that receives multiple wire bonds frees up valuable space on the substrate. The freed up space can be used for larger semiconductor die, which in turn provides the significant advantage of greater storage capacity without increasing the overall form factor of the semiconductor device. Alternatively, the freed up space can be used for features that enhance the performance of the semiconductor device. For example, the freed up space can be used for one or more via fences, which are rows of vias that are used to improve electrical isolation between components that would otherwise generate noise and crosstalk through electromagnetic field coupling. In other embodiments, the freed up space can be used for other purposes.

[0068] Currently, ball bumps are manufactured with a diameter of 50μm to 55μm, thereby defining the minimum size of the contact fingers. It is conceivable that ball bumps will be manufactured smaller in the future. Thus, for example, in the case where ball bumps with a diameter of 40μm to 50μm become available, contact fingers according to the present technology may be provided with a length and / or width of 40μm to 50μm. In the case where ball bumps with a diameter of 30μm to 40μm become available, for example, contact fingers according to the present technology may be provided with a length and / or width of 30μm to 40μm.

[0069] It should be understood that in other embodiments, the number of groups of semiconductor die can be greater or less than four, including, for example, groups of 2, 3, 5, and 6. Other numbers of groups are possible. Fig.19 Shown is an enlarged shot of an actual vertical column 146 on the contact finger 110. The column 146 is made up of six ball bumps 130 and six stitch bonds 148 from bond wires (eg, bond wires 134) extending to a group of six stacked semiconductor dies.

[0070] In the above-described embodiment, the die bonding pads are provided on one side of the semiconductor die 125, and all bonding wires extend away from a single side of the die stack. Fig. 20 , adjacent groups of die may be stepped in opposite directions, with bond wires 154 extending away from both sides of the die stack. In such an embodiment, substrate 100 may include contact fingers 110 on opposite edges of the substrate. In such an embodiment, vertical columns 146 of ball bumps 130 and stitch bonds may be formed on each of the contact fingers at both edges of substrate 100. Fig. 20The embodiment shown in includes two groups of die having wire bonds extending away from a first edge of the semiconductor device 150, and two groups of die having wire bonds extending away from a second, opposing edge of the semiconductor device 150. It should be understood that in other embodiments, this embodiment may include a greater or lesser number of groups.

[0071] In step 228, Fig.21 As shown, after electrically connecting the groups of bare die 125 to each other and to substrate 100, semiconductor device 150 can be encapsulated in molding compound 160. Molding compound 160 can include, for example, solid epoxy resin, phenolic resin, fused quartz, crystalline quartz, carbon black and / or metal hydroxide. Other molding compounds from other manufacturers are contemplated. The molding compound can be applied by various known processes, including by compression molding, FFT (free flow thin) molding, transfer molding or injection molding techniques.

[0072] At step 230, solder balls 162 may be attached to contact fingers 110 on lower surface 114 of substrate 100, such as Fig.21 Solder balls 162 may be used to solder semiconductor device 150 to a host device, such as a printed circuit board. Solder balls 162 may be omitted in embodiments where semiconductor device 150 is used as a land grid array (LGA) package. After encapsulation and forming solder balls 162 (if included), the semiconductor device may be singulated from the substrate panel in step 232 to form Fig.21 The completed semiconductor device 150 is shown in FIG.

[0073] Figure 1-21 A first embodiment is directed to minimizing the size of the contact fingers on the substrate by forming all wire bonds in a single vertical column. In other embodiments, Figure 22-30 It involves minimizing the area of ​​the contact finger substrate that receives multiple wire bonds. Fig. 22 3 is a perspective view showing a portion of the upper surface of a substrate panel 300. The panel 300 includes an array of substrates 302 separated by first keep-out regions 306 and second keep-out regions 308, which may be orthogonal to each other. The embodiment also includes a number of dummy contact fingers 312 paired with each contact finger 310.

[0074] Each substrate 302 includes a number of contact fingers 310, which may be similar in size and configuration to the contact fingers 110 described above. Fig. 22 In the embodiment shown in , the dummy contact fingers 312 may be in the keep-out region 306 , ie, a keep-out region adjacent to the edge of the substrate 302 containing the contact fingers 310 .

[0075] Fig.23 and Fig.24 is used Fig. 22302 is shown as a side view and a perspective view of a semiconductor device 350 constructed on the substrate 302. Although a single semiconductor device 350 is shown, it should be understood that Fig.23 and Fig.24 The device 350 is a portion of a panel 300 of such a device 350 at the stage of manufacture shown. In addition to the differences set forth below, Fig.23 and Fig.24 The semiconductor device 350 is similar in composition and structure to Fig.13 and Fig.14 The semiconductor device 150 shown in FIG. Fig.13 and Fig.14 150, the device 350 can include passive components 120 and controller die 122 mounted to substrate 302, and a group of two semiconductor die 125 mounted above controller die 122 by spacers 126. The two groups of die 125 can be mounted in the stepped, offset configuration described above, with the bottom-most die of the two groups having front edges aligned in reference plane R. Although each group is shown as having four semiconductor die 125, the groups can have more or fewer die in other embodiments. The groups of die can be separated by WEF layer 136.

[0076] The substrate 302 may be similar in construction to the substrate 100 described above, except that it also includes dummy contact fingers 312 in the keep-out regions 306 as described above. Fig.23 and Fig.24 as well as Fig.25 and Fig.26 As seen in the enlarged partial side view of , bonding wires 320 may be provided to electrically couple the die bonding pads of the first (lower) group of die 125 to each other and to the contact fingers 310 of the substrate 302. The wire bonds may be formed by a ball bonding technique, in which a ball is deposited, for example, on the first die bonding pad of the bottom-most die in the first group. The wire bonding cutter then releases the wire and forms a stitch bond on the first contact finger 310. The wire bonding cutter then continues upward along the stack of the first group and then across the stack. In an embodiment, the contact fingers 310 do not have ball bumps initially deposited thereon, but it is contemplated that they may include initial ball bumps and that the stitch bonds are formed on top of the ball bumps as described above.

[0077] Bond wires 324 may be provided to electrically couple the die bond pads of the second (upper) set of die 125 to each other and to the dummy contact fingers 312 of the substrate 302. The wire bonds with wires 324 may be formed in the same manner as wires 320. In an embodiment, the dummy contact fingers 312 do not have ball bumps initially deposited thereon, although it is contemplated that they may include initial ball bumps, with stitch bonds formed on top of the ball bumps as described above.

[0078] In an embodiment, when forming a wire connection between the bottommost bare die 125 in the second group and the dummy contact finger 312, the wire loop passes directly near or just above the contact finger 310, such as Fig.25 and Fig.26 Wire bonding techniques allow the wires to bend as they are released from the wire bonding knife, so that the wire 324 can extend downward toward the contact finger 310 and then turn toward the dummy contact finger 312 where a bond is formed.

[0079] Reference Fig.26 Once the wire bonds are formed using the bonding wires 320 and 324, a bond ball 330 may be deposited on each contact finger 310 of the substrate 302. Both wires 320 and 324 are embedded within the bond ball 330 as the bond ball 330 is formed, securing and electrically coupling the wires 320 and 324 to each other and to the respective contact fingers 310. The bond ball 330 may be, for example, a solder alloy including, for example, a tin / silver / copper alloy, a tin / silver alloy, a tin / lead alloy, a gold / tin alloy, an indium / tin alloy, or a tin / bismuth alloy. Other materials are contemplated.

[0080] The bonding balls can be applied by various methods, including, for example, by laser alloy ball spraying. Such a process is a known process, performed by, for example, Pac Tech (Packaging Technologies GmbH) of Nauen, Germany. However, in general, the process involves spraying solder balls from a wedge as the solder balls are reflowed by a laser within the wedge. Once heated by the laser, the solder balls melt around the bonding wires 320, 324 and onto the contact fingers 310. It has been found that the laser ball spraying process has the following advantages: minimizing the negative effects of intermetallic compound formation, and optimizing the atomic diffusion of the contact fingers and bonding wires. However, other processes can be used to apply the bonding balls.

[0081] Once the wires 320 , 324 have been bonded to the contact fingers 310 by the bond balls 330 , the semiconductor device 350 may be encapsulated in the molding compound 160 as described above and then singulated along the saw lines 336 , which separate the dummy contact fingers 312 from the finished semiconductor device 350 .

[0082] As mentioned, the number of die groups may be greater than two in other embodiments. In such embodiments, more than one bond ball may be applied to the contact finger if desired to embed all wire bonds. Fig. 27 and Fig.28. Three groups of die 125 are bonded to substrate 302, with the first (lowest) group having bond wires 320 bonded to contact fingers 310. The second and third groups of die have bond wires 324 and 338, respectively, bonded to dummy contact fingers 312. As above, the bond wires 324, 338 may have a low profile, passing directly near or just above the contact fingers 310.

[0083] Once the wires 324, 338 are bonded to the dummy contact fingers 312, the bond balls 330 may be applied to the contact fingers 310, embedding the bond wires 320, 324, and 338 and bonding them to the contact fingers 310. As shown, the bond balls 330 may be stacked one above the other until the bond wires are embedded. In other embodiments, more than two bond balls may be stacked one above the other. Thereafter, the device 350 may be encapsulated in the molding compound 160 and singulated along the dicing lines 336, separating the dummy contact fingers from the device 350. As above, the semiconductor device 350 provides contact fingers that have a small footprint while bonding multiple bond wires.

[0084] Fig.29 and Fig.30 A semiconductor package 350 is shown in accordance with yet another embodiment of the present technology. Fig.29 and Fig.30 The semiconductor device 380 is similar in composition and structure to Fig.13 and Fig.14 The semiconductor device 150 shown in FIG. 1 is a semiconductor device 150 that uses bonding balls to couple bonding wires to contact fingers, as described above with respect to FIG. Fig. 27 and Fig.28 However, in Fig.29 and Fig.30 In an embodiment, the bonding wire is not embedded in the bonding ball. In such an embodiment, the dummy contact finger can be omitted and the above-mentioned Figure 1-21 A substrate 100 is described.

[0085] In particular, refer to Fig.29 , after the first (lower) group of die 125 is mounted on substrate 100, a first set of bonding wires 362 can be connected between the die in the first group and the contact fingers. The bond can be formed by a ball bonding technique, including: depositing a ball on the first die bond pad of the bottom-most die, releasing the wires, and stitch bonding to the first contact finger. The wire bonding can continue upward and across the die in the first group. Thereafter, a bond ball 364 can be deposited on top of the stitch bond on contact finger 110 and allowed to harden (at room temperature or in a curing process).

[0086] Next, refer to Fig.30Zoomed in side view, after the second (upper) group of die 125 is mounted on the first group of die, a second set of bonding wires 366 can be connected between the die in the second group and the contact fingers 110. According to this embodiment, ball bumps 368 can be deposited on top of the bond balls 364. Thereafter, a wire bonding cutter can deposit balls on the first die bonding pads of the bottom-most die, release wires, and stitch bond to the ball bumps 364. Wire bonding can then continue in the same manner up and across the die in the second group.

[0087] Once completed, the semiconductor device 380 can be packaged and singulated as described above. As above, the semiconductor device 380 provides contact fingers that bond multiple bond wires while having a small footprint. In an embodiment, Figure 29-30 The contact fingers 110 may have a length and / or a width of 50 μm to 70 μm, for example 55 μm.

[0088] The foregoing detailed description of the technology has been given for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were selected in order to best explain the principles of the technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments with various modifications suitable for the particular use contemplated. It is intended that the scope of the technology be defined by the appended claims.

Claims

1. A semiconductor device comprising: Substrate, comprising: a first surface; and a plurality of contact fingers formed in the first surface; and a plurality of bonding wires, each bonding wire having an end with a ball bump, each ball bump of the plurality of bonding wires being vertically stacked on a contact finger of the plurality of contact fingers; The contact finger has an area smaller than an area required to accommodate two or more bonding wires of the plurality of bonding wires mounted side by side on the contact finger. 2 . The semiconductor device of claim 1 , wherein the contact finger is configured to receive between 2 and 6 bonding wires.

3. The semiconductor device of claim 1, further comprising a solder resist mask applied over the first surface, the solder resist mask being etched to form a window over each of the plurality of contact fingers. 4 . The semiconductor device of claim 1 , wherein the contact finger has a length between 50 μm and 70 μm, and a width between 50 μm and 70 μm. 5 . The semiconductor device according to claim 1 , wherein the end portion of each bonding wire further comprises a stitch bonding body formed at the end portion of each bonding wire among the plurality of bonding wires. 6 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a plurality of semiconductor dies, wherein the plurality of semiconductor dies comprises between 2 and 6 semiconductor dies. 7 . The semiconductor device of claim 1 , wherein an area of ​​the contact finger among the plurality of contact fingers that is larger than an area of ​​a ball bump directly attached to the contact finger is less than 28% of an area of ​​the ball bump.

8. The semiconductor device of claim 1, wherein the semiconductor device comprises a plurality of semiconductor bare cores, each of the plurality of semiconductor bare cores belongs to a different group of semiconductor bare cores, and each group of semiconductor bare cores comprises at least two semiconductor bare cores stacked one above the other in the semiconductor device.

9. The semiconductor device of claim 8, wherein the plurality of semiconductor die include a bottommost semiconductor die in each group of stacked semiconductor die, and bonding wires in the plurality of bonding wires extend directly between the bottommost semiconductor die and the contact fingers. 10 . The semiconductor device of claim 9 , wherein each of the plurality of semiconductor dies comprises an edge including a die bonding pad, the edges of the plurality of semiconductor dies being aligned with each other in a reference plane.

11. The semiconductor device of claim 8, wherein the group includes between 2 and 6 groups of semiconductor dies, and the plurality of bonding wires bonded to a single contact finger includes between 2 and 6 bonding wires.

12. A semiconductor device comprising: Substrate, comprising: a first surface, and a plurality of contact fingers formed in the first surface; at least two groups of semiconductor die stacked on the first surface, each group including one or more semiconductor die; a plurality of bonding wires extending directly between a semiconductor die from each group of semiconductor die and the contact fingers, each bonding wire having an end with a ball bump, each ball bump of the plurality of bonding wires being vertically stacked on a contact finger of the plurality of contact fingers; The contact finger has an area smaller than an area required to accommodate two or more bonding wires of the plurality of bonding wires mounted side by side on the contact finger.

13. The semiconductor device of claim 12, wherein the at least two groups of semiconductor dies include between 2 and 6 groups, each group including between 2 and 4 semiconductor dies. 14 . The semiconductor device of claim 12 , wherein a contact finger of the plurality of contact fingers has a length between 50 μm and 70 μm, and a width between 50 μm and 70 μm.

15. The semiconductor device of claim 12, wherein the contact finger is configured to receive between 2 and 6 bonding wires.

16. The semiconductor device according to claim 12, wherein: The group of semiconductor dies includes between 2 and 6 semiconductor dies.

17. The semiconductor device according to claim 12, wherein: The group of semiconductor dies includes between 2 and 4 groups of semiconductor dies. 18 . The semiconductor device of claim 12 , wherein an area of ​​the contact finger among the plurality of contact fingers that is larger than a ball bump directly attached to the contact finger is less than 28% of an area of ​​the ball bump.

Images