Power semiconductor device and method for manufacturing the same

Abstract

A power semiconductor device is provided, comprising: a semiconductor layer of SiC; a gate insulating layer; a gate electrode layer; a drift region, the drift region comprising at least one protruding portion in the semiconductor layer and having a first conductivity type; a well region, the well region comprising a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region, the second well region being located in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type; a source region comprising a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type; and a channel region under the gate electrode layer, the channel region being located in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0061694 filed in the Korean Intellectual Property Office on May 22, 2020, Patent Application No. 10-2020-0073130 filed in the Korean Intellectual Property Office on June 16, 2020, Patent Application No. 10-2020-0076554 filed in the Korean Intellectual Property Office on June 23, 2020, Patent Application No. 10-2020-0080162 filed in the Korean Intellectual Property Office on June 30, 2010, Patent Application No. 10-2020-0080163 filed in the Korean Intellectual Property Office on June 30, 2010, and Patent Application No. 10-2020-0083474 filed in the Korean Intellectual Property Office on July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method for manufacturing the same. Background Art

[0004] A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Power semiconductor devices are used in fields that require high power switching. For example, in power conversion, power converters, inverters, etc. For example, power semiconductor devices may include insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFTs), etc. Power semiconductor devices basically require high withstand voltage characteristics, and nowadays, power semiconductor devices additionally require high-speed switching operations.

[0005] Therefore, a power semiconductor device using silicon carbide (SiC) instead of silicon (Si) is being developed. Silicon carbide (SiC) is a wide-gap semiconductor material with a higher band gap than silicon, and can maintain stability even at high temperatures compared to silicon. In addition, since the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, power semiconductor devices using silicon carbide as a semiconductor layer show stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0006] When power semiconductor devices use silicon carbide, the negative charge caused by the formation of carbon clusters in the gate insulating layer causes the band gap on the surface of silicon carbide to rise. Therefore, there is a problem of increased threshold voltage and increased channel resistance. In addition, when the source contact structure is provided between the gate electrodes, it is also difficult to reduce the distance between the gate electrodes. Therefore, there is a limitation in reducing the channel density. Summary of the invention

[0007] The present disclosure aims to solve the above-mentioned problems existing in the prior art, while the advantages achieved by the prior art are fully maintained.

[0008] One aspect of the present disclosure provides a silicon carbide power semiconductor device capable of improving channel density and a method for manufacturing the same. However, these issues are exemplary, and the scope of the present disclosure is not limited thereto.

[0009] The technical problems to be solved by the inventive concept are not limited to the above problems, and any other technical problems not mentioned herein can be clearly understood by ordinary technicians in the field to which the present invention belongs from the following description.

[0010] According to one aspect of the present disclosure, a power semiconductor device includes: a semiconductor layer of silicon carbide (SiC); a gate insulating layer on at least a portion of the semiconductor layer; a gate electrode layer on the gate insulating layer; a drift region, including at least one protruding portion below the gate electrode layer in the semiconductor layer and having a first conductivity type; a well region, including: a first well region, the first well region is formed in the semiconductor layer below the gate electrode layer and is in contact with the at least one protruding portion; and a second well region, the second well region is formed in the semiconductor layer outside the gate electrode layer and is connected to the first well region, and has a second conductivity type; a source region, including a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region, and has a first conductivity type; and a channel region, disposed below the gate electrode layer, configured to be formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region to form an inversion channel, and having a first conductivity type.

[0011] The power semiconductor device may further include a source electrode layer connected to the second source region outside the gate electrode layer.

[0012] The power semiconductor device may further include a well contact region configured to extend from the second well region in the second source region through the second source region connected to the source electrode layer and having a second conductivity type, and the well contact region may be doped at a higher concentration than the well region.

[0013] The at least one protruding portion of the drift region, the first well region, and the first source region extends in one direction.

[0014] The first well region, the first source region, and the channel region may be respectively formed in the semiconductor layer on opposite sides of the at least one protruding portion of the drift region.

[0015] The channel region may be a portion of the well region.

[0016] The at least one protruding portion may include a plurality of protruding portions, sidewalls of the plurality of protruding portions are surrounded by the first well region, and the channel region may be formed between the plurality of protruding portions and the first source region.

[0017] The plurality of protruding portions may extend side by side in one direction.

[0018] The first well region may be formed symmetrically with respect to the second well region, the first source region may be formed symmetrically with respect to the second source region, and the channel region may be formed symmetrically with respect to the second well region or the second source region.

[0019] The at least one protrusion portion may include a plurality of protrusion portions symmetrically disposed with respect to the second well region or the second source region, and the plurality of protrusion portions may extend in one direction.

[0020] The gate electrode layer may be formed to expose the second source region and cover the first source region, the channel region, and at least one protruding portion of the drift region.

[0021] The power semiconductor device may further include a drain region having the first conductivity type in the semiconductor layer below the drift region, and the drain region may be doped at a higher concentration than the drift region.

[0022] According to one aspect of the present disclosure, a method for manufacturing a power semiconductor device includes: forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type to allow the drift region to include at least one protruding portion, and including a first well region defining the at least one protruding portion and a second well region connected to the first well region; forming a source region, the source region including a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region, and having the first conductivity type; forming a channel region formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, forming an inversion channel, and having the first conductivity type; forming a gate insulating layer on at least the channel region and the at least one protruding portion of the drift region; and forming at least one gate electrode layer on the gate insulating layer, wherein the second well region is formed in the semiconductor layer outside the gate electrode layer.

[0023] The method for manufacturing a power semiconductor device may also include: forming a well contact region, which extends from the second well region in the second source region outside the gate electrode layer through the second source region connected to the source electrode layer and has a second conductivity type, and the well contact region can be doped at a higher concentration than the well region.

[0024] The method of manufacturing a power semiconductor device may further include forming the source electrode layer on the semiconductor layer to be connected to the second source region and the well contact region.

[0025] The formation of the well region and the channel region may be performed by implanting impurities of the second conductivity type into the semiconductor layer, and the formation of the source region may be performed by implanting impurities of the first conductivity type into the well region.

[0026] The at least one protruding portion may include a plurality of protruding portions, sidewalls of the plurality of protruding portions are surrounded by the first well region, and the channel region may be formed between the plurality of protruding portions and the source region.

[0027] The first well region may be formed symmetrically with respect to the second well region, the first source region may be formed symmetrically with respect to the second source region, and the channel region may be formed symmetrically with respect to the second well region or the second source region.

[0028] The drift region may be formed on a drain region having a first conductivity type, and the drift region may be formed as an epitaxial layer on the drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present disclosure will become more apparent through the following detailed description in conjunction with the accompanying drawings:

[0030] Figure 1 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0031] Figure 2 is shown along Figure 1 A plan view of the power semiconductor device taken along line II-II;

[0032] Figure 3 is shown along Figure 2 A cross-sectional view of the power semiconductor device taken along line III-III;

[0033] Figure 4 is shown along Figure 2 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0034] Figure 5 is shown along Figure 2 A cross-sectional view of the power semiconductor device taken along line VV;

[0035] Figure 6 is shown along Figure 2 A cross-sectional view of the power semiconductor device taken along line VI-VI;

[0036] Figures 7 to 10 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0037] Fig.11 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0038] Fig.12 is shown along Fig.11 A plan view of the power semiconductor device taken along line II-II;

[0039] Fig.13 is shown along Fig.12 A cross-sectional view of the power semiconductor device taken along line III-III;

[0040] Fig.14 is shown along Fig.12 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0041] Fig.15 is shown along Fig.12 A cross-sectional view of the power semiconductor device taken along line VV;

[0042] Figures 16 to 20is a cross-sectional view showing a power semiconductor device according to other embodiments of the present disclosure;

[0043] Figure 21 to Figure 23 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0044] Fig.24 is a graph showing an electric field depending on a junction structure in a power semiconductor device according to an embodiment of the present disclosure;

[0045] Fig.25 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0046] Fig.26 is shown along Fig.25 A plan view of the power semiconductor device taken along line II-II;

[0047] Fig. 27 is shown along Fig.26 A cross-sectional view of the power semiconductor device taken along line III-III;

[0048] Fig.28 is shown along Fig.26 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0049] Figure 29 to Figure 32 is a cross-sectional view showing a power semiconductor device according to other embodiments of the present disclosure;

[0050] Figure 33 to Figure 35 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0051] Fig.36 is a graph showing a change in an electric field depending on a depth of a power semiconductor device according to an embodiment of the present disclosure;

[0052] Fig.37 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0053] Fig.38 is shown along Fig.37 A plan view of the power semiconductor device taken along line II-II;

[0054] Fig.39 is shown along Fig.38 A cross-sectional view of the power semiconductor device taken along line III-III;

[0055] Fig.40 is shown along Fig.38 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0056] Fig.41 is shown along Fig.38 A cross-sectional view of the power semiconductor device taken along line VV;

[0057] Figures 42 to 45 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention;

[0058] Figure 46 to Figure 48 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0059] Fig.49 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0060] Fig.50 is shown along Fig.49 A plan view of the power semiconductor device taken along line II-II;

[0061] Fig.51 is shown along Fig.50 A cross-sectional view of the power semiconductor device taken along line III-III;

[0062] Fig.52 is shown along Fig.50 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0063] Fig.53 is shown along Fig.50 A cross-sectional view of the power semiconductor device taken along line VV;

[0064] Figures 54 to 56 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention;

[0065] Figure 57 to Figure 59 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0066] Fig.60 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0067] Fig.61 is shown along Fig.60 A plan view of the power semiconductor device taken along line II-II;

[0068] Fig.62 is shown along Fig.61 A cross-sectional view of the power semiconductor device taken along line III-III;

[0069] Fig.63 is shown along Fig.61 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0070] Fig.64 is shown along Fig.61 A cross-sectional view of the power semiconductor device taken along line VV;

[0071] Fig.65 and Fig.66 is a cross-sectional view showing a power semiconductor device according to other embodiments of the present disclosure;

[0072] Figure 67 to Figure 69 is a cross-sectional view showing a power semiconductor device according to other embodiments of the present disclosure;

[0073] Figure 70 to Figure 72 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure; and

[0074] Fig.73 is a graph showing characteristics of a diode of a power semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments disclosed below. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the scope and spirit of the present disclosure to those skilled in the art. In addition, for ease of description, the size of at least some components or elements shown in the accompanying drawings may be enlarged or reduced. In the accompanying drawings, the same symbols refer to the same elements.

[0076] Unless otherwise defined, all terms used herein should be interpreted as meanings commonly understood by those skilled in the art. In the drawings, the sizes of layers and regions are exaggerated for description, and thus are provided to describe the normal structure of the present disclosure.

[0077] The same reference numerals indicate the same components. When a first component such as a layer, region, or substrate is described as being on a second component, it should be understood that the first component is directly on the second component or a third component is interposed therebetween. On the other hand, when a first component is described as being "directly located on" a second component, it should be understood that any intermediate components are not interposed therebetween.

[0078] Figure 1 is a schematic perspective view showing a power semiconductor device 100 - 1 according to an embodiment of the present disclosure, Figure 2 It shows that along Figure 1 A plan view of the power semiconductor device 100 - 1 taken along line II-II, Figure 3 It shows that along Figure 2 A cross-sectional view of the power semiconductor device 100 - 1 taken along line III-III, Figure 4 It shows that along Figure 2 A cross-sectional view of the power semiconductor device 100 - 1 taken along line IV-IV, Figure 5 It shows that along Figure 2 A cross-sectional view of the power semiconductor device 100 - 1 taken along line VV of FIG. Figure 6 It shows that along Figure 2 1 is a cross-sectional view of the power semiconductor device 100 - 1 taken along line VI-VI.

[0079] refer to Figures 1 to 6 The power semiconductor device 100-1 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-1 may have a power MOSFET structure.

[0080] The semiconductor layer 105 may refer to one or more semiconductor material layers, and may refer to, for example, one or more epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0081] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). Specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0082] Silicon carbide (SiC) can have a wider band gap than silicon, and thus can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, the power semiconductor device 100-2 using silicon carbide as the semiconductor layer 105 exhibits stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0083] Specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0084] Furthermore, the drift region 107 may include at least one protruding portion 107a disposed below the gate electrode layer 120. The protruding portion 107a may provide a vertical movement path of charges during operation of the power semiconductor device 100-1.

[0085] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in drift region 107 .

[0086] For example, the well region 110 may include: a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. In essence, the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and specifically, may be in contact with the sidewall of the first well region 110a.

[0087] Source region 112 may be formed in well region 110 and may have a first conductivity type. For example, source region 112 may be formed by doping well region 110 with impurities of the first conductivity type. Source region 112 may be formed by doping impurities of the first conductivity type having a higher concentration than drift region 107.

[0088] For example, the source region 112 may include a first source region 112a formed in the first well region 110a and a second source region 112b formed in the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed below the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0089] The second source region 112b may include a source contact region 113 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 113 may be a portion of the second source region 112b, and may refer to a portion to which the source electrode layer 140 is connected.

[0090] Well contact region 114 may be formed in second source region 112b, specifically, in source contact region 113. For example, well contact region 114 may extend from second well region 110b through second source region 112b and may have the second conductivity type. One or more well contact regions 114 may be formed in source contact region 113.

[0091] Well contact region 114 may be connected to source electrode layer 140. When connected to source electrode layer 140, well contact region 114 may be formed by doping impurities of the second conductivity type having a higher concentration than well region 110 to reduce contact resistance.

[0092] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 110c may have the second conductivity type so that an inversion channel is formed.

[0093] Because the channel region 110c has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110c, the source region 112, and the drift region 107 may form a diode junction. Therefore, the channel region 110c may not allow the movement of charges under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein to allow the movement of charges.

[0094] For example, the channel region 110c may be a part of the well region 110, in which case the channel region 110c may be formed to be continuously connected to the well region 110a. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as the doping concentration of the other parts of the well region 110, or may be different therefrom for adjusting the threshold voltage.

[0095] In some embodiments, the drift region 107, the first well region 110a, the channel region 110c and / or the protruding portion 107a of the first source region 112a may extend in one direction. Figure 2 The direction of line VV or line VI-VI can be one direction.

[0096] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be symmetrically formed based on the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed on the semiconductor layer 105 on opposite sides of the protruding portion 107a of the drift region 107, respectively.

[0097] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a, the sidewalls of which are surrounded by the first well region 110a. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In this case, the protruding portions 107a may extend side by side in one direction.

[0098] In addition, the first source region 112a may be formed in a stripe pattern in the first well region 110a. A channel region 110c may be formed between the protruding portion 107a and the first source region 112a.

[0099] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the drift region 107 and the protruding portion 107a of the channel region 110c may be formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0100] In addition, the first well region 110a and the second well region 110b may be repeatedly and alternately formed in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

[0101] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration than the drift region 107 .

[0102] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or a substrate separated from the semiconductor layer 105 .

[0103] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. Specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0104] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stack structure thereof.

[0105] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. Specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. In addition, the second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0106] For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, metal silicide, etc., or may include a stack structure thereof.

[0107] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide layer, a nitride layer, or a stack structure thereof.

[0108] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, specifically, the second source region 112b. In addition, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, etc.

[0109] In the power semiconductor device 100-1, the first conductivity type and the second conductivity type may have opposite conductivity types, but may be any one of N type and P type, respectively. For example, when the first conductivity type is N type, the second conductivity type is P type, and vice versa.

[0110] Specifically, when the power semiconductor device 100 - 1 is an N-type MOSFET, the drift region 107 may be an N region, the source region 112 and the drain region 102 may be N+ regions, the well region 110 and the channel region 110 c may be P regions, and the well contact region 114 may be a P+ region.

[0111] During operation of the power semiconductor device 100 - 1 , current may generally flow from the drain region 102 in a vertical direction along the protruding portion 107 a of the drift region 107 , and may then flow through the channel region 110 c to the source region 112 .

[0112] In the above-described power semiconductor device 100-1, the source contact region 113 and the well contact region 114 may be respectively disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed such that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed under the gate electrode layer 120. Therefore, the power semiconductor device 100-1 may have a high degree of integration.

[0113] Figures 7 to 10 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 1 according to an embodiment of the present disclosure.

[0114] refer to Figure 7 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0115] Subsequently, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0116] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes at least one protruding portion 107a surrounded by at least a portion of the well region 110. Specifically, the well region 110 may be formed by doping the drift region 107 with impurities having a conductivity type opposite to that of the drift region 107.

[0117] The well region 110 may be divided into a first well region 110a where a channel region 110c is to be formed and a second well region 110b where a well contact region 114 is to be formed. For example, the first well region 110a may define a protruding portion 107a of the drift region 107. The first well region 110a and the second well region 110b may be connected to each other.

[0118] refer to Figure 8 , a source region 112 having the first conductivity type may be formed in the well region 110. For example, the formation of the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110.

[0119] For example, the formation of the source region 112 may include forming a first source region 112a in the first well region 110a and forming a second source region 112b in the second well region 110b. A portion of the second source region 112b may be allocated as a source contact region 113 to connect to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other.

[0120] In addition to the formation of the source region 112, a channel region 110c having a second conductivity type may be formed to form an inversion channel in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0121] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting a portion of the well region 110 with second conductivity type impurities to a higher concentration than the well region 110.

[0122] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed when the impurities are implanted into the semiconductor layer 105 or when the epitaxial layer is formed. However, in order to implant impurities in a selective region, an ion implantation method using a mask pattern may be used.

[0123] Optionally, after the ion implantation, heat treatment for activating or diffusing the impurities may be subsequently performed.

[0124] refer to Fig. 9The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0125] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105 .

[0126] Subsequently, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0127] The patterning process may be performed using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer using a photolithography process and a development process. The etching process may include a process of selectively etching an underlying structure using the photoresist pattern.

[0128] refer to Fig.10 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Alternatively, when the interlayer insulating layer 130 is completely formed on the underlying structure, a process of forming a contact hole pattern for exposing the source contact region 113 and the well contact region 114 may be subsequently performed.

[0129] Subsequently, source electrode layer 140 may be formed on semiconductor layer 105 to be connected to second source region 112b and well contact region 114. For example, source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0130] According to the above-described manufacturing method, a highly integrated power semiconductor device 100 - 1 can be economically manufactured by using the semiconductor layer 105 of silicon carbide in a process used in an existing silicon substrate.

[0131] Fig.11 is a schematic perspective view showing a power semiconductor device 100 - 2 according to an embodiment of the present disclosure, Fig.12 It is shown along Fig.11 A plan view of the power semiconductor device 100 - 2 taken along line II-II, Fig.13 It is shown along Fig.12 A cross-sectional view of the power semiconductor device 100 - 2 taken along line III-III, Fig.14 It is shown along Fig.12 A cross-sectional view of the power semiconductor device 100 - 2 taken along line IV-IV of FIG. 1 , and Fig.15 It is shown along Fig.12 1 is a cross-sectional view of the power semiconductor device 100 - 2 taken along line VV.

[0132] refer to Figures 11 to 15 The power semiconductor device 100-2 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-2 may have a power MOSFET structure.

[0133] The semiconductor layer 105 may refer to one or more semiconductor material layers, and may refer to, for example, one or more epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0134] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). Specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0135] Silicon carbide (SiC) can have a wider band gap than silicon, and thus can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, the power semiconductor device 100-2 using silicon carbide as the semiconductor layer 105 exhibits stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0136] Specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0137] The drift region 107 may provide a vertical movement path of charges. In addition, the drift region 107 may include at least one protruding portion 107a disposed below the gate electrode layer 120. The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105.

[0138] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in semiconductor layer 105 or drift region 107.

[0139] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. In essence, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and specifically, may be in contact with the sidewall of the first well region 110a.

[0140] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping impurities of the first conductivity type having a higher concentration than the drift region 107.

[0141] For example, the source region 112 may include a first source region 112a formed on or in the first well region 110a and a second source region 112b formed on or in the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed below the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0142] The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 112b1 may be a portion of the second source region 112b, and may refer to a portion to which the source electrode layer 140 is connected.

[0143] The avalanche sensing region 115 may be formed to contact the drift region 107 through the second well region 110b and may be formed to have the second conductivity type. The avalanche sensing region 115 may be doped with impurities of the second conductivity type having a higher concentration than the well region 110. The avalanche sensing region 115 may be connected to the source electrode layer 140.

[0144] Well contact region 114 may be formed in second source region 112b, specifically, in source contact region 112b1. For example, well contact region 114 may be connected to second well region 110b through second source region 112b and may have a second conductivity type. One or more well contact regions 114 may be formed in source contact region 112b1.

[0145] Well contact region 114 may be connected to source electrode layer 140. When connected to source electrode layer 140, well contact region 114 may be formed by doping impurities of the second conductivity type having a higher concentration than well region 110 to reduce contact resistance.

[0146] In some embodiments, the well contact region 114 and the avalanche sensing region 115 may be formed as an integrated structure. In this case, the well contact region 114 refers to a component connecting the second well region 110b and the source electrode layer 140 in the integrated structure. The avalanche sensing region 115 may refer to a portion connected to the well contact region 114 or the source electrode layer 140 while contacting the drift region 107 in the integrated structure.

[0147] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0148] For example, the channel region 110c may have a second conductivity type so that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c, the source region 112, and the drift region 107 may form a diode junction. Therefore, the channel region 110c may not allow the movement of charges under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein to allow the movement of charges.

[0149] For example, the channel region 110c may be a portion of the well region 110. In detail, the channel region 110c may be a portion of the well region 110 adjacent to the lower portion of the gate electrode layer 120. In this case, the channel region 110c may be formed to be integrally or continuously connected to the well region 110a. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as the doping concentration of the other portions of the well region 110, or may be different therefrom, for adjusting the threshold voltage.

[0150] In some embodiments, the drift region 107, the first well region 110a, the channel region 110c and / or the protruding portion 107a of the first source region 112a may extend in one direction. Fig.12 The direction of the line IV-IV may be one direction. The extending direction of the channel region 110c does not mean the moving direction of the charges.

[0151] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed on the semiconductor layer 105 on opposite sides of the protruding portion 107a of the drift region 107, respectively.

[0152] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a formed parallel to each other in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In addition, the first source region 112a may be formed in a stripe pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0153] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0154] In addition, the first well region 110a and the second well region 110b may be repeatedly and alternately formed in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

[0155] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration than the drift region 107 .

[0156] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or a substrate separated from the semiconductor layer 105 .

[0157] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. Specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0158] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stack structure thereof.

[0159] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. Specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. In addition, the second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0160] For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, metal silicide, etc., or may include a stack structure thereof.

[0161] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide layer, a nitride layer, or a stack structure thereof.

[0162] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, specifically, the second source region 112b or the source contact region 112b1. In addition, the source electrode layer 140 may be commonly connected to the second source region 112b, the well contact region 114, and the avalanche sensing region 115. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0163] In the above power semiconductor device 100 - 2 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be any one of N type and P type, respectively. For example, when the first conductivity type is N type, the second conductivity type is P type, and vice versa.

[0164] Specifically, when the power semiconductor device 100 - 2 is an N-type MOSFET, the drift region 107 may be an N region, the source region 112 and the drain region 102 may be N+ regions, the well region 110 and the channel region 110 c may be P regions, and the well contact region 114 and the avalanche induction region 115 may be P+ regions.

[0165] During operation of the power semiconductor device 100 - 2 , current may generally flow from the drain region 102 in a vertical direction along the protruding portion 107 a of the drift region 107 , and may then flow through the channel region 110 c to the source region 112 .

[0166] In the power semiconductor device 100-2, the source contact region 112b1, the well contact region 114, and the avalanche induction region 115 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed under the gate electrode layer 120. Therefore, the power semiconductor device 100-2 may have a high degree of integration.

[0167] In the power semiconductor device 100-2, when latch occurs in the power semiconductor device 100-2, the avalanche induction region 115 has avalanche breakdown. The edge portion of the first well region 110a is a weak portion due to the concentration of the electric field. When avalanche breakdown occurs through the edge portion, a problem of abnormally increased current occurs.

[0168] like Fig.24 As shown, it can be seen that a higher electric field is applied in the junction structure G1 of the avalanche induction region 115 and the drift region 107 than in the junction structure G2 of the first well region 110a and the drift region 107. Therefore, before avalanche breakdown occurs through the first well region 110a, avalanche breakdown can be induced to the second well region 110b through the avalanche induction region 115. The avalanche current can flow to the ground through the source electrode layer 140.

[0169] Therefore, the occurrence of avalanche breakdown in the first well region 110a can be suppressed, thereby suppressing the occurrence of latch-up. Therefore, the operation reliability of the power semiconductor device 100-2 can be increased.

[0170] Figures 16 to 20 1 is a cross-sectional view showing power semiconductor devices 100a-2, 100b-2, 100c-2, 100d-2, and 100e-2 according to other embodiments of the present disclosure. The power semiconductor devices 100a-2, 100b-2, 100c-2, 100d-2, and 100e-2 are partially modified or added to Figures 11 to 15 The power semiconductor device 100 - 2 of the present invention is described herein, and thus these embodiments may be referred to as one another, and redundant descriptions are omitted.

[0171] refer to Fig.16 , the power semiconductor device 100a-2 may include at least one trench 138 penetrating the second source region 112b and exposing the second well region 110b. The trench 138 may be formed to expose the surface of the second well region 110b or to be recessed so that the second well region 110b has a certain depth.

[0172] The well contact region 114a may be formed under the trench 138 to contact the second well region 110b. For example, a sidewall of the well contact region 114a may contact the second well region 110b. The avalanche induction region 115a may be formed to contact the drift region 107 under the groove 138.

[0173] For example, the well contact region 114a and the avalanche induction region 115a may be formed by doping high-concentration impurities of the second conductivity type from the second well region 110b exposed to a certain depth of the drift region 107 through the trench 138. The avalanche induction region 115a may be formed to be recessed to a certain depth in the drift region 107.

[0174] The source electrode layer 140 may be formed to fill the groove 138 and thus may be connected to the well contact region 114a, the avalanche sensing region 115a, the second well region 110b and / or the second source region 112b. For example, the avalanche sensing region 115a and the well contact region 114a may be formed as an integrated structure in contact with the drift region 107, the second well region 110b and the source electrode layer 140.

[0175] In some embodiments, the well contact region 114a may be completely formed on the surface of the second well region 110b exposed to the trench 138. Therefore, the well contact region 114a may be formed on the second well region 110b to be exposed to the bottom and sidewall of the trench 138. The structure of the well contact region 114a may further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0176] refer to Fig.17 , the power semiconductor device 100b-2 can represent Fig.15 In the power semiconductor device 100 b - 2 , the avalanche induction region 115 and the well contact region 114 may be formed to be separated from each other.

[0177] For example, the well contact region 114 may be formed to pass through the second source region 112b and be connected to the second well region 110b. The avalanche sensing region 115 may be formed to pass through the second source region 112b and the second well region 110b and contact the drift region 107. The avalanche sensing region 115 and the well contact region 114 may be commonly connected to the source electrode layer 140.

[0178] refer to Fig.18 In the power semiconductor device 100c-2, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type so that an accumulation channel is formed.

[0179] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 may have a structure that is generally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated when carbon clusters are formed in the gate insulating layer 118, the band of the channel region 107b is bent upward, resulting in a potential barrier. Therefore, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows the flow of charge or current may be formed in the channel region 107b.

[0180] Therefore, a threshold voltage to be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107 b may be significantly lower than a threshold voltage to be applied to the gate electrode layer 120 to form a conventional inversion channel.

[0181] In some embodiments, the channel region 107b may be a part of the drift region 107. Specifically, the channel region 107b may be a part of the protruding portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107.

[0182] The drift region 107 may be connected to the source region 112 through the channel region 107b. Specifically, in the channel region 107b, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other.

[0183] For example, the doping concentration of the first conductivity type impurities in the channel region 107 b may be the same as that of other portions of the drift region 107 , or may be different therefrom, for adjusting the threshold voltage.

[0184] In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend to the trench portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed thereon. This structure may allow the channel region 107b to be defined between the gate electrode layer 120 and the well region 110.

[0185] In some embodiments, the first well region 110a and the first source region 112a may have the same width. In this case, the first source region 112a may contact the protruding portion 107a of the drift region 107, and the channel region 107b may be defined at a portion contacting the protruding portion 107a.

[0186] refer to Fig.19In the power semiconductor device 100d-2, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a tab portion extending toward the gate electrode layer 120 at its end.

[0187] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a curved shape on the protruding portion and the tab portion of the first well region 110a. This structure may allow the channel region 107b1 to be more confined between the gate electrode layer 120 and the first well region 110a.

[0188] refer to Fig. 20 In the power semiconductor device 100e-2, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a convex portion extending at its end toward the gate electrode layer 120. In addition, the protruding portion 107a of the drift region 107 may further extend between the lower portion of the first source region 112a and the first well region 110a.

[0189] The channel region 107b2 may be formed to further extend into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a curved shape from the upper portion of the convex portion of the first well region 110a to the lower portion of the first source region 112a. This structure may help widen the contact area between the channel region 107b2 and the first source region 112a.

[0190] Figure 21 to Figure 23 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 2 according to an embodiment of the present disclosure.

[0191] refer to Fig.21 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC) to provide a vertical movement path for charges. For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may serve as a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0192] Subsequently, a well region 110 having a second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107. In detail, the well region 110 may be formed on the semiconductor layer 105 to contact the protruding portion 107a to define at least one protruding portion 107a of the drift region 107. Specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with impurities of a conductivity type opposite to that of the drift region 107 (e.g., impurities of the second conductivity type).

[0193] The well region 110 may be divided into a first well region 110a under the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a may define a protruding portion 107a of the drift region 107, and a well contact region 114 may be formed later in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0194] In addition, source region 112 having the first conductivity type may be formed on or in well region 110. For example, the formation of source region 112 may be performed by implanting impurities of the first conductivity type into well region 110 or into semiconductor layer 105.

[0195] For example, the formation of the source region 112 may include forming the first source region 112a on or in the first well region 110a and forming the second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be allocated as a source contact region 112b1 to connect to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed substantially from the surface of the semiconductor layer 105 into or above the well region 110, with a certain depth.

[0196] In addition to the formation of the source region 112, a channel region 110c having a second conductivity type may be formed to form an inversion channel in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c as a part of the first well region 110a may not be formed separately but may be formed together with the first well region 110a.

[0197] In addition, the avalanche induction region 115 may be formed by doping impurities of the second conductivity type having a higher concentration than the well region 110 to contact the drift region 107 through the second well region 110 b .

[0198] In addition, a well contact region 114 connected to the second well region 110b may be formed in the second source region 112b through the second source region 112b. For example, the well contact region 114 may be formed by implanting impurities of the second conductivity type into a portion of the second well region 110b to make it higher in concentration than the well region 110.

[0199] In a modified example of this embodiment, the impurity doping sequence of the well region 110 , the source region 112 , the channel region 110 c , the well contact region 114 , and the avalanche inducing region 115 may be appropriately changed.

[0200] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed when the impurities are implanted into the semiconductor layer 105 or when the epitaxial layer is formed. However, in order to implant impurities in a selective region, an ion implantation method using a mask pattern may be used.

[0201] Optionally, after the ion implantation, heat treatment for activating or diffusing the impurities may be subsequently performed.

[0202] refer to Fig.21 The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0203] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105 .

[0204] Subsequently, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0205] The patterning process may be performed using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer using a photolithography process and a development process. The etching process may include a process of selectively etching an underlying structure using the photoresist pattern.

[0206] refer to Fig. 22 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Alternatively, when the interlayer insulating layer 130 is completely formed on the underlying structure, a process of forming a contact hole pattern for exposing the source contact region 113 and the well contact region 114 may be subsequently performed.

[0207] Subsequently, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b, the well contact region 114, and the avalanche induction region 115. For example, the source electrode layer 140 may be formed by forming a conductive layer (e.g., a metal layer) on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0208] at the same time, Fig.16 The power semiconductor device 100 a - 2 may be manufactured by adding or modifying some processes to the manufacturing process of the power semiconductor device 100 - 2 described above.

[0209] Fig.16 The manufacturing of the power semiconductor device 100a-2 may also include forming at least one trench 138 through the second source region 112b and exposing the second well region 110b in the second source region 112b, forming a well contact region 114a in contact with the second well region 110b and an avalanche induction region 115a in contact with the drift region 107 below the trench 138, and filling the trench 138 to form a source electrode layer 140 to be connected to the source region 112, the well contact region 114 and the avalanche induction region 115a.

[0210] At the same time, when manufacturing Figures 18 to 20 When the power semiconductor devices 100 c - 2 , 100 d - 2 , and 100 e - 2 are formed, the channel regions 107 b , 107 b 1 , and 107 b 2 may have the first conductivity type to form an accumulation channel. For example, the channel regions 107 b , 107 b 1 , and 107 b 2 may be formed as part of the drift region 107 .

[0211] According to the above-described manufacturing method, a highly integrated power semiconductor device 100 - 2 can be economically manufactured by using the semiconductor layer 105 of silicon carbide in a process used in an existing silicon substrate.

[0212] Fig.25 is a schematic perspective view showing a power semiconductor device 100 - 3 according to an embodiment of the present disclosure, Fig.26 It is shown along Fig.25 A plan view of the power semiconductor device 100 - 3 taken along line II-II, Fig. 27 It is shown along Fig.26 A cross-sectional view of the power semiconductor device 100 - 3 taken along line III-III of FIG. 1 , and Fig.28 It is shown along Fig.26 1 is a cross-sectional view of the power semiconductor device 100 - 3 taken along line IV-IV.

[0213] refer to Figure 25 to Figure 28The power semiconductor device 100-3 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-3 may have a power MOSFET structure.

[0214] The semiconductor layer 105 may refer to one or more semiconductor material layers, and may refer to, for example, one or more epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0215] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). Specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0216] Silicon carbide (SiC) can have a wider band gap than silicon, and thus can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, the power semiconductor device 100-3 using silicon carbide as the semiconductor layer 105 exhibits stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0217] Specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0218] The drift region 107 may provide a vertical movement path of charges. In addition, the drift region 107 may include at least one protruding portion 107a disposed below the gate electrode layer 120. The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105.

[0219] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in semiconductor layer 105 or drift region 107.

[0220] For example, the well region 110 may include: a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. In essence, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and specifically, may be in contact with the sidewall of the first well region 110a.

[0221] A stud region 111 having a conductivity type different from that of the drift region 107 may be formed in the semiconductor layer 105 to form a super junction with the drift region 107. For example, the stud region 111 may have a second conductivity type and may be formed in the semiconductor layer 105 under the well region 110 to contact the well region 110.

[0222] For example, the stud region 111 may be formed to contact or surround a sidewall of the drift region 107. As another example, a plurality of stud regions 111 may be provided, and the stud regions 111 and the drift region 107 may be alternately formed and may contact each other.

[0223] In some embodiments, the pillar region 111 may have a width narrower than that of the well region 110 to expose at least a portion of the bottom surface of the well region 110, and may be shortened inward from an end of the well region 110 to be formed under the well region 110. Therefore, the well region 110 may be formed to protrude further toward the protruding portion 107a of the drift region 107 than the pillar region 111.

[0224] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping impurities of the first conductivity type having a higher concentration than the drift region 107.

[0225] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed below the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0226] The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 112b1 may be a portion of the second source region 112b, and may refer to a portion to which the source electrode layer 140 is connected.

[0227] Well contact region 114 may be formed in second source region 112b, specifically, in source contact region 112b1. For example, well contact region 114 may extend from second well region 110b through second source region 112b and may have the second conductivity type. One or more well contact regions 114 may be formed in source contact region 112b1.

[0228] Well contact region 114 may be connected to source electrode layer 140. When connected to source electrode layer 140, well contact region 114 may be formed by doping impurities of the second conductivity type having a higher concentration than well region 110 to reduce contact resistance.

[0229] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0230] For example, the channel region 110c may have a second conductivity type so that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c, the source region 112, and the drift region 107 may form a diode junction. Therefore, the channel region 110c may not allow the movement of charges under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein to allow the movement of charges.

[0231] For example, the channel region 110c may be a part of the well region 110. In detail, the channel region 110c may be a part of the well region 110 adjacent to the lower portion of the gate electrode layer 120 of the well region 110. In this case, the channel region 110c may be formed to be integrally or continuously connected to the well region 110a. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as the doping concentration of the other parts of the well region 110, or may be different therefrom, for adjusting the threshold voltage.

[0232] In some embodiments, the drift region 107, the first well region 110a, the channel region 110c and / or the protruding portion 107a of the first source region 112a may extend in one direction. Fig.26 The direction of the line IV-IV may be one direction. Here, the extending direction of the channel region 110c does not mean the moving direction of the charges.

[0233] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be respectively formed on the semiconductor layer 105 on opposite sides of the protruding portion 107a of the drift region 107. In addition, a pillar region 111 may be further formed under the first well region 110a on opposite sides of the protruding portion 107a of the drift region 107.

[0234] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a formed parallel to each other in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In addition, the first source region 112a may be formed in a stripe pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0235] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0236] In addition, the first well region 110a and the second well region 110b may be repeatedly and alternately formed in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

[0237] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration than the drift region 107 .

[0238] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or a substrate separated from the semiconductor layer 105 .

[0239] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. Specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0240] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stack structure thereof.

[0241] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. Specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0242] For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, metal silicide, etc., or may include a stack structure thereof.

[0243] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide layer, a nitride layer, or a stack structure thereof.

[0244] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, specifically, the second source region 112b or the source contact region 112b1. In addition, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, etc.

[0245] In the above power semiconductor device 100 - 3 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be any one of N type and P type, respectively. For example, when the first conductivity type is N type, the second conductivity type is P type, and vice versa.

[0246] Specifically, when the power semiconductor device 100 - 3 is an N-type MOSFT, the drift region 107 may be an N region, the source region 112 and the drain region 102 may be N+ regions, the well region 110 , the channel region 110 c and the column region 111 may be P- regions, and the well contact region 114 may be a P+ region.

[0247] During operation of the power semiconductor device 100 - 3 , current may generally flow from the drain region 102 in a vertical direction along the protruding portion 107 a of the drift region 107 , and may then flow through the channel region 110 c to the source region 112 .

[0248] In the above-described power semiconductor device 100-3, the source contact region 112b and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed such that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed under the gate electrode layer 120. Therefore, the power semiconductor device 100-3 may have a high degree of integration.

[0249] At the same time, the power semiconductor device 100-3 is required to have a high withstand voltage characteristic because it is used for high power switching. When a high voltage is applied to the drain region 102, a depletion region may extend from the semiconductor layer 105 adjacent to the drain region 102, and thus the voltage barrier of the channel may be reduced. This phenomenon is called drain induced barrier lowering (DIBL).

[0250] The DIBL may cause abnormal conduction of the channel region 110 c , and further cause a punch-through phenomenon in which a depletion layer between the drain region 102 and the source region 112 expands and contacts each other.

[0251] However, the power semiconductor device 100-3 described above can reduce the resistance of the drift region 107 and the channel region 110c using the pillar region 111 forming a super junction with the drift region 107, and can suppress the abnormal current flow and punch-through phenomenon caused by DIBL to ensure appropriate withstand voltage characteristics. Therefore, although the thickness of the drift region 107 constituting the body is reduced, a high breakdown voltage can be maintained.

[0252] The breakdown voltage characteristics may be further improved by adjusting the amount of charges in the stud region 111 and the amount of charges in the drift region 107 .

[0253] Fig.36 is a graph showing a change in electric field depending on the depth of the power semiconductor device 100 - 3 according to an embodiment of the present disclosure. Fig.36 In FIG. 1 , the position of “A” indicates the surface of the first well region 110 a , the position of “B” indicates the bottom surface of the column region 111 , and the position of “C” indicates the bottom surface of the drift region 107 .

[0254] refer to Fig.36 When the amount of charge Qp of the pillar region 111 is greater than the amount of charge Qn of the drift region 107, a maximum electric field during operation of the power semiconductor device 100-3 may be generated in the drift region 107 on the same line as the bottom surface of the pillar region 111, thereby increasing the breakdown voltage. Fig.36 In the embodiment, the slope of the electric field strength between the “A” position and the “B” position can be controlled by adjusting the charge Qp of the pillar region 111 .

[0255] For example, the doping concentration of the second conductive type impurity in the column region 111 may be higher than the doping concentration of the first conductive type impurity in the drift region 107, thereby adjusting the charge balance. Therefore, the field applied to the gate insulating layer 118 may be reduced and the DIBL margin may be increased by charge balance adjustment, thereby improving the withstand voltage characteristics of the power semiconductor device 100-3.

[0256] Therefore, according to the above-described power semiconductor device 100 - 3 , while increasing the channel density to increase the integration degree, the breakdown voltage can be maintained, thereby reducing the operating loss.

[0257] Figure 29 to Figure 32 1 is a cross-sectional view showing power semiconductor devices 100a-3, 100b-3, 100c-3, and 100d-3 according to other embodiments of the present disclosure. The power semiconductor devices 100a-3, 100b-3, 100c-3, and 100d-3 are partially modified or added to Figure 25 to Figure 28 The power semiconductor device 100 - 3 of the present invention is described above, and thus these embodiments may be referred to as one another, and redundant descriptions are omitted.

[0258] refer to Fig.29 , the power semiconductor device 100a-3 may include at least one trench 138 penetrating the second source region 112b and exposing the second well region 110b. The trench 138 may be formed to expose the surface of the second well region 110b or to be recessed so that the second well region 110b has a specific depth. The well contact region 114a may be formed on at least the bottom surface of the groove 138 to contact the second well region 110b.

[0259] Source electrode layer 140 may be formed to fill groove 138 and thus may be connected to well contact region 114a, second well region 110b and / or second source region 112b. This structure may help reduce contact resistance between source electrode layer 140 and second well region 110b and second source region 112b by increasing the contact area therebetween.

[0260] In some embodiments, the well contact region 114a may be completely formed on the surface of the second well region 110b exposed to the trench 138. Therefore, the well contact region 114a may be formed on the second well region 110b to be exposed to the bottom and sidewall of the trench 138. The structure of the well contact region 114a may further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0261] refer to Fig.30 In the power semiconductor device 100b-3, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type so that an accumulation channel is formed.

[0262] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 may have a structure that is generally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated when carbon clusters are formed in the gate insulating layer 118, the band of the channel region 107b is bent upward, resulting in a potential barrier. Therefore, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows the flow of charge or current may be formed in the channel region 107b.

[0263] Therefore, a threshold voltage to be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107 b may be significantly lower than a threshold voltage to be applied to the gate electrode layer 120 to form a conventional inversion channel.

[0264] In some embodiments, the channel region 107b may be a part of the drift region 107. Specifically, the channel region 107b may be a part of the protruding portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107.

[0265] The drift region 107 may be connected to the source region 112 through the channel region 107b. Specifically, in the channel region 107b, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other.

[0266] For example, the doping concentration of the first conductivity type impurities in the channel region 107 b may be the same as that of other portions of the drift region 107 , or may be different therefrom, for adjusting the threshold voltage.

[0267] In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend to the trench portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed thereon. This structure may allow the channel region 107b to be defined between the gate electrode layer 120 and the well region 110.

[0268] In some embodiments, the first well region 110a and the first source region 112a may have the same width. In this case, the first source region 112a may contact the protruding portion 107a of the drift region 107, and the channel region 107b may be defined at a portion contacting the protruding portion 107a.

[0269] refer to Fig.31In the power semiconductor device 100 c - 3 , the first well region 110 a may further protrude from the first source region 112 a toward the protruding portion 107 a of the drift region 107 , and may include a tab portion extending toward the gate electrode layer 120 at a distal end thereof.

[0270] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a curved shape on the protruding portion and the tab portion of the first well region 110a. This structure may allow the channel region 107b1 to be more confined between the gate electrode layer 120 and the first well region 110a.

[0271] refer to Fig.32 In the power semiconductor device 100d-3, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a convex portion extending at its end toward the gate electrode layer 120. In addition, the protruding portion 107a of the drift region 107 may further extend between the lower portion of the first source region 112a and the first well region 110a.

[0272] The channel region 107b2 may be formed to further extend into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a curved shape from the upper portion of the convex portion of the first well region 110a to the lower portion of the first source region 112a. This structure may help widen the contact area between the channel region 107b2 and the first source region 112a.

[0273] Figure 33 to Figure 35 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 3 according to an embodiment of the present disclosure.

[0274] refer to Fig.33 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC) to provide a vertical movement path for charges. For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may serve as a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0275] Subsequently, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0276] In detail, the well region 110 may be formed on the semiconductor layer 105 in contact with the protruding portion 107a to define at least one protruding portion 107a of the drift region 107. Specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with impurities of a conductivity type opposite to that of the drift region 107.

[0277] The well region 110 may be divided into a first well region 110a under the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a may define a protruding portion 107a of the drift region 107, and a well contact region 114 may be formed later in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0278] The pillar region 111 may be formed in the semiconductor layer 105 below the well region 110 to contact the well region 110. The pillar region 111 may have the second conductivity type to form a super junction with the drift region 107. For example, the pillar region 111 may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 or the drift region 107.

[0279] In addition, source region 112 having the first conductivity type may be formed on or in well region 110. For example, the formation of source region 112 may be performed by implanting impurities of the first conductivity type into well region 110 or into semiconductor layer 105.

[0280] For example, the formation of the source region 112 may include forming the first source region 112a on or in the first well region 110a and forming the second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be allocated as a source contact region 112b1 to connect to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed substantially from the surface of the semiconductor layer 105 into or above the well region 110, with a certain depth.

[0281] In addition to the formation of the source region 112, a channel region 110c having a second conductivity type may be formed to form an inversion channel in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c as a part of the first well region 110a may not be formed separately but may be formed together with the first well region 110a.

[0282] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than the well region 110 into a portion of the well region 110.

[0283] In a modified example of this embodiment, the impurity doping order of the well region 110 , the pillar region 111 , the source region 112 , the channel region 110 c , and the well contact region 114 may be appropriately changed.

[0284] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed when the impurities are implanted into the semiconductor layer 105 or when the epitaxial layer is formed. However, in order to implant impurities in a selective region, an ion implantation method using a mask pattern may be used.

[0285] Optionally, after the ion implantation, heat treatment for activating or diffusing the impurities may be subsequently performed.

[0286] refer to Fig.34 The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0287] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105 .

[0288] Subsequently, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0289] The patterning process may be performed using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer using a photolithography process and a development process. The etching process may include a process of selectively etching an underlying structure using the photoresist pattern.

[0290] refer to Fig.35 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Alternatively, when the interlayer insulating layer 130 is completely formed on the underlying structure, a process of forming a contact hole pattern for exposing the source contact region 113 and the well contact region 114 may be subsequently performed.

[0291] Subsequently, source electrode layer 140 may be formed on semiconductor layer 105 to be connected to second source region 112b and well contact region 114. For example, source electrode layer 140 may be formed by forming a conductive layer such as a metal layer on interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0292] at the same time, Fig.29 The power semiconductor device 100 a - 3 may be manufactured by adding or modifying some processes to the manufacturing process of the power semiconductor device 100 - 3 described above.

[0293] Fig.29 The manufacture of the power semiconductor device 100a-3 may also include: forming at least one trench 138 through the second source region 112b and exposing the second well region 110b in the second source region 112b; forming a well contact region 114 to contact the well region 110 on the bottom surface of the trench 138; and filling the trench 138 to form a source electrode layer 140 to be connected to the source region 112 and the well contact region 114.

[0294] At the same time, when manufacturing Figure 30 to Figure 32 When the power semiconductor devices 100 b - 3 , 100 c - 3 , and 100 d - 3 are formed, the channel regions 107 b , 107 b 1 , and 107 b 2 may have the first conductivity type to form an accumulation channel. For example, the channel regions 107 b , 107 b 1 , and 107 b 2 may be formed as part of the drift region 107 .

[0295] According to the above-described manufacturing method, a highly integrated power semiconductor device 100 - 3 can be economically manufactured by using the semiconductor layer 105 of silicon carbide in a process used in an existing silicon substrate.

[0296] Fig.37 is a schematic perspective view showing a power semiconductor device 100 - 4 according to an embodiment of the present disclosure, Fig.38 It is shown along Fig.37 A plan view of the power semiconductor device 100 - 4 taken along line II-II, Fig.39 It is shown along Fig.38 A cross-sectional view of the power semiconductor device 100 - 4 taken along line III-III, Fig.40 It is shown along Fig.38 A cross-sectional view of the power semiconductor device 100 - 4 taken along line IV-IV of FIG. 1 , and Fig.41 It is shown along Fig.38 1 is a cross-sectional view of the power semiconductor device 100 - 4 taken along line VV.

[0297] refer to Figures 37 to 41The power semiconductor device 100-4 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-4 may have a power MOSFET structure.

[0298] The semiconductor layer 105 may refer to one or more semiconductor material layers, and may refer to, for example, one or more epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0299] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). Specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0300] Silicon carbide (SiC) can have a wider band gap than silicon, and thus can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, the power semiconductor device 100-4 using silicon carbide as the semiconductor layer 105 exhibits stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0301] Specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0302] The drift region 107 may provide a vertical movement path of charges. In addition, the drift region 107 may include at least one protruding portion 107a disposed below the gate electrode layer 120. The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105.

[0303] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in semiconductor layer 105 or drift region 107.

[0304] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. In essence, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and specifically, may be in contact with the sidewall of the first well region 110a.

[0305] The deep well region 111 may be formed in the semiconductor layer 105 below the well region 110, and its conductivity type is different from the conductivity type of the drift region 107. For example, the deep well region 111 may have the same second conductivity type as the well region 110, and may be formed in the semiconductor layer 105 below the well region 110, contacting the well region 110 and the drift region 107. The impurity doping concentration of the second conductivity type in the deep well region 111 may be equal to or less than the impurity doping concentration of the second conductivity type in the well region 110.

[0306] For example, the deep well region 111 may be formed to contact or surround a sidewall of the drift region 107 below the well region 110. As another example, a plurality of deep well regions 111 may be provided and may be alternately formed to contact the drift region 107.

[0307] In some embodiments, the deep well region 111 may have a width narrower than that of the well region 110 to expose at least a portion of the bottom surface of the well region 110 in one direction. For example, opposite ends of the deep well region 111 may be shortened inwardly from opposite ends of the well region 110 in one direction and may be formed below the well region 110. The one direction may refer to Fig.38 Therefore, the well region 110 may be formed to protrude further toward the protruding portion 107 a of the drift region 107 than the deep well region 111 in one direction.

[0308] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping impurities of the first conductivity type having a higher concentration than the drift region 107.

[0309] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed below the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0310] The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 112b1 may be a portion of the second source region 112b, and may refer to a portion to which the source electrode layer 140 is connected.

[0311] Well contact region 114 may be formed in second source region 112b, specifically, in source contact region 112b1. For example, well contact region 114 may extend from second well region 110b through second source region 112b and may have the second conductivity type. One or more well contact regions 114 may be formed in source contact region 112b1.

[0312] Well contact region 114 may be connected to source electrode layer 140. When connected to source electrode layer 140, well contact region 114 may be formed by doping impurities of the second conductivity type having a higher concentration than well region 110 to reduce contact resistance.

[0313] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0314] For example, the channel region 110c may have a second conductivity type so that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c, the source region 112, and the drift region 107 may form a diode junction. Therefore, the channel region 110c may not allow the movement of charges under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein to allow the movement of charges.

[0315] For example, the channel region 110c may be a part of the well region 110. In detail, the channel region 110c may be a part of the well region 110 adjacent to the lower portion of the gate electrode layer 120 of the well region 110. In this case, the channel region 110c may be formed to be integrally or continuously connected to the well region 110a. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as the doping concentration of the other parts of the well region 110, or may be different therefrom, for adjusting the threshold voltage.

[0316] In some embodiments, the drift region 107, the first well region 110a, the channel region 110c and / or the protruding portion 107a of the first source region 112a may extend in one direction. When the first well region 110a extends in one direction, the deep well region 111 below the first well region 110a may also extend in one direction. Here, the extending direction of the channel region 110c does not mean the moving direction of the charges.

[0317] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be respectively formed on the semiconductor layer 105 on opposite sides of the protruding portion 107a of the drift region 107. In addition, a portion of the deep well region 111 may also be formed below the first well region 110a on opposite sides of the protruding portion 107a of the drift region 107.

[0318] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a formed parallel to each other in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In addition, the first source region 112a may be formed in a stripe pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0319] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0320] In addition, the first well region 110a and the second well region 110b may be repeatedly and alternately formed in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

[0321] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration than the drift region 107 .

[0322] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or a substrate separated from the semiconductor layer 105 .

[0323] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. Specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0324] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stack structure thereof.

[0325] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. Specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0326] For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, metal silicide, etc., or may include a stack structure thereof.

[0327] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide layer, a nitride layer, or a stack structure thereof.

[0328] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, specifically, the second source region 112b or the source contact region 112b1. In addition, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, etc.

[0329] In the power semiconductor device 100 - 4 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be either N-type or P-type, respectively. For example, when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.

[0330] Specifically, when the power semiconductor device 100-4 is an N-type MOSFT, the drift region 107 can be an N region, the source region 112 and the drain region 102 can be N+ regions, the well region 110, the channel region 110c and the deep well region 111 can be P regions, and the well contact region 114 can be a P+ region.

[0331] During operation of the power semiconductor device 100 - 4 , current may generally flow from the drain region 102 in a vertical direction along the protruding portion 107 a of the drift region 107 , and may then flow through the channel region 110 c to the source region 112 .

[0332] In the above-described power semiconductor device 100-4, the source contact region 112b and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed such that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed under the gate electrode layer 120. Therefore, the power semiconductor device 100-4 may have a high degree of integration.

[0333] In the case of the above-described power semiconductor device 100-4, the deep well region 111 may be disposed below the well region 110, and thus the electric field of the gate insulating layer 118 applied to the protruding portion 107a of the drift region 107 between the well regions 110 may be reduced. In addition, lowering the electric field may allow the junction resistance of the power semiconductor device 100-4 to be reduced. Therefore, the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100-4 may be increased, and the operating reliability of the power semiconductor device 100-4 may be improved.

[0334] Figure 42 to Figure 45 1 is a cross-sectional view showing power semiconductor devices 100a-4, 100b-4, 100c-4, and 100d-4 according to other embodiments of the present disclosure. The power semiconductor devices 100a-4, 100b-4, 100c-4, and 100d-4 are partially modified or added to Figures 37 to 41 The power semiconductor device 100 - 4 of the present invention is described below, and thus these embodiments may be referred to as one another, and redundant descriptions are omitted.

[0335] refer to Fig.42 , the power semiconductor device 100a-4 may include at least one trench 138 penetrating the second source region 112b and exposing the second well region 110b. The trench 138 may be formed to expose the surface of the second well region 110b or to be recessed so that the second well region 110b has a specific depth. The well contact region 114a may be formed on at least the bottom surface of the groove 138 to contact the second well region 110b.

[0336] Source electrode layer 140 may be formed to fill groove 138 and thus may be connected to well contact region 114a, second well region 110b and / or second source region 112b. This structure may help reduce contact resistance between source electrode layer 140 and second well region 110b and second source region 112b by increasing the contact area therebetween.

[0337] In some embodiments, the well contact region 114a may be completely formed on the surface of the second well region 110b exposed by the trench 138. Therefore, the well contact region 114a may be formed on the second well region 110b to be exposed to the bottom and sidewall of the trench 138. The structure of the well contact region 114a may further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0338] refer to Fig.43 In the power semiconductor device 100b-4, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type so that an accumulation channel is formed.

[0339] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 may have a structure that is generally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated when carbon clusters are formed in the gate insulating layer 118, the band of the channel region 107b is bent upward, resulting in a potential barrier. Therefore, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows the flow of charge or current may be formed in the channel region 107b.

[0340] Therefore, a threshold voltage to be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107 b may be significantly lower than a threshold voltage to be applied to the gate electrode layer 120 to form a conventional inversion channel.

[0341] In some embodiments, the channel region 107b may be a part of the drift region 107. Specifically, the channel region 107b may be a part of the protruding portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107.

[0342] The drift region 107 may be connected to the source region 112 through the channel region 107b. Specifically, in the channel region 107b, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other.

[0343] For example, the doping concentration of the first conductivity type impurities in the channel region 107 b may be the same as that of other portions of the drift region 107 , or may be different therefrom, for adjusting the threshold voltage.

[0344] In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend to the trench portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed thereon. This structure may allow the channel region 107b to be defined between the gate electrode layer 120 and the well region 110.

[0345] In some embodiments, the first well region 110a and the first source region 112a may have the same width. In this case, the first source region 112a may contact the protruding portion 107a of the drift region 107, and the channel region 107b may be defined at a portion contacting the protruding portion 107a.

[0346] refer to Fig.44 In the power semiconductor device 100 c - 4 , the first well region 110 a may further protrude from the first source region 112 a toward the protruding portion 107 a of the drift region 107 , and may include a tab portion extending toward the gate electrode layer 120 at a distal end thereof.

[0347] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a curved shape on the protruding portion and the tab portion of the first well region 110a. This structure may allow the channel region 107b1 to be more confined between the gate electrode layer 120 and the first well region 110a.

[0348] refer to Fig.45 In the power semiconductor device 100d-4, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a convex portion extending at its end toward the gate electrode layer 120. In addition, the protruding portion 107a of the drift region 107 may further extend between the lower portion of the first source region 112a and the first well region 110a.

[0349] The channel region 107b2 may be formed to further extend into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a curved shape from the upper portion of the convex portion of the first well region 110a to the lower portion of the first source region 112a. This structure may help widen the contact area between the channel region 107b2 and the first source region 112a.

[0350] Figure 46 to Figure 48is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 4 according to an embodiment of the present disclosure.

[0351] refer to Fig.46 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC) to provide a vertical movement path for charges. For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0352] Subsequently, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0353] In detail, the well region 110 may be formed on the semiconductor layer 105 in contact with the protruding portion 107a to define at least one protruding portion 107a of the drift region 107. Specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with impurities of a conductivity type opposite to that of the drift region 107.

[0354] The well region 110 may be divided into a first well region 110a under the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a may define a protruding portion 107a of the drift region 107, and a well contact region 114 may be formed later in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0355] The deep well region 111 may be formed in the semiconductor layer 105 under the well region 110 to contact the well region 110 and the drift region 107. The deep well region 111 may have a second conductivity type that is opposite to the conductivity type of the impurities of the drift region 107 and is the same as the conductivity type of the impurities of the well region 110. For example, the deep well region 111 may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 or the drift region 107.

[0356] In addition, source region 112 having the first conductivity type may be formed on or in well region 110. For example, the formation of source region 112 may be performed by implanting impurities of the first conductivity type into well region 110 or into semiconductor layer 105.

[0357] For example, the formation of the source region 112 may include forming the first source region 112a on or in the first well region 110a and forming the second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be allocated as a source contact region 112b1 to connect to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed substantially from the surface of the semiconductor layer 105 into or above the well region 110, with a certain depth.

[0358] In addition to the formation of the source region 112, a channel region 110c having a second conductivity type may be formed to form an inversion channel in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c as a part of the first well region 110a may not be formed separately but may be formed together with the first well region 110a.

[0359] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than the well region 110 into a portion of the well region 110.

[0360] In a modified example of this embodiment, the impurity doping order of the well region 110 , the deep well region 111 , the source region 112 , the channel region 110 c , and the well contact region 114 may be appropriately changed.

[0361] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed when the impurities are implanted into the semiconductor layer 105 or when the epitaxial layer is formed. However, in order to implant impurities in a selective region, an ion implantation method using a mask pattern may be used.

[0362] Optionally, after the ion implantation, heat treatment for activating or diffusing the impurities may be subsequently performed.

[0363] refer to Fig.47 The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0364] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105 .

[0365] Subsequently, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0366] The patterning process may be performed using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer using a photolithography process and a development process. The etching process may include a process of selectively etching an underlying structure using the photoresist pattern.

[0367] refer to Fig.48 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Alternatively, when the interlayer insulating layer 130 is completely formed on the underlying structure, a process of forming a contact hole pattern for exposing the source contact region 112b1 and the well contact region 114 may be subsequently performed.

[0368] Subsequently, source electrode layer 140 may be formed on semiconductor layer 105 to be connected to second source region 112b and well contact region 114. For example, source electrode layer 140 may be formed by forming a conductive layer such as a metal layer on interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0369] at the same time, Fig.42 The power semiconductor device 100 a - 4 may be manufactured by adding or modifying some processes to the manufacturing process of the power semiconductor device 100 - 4 described above.

[0370] Fig.42 The manufacture of the power semiconductor device 100a-4 may also include: forming at least one trench 138 through the second source region 112b and exposing the second well region 110b in the second source region 112b; forming a well contact region 114 to contact the well region 110 on the bottom surface of the trench 138; and filling the trench 138 to form a source electrode layer 140 to be connected to the source region 112 and the well contact region 114.

[0371] At the same time, when manufacturing Figure 43 to Figure 45 When the power semiconductor devices 100 b - 4 , 100 c - 4 , and 100 d - 4 are formed, the channel regions 107 b , 107 b 1 , and 107 b 2 may have the first conductivity type to form an accumulation channel. For example, the channel regions 107 b , 107 b 1 , and 107 b 2 may be formed as part of the drift region 107 .

[0372] According to the above-described manufacturing method, a highly integrated power semiconductor device 100 - 4 can be economically manufactured by using the semiconductor layer 105 of silicon carbide in a process used in an existing silicon substrate.

[0373] Fig.49 is a schematic perspective view showing a power semiconductor device 100 - 5 according to an embodiment of the present disclosure, Fig.50 It is shown along Fig.49 A plan view of the power semiconductor device 100 - 5 taken along line II-II, Fig.51 It is shown along Fig.50 A cross-sectional view of the power semiconductor device 100 - 5 taken along line III-III, Fig.52 It is shown along Fig.50 A cross-sectional view of the power semiconductor device 100 - 5 taken along line IV-IV of FIG. 1 , and Fig.53 It is shown along Fig.50 1 is a cross-sectional view of the power semiconductor device 100 - 5 taken along line VV.

[0374] refer to Figures 49 to 53 The power semiconductor device 100-5 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-5 may have a power MOSFET structure.

[0375] The semiconductor layer 105 may refer to one or more semiconductor material layers, and may refer to, for example, one or more epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0376] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). Specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0377] Silicon carbide (SiC) can have a wider band gap than silicon, and thus can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, the power semiconductor device 100-1 using silicon carbide as the semiconductor layer 105 exhibits stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0378] Specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0379] The drift region 107 may provide a vertical movement path of charges. In addition, the drift region 107 may include at least one protruding portion 107a disposed below the gate electrode layer 120. The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105.

[0380] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in semiconductor layer 105 or drift region 107.

[0381] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. In essence, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and specifically, may be in contact with the sidewall of the first well region 110a.

[0382] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping impurities of the first conductivity type having a higher concentration than the drift region 107.

[0383] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed below the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0384] The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 112b1 may be a portion of the second source region 112b, and may refer to a portion to which the source electrode layer 140 is connected.

[0385] Well contact region 114 may be formed in second source region 112b, specifically, in source contact region 112b1. For example, well contact region 114 may extend from second well region 110b through second source region 112b and may have the second conductivity type. One or more well contact regions 114 may be formed in source contact region 112b1.

[0386] Well contact region 114 may be connected to source electrode layer 140. When connected to source electrode layer 140, well contact region 114 may be formed by doping impurities of the second conductivity type having a higher concentration than well region 110 to reduce contact resistance.

[0387] The channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type so that an accumulation channel is formed.

[0388] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 may have a structure that is generally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated when carbon clusters are formed in the gate insulating layer 118, the band of the channel region 107b is bent upward, resulting in a potential barrier. Therefore, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows the flow of charge or current may be formed in the channel region 107b.

[0389] Therefore, a threshold voltage to be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107 b may be significantly lower than a threshold voltage to be applied to the gate electrode layer 120 to form a conventional inversion channel.

[0390] In some embodiments, the channel region 107b may be a part of the drift region 107. Specifically, the channel region 107b may be a part of the protruding portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107.

[0391] The drift region 107 may be connected to the source region 112 through the channel region 107b. Specifically, in the channel region 107b, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other.

[0392] For example, the doping concentration of the first conductivity type impurities in the channel region 107 b may be the same as that of other portions of the drift region 107 , or may be different therefrom, for adjusting the threshold voltage.

[0393] In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend to the trench portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed thereon. This structure may allow the channel region 107b to be defined between the gate electrode layer 120 and the well region 110.

[0394] In some embodiments, the first well region 110a and the first source region 112a may have the same width. In this case, the first source region 112a may contact the protruding portion 107a of the drift region 107, and the channel region 107b may be defined at a portion contacting the protruding portion 107a.

[0395] In some embodiments, the drift region 107, the first well region 110a, the channel region 107b and / or the protruding portion 107a of the first source region 112a may extend in one direction. Fig.50 The direction of the line IV-IV or the line VV may be one direction. Here, the extending direction of the channel region 107b does not mean the moving direction of the charges.

[0396] In some embodiments, the first well region 110a, the channel region 107b, and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 107b, and the first source region 112a may be formed on the semiconductor layer 105 on opposite sides of the protruding portion 107a of the drift region 107, respectively.

[0397] In some embodiments, the drift region 107 may include a plurality of protrusions 107a formed parallel to each other in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protrusions 107a may also be formed in a stripe pattern.

[0398] In addition, the first source region 112a may be formed in a stripe pattern on the first well region 110a. A channel region 107b may be formed between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0399] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a and the channel region 107b of the drift region 107 may be formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0400] In addition, the first well region 110a and the second well region 110b may be repeatedly and alternately formed in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

[0401] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration than the drift region 107 .

[0402] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or a substrate separated from the semiconductor layer 105 .

[0403] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 107b. Specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 107b, and the protruding portion 107a of the drift region 107.

[0404] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stack structure thereof.

[0405] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 107b. Specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 107b, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0406] For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, metal silicide, etc., or may include a stack structure thereof.

[0407] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide layer, a nitride layer, or a stack structure thereof.

[0408] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, specifically, the second source region 112b or the source contact region 112b1. In addition, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0409] In the above power semiconductor device 100 - 5 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be any one of N type and P type, respectively. For example, when the first conductivity type is N type, the second conductivity type is P type, and vice versa.

[0410] Specifically, when the power semiconductor device 100 - 5 is an N-type MOSFET, the drift region 107 and the channel region 107 b may be N regions, the source region 112 and the drain region 102 may be N+ regions, the well region 110 may be a P region, and the well contact region 114 may be a P+ region.

[0411] During operation of the power semiconductor device 100 - 5 , current may generally flow from the drain region 102 in a vertical direction along the protruding portion 107 a of the drift region 107 , and may then flow through the channel region 107 b to the source region 112 .

[0412] In the above-described power semiconductor device 100-5, the source contact region 112b and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed such that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 107b may be densely formed under the gate electrode layer 120. Therefore, the power semiconductor device 100-5 may have a high degree of integration.

[0413] Figures 54 to 56 1 is a cross-sectional view showing power semiconductor devices 100a-5, 100b-5, and 100c-5 according to other embodiments of the present disclosure. The power semiconductor devices 100a-5, 100b-5, and 100c-5 are partially modified or added to Figures 49 to 53 The power semiconductor device 100 - 5 of the present invention is described below, and thus these embodiments may be referred to as one another, and redundant descriptions are omitted.

[0414] refer to Fig.54 The power semiconductor device 100a-5 may include at least one trench 138 penetrating the second source region 112b and recessed in the second well region 110b having a certain depth. A well contact region 114a may be formed on at least a bottom surface of the trench 138 to contact the second well region 110b.

[0415] Source electrode layer 140 may be formed to fill groove 138 and thus may be connected to well contact region 114a, second well region 110b and / or second source region 112b. This structure may help reduce contact resistance between source electrode layer 140 and second well region 110b and second source region 112b by increasing the contact area therebetween.

[0416] In some embodiments, the well contact region 114a may be completely formed on the surface of the second well region 110b exposed to the trench 138. Therefore, the well contact region 114a may be formed on the second well region 110b to be exposed to the bottom and sidewall of the trench 138. The structure of the well contact region 114a may further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0417] refer to Fig.55 , in the power semiconductor device 100b-5, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a convex portion extending toward the gate electrode layer 120 at its end. A channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a curved shape on the protruding portion and the convex portion of the first well region 110a. This structure may allow the channel region 107b1 to be more confined between the gate electrode layer 120 and the first well region 110a.

[0418] refer to Fig.56 In the power semiconductor device 100c-5, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a convex portion extending at its end toward the gate electrode layer 120. In addition, the protruding portion 107a of the drift region 107 may further extend between the lower portion of the first source region 112a and the first well region 110a.

[0419] The channel region 107b2 may be formed to further extend into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a curved shape from the upper portion of the convex portion of the first well region 110a to the lower portion of the first source region 112a. This structure may help widen the contact area between the channel region 107b2 and the first source region 112a.

[0420] Figure 57 to Figure 59 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 5 according to an embodiment of the present disclosure.

[0421] refer to Fig.57 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC) to provide a vertical movement path for charges. For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may serve as a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0422] Subsequently, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0423] In detail, the well region 110 may be formed on the semiconductor layer 105 in contact with the protruding portion 107a to define at least one protruding portion 107a of the drift region 107. Specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with impurities of a conductivity type opposite to that of the drift region 107.

[0424] The well region 110 may be divided into a first well region 110a under the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a may define a protruding portion 107a of the drift region 107, and a well contact region 114 may be formed later in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0425] In addition, source region 112 having the first conductivity type may be formed on or in well region 110. For example, the formation of source region 112 may be performed by implanting impurities of the first conductivity type into well region 110 or into semiconductor layer 105.

[0426] For example, the formation of the source region 112 may include forming the first source region 112a on or in the first well region 110a and forming the second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be allocated as a source contact region 112b1 to connect to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed substantially from the surface of the semiconductor layer 105 into or above the well region 110, with a certain depth.

[0427] In addition to the formation of the source region 112, a channel region 107b having a first conductivity type may be formed to form an accumulation channel in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 107b as a part of the first well region 110a may not be formed separately but may be formed together with the first well region 110a.

[0428] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than the well region 110.

[0429] In a modified example of this embodiment, the impurity doping order of the well region 110 , the source region 112 , the channel region 107 b , and the well contact region 114 may be appropriately changed.

[0430] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed when the impurities are implanted into the semiconductor layer 105 or when the epitaxial layer is formed. However, in order to implant impurities in a selective region, an ion implantation method using a mask pattern may be used.

[0431] Optionally, after the ion implantation, heat treatment for activating or diffusing the impurities may be subsequently performed.

[0432] refer to Fig.58 The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 107b and the protruding portion 107a of the drift region 107.

[0433] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105 .

[0434] Subsequently, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0435] The patterning process may be performed using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer using a photolithography process and a development process. The etching process may include a process of selectively etching an underlying structure using the photoresist pattern.

[0436] refer to Fig.59 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Alternatively, when the interlayer insulating layer 130 is completely formed on the underlying structure, a process of forming a contact hole pattern for exposing the source contact region 112b1 and the well contact region 114 may be subsequently performed.

[0437] Subsequently, source electrode layer 140 may be formed on semiconductor layer 105 to be connected to second source region 112b and well contact region 114. For example, source electrode layer 140 may be formed by forming a conductive layer such as a metal layer on interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0438] at the same time, Fig.54 The power semiconductor device 100 a - 5 may be manufactured by adding or modifying some processes to the manufacturing process of the power semiconductor device 100 - 5 described above.

[0439] Fig.54The manufacture of the power semiconductor device 100a-5 may also include: forming at least one trench 138 in the second source region 112b that passes through the second source region 112b and is recessed in the second well region 110b; forming a well contact region 114 on the bottom surface of the trench 138 to contact the well region 110; and filling the trench 138 to form a source electrode layer 140 that will be connected to the source region 112 and the well contact region 114.

[0440] According to the above-described manufacturing method, a highly integrated power semiconductor device 100 - 5 can be economically manufactured by using the semiconductor layer 105 of silicon carbide in a process used in an existing silicon substrate.

[0441] Fig.60 is a schematic perspective view showing a power semiconductor device 100 - 6 according to an embodiment of the present disclosure, Fig.61 It shows that along Fig.60 A plan view of the power semiconductor device 100 - 6 taken along line II-II, Fig.62 It is shown along Fig.61 A cross-sectional view of the power semiconductor device 100 - 6 taken along line III-III, Fig.63 It is shown along Fig.61 A cross-sectional view of the power semiconductor device 100 - 6 taken along line IV-IV of FIG. 1 , and Fig.64 It is shown along Fig.61 1 is a cross-sectional view of the power semiconductor device 100 - 6 taken along line VV.

[0442] refer to Figure 60 to Figure 64 The power semiconductor device 100-6 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-6 may have a power MOSFET structure.

[0443] The semiconductor layer 105 may refer to one or more semiconductor material layers, and may refer to, for example, one or more epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0444] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). Specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0445] Silicon carbide (SiC) can have a wider band gap than silicon, and thus can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with silicon, the power semiconductor device 100-6 using silicon carbide as the semiconductor layer 105 exhibits stable operating characteristics due to higher breakdown voltage and excellent heat release.

[0446] Specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0447] The drift region 107 may provide a vertical movement path of charges. In addition, the drift region 107 may include at least one protruding portion 107a disposed below the gate electrode layer 120. The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105.

[0448] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in semiconductor layer 105 or drift region 107.

[0449] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. In essence, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and specifically, may be in contact with the sidewall of the first well region 110a.

[0450] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping impurities of the first conductivity type having a higher concentration than the drift region 107.

[0451] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed below the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0452] The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 112b1 may be a portion of the second source region 112b, and may refer to a portion to which the source electrode layer 140 is connected.

[0453] Well contact region 114 may be formed in second source region 112b, specifically, in source contact region 112b1. For example, well contact region 114 may extend from second well region 110b through second source region 112b and may have the second conductivity type. One or more well contact regions 114 may be formed in source contact region 112b1.

[0454] Well contact region 114 may be connected to source electrode layer 140. When connected to source electrode layer 140, well contact region 114 may be formed by doping impurities of the second conductivity type having a higher concentration than well region 110 to reduce contact resistance.

[0455] In some embodiments, in the source contact region 112b1, at least a portion of the second well region 110b may be exposed from the second source region 112b. A portion 107c of the drift region 107 may penetrate a portion of the second well region 110b exposed to the second source region 112b, and may be exposed to the surface of the semiconductor layer 105. Therefore, the portion 107c of the drift region 107 may be spaced apart from the second source region 112b by a portion of the second well region 110b.

[0456] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0457] For example, the channel region 110c may have a second conductivity type so that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c, the source region 112, and the drift region 107 may form a diode junction. Therefore, the channel region 110c may not allow the movement of charges under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein to allow the movement of charges.

[0458] For example, the channel region 110c may be a part of the well region 110. In detail, the channel region 110c may be a part of the well region 110 adjacent to the lower portion of the gate electrode layer 120 of the well region 110. In this case, the channel region 110c may be formed to be integrally or continuously connected to the well region 110a. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as the doping concentration of the other parts of the well region 110, or may be different therefrom, for adjusting the threshold voltage.

[0459] In some embodiments, the drift region 107, the first well region 110a, the channel region 110c and / or the protruding portion 107a of the first source region 112a may extend in one direction. Here, the extending direction of the channel region 110c does not mean the moving direction of charges.

[0460] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed on the semiconductor layer 105 on opposite sides of the protruding portion 107a of the drift region 107, respectively.

[0461] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a formed parallel to each other in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In addition, the first source region 112a may be formed in a stripe pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0462] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0463] In addition, the first well region 110a and the second well region 110b may be repeatedly and alternately formed in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

[0464] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration than the drift region 107 .

[0465] In some embodiments, the drain region 102 may be provided with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or a substrate separated from the semiconductor layer 105 .

[0466] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. Specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0467] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stack structure thereof.

[0468] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. Specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0469] For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, metal silicide, etc., or may include a stack structure thereof.

[0470] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide layer, a nitride layer, or a stack structure thereof.

[0471] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112 , specifically, the second source region 112 b or the source contact region 112 b 1 . In addition, the source electrode layer 140 may also be connected to the well contact region 114 .

[0472] In addition, the source electrode layer 140 may contact the portion 107c of the drift region 107, thereby forming a Schottky barrier diode (SBD). For example, the source electrode layer 140 may contact the portion 107c of the drift region 107 exposed from the second well region 110b on the surface of the semiconductor layer 105. The Schottky barrier diode (SBD) may refer to a diode using a Schottky barrier generated by a junction of a metal and a semiconductor.

[0473] In addition to the Schottky barrier diode (SBD), a body diode may be parasitically formed in the power semiconductor device 100-6. For example, the body diode may be formed between the well region 110 and the drift region 107. The body diode may be one of PN diodes formed by a junction of semiconductors of different polarities.

[0474] like Fig.73As shown, it can be seen that compared with the PN diode, the Schottky barrier diode SBD has a low forward voltage VF and fast switching characteristics.

[0475] The Schottky barrier diode (SBD) can reduce switching losses together with the body diode during operation of the power semiconductor device 100 - 6 . For example, the Schottky barrier diode (SBD) and the body diode can be used as a freewheeling diode during operation of the power semiconductor device 100 - 6 .

[0476] In some embodiments, the source electrode layer 140 may be commonly connected to the second source region 112b, the well contact region 114, and a portion 107c of the drift region 107. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0477] In the above power semiconductor device 100 - 6 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be any one of N type and P type, respectively. For example, when the first conductivity type is N type, the second conductivity type is P type, and vice versa.

[0478] Specifically, when the power semiconductor device 100 - 6 is an N-type MOSFET, the drift region 107 may be an N region, the source region 112 and the drain region 102 may be N+ regions, the well region 110 and the channel region 110 c may be P regions, and the well contact region 114 may be a P+ region.

[0479] During operation of the power semiconductor device 100 - 6 , current may generally flow from the drain region 102 in a vertical direction along the protruding portion 107 a of the drift region 107 , and may then flow through the channel region 110 c to the source region 112 .

[0480] In the above-described power semiconductor device 100-6, the source contact region 112b and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed such that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed under the gate electrode layer 120. Therefore, the power semiconductor device 100-6 may have a high degree of integration.

[0481] Fig.65 and 66 1 is a cross-sectional view showing a power semiconductor device 100a-6 according to another embodiment of the present disclosure. Figure 60 to Figure 64 The present invention relates to modified or additional components of the power semiconductor device 100 - 6 , and thus these embodiments may be referred to as one another, and redundant descriptions are omitted.

[0482] refer to Fig.65 and66 , the power semiconductor device 100a-6 may include at least one trench 138 formed by partially etching a portion of the second well region 110b exposed from the second source region 112b and a portion 107c of the drift region 107. The trench 138 may be formed to expose the surface of the second well region 110b or to be recessed so that the second well region 110b has a certain depth. The well contact region 114a may be formed on at least the bottom surface of the groove.

[0483] The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a and the second source region 112b within the groove 138. In addition, the source electrode layer 140 may contact a portion 107c of the drift region 107 within the groove 138 to form a Schottky barrier diode. For example, the source electrode layer 140 may contact a portion 107c of the drift region 107 on the bottom surface of the groove 138. The groove structure may help reduce the contact resistance between the source electrode layer 140 and the second source region 112b and the well contact region 114a by increasing the contact area therebetween.

[0484] In some embodiments, the well contact region 114a may be completely formed on the surface of the second well region 110b exposed to the trench 138. Therefore, the well contact region 114a may be formed on the second well region 110b to be exposed to the bottom and sidewall of the trench 138. The structure of the well contact region 114a may further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0485] Figures 67 to 69 1 is a cross-sectional view showing power semiconductor devices 100b-6, 100c-6, and 100d-6 according to other embodiments of the present disclosure. The power semiconductor devices 100b-6, 100c-6, and 100d-6 are partially modified or added to Figures 60 to 64 The power semiconductor device 100 - 6 of the present invention is described above, and thus these embodiments may be referred to as one another, and redundant descriptions are omitted.

[0486] refer to Fig.67 In the power semiconductor device 100b-6, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type so that an accumulation channel is formed.

[0487] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 may have a structure that is generally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated when carbon clusters are formed in the gate insulating layer 118, the band of the channel region 107b is bent upward, resulting in a potential barrier. Therefore, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows the flow of charge or current may be formed in the channel region 107b.

[0488] Therefore, a threshold voltage to be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107 b may be significantly lower than a threshold voltage to be applied to the gate electrode layer 120 to form a conventional inversion channel.

[0489] In some embodiments, the channel region 107b may be a part of the drift region 107. Specifically, the channel region 107b may be a part of the protruding portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107.

[0490] The drift region 107 may be connected to the source region 112 through the channel region 107b. Specifically, in the channel region 107b, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other.

[0491] For example, the doping concentration of the first conductivity type impurities in the channel region 107 b may be the same as that of other portions of the drift region 107 , or may be different therefrom, for adjusting the threshold voltage.

[0492] In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend to the trench portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed thereon. This structure may allow the channel region 107b to be defined between the gate electrode layer 120 and the well region 110.

[0493] In some embodiments, the first well region 110a and the first source region 112a may have the same width. In this case, the first source region 112a may contact the protruding portion 107a of the drift region 107, and the channel region 107b may be defined at a portion contacting the protruding portion 107a.

[0494] refer to Fig.68In the power semiconductor device 100 c - 6 , the first well region 110 a may further protrude from the first source region 112 a toward the protruding portion 107 a of the drift region 107 , and may include a tab portion extending toward the gate electrode layer 120 at a distal end thereof.

[0495] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a curved shape on the protruding portion and the tab portion of the first well region 110a. This structure may allow the channel region 107b1 to be more confined between the gate electrode layer 120 and the first well region 110a.

[0496] refer to Fig.69 In the power semiconductor device 100d-6, the first well region 110a may further protrude from the first source region 112a toward the protruding portion 107a of the drift region 107, and may include a convex portion extending at its end toward the gate electrode layer 120. In addition, the protruding portion 107a of the drift region 107 may further extend between the lower portion of the first source region 112a and the first well region 110a.

[0497] The channel region 107b2 may be formed to further extend into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a curved shape from the upper portion of the convex portion of the first well region 110a to the lower portion of the first source region 112a. This structure may help widen the contact area between the channel region 107b2 and the first source region 112a.

[0498] Figure 70 to Figure 72 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 6 according to an embodiment of the present disclosure.

[0499] refer to Fig.70 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC) to provide a vertical movement path for charges. For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may serve as a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0500] Subsequently, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0501] In detail, the well region 110 may be formed on the semiconductor layer 105 in contact with the protruding portion 107a to define at least one protruding portion 107a of the drift region 107. Specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with impurities of a conductivity type opposite to that of the drift region 107.

[0502] The well region 110 may be divided into a first well region 110a under the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a may define a protruding portion 107a of the drift region 107, and a well contact region 114 may be formed later in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0503] In addition, source region 112 having the first conductivity type may be formed on or in well region 110. For example, the formation of source region 112 may be performed by implanting impurities of the first conductivity type into well region 110 or into semiconductor layer 105.

[0504] For example, the formation of the source region 112 may include forming the first source region 112a on or in the first well region 110a and forming the second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be allocated as a source contact region 112b1 to connect to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed substantially from the surface of the semiconductor layer 105 into or above the well region 110, with a certain depth.

[0505] In addition to the formation of the source region 112, a channel region 110c having a second conductivity type may be formed to form an inversion channel in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c as a part of the first well region 110a may not be formed separately but may be formed together with the first well region 110a.

[0506] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than the well region 110 into a portion of the well region 110.

[0507] A portion of the second well region 110 b may be exposed from the second source region 112 b , and a portion 107 c of the drift region 107 may be exposed from the surface of the semiconductor layer 105 through a portion of the second well region 110 b .

[0508] In a modified example of this embodiment, the impurity doping order of the well region 110 , the source region 112 , the channel region 110 c , and the well contact region 114 may be appropriately changed.

[0509] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed when the impurities are implanted into the semiconductor layer 105 or when the epitaxial layer is formed. However, in order to implant impurities in a selective region, an ion implantation method using a mask pattern may be used.

[0510] Optionally, after the ion implantation, heat treatment for activating or diffusing the impurities may be subsequently performed.

[0511] refer to Fig.71 The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0512] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105 .

[0513] Subsequently, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0514] The patterning process may be performed using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer using a photolithography process and a development process. The etching process may include a process of selectively etching an underlying structure using the photoresist pattern.

[0515] refer to Fig.72 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Alternatively, when the interlayer insulating layer 130 is completely formed on the underlying structure, a process of forming a contact hole pattern for exposing the source contact region 112b1 and the well contact region 114 may be subsequently performed.

[0516] Subsequently, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b of the well contact region 114 and the portion 107c of the drift region 107. The contact structure between the source electrode layer 140 and the portion 107c of the drift region 107 may form a Schottky barrier diode (SBD). For example, the source electrode layer 140 may be formed by forming a conductive layer (e.g., a metal layer) on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0517] at the same time, Fig.65 and 66 The power semiconductor device 100 a - 6 may be manufactured by adding or modifying some processes to the manufacturing process of the power semiconductor device 100 - 6 described above.

[0518] Manufacturing the power semiconductor device 100a-6 may further include forming at least one trench 138 by partially etching a portion of the second well region 110b and a portion 107c of the drift region 107 exposed from the second source region 112b, forming a well contact region 114 having a second conductivity type on a portion of the second well region 110b in a portion of the bottom surface of the trench 138, and filling the trench 138 to form a source electrode layer 140 to be connected to the second source region 112b, the well contact region 114 and a portion 107c of the drift region 107.

[0519] At the same time, when manufacturing Figure 67 to Figure 69 When the power semiconductor devices 100 b - 6 , 100 c - 6 , and 100 d - 6 are formed, the channel regions 107 b , 107 b 1 , and 107 b 2 may have the first conductivity type to form an accumulation channel. For example, the channel regions 107 b , 107 b 1 , and 107 b 2 may be formed as part of the drift region 107 .

[0520] According to the above-described manufacturing method, a highly integrated power semiconductor device 100 - 6 can be economically manufactured by using the semiconductor layer 105 of silicon carbide in a process used in an existing silicon substrate.

[0521] According to the power semiconductor device and the method for manufacturing the same according to the embodiments of the present disclosure as described above, the degree of integration can be increased by increasing the channel density.

[0522] Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

[0523] Although the present disclosure has been described above with reference to exemplary embodiments and the accompanying drawings, the present disclosure is not limited thereto, and those skilled in the art may make various modifications and changes to the present disclosure without departing from the spirit and scope of the present disclosure as claimed in the appended claims.

Claims

1. A power semiconductor device, comprising: Semiconductor layer of silicon carbide SiC; a gate insulating layer disposed on at least a portion of the semiconductor layer; a gate electrode layer disposed on the gate insulating layer; a drift region including at least one protruding portion disposed below the gate electrode layer in the semiconductor layer and having a first conductivity type; a well region including a first well region disposed in the semiconductor layer at a lower portion of the gate electrode layer and in contact with the at least one protruding portion; and a second well region, which is disposed in the semiconductor layer outside the gate electrode layer and connected to the first well region and has a second conductivity type; a source region including a first source region disposed in the first well region and a second source region disposed in the second well region and connected to the first source region, and having the first conductivity type; a channel region disposed below the gate electrode layer, disposed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, and having the second conductivity type; a source electrode layer connected to the second source region outside the gate electrode layer; as well as a plurality of well contact regions formed in the second source region, extending from the second well region through the second source region, connected to the source electrode layer, and having a second conductivity type, The first source region is symmetrically formed on both sides of the second source region. The plurality of well contact regions are formed as a straight line at a predetermined distance in the same direction as the extending direction of the second source region and are not provided in the first source region, The first source region and the second source region extend in two directions.

2. The power semiconductor device according to claim 1, in, The plurality of well contact regions are doped with impurities having a higher concentration than the well region.

3. The power semiconductor device according to claim 1, wherein: The at least one protruding portion of the drift region, the first well region, and the first source region extends in one direction.

4. The power semiconductor device according to claim 3, wherein: The first well region, the first source region, and the channel region are respectively disposed in the semiconductor layer on opposite sides of the at least one protruding portion of the drift region.

5. The power semiconductor device according to claim 1, wherein: The channel region is a portion of the well region.

6. The power semiconductor device according to claim 1, wherein: The at least one protruding portion includes a plurality of protruding portions, sidewalls of the plurality of protruding portions are surrounded by the first well region, and Wherein, the channel region is arranged between the plurality of protruding portions and the first source region.

7. The power semiconductor device according to claim 6, wherein: The plurality of protruding portions extend side by side in one direction.

8. The power semiconductor device according to claim 1, wherein: The first well region is arranged symmetrically with respect to the second well region, wherein the first source region is symmetrically arranged relative to the second source region, and Wherein, the channel region is symmetrically arranged relative to the second well region or the second source region.

9. The power semiconductor device according to claim 8, wherein: The at least one protruding portion includes a plurality of protruding portions symmetrically disposed with respect to the second well region or the second source region, and Wherein, the plurality of protruding portions extend in one direction.

10. The power semiconductor device according to claim 1, wherein: The gate electrode layer exposes the second source region and covers the first source region, the channel region, and the at least one protruding portion of the drift region.

11. The power semiconductor device according to claim 1, further comprising: a drain region having the first conductivity type in the semiconductor layer below the drift region, The drain region is doped with impurities having a higher concentration than that of the drift region.

12. A method for manufacturing a power semiconductor device, the method comprising: forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide SiC; forming a well region having a second conductivity type to allow the drift region to include at least one protruding portion, and including a first well region defining the at least one protruding portion and a second well region connected to the first well region; forming a source region, the source region including a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region, and having the first conductivity type; forming a channel region having the second conductivity type in the semiconductor layer between the at least one protruding portion of the drift region and the first source region; forming a gate insulating layer on at least the channel region and the at least one protruding portion of the drift region; forming at least one gate electrode layer on the gate insulating layer; forming a plurality of well contact regions in the second source region, the plurality of well contact regions extending from the second well region outside the gate electrode layer through the second source region, connected to the source electrode layer, and having the second conductivity type; as well as forming the source electrode layer on the semiconductor layer to be connected to the second source region and the plurality of well contact regions; wherein the second well region is formed in the semiconductor layer outside the gate electrode layer, The first source region is symmetrically formed on both sides of the second source region, The plurality of well contact regions are formed as a straight line at a predetermined distance in the same direction as the extending direction of the second source region and are not provided in the first source region, The first source region and the second source region extend in two directions.

13. The method according to claim 12, in, The plurality of well contact regions are doped with impurities having a higher concentration than the well region.

14. The method according to claim 12, wherein: forming the well region and the channel region by implanting impurities of the second conductivity type into the semiconductor layer, and The forming of the source region is performed by implanting impurities of the first conductivity type into the well region.

15. The method according to claim 12, wherein: The at least one protruding portion includes a plurality of protruding portions, sidewalls of the plurality of protruding portions are surrounded by the first well region, and Wherein, the channel region is formed between the plurality of protruding portions and the source region.

16. The method according to claim 12, wherein: The first well region is formed symmetrically with respect to the second well region, wherein the first source region is formed symmetrically with respect to the second source region, and Wherein, the channel region is formed symmetrically with respect to the second well region or the second source region.

17. The method according to claim 12, wherein: The drift region is formed on the drain region having the first conductivity type, and Wherein, the drift region is formed as an epitaxial layer on the drain region.

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