Phase detection method, device and equipment

Abstract

The present invention discloses a phase detection method, apparatus, and device thereof. The phase detection device includes a signal processing component, a phase detector, and a phase comparison component. The signal processing component is used to obtain a reference clock signal and its initial phase value. The phase detector is used to obtain a clock signal to be measured and obtain a first phase difference signal based on the reference clock signal and the clock signal to be measured. The phase comparison component is used to obtain a phase adjustment signal based on the first phase difference signal. In addition, the signal processing component is also used to adjust the phase of the reference clock signal based on the phase adjustment signal to reduce the first phase difference signal, and accumulate the adjusted phase value to obtain a phase accumulation value, and obtain the phase value of the clock signal to be measured based on the phase accumulation value and the initial phase value. In an embodiment of the present invention, the phase of the reference clock signal can be made close to the phase of the clock signal to be measured through a limited number of processing times, thereby enabling the measurement of the clock phase to be completed with high precision and high speed.

Description

Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of communication technology, and in particular to a phase detection method, apparatus, and device thereof. Background Art

[0002] 5G communications are placing increasingly high demands on 1588 clock time accuracy, with single-node synchronization now required to be within a few nanoseconds. Further improving clock signal accuracy requires either increasing the frequency or measuring and then compensating the phase. The former approach places higher demands on chips and processes, while the latter offers lower requirements and, therefore, a higher cost-performance ratio.

[0003] Currently, there are three main types of clock phase measurement methods: the first uses a very high-frequency clock signal to sample the clock signal under test to obtain phase information; the second method first phase-shifts a clock signal to generate several clock signals with the same frequency but different phases, then compares them with the clock signal under test to find the clock signal with the closest phase to obtain phase information; the third method phase-shifts a clock signal by a very small step size while simultaneously sampling the clock signal under test, and after a cycle, obtains phase information from the sampled values. The first method has high requirements for chips and processes; the second method is less expensive to implement but has low accuracy; the third method has high accuracy but slow measurement speed, and the higher the accuracy, the slower the speed.

[0004] Therefore, how to complete the measurement of clock phase with high precision and high speed is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiments of the present invention provide a phase detection method, an apparatus and a device thereof, which can improve the phase detection accuracy and phase detection speed of a clock signal.

[0007] In a first aspect, an embodiment of the present invention provides a phase detection device, including:

[0008] a signal processing component, configured to obtain a reference clock signal and an initial phase value of the reference clock signal, and output the reference clock signal;

[0009] a phase detection component connected to the signal processing component, configured to obtain a clock signal to be measured, and obtain and output a first phase difference signal based on the reference clock signal and the clock signal to be measured;

[0010] a phase comparison component, connected to the phase detection component and the signal processing component respectively, and configured to obtain and output a phase adjustment signal according to the first phase difference signal;

[0011] The signal processing component is also used to perform phase adjustment on the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, and accumulate the adjusted phase value to obtain a phase accumulation value, and obtain the phase value of the clock signal to be measured based on the phase accumulation value and the initial phase value.

[0012] In a second aspect, an embodiment of the present invention further provides a phase detection method, which is applied to a phase detection device, wherein the phase detection device includes a signal processing component, a phase detection component, and a phase comparison component connected end to end in sequence;

[0013] The method comprises:

[0014] The signal processing component obtains a reference clock signal and an initial phase value of the reference clock signal, and outputs the reference clock signal to the phase detection component;

[0015] The phase detection component obtains the clock signal to be measured, obtains a first phase difference signal according to the reference clock signal and the clock signal to be measured, and outputs the first phase difference signal to the phase comparison component;

[0016] The phase comparison component obtains a phase adjustment signal according to the first phase difference signal, and outputs the phase adjustment signal to the signal processing component;

[0017] The signal processing component performs phase adjustment on the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, accumulates the adjusted phase value to obtain a phase accumulation value, and obtains the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value.

[0018] In a third aspect, an embodiment of the present invention further provides a device comprising the phase detection apparatus according to the first aspect described above.

[0019] An embodiment of the present invention includes: a signal processing component, a phase detection component and a phase comparison component connected end to end in sequence, wherein the signal processing component is used to obtain a reference clock signal and an initial phase value of the reference clock signal; the phase detection component is used to obtain a clock signal to be measured, and obtain and output a first phase difference signal based on the reference clock signal and the clock signal to be measured; the phase comparison component is used to obtain and output a phase adjustment signal based on the first phase difference signal; in addition, the signal processing component is also used to adjust the phase of the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, and accumulate the adjusted phase value, and obtain the phase value of the clock signal to be measured based on the accumulated phase value and the initial phase value. According to the solution provided by an embodiment of the present invention, a phase comparison component obtains a phase adjustment signal based on a first phase difference signal output by a phase detector component, wherein the first phase difference signal is obtained by the phase detector component based on a reference clock signal and a clock signal to be measured. The signal processing component performs phase adjustment on the reference clock signal based on the phase adjustment signal to reduce the first phase difference signal. That is, by adjusting the phase of the reference clock signal, the first phase difference signal output by the phase detector component based on the reference clock signal and the clock signal to be measured is gradually reduced, so that the phase of the reference clock signal can approach the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detector component, and thus improving the phase detection accuracy of the clock signal. In addition, because the phase adjustment of the reference clock signal is performed within the numerical range of the first phase difference signal and is intended to reduce the first phase difference signal, only a limited number of processing operations within the numerical range of the first phase difference signal are required to achieve phase detection of the clock signal. Compared with the method of traversing a clock cycle to obtain phase information in the related art, the solution provided by the embodiment of the present invention has a better phase detection speed. Therefore, the solution provided by the embodiment of the present invention can improve the phase detection accuracy and phase detection speed of the clock signal.

[0020] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation to the technical solution of the present invention.

[0022] Figure 1 is a schematic diagram of a phase detection device provided by an embodiment of the present invention;

[0023] Figure 2is a schematic diagram of a phase detection device provided by another embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a phase detection device provided by another embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of a phase detection device provided by another embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of a phase detection device provided by another embodiment of the present invention;

[0027] Figure 6 is a flow chart of a phase detection method provided by one embodiment of the present invention;

[0028] Figure 7 is a flow chart of a phase detection method provided by another embodiment of the present invention;

[0029] Figure 8 is a flow chart of a phase detection method provided by another embodiment of the present invention;

[0030] Figure 9 is a flow chart of a phase detection method provided by another embodiment of the present invention;

[0031] Figure 10 is a flow chart of a phase detection method provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and so on, in the specification, claims, and drawings, are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0034] The present invention provides a phase detection method and apparatus and device thereof, wherein the phase detection apparatus includes a signal processing component, a phase detection component, and a phase comparison component connected end to end in sequence, wherein the phase comparison component obtains a phase adjustment signal based on a first phase difference signal output by the phase detection component, wherein the first phase difference signal is obtained by the phase detection component based on a reference clock signal and a clock signal to be measured, and the signal processing component adjusts the phase of the reference clock signal based on the phase adjustment signal to reduce the first phase difference signal, that is, by adjusting the phase of the reference clock signal to gradually reduce the first phase difference signal output by the phase detection component based on the reference clock signal and the clock signal to be measured, so that the reference clock signal is The phase of the signal can approach the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component, and further improving the phase detection accuracy of the clock signal; in addition, since the phase of the reference clock signal is adjusted within the numerical range of the first phase difference signal, and the purpose is to reduce the first phase difference signal, only a limited number of processing times within the numerical range of the first phase difference signal are required to realize the phase detection of the clock signal. Compared with the method of traversing a clock cycle to obtain phase information in the related art, it can have a better phase detection speed, so it can improve the phase detection accuracy and phase detection speed of the clock signal.

[0035] The embodiments of the present invention are further described below with reference to the accompanying drawings.

[0036] like Figure 1 As shown, Figure 1 FIG. 1 is a schematic diagram of a phase detection device provided by an embodiment of the present invention. Figure 1 In the example, the phase detection device 100 includes a signal processing component 110, a phase detector 120, and a phase comparison component 130, which are connected end-to-end. The signal processing component 110 can be used to obtain a reference clock signal and an initial phase value of the reference clock signal, and output the reference clock signal; the phase detector 120 can be used to obtain a clock signal to be measured, and obtain and output a first phase difference signal based on the reference clock signal and the clock signal to be measured; the phase comparison component 130 can be used to obtain and output a phase adjustment signal based on the first phase difference signal; and the signal processing component 110 can also be used to adjust the phase of the reference clock signal based on the phase adjustment signal to reduce the first phase difference signal, and accumulate the adjusted phase value to obtain a phase accumulation value. The phase value of the clock signal to be measured is obtained based on the phase accumulation value and the initial phase value. Therefore, the signal processing component 110, the phase detector 120, and the phase comparison component 130 can cooperate with each other to achieve phase detection of the clock signal.

[0037] In one embodiment, the clock signal to be measured is a clock signal that requires phase detection, and the reference clock signal is a known clock signal used to detect the phase of the clock signal to be measured. When the signal processing component 110 first obtains the reference clock signal, the signal processing component 110 can obtain the initial phase value of the reference clock signal, thereby providing the necessary basic conditions for obtaining the phase value of the clock signal to be measured in subsequent operations.

[0038] In one embodiment, the first phase difference signal is a signal obtained by the phase detector 120 based on the reference clock signal and the clock signal to be measured. Due to limitations such as the manufacturing process or calculation accuracy of the phase detector 120, the first phase difference signal output by the phase detector 120 is not accurate. Therefore, by providing the signal processing component 110 and the phase comparison component 130, the signal processing component 110, the phase detector 120 and the phase comparison component 130 are connected end to end in sequence, and the phase comparison component 130 can obtain the phase adjustment signal according to the first phase difference signal output by the phase detector 120. Signal processing component 110 can adjust the phase of the reference clock signal based on the phase adjustment signal to reduce the value of the first phase difference signal. Specifically, through the interaction between phase detector 120, phase comparison component 130, and signal processing component 110, the phase of the reference clock signal is adjusted to gradually reduce the first phase difference signal output by phase detector 120, so that the phase of the reference clock signal gradually approaches the phase of the clock signal to be measured, thereby improving the accuracy of the first phase difference signal obtained by phase detector 120 based on the reference clock signal and the clock signal to be measured. Furthermore, because the phase adjustment of the reference clock signal is performed within the value range of the first phase difference signal and is intended to reduce the first phase difference signal, only a limited number of processing operations within the value range of the first phase difference signal are required to achieve phase detection of the clock signal to be measured. Compared to the related art method of traversing a clock cycle to obtain phase information, this embodiment can achieve a better phase detection speed, thereby improving the phase detection accuracy and speed of the clock signal.

[0039] In one embodiment, the signal processing component 110 may include a field programmable gate array (FPGA) chip configured with a phase shifter function, or may include a combination of a digital signal processing (DSP) chip and a digital phase shifter, although this embodiment is not particularly limited thereto. If the signal processing component 110 includes a combination of a DSP chip and a digital phase shifter, the digital phase shifter will obtain a reference clock signal, while the DSP chip will obtain the reference clock signal and an initial phase value of the reference clock signal. Based on the phase adjustment signal output by the phase comparison component 130, the DSP chip will output a configuration signal to the digital phase shifter, causing the digital phase shifter to adjust the phase of the reference clock signal based on the configuration signal to reduce the first phase difference signal obtained by the phase detection component 120 based on the reference clock signal and the clock signal to be measured. Furthermore, the DSP chip will accumulate the phase value of the reference clock signal during the phase adjustment and obtain the phase value of the clock signal to be measured based on the accumulated phase value and the initial phase value of the reference clock signal.

[0040] In one embodiment, the phase detector 120 may be a digital phase detector or an analog phase detector. When the phase detector 120 is a digital phase detector, the phase detector 120 may be an independent digital phase detector or a digital phase detector integrated into the signal processing component 110. For example, the phase detector 120 may be a functional component in an FPGA chip. This embodiment does not specifically limit the specific implementation of the phase detector 120.

[0041] In one embodiment, the phase comparison component 130 may include a signal processing chip such as an FPGA chip, or may include a logic processing chip such as a comparator, which is not specifically limited in this embodiment.

[0042] When the phase comparison component 130 includes a signal processing chip such as an FPGA chip, upon receiving the first phase difference signal output by the phase detector 120, the phase comparison component 130 may first determine whether the first phase difference signal satisfies a preset condition. If the preset condition is satisfied, the phase comparison component 130 outputs a corresponding phase adjustment signal. For example, if the phase comparison component 130 determines that the first phase difference signal is within a first preset interval, the phase comparison component 130 may output a phase adjustment signal for positively shifting the reference clock signal. If the phase comparison component 130 determines that the first phase difference signal is within a second preset interval, the phase comparison component 130 may output a phase adjustment signal for negatively shifting the reference clock signal. It is worth noting that the preset condition can be appropriately set based on actual application needs and is not specifically limited in this embodiment. Furthermore, the first and second preset intervals can also be appropriately set based on actual application needs and are not specifically limited in this embodiment.

[0043] When the phase comparison component 130 includes a logic processing chip such as a comparator, upon receiving the first phase difference signal output by the phase detector 120, the phase comparison component 130 may perform a logical comparison between the first phase difference signal and a reference signal and output a corresponding phase adjustment signal based on the comparison result. For example, when the first phase difference signal is greater than the reference signal, the phase comparison component 130 may output a phase adjustment signal for causing a negative phase shift in the reference clock signal; whereas, when the first phase difference signal is less than the reference signal, the phase comparison component 130 may output a phase adjustment signal for causing a positive phase shift in the reference clock signal. It is worth noting that the reference signal can be a signal set based on experience or a signal related to the reference clock signal. It can be appropriately set based on actual application needs and is not specifically limited in this embodiment.

[0044] In addition, refer to Figure 2 In one embodiment, the phase comparison component 130 includes, but is not limited to, a first signal generating component 131 and a signal comparing component 132. The first signal generating component 131 is connected to the phase detector 120, and the signal comparing component 132 is connected to the first signal generating component 131 and the signal processing component 110, respectively. The first signal generating component 131 can be used to obtain a first voltage signal based on the first phase difference signal; the signal comparing component 132 can be used to obtain a reference voltage signal and the first voltage signal, and to obtain a phase adjustment signal for adjusting the phase of the reference clock signal based on the reference voltage signal and the first voltage signal.

[0045] In one embodiment, the first signal generating component 131 may be a charge pump, also known as a switched capacitor voltage converter, which can output a voltage value by charging and storing energy. When the first signal generating component 131 receives the first phase difference signal output by the phase detector 120, the first signal generating component 131 can charge according to the duration indicated by the first phase difference signal, thereby generating a first voltage signal, thereby providing the necessary foundation for obtaining the phase adjustment signal in the subsequent steps.

[0046] In one embodiment, the signal comparison component 132 may be a voltage comparator, wherein the reference voltage signal may be a voltage signal set based on experience or a voltage signal related to the reference clock signal. The reference voltage signal may be appropriately set based on actual application needs and is not specifically limited in this embodiment. After the signal comparison component 132 obtains the reference voltage signal and the first voltage signal, the signal comparison component 132 may derive a phase adjustment signal for phase adjustment of the reference clock signal based on the reference voltage signal and the first voltage signal. For example, when the voltage value of the first voltage signal is greater than the voltage value of the reference voltage signal, the signal comparison component 132 may output a phase adjustment signal with a high level value. This high level phase adjustment signal can be used to cause the signal processing component 110 to perform a negative phase shift on the reference clock signal. When the voltage value of the first voltage signal is less than the voltage value of the reference voltage signal, the signal comparison component 132 may output a phase adjustment signal with a low level value. This low level phase adjustment signal can be used to cause the signal processing component 110 to perform a positive phase shift on the reference clock signal. When the voltage value of the first voltage signal is equal to the voltage value of the reference voltage signal, the signal comparison component 132 may output a phase adjustment signal with an intermediate level value. This intermediate level phase adjustment signal can be used to cause the signal processing component 110 to stop performing the phase adjustment operation on the reference clock signal. It is worth noting that the intermediate level is a level between a high level and a low level. Therefore, through the mutual cooperation of the first signal generating component 131 and the signal comparing component 132, an accurate adjustment direction can be provided for the phase adjustment of the reference clock signal by the signal processing component 110, so that the phase of the reference clock signal can be close to the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component 120, and further improving the phase detection accuracy of the clock signal.

[0047] In addition, refer to Figure 3In one embodiment, the phase comparison component 130 may further include a second signal generating component 133, wherein the second signal generating component 133 is connected to the signal comparing component 132. The second signal generating component 133 may be configured to obtain a phase reference signal and obtain a reference voltage signal based on the phase reference signal, wherein the phase reference signal is obtained based on the reference clock signal.

[0048] In one embodiment, the second signal generating component 133 may be a charge pump, also known as a switched capacitor voltage converter, which can output a voltage value by storing energy through charging. When the second signal generating component 133 receives a phase reference signal, it can charge according to the duration indicated by the phase reference signal to generate a reference voltage signal, thereby providing the necessary foundation for obtaining the phase adjustment signal in subsequent steps.

[0049] In one embodiment, the phase reference signal can be obtained based on the period of the reference clock signal. For example, the phase reference signal can be half a period of the reference clock signal or a quarter of a period of the reference clock signal. An appropriate selection can be made based on actual usage needs, and this embodiment does not make any specific limitations.

[0050] In one embodiment, the phase reference signal is a preset fixed value. Therefore, the reference voltage signal obtained by the second signal generating component 133 by charging according to the duration represented by the phase reference signal is also a fixed value, which can be easily compared with the first voltage signal to obtain the phase adjustment signal.

[0051] In addition, refer to Figure 4 In one embodiment, the signal processing component 110 includes, but is not limited to, a controller 111 and a phase shifting component 112, wherein the phase comparison component 130, the controller 111, the phase shifting component 112, and the phase detector 120 are sequentially connected. The controller 111 can be used to obtain an initial phase value of a reference clock signal, and can be used to obtain a phase-shifted signal based on a phase adjustment signal output by the phase comparison component 130, and can be used to send this phase-shifted signal to the phase shifting component 112. The phase shifting component 112 can be used to obtain the reference clock signal and adjust the phase of the reference clock signal based on the phase-shifted signal to reduce a first phase difference signal output by the phase detector 120 based on the reference clock signal and the clock signal to be measured. In addition, the controller 111 can also be used to accumulate the phase-shifted signal to obtain a phase accumulation value, and then obtain the phase value of the clock signal to be measured based on this phase accumulation value and the initial phase value of the reference clock signal.

[0052] In one embodiment, the controller 111 can have different implementations. For example, the controller 111 can be an FPGA chip, a DSP chip, or a combination of a control chip and a frequency divider, which is not specifically limited in this embodiment. When the controller 111 is a combination of a control chip and a frequency divider, the frequency divider can be responsible for generating binary information (such as the phase-shifted signal in this embodiment), and the control chip can be responsible for configuring the binary information for the phase shift component 112, so that the phase shift component 112 can adjust the phase shift of the reference clock signal based on the binary information. In addition, the phase shift component 112 can also have different implementations. For example, the phase shift component 112 can be a digital phase shifter or an analog phase shifter with configuration capabilities, which is not specifically limited in this embodiment.

[0053] In one embodiment, when the controller 111 cooperates with the phase shifting component 112 to adjust the phase of the reference clock signal, the controller 111 can also accumulate the phase shifted signal to obtain a phase accumulation value. Therefore, when the detection is completed, the phase value of the clock signal to be measured can be obtained based on the phase accumulation value and the initial phase value of the reference clock signal, thereby realizing the detection process of the phase of the clock signal to be measured. Taking a specific example to illustrate, when the controller receives the phase adjustment signal, the controller can obtain the phase shifted signal based on the phase adjustment signal. Among them, k is the number of phase adjustments to the reference clock signal, and T is the period of the reference clock signal. Therefore, when the controller accumulates the phase-shifted signal, the phase accumulation value can be obtained as

[0054] In one embodiment, when the phase comparison component 130 includes a signal comparison component 132, and the signal comparison component 132 outputs a phase adjustment signal for performing phase adjustment on the reference clock signal to the controller 111, the controller 111 may send different types of configuration information to the phase shift component 112 according to different types of the phase adjustment signal, so that the phase shift component 112 can perform different phase adjustment processing on the reference clock signal according to different types of configuration information. For example, when the level of the phase adjustment signal is high, the controller 111 sends configuration information indicating a negative phase shift to the phase shift component 112, causing the phase shift component 112 to perform a negative phase shift on the reference clock signal according to the configuration information indicating a negative phase shift. When the level of the phase adjustment signal is low, the controller 111 sends configuration information indicating a positive phase shift to the phase shift component 112, causing the phase shift component 112 to perform a positive phase shift on the reference clock signal according to the configuration information indicating a positive phase shift. When the level of the phase adjustment signal is an intermediate level, the controller 111 does not send any configuration information to the phase shift component 112, meaning that the phase shift component 112 does not perform a phase adjustment on the reference clock signal. It is worth noting that an intermediate level is a level between a high level and a low level. Therefore, through the cooperation between the controller 111 and the phase shift component 112, the phase of the reference clock signal can be adjusted in an accurate adjustment direction, so that the phase of the reference clock signal can approach the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component 120, and further improving the phase detection accuracy of the clock signal.

[0055] In addition, in one embodiment, the signal processing component 110 further includes a counter, wherein the counter may be built into the controller 111 or may be external to the controller 111 and connected to the controller 111 .

[0056] In one embodiment, the count value of the counter can not only be used to indicate the number of times the signal processing component 110 adjusts the phase of the reference clock signal, but can also be used to obtain a phase shift signal for adjusting the phase of the reference clock signal.

[0057] In one embodiment, a maximum count value can be set for the counter. When the current count value of the counter reaches the maximum count value, that is, the number of phase adjustments performed by the signal processing component 110 on the reference clock signal reaches the preset maximum number of adjustments, or when the controller 111 receives a phase adjustment signal with an intermediate level, the controller 111 will reset the counter to 0. When the controller 111 resets the counter, it indicates that the phase measurement has ended, facilitating the next phase detection. It is worth noting that the intermediate level is a level between a high level and a low level.

[0058] In addition, in one embodiment, the controller 111 is specifically configured to obtain the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value using the following formula:

[0059]

[0060] Wherein, T1 is the phase value of the clock signal to be measured; T2 is the initial phase value of the reference clock signal; is the phase accumulation value; T is the period of the reference clock signal; n is the number of phase adjustments made to the reference clock signal, n≥1.

[0061] In one embodiment, This determines the accuracy of phase detection. Let's take a specific example to illustrate:

[0062] For example, if phase detection is required for a 125 MHz stamped clock signal with an 8 ns period, then, using a reference clock signal with the same frequency as the stamped clock signal, the phase detection apparatus 100 of this embodiment performs phase detection on the stamped clock signal. If the maximum count value of the counter is set to 10, i.e., the signal processing component 110 performs nine phase adjustments on the reference clock signal (with no initial phase adjustment), then, according to the above formula, the final measurement accuracy is approximately 8 ps. If, however, measurement is performed using the related art method of traversing a clock cycle to obtain phase information, 1000 phase shift operations are required to achieve the same measurement accuracy, i.e., traversing a clock cycle with an 8 ps step to obtain phase information. Therefore, compared to the related art, the present embodiment has a superior phase detection speed. Furthermore, when the same number of phase shifts is performed, as can be seen from the above example, the present embodiment has superior phase detection accuracy compared to the related art.

[0063] In addition, refer to Figure 5 Another embodiment of the present invention further provides a phase detection device, which includes a controller 211, a digital phase shifter 212, a digital phase detector 220, a first charge pump 231, a voltage comparator 232, a second charge pump 233, and a counter 213. The controller 211, the digital phase shifter 212, the digital phase detector 220, the first charge pump 231, and the voltage comparator 232 are connected end to end in sequence. The controller 211 is also connected to the counter 213, and the voltage comparator 232 is also connected to the second charge pump 233.

[0064] Reference Figure 5 When the phase detection device 200 is used to perform phase detection on the clock signal to be measured, the various components in the phase detection device 200 cooperate with each other to implement the following detection principle:

[0065] Before starting the phase detection operation, the second charge pump 233 first performs a phase detection operation for a period of The charging process is performed to obtain a reference voltage signal with a voltage value of Vref, where T is the period of the reference clock signal, and the second charge pump 233 sends the reference voltage signal to the voltage comparator 232.

[0066] The controller 211 sets the maximum count value of the counter 213 to n, and enables the counter 213 to start counting from 0.

[0067] Before starting the phase detection operation, since the current count value of the counter 213 is 0, the phase adjustment of the reference clock signal is not performed. At this time, the digital phase shifter 212 outputs the initial reference clock signal to the digital phase detector 220. The digital phase detector 220 obtains and outputs a first phase difference signal to the first charge pump 231 based on the initial reference clock signal and the clock signal to be measured. The first charge pump 231 charges according to the duration represented by the first phase difference signal and outputs a first voltage signal to the voltage comparator 232. The voltage comparator 232 obtains and outputs a phase adjustment signal to the controller 211 based on the first voltage signal and the reference voltage signal.

[0068] When the controller 211 receives the phase adjustment signal, it starts to perform the phase detection operation on the clock signal to be measured. At this time, the count value of the counter 213 increases by 1. When the level value of the phase adjustment signal is high, the controller 211 cooperates with the digital phase shifter 212 to make the reference clock signal shift by Perform negative phase shifting to make the phase of the reference clock signal close to the phase of the clock signal to be measured; when the level value of the phase adjustment signal is low, the controller 211 cooperates with the digital phase shifter 212 to make the reference clock signal shift by Positive phase shift is performed so that the phase of the reference clock signal can approach the phase of the clock signal to be measured.

[0069] After the controller 211 and the digital phase shifter 212 cooperate to adjust the phase of the reference clock signal, the phase-adjusted reference clock signal is input into the digital phase detector 220. At this point, the digital phase detector 220 obtains and outputs a new first phase difference signal based on the phase-adjusted reference clock signal and the clock signal to be measured. The first charge pump 231 and the voltage comparator 232 cooperate to output a new phase adjustment signal to the controller 211 based on the new first phase difference signal. This detection cycle continues until the count value of the counter 213 reaches a preset maximum count value, completing the phase detection operation for the clock signal to be measured. At this point, the following results can be obtained:

[0070]

[0071] Wherein, T1 is the phase value of the clock signal to be measured; T2 is the initial phase value of the reference clock signal; is the phase accumulation value; T is the period of the reference clock signal; n is the number of phase adjustments made to the reference clock signal, n≥1.

[0072] Furthermore, it's worth noting that when the phase adjustment signal reaches an intermediate level (i.e., a level between a high level and a low level), this indicates that the phase difference between the reference clock signal and the clock signal under test is half a cycle. At this point, the phase adjustment operation on the reference clock signal is terminated, and the phase detection operation ends. In this case, the phase value of the clock signal under test can also be obtained according to the aforementioned formula, which will not be further described here.

[0073] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0074] In addition, refer to Figure 6 An embodiment of the present invention further provides a phase detection method, which can be applied to the phase detection device in the above device embodiment. The phase detection method includes but is not limited to the following steps:

[0075] Step S100: The signal processing component obtains a reference clock signal and an initial phase value of the reference clock signal, and outputs the reference clock signal to the phase detection component;

[0076] Step S200: The phase detector component obtains the clock signal to be measured, obtains a first phase difference signal according to the reference clock signal and the clock signal to be measured, and outputs the first phase difference signal to the phase comparison component;

[0077] Step S300: The phase comparison component obtains a phase adjustment signal according to the first phase difference signal, and outputs the phase adjustment signal to the signal processing component;

[0078] In step S400, the signal processing component performs phase adjustment on the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, and accumulates the adjusted phase value to obtain a phase accumulation value, and obtains the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value.

[0079] In one embodiment, the clock signal to be measured is a clock signal that requires phase detection, and the reference clock signal is a known clock signal used to detect the phase of the clock signal to be measured. When the signal processing component first obtains the reference clock signal, the signal processing component can obtain the initial phase value of the reference clock signal, thereby providing the necessary basic conditions for obtaining the phase value of the clock signal to be measured in subsequent operations.

[0080] In one embodiment, the first phase difference signal is a signal obtained by a phase detector based on a reference clock signal and a clock signal to be measured. Due to limitations such as manufacturing processes or calculation accuracy of the phase detector, the first phase difference signal output by the phase detector is not accurate. Therefore, the first phase difference signal output by the phase detector is transmitted to a phase comparison component, so that the phase comparison component can obtain a phase adjustment signal based on the first phase difference signal. The phase adjustment signal is then transmitted to a signal processing component, and the signal processing component adjusts the phase of the reference clock signal based on the phase adjustment signal to reduce the value of the first phase difference signal. In other words, through the interaction between the phase detector, the phase comparison component, and the signal processing component, the phase of the reference clock signal is adjusted to gradually reduce the first phase difference signal output by the phase detector, so that the phase of the reference clock signal gradually approaches the phase of the clock signal to be measured, thereby improving the accuracy of the first phase difference signal obtained by the phase detector based on the reference clock signal and the clock signal to be measured. In addition, since the phase adjustment of the reference clock signal is performed within the numerical range of the first phase difference signal and is intended to reduce the first phase difference signal, only a limited number of processing times within the numerical range of the first phase difference signal are required to achieve phase detection of the clock signal to be measured. Compared with the method of traversing a clock cycle to obtain phase information in the related art, this embodiment can have a better phase detection speed. Therefore, this embodiment can improve the phase detection accuracy and phase detection speed of the clock signal.

[0081] It is worth noting that since the phase detection method of this embodiment can be applied to the phase detection device in the above-mentioned device embodiment, the specific implementation methods of the signal processing component, phase detection component and phase comparison component in this embodiment can refer to the relevant description in the above-mentioned device embodiment and will not be repeated here.

[0082] In addition, in one embodiment, when the phase comparison component includes a first signal generating component and a signal comparing component, and the signal processing component, the phase detection component, the first signal generating component and the signal comparing component are connected end to end in sequence, then, referring to Figure 7 The step S300 may include but is not limited to the following steps:

[0083] Step S310: The first signal generating component obtains a first voltage signal according to the first phase difference signal, and outputs the first voltage signal to the signal comparing component;

[0084] In step S320 , the signal comparison component obtains the reference voltage signal and the first voltage signal, and obtains a phase adjustment signal according to the reference voltage signal and the first voltage signal. The signal comparison component outputs the phase adjustment signal to the signal processing component.

[0085] In one embodiment, the first signal generating component may be a charge pump, also known as a switched capacitor voltage converter, which can output a voltage value by charging and storing energy. After receiving the first phase difference signal output by the phase detector component, the first signal generating component may charge according to the duration indicated by the first phase difference signal, thereby generating a first voltage signal, thereby providing the necessary foundation for obtaining the phase adjustment signal in subsequent steps.

[0086] In one embodiment, the reference voltage signal may be a voltage signal set based on experience, or a voltage signal related to a reference clock signal. It may be appropriately set according to actual application requirements, and this embodiment does not impose any specific limitation.

[0087] In one embodiment, after the signal comparison component obtains the reference voltage signal and the first voltage signal, the signal comparison component may obtain a phase adjustment signal for performing phase adjustment on the reference clock signal based on the reference voltage signal and the first voltage signal. For example, when the voltage value of the first voltage signal is greater than the voltage value of the reference voltage signal, the signal comparison component may output a phase adjustment signal with a high level. The phase adjustment signal with a high level may be used to cause the signal processing component to perform a phase adjustment on the reference clock signal by performing a negative phase shift. For another example, when the voltage value of the first voltage signal is less than the voltage value of the reference voltage signal, the signal comparison component may output a phase adjustment signal with a low level. The phase adjustment signal with a low level may be used to cause the signal processing component to perform a phase adjustment on the reference clock signal by performing a positive phase shift. For another example, when the voltage value of the first voltage signal is equal to the voltage value of the reference voltage signal, the signal comparison component may output a phase adjustment signal with an intermediate level (i.e., a level between a high level and a low level). The phase adjustment signal with an intermediate level may be used to cause the signal processing component to stop performing a phase adjustment operation on the reference clock signal. It is worth noting that among the various specific examples in which the signal comparison component obtains the phase adjustment signal according to the reference voltage signal and the first voltage signal, different combination examples can be formed according to actual conditions. In order to avoid repetition, they will not be described here.

[0088] In one embodiment, through the mutual cooperation of the first signal generating component and the signal comparing component, an accurate adjustment direction can be provided for the phase adjustment of the reference clock signal by the signal processing component, so that the phase of the reference clock signal can be close to the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component, and further improving the phase detection accuracy of the clock signal.

[0089] In addition, in one embodiment, when the phase comparison component further includes a second signal generating component, and the second signal generating component is connected to the signal comparison component, then, referring to Figure 8 , the phase detection method may further include the following steps:

[0090] Step S500: The second signal generating component obtains a phase reference signal and obtains a reference voltage signal according to the phase reference signal, wherein the phase reference signal is obtained according to a reference clock signal;

[0091] In step S600 , the second signal generating component outputs a reference voltage signal to the signal comparing component.

[0092] In one embodiment, the second signal generating component may be a charge pump, also known as a switched capacitor voltage converter, which can output a voltage value by charging and storing energy. When the second signal generating component receives a phase reference signal, it can charge according to the duration indicated by the phase reference signal to generate a reference voltage signal, thereby providing the necessary foundation for obtaining a phase adjustment signal in subsequent steps.

[0093] In one embodiment, the phase reference signal can be obtained based on the period of the reference clock signal. For example, the phase reference signal can be half a period of the reference clock signal or a quarter of a period of the reference clock signal. An appropriate selection can be made based on actual usage needs, and this embodiment does not make any specific limitations.

[0094] In addition, in one embodiment, the signal processing component in step S400 performs phase adjustment on the reference clock signal according to the phase adjustment signal, which may include different specific steps in different embodiments:

[0095] In step S401 , when the level of the phase adjustment signal is high, the signal processing component performs a negative phase shift on the reference clock signal.

[0096] In step S402 , when the level of the phase adjustment signal is low, the signal processing component performs a positive phase shift adjustment on the reference clock signal.

[0097] In step S403 , when the level of the phase adjustment signal is an intermediate level, the signal processing component does not perform phase adjustment on the reference clock signal, wherein the intermediate level is a level between a high level and a low level.

[0098] It is worth noting that the above-mentioned steps S401, S402 and S403 can be parallel technical solutions, or can be combined to form different technical solutions. Appropriate selection can be made according to actual conditions, and this embodiment does not make any specific restrictions on this.

[0099] In one embodiment, based on different level values ​​of the phase adjustment signal, the signal processing component can perform phase adjustment on the reference clock signal in different directions, so that the phase of the reference clock signal can be close to the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component, and further improving the phase detection accuracy of the clock signal.

[0100] In addition, in one embodiment, when the signal processing component includes a controller and a phase shift component, and the phase comparison component, the controller, the phase shift component and the phase detector component are connected end to end in sequence, then, referring to Figure 9 The step S400 may include but is not limited to the following steps:

[0101] Step S410: The controller obtains a phase-shifted signal according to the phase adjustment signal and outputs the phase-shifted signal to the phase-shifting component;

[0102] Step S420: the phase shifting component adjusts the phase of the reference clock signal according to the phase shift signal to reduce the first phase difference signal;

[0103] In step S430 , the controller accumulates the phase-shifted signal to obtain a phase accumulation value, and obtains a phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value.

[0104] In one embodiment, when the controller cooperates with the phase shifting component to adjust the phase of the reference clock signal, the controller can also accumulate the phase shifted signal to obtain a phase accumulation value. Therefore, when the detection is completed, the phase value of the clock signal to be measured can be obtained based on the phase accumulation value and the initial phase value of the reference clock signal, thereby realizing the detection process of the phase of the clock signal to be measured. Taking a specific example to illustrate, when the controller receives the phase adjustment signal, the controller can obtain the phase shifted signal based on the phase adjustment signal. Among them, k is the number of phase adjustments to the reference clock signal, and T is the period of the reference clock signal. Therefore, when the controller accumulates the phase-shifted signal, the phase accumulation value can be obtained as

[0105] In one embodiment, after receiving a phase adjustment signal, the controller may send different types of configuration information to the phase shift component based on the type of phase adjustment signal, so that the phase shift component can perform different phase adjustments on the reference clock signal based on the different types of configuration information. For example, when the level of the phase adjustment signal is high, the controller may send configuration information indicating a negative phase shift to the phase shift component, causing the phase shift component to perform a negative phase adjustment on the reference clock signal based on the configuration information indicating a negative phase shift. When the level of the phase adjustment signal is low, the controller may send configuration information indicating a positive phase shift to the phase shift component, causing the phase shift component to perform a positive phase adjustment on the reference clock signal based on the configuration information indicating a positive phase shift. When the level of the phase adjustment signal is an intermediate level, the controller may not send any configuration information to the phase shift component, i.e., the phase shift component may not perform a phase adjustment on the reference clock signal. It is worth noting that an intermediate level is a level between a high level and a low level. Therefore, through the mutual cooperation between the controller and the phase shift component, the phase of the reference clock signal can be adjusted in the accurate adjustment direction, so that the phase of the reference clock signal can approach the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component, and further improving the phase detection accuracy of the clock signal.

[0106] In addition, in one embodiment, when the signal processing component further includes a counter, and the counter is built into the controller, or the counter is external to the controller and connected to the controller, then, referring to Figure 10 The controller in step S410 obtains the phase-shifted signal according to the phase adjustment signal, which may include the following specific steps:

[0107] Step S411, the controller obtains the count value in the counter;

[0108] In step S412, the controller obtains a phase-shift signal according to the count value.

[0109] In one embodiment, the count value of the counter can be used not only to indicate the number of times the signal processing component has adjusted the phase of the reference clock signal, but can also be used to obtain a phase-shifted signal used to adjust the phase of the reference clock signal. Therefore, by obtaining the count value in the counter, it is possible to easily obtain the phase-shifted signal used to adjust the phase of the reference clock signal. Furthermore, the accumulated phase-shifted signals can be statistically calculated based on the count value to obtain the phase value of the clock signal to be measured.

[0110] In one embodiment, a maximum count value can be set for the counter. When the current count value of the counter is the maximum count value, that is, the number of phase adjustments of the reference clock signal by the signal processing component reaches a preset maximum number of adjustments, the controller can reset the counter to 0. When the controller resets the counter, it indicates that the phase measurement is completed, so that the next phase detection can be performed.

[0111] In addition, in one embodiment, the controller in step S430 obtains the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value, which may include the following specific steps:

[0112] In step S431, the controller obtains the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value using the following formula:

[0113]

[0114] Wherein, T1 is the phase value of the clock signal to be measured; T2 is the initial phase value; is the phase accumulation value; T is the period of the reference clock signal; n is the number of phase adjustments made to the reference clock signal, n≥1.

[0115] In one embodiment, according to the above formula, The accuracy of phase detection is determined. That is, when the phase detection method of this embodiment is used to perform phase detection on the clock signal to be measured, it is only necessary to perform a limited number of phase shifting processes on the reference clock signal to achieve relatively precise measurement accuracy. For example, when performing phase detection on a stamped clock signal with a frequency of 125 MHz, it is only necessary to perform 9 phase adjustments on the reference clock signal to obtain a detection result with a measurement accuracy of approximately 8 ps. However, if the method of traversing a clock cycle to obtain phase information in the related art is used for measurement, if the same measurement accuracy needs to be achieved, that is, traversing a clock cycle with a step of 8 ps to obtain phase information, 1000 phase shifting operations need to be performed. Therefore, compared with the related art, the present embodiment has a better phase detection speed. In addition, when the same number of phase shifting operations are performed, it can be seen from the above analysis that compared with the related art, the present embodiment has better phase detection accuracy.

[0116] In addition, an embodiment of the present invention further provides a device, which may include the phase detection device in any of the above device embodiments.

[0117] Since the device in this embodiment includes the phase detection device in any of the above embodiments, the device in this embodiment has the hardware structure of the phase detection device in the above embodiments, and the various components in the phase detection device can cooperate with each other to enable the device in this embodiment to perform the phase detection method in any of the above method embodiments. Therefore, the specific implementation of the device in this embodiment can refer to the above embodiments and will not be repeated here to avoid redundancy.

[0118] Since the device in this embodiment has the phase detection device in any of the above embodiments, the device in this embodiment has the technical effects brought by the phase detection device in the above embodiments, that is, compared with the related technology, the device in this embodiment can improve the phase detection accuracy and phase detection speed of the clock signal.

[0119] Those skilled in the art will appreciate that all or some of the steps and systems in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include computer storage media (or non-transitory media) and communication media (or temporary media). As known to those skilled in the art, the term computer storage media is included in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data) and is volatile and non-volatile, removable, and non-removable. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0120] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above implementation. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A phase detection device, characterized in that: include: a signal processing component, configured to obtain a reference clock signal and an initial phase value of the reference clock signal, and output the reference clock signal; a phase detection component connected to the signal processing component, configured to obtain a clock signal to be measured, and obtain and output a first phase difference signal based on the reference clock signal and the clock signal to be measured; a phase comparison component, connected to the phase detection component and the signal processing component respectively, and configured to obtain and output a phase adjustment signal according to the first phase difference signal; The signal processing component is further configured to perform phase adjustment on the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, accumulate the adjusted phase value to obtain a phase accumulation value, and obtain the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value; Wherein, the signal processing component includes: a controller, connected to the phase comparison component, configured to obtain an initial phase value of the reference clock signal and obtain and output a phase-shifted signal according to the phase adjustment signal; a phase shifting component, connected to the controller and the phase detector respectively, for acquiring the reference clock signal and adjusting the phase of the reference clock signal according to the phase shifting signal to reduce the first phase difference signal; The controller is further configured to accumulate the phase-shifted signal to obtain a phase accumulation value, and obtain a phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value.

2. The phase detection device according to claim 1, wherein The phase comparison component comprises: a first signal generating component, connected to the phase detection component, configured to obtain and output a first voltage signal according to the first phase difference signal; A signal comparison component is connected to the first signal generating component and the signal processing component respectively, and is used to obtain a reference voltage signal and the first voltage signal, and obtain and output the phase adjustment signal according to the reference voltage signal and the first voltage signal.

3. The phase detection device according to claim 2, wherein: The phase comparison component further comprises: The second signal generating component is connected to the signal comparing component, and is used to obtain a phase reference signal, and obtain and output the reference voltage signal according to the phase reference signal, wherein the phase reference signal is obtained according to the reference clock signal.

4. The phase detection device according to claim 1, wherein The signal processing component further includes: The counter is built into the controller or externally located in the controller and connected to the controller.

5. The phase detection device according to claim 1, wherein The controller is specifically configured to obtain the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value using the following formula: Wherein, T1 is the phase value of the clock signal to be measured; T2 is the initial phase value; is the phase cumulative value; T is the period of the reference clock signal; n is the number of phase adjustments made to the reference clock signal, n≥1; + / - represents positive phase shift and negative phase shift.

6. A phase detection method, applied to a phase detection device, the phase detection device comprising a signal processing component, a phase detector, and a phase comparison component connected end to end in sequence; the signal processing component comprising a controller and a phase shifter, the phase comparison component, the controller, the phase shifter, and the phase detector connected end to end in sequence; The method comprises: The signal processing component obtains a reference clock signal and an initial phase value of the reference clock signal, and outputs the reference clock signal to the phase detection component; The phase detection component obtains the clock signal to be measured, obtains a first phase difference signal according to the reference clock signal and the clock signal to be measured, and outputs the first phase difference signal to the phase comparison component; The phase comparison component obtains a phase adjustment signal according to the first phase difference signal, and outputs the phase adjustment signal to the signal processing component; The controller obtains a phase-shifted signal according to the phase adjustment signal, and outputs the phase-shifted signal to the phase-shifting component; The phase shifting component adjusts the phase of the reference clock signal according to the phase shift signal to reduce the first phase difference signal; The controller accumulates the phase-shifted signal to obtain a phase accumulation value, and obtains a phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value.

7. The method according to claim 6, characterized in that The phase comparison component includes a first signal generating component and a signal comparing component, and the signal processing component, the phase detection component, the first signal generating component and the signal comparing component are connected end to end in sequence; The phase comparison component obtains a phase adjustment signal according to the first phase difference signal, and outputs the phase adjustment signal to the signal processing component, comprising: The first signal generating component obtains a first voltage signal according to the first phase difference signal, and outputs the first voltage signal to the signal comparing component; The signal comparison component acquires a reference voltage signal and the first voltage signal, and obtains a phase adjustment signal according to the reference voltage signal and the first voltage signal. The signal comparison component outputs the phase adjustment signal to the signal processing component.

8. The method according to claim 7, characterized in that The signal comparing component obtains a phase adjustment signal according to the reference voltage signal and the first voltage signal, including at least one of the following: When the first voltage signal is greater than the reference voltage signal, the signal comparison component outputs a phase adjustment signal with a high level value; When the first voltage signal is equal to the reference voltage signal, the signal comparison component outputs a phase adjustment signal with an intermediate level, wherein the intermediate level is a level between a high level and a low level; When the first voltage signal is lower than the reference voltage signal, the signal comparison component outputs a phase adjustment signal with a low level value.

9. The method according to claim 7, characterized in that The phase comparison component further includes a second signal generating component, wherein the second signal generating component is connected to the signal comparing component; The method further comprises: The second signal generating component acquires a phase reference signal and obtains a reference voltage signal according to the phase reference signal, wherein the phase reference signal is obtained according to the reference clock signal; The second signal generating section outputs the reference voltage signal to the signal comparing section.

10. The method according to claim 6, characterized in that The signal processing component performs phase adjustment on the reference clock signal according to the phase adjustment signal, including at least one of the following: When the level value of the phase adjustment signal is a high level, the signal processing component performs a phase adjustment of a negative phase shift on the reference clock signal; When the level value of the phase adjustment signal is a low level, the signal processing component performs a positive phase shift on the reference clock signal; When the level value of the phase adjustment signal is an intermediate level, the signal processing component does not perform phase adjustment on the reference clock signal, wherein the intermediate level is a level between a high level and a low level.

11. The method according to claim 6, characterized in that The signal processing component further includes a counter, which is built into the controller or external to the controller and connected to the controller; The controller obtains a phase-shift signal according to the phase adjustment signal, including: The controller obtains the count value in the counter; The controller obtains a phase shift signal according to the count value.

12. The method according to claim 6, characterized in that The controller obtains the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value, including: The controller obtains the phase value of the clock signal to be measured according to the phase accumulation value and the initial phase value using the following formula: Wherein, T1 is the phase value of the clock signal to be measured; T2 is the initial phase value; is the phase cumulative value; T is the period of the reference clock signal; n is the number of phase adjustments made to the reference clock signal, n≥1; + / - represents positive phase shift and negative phase shift.

13. A communication device, characterized in that: The method comprises a phase detection device as claimed in any one of claims 1 to 5.

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