Solid-state imaging device and distance measuring device

Abstract

According to the present invention, the ranging accuracy is improved. A solid-state imaging device according to the embodiment includes a pixel array unit (101), in which a plurality of pixels (20-1) are arranged in a matrix, wherein each of the pixels includes: a plurality of photoelectric conversion units (211, 212) that perform photoelectric conversion on incident light to generate electric charge; a floating diffusion region (27) in which the electric charge is accumulated; a plurality of transfer circuits (23, 24, 25) that transfer the electric charge generated in each of the plurality of photoelectric conversion units to the floating diffusion region; and a first transistor (28) that causes a pixel signal having a voltage value corresponding to the charge amount of the electric charge accumulated in the floating diffusion region to appear on a signal line.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and a distance measuring device. Background Art

[0002] In the prior art, a distance measurement sensor using an indirect ToF (time of flight) method (hereinafter referred to as an indirect ToF sensor) is known. In an indirect ToF sensor, the distance to an object is measured based on a signal charge obtained by emitting light from a light source at a specific phase and receiving reflected light.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: JP 2019-4149A Summary of the invention

[0006] Technical issues

[0007] As a pixel architecture of an indirect ToF sensor, a 2-tap type pixel architecture in which one pixel has two memories is common. In the 2-tap type pixel architecture, a distance image representing the distance to an object is generated based on the ratio of charges accumulated in each of the two memories of each pixel.

[0008] Here, the characteristics of the two memories included in each pixel are generally different. This characteristic difference causes individual differences in the amount of charge accumulated in the memory of each pixel, resulting in a problem of reduced distance measurement accuracy of the indirect ToF sensor.

[0009] Therefore, the present disclosure proposes a solid-state imaging device and a distance measuring device capable of improving distance measuring accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 : is a block diagram showing a schematic configuration example of a ToF sensor as a distance measuring device according to the first embodiment.

[0011] Figure 2 is a block diagram showing a schematic configuration example of a solid-state image pickup device serving as a light receiving unit according to the first embodiment.

[0012] Figure 3 : is a circuit diagram showing a circuit configuration example of a unit pixel which is a basis of the unit pixel according to the first embodiment.

[0013] Figure 4 It is shown Figure 3 A plan view of an example layout of a unit pixel illustrated in FIG.

[0014] Figure 5 This is a diagram for explaining an overview of a distance measurement method based on an indirect ToF method (Part 1).

[0015] Figure 6 This is a diagram for explaining an overview of a distance measurement method based on an indirect ToF method (part 2).

[0016] Figure 7 is a circuit diagram showing a circuit configuration example of a unit pixel according to a first configuration example of the first embodiment.

[0017] Figure 8 is a plan view showing an example of a plan layout of a unit pixel according to a first configuration example of the first embodiment.

[0018] Fig. 9 is a circuit diagram showing a circuit configuration example of a unit pixel according to a second configuration example of the first embodiment.

[0019] Fig.10 is a plan view showing an example of a plan layout of a unit pixel according to a second configuration example of the first embodiment.

[0020] Fig.11 is a plan view showing an example of a plan layout of a unit pixel according to a third configuration example of the first embodiment.

[0021] Fig.12 is a circuit diagram showing a circuit configuration example of a unit pixel according to a fourth configuration example of the first embodiment.

[0022] Fig.13 is a plan view showing an example of a plan layout of a unit pixel according to a fourth configuration example of the first embodiment.

[0023] Fig.14 is a circuit diagram showing a circuit configuration example of a unit pixel according to a fifth configuration example of the first embodiment.

[0024] Fig.15 is a circuit diagram showing a circuit configuration example of a unit pixel according to a sixth configuration example of the first embodiment.

[0025] Fig.16 is a circuit diagram showing a circuit configuration example of a unit pixel according to a seventh configuration example of the first embodiment.

[0026] Fig.17 is a plan view showing a plan layout example of a pixel separation portion according to a first layout example of the first embodiment.

[0027] Fig.18 is a plan view showing a plan layout example of a pixel separation portion according to a second layout example of the first embodiment.

[0028] Fig.19 is a plan view showing a plan layout example of a pixel separation portion according to a third layout example of the first embodiment.

[0029] Fig. 20 : is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a first cross-sectional structural example of the first embodiment.

[0030] Fig.21 : is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a first cross-sectional structural example of the first embodiment.

[0031] Fig. 22 : is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a second cross-sectional structural example of the first embodiment.

[0032] Fig.23 : is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a second cross-sectional structural example of the first embodiment.

[0033] Fig.24 : is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a third cross-sectional structural example of the first embodiment.

[0034] Fig.25 is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a third cross-sectional structural example of the first embodiment.

[0035] Fig.26 : is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a fourth cross-sectional structural example of the first embodiment.

[0036] Fig. 27 : is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a fourth cross-sectional structural example of the first embodiment.

[0037] Fig.28 is a schematic diagram showing an example of a planar layout of a memory according to a first variation of the first embodiment.

[0038] Fig.29 is a schematic diagram showing an example of a planar layout of a memory according to a second variation of the first embodiment.

[0039] Fig.30 is a schematic diagram showing an example of a planar layout of a memory according to a third variation of the first embodiment.

[0040] Fig.31is a schematic diagram showing a planar layout example of a memory according to a fourth variation of the first embodiment.

[0041] Fig.32 is a schematic diagram showing an example of a planar layout of a memory according to a fifth variation of the first embodiment.

[0042] Fig.33 is a schematic diagram showing an example of a planar layout of a memory according to a sixth variation of the first embodiment.

[0043] Fig.34 is a schematic diagram showing a planar layout example of a memory according to a seventh variation of the first embodiment.

[0044] Fig.35 is a schematic diagram showing a plan layout example of a memory according to an eighth variation of the first embodiment.

[0045] Fig.36 is a schematic diagram showing a planar layout example of a memory according to a ninth variation of the first embodiment.

[0046] Fig.37 is a schematic diagram showing an example of a planar layout of a memory according to a tenth variation of the first embodiment.

[0047] Fig.38 is a schematic diagram showing a plan layout example of a memory according to an eleventh variation of the first embodiment.

[0048] Fig.39 is a schematic diagram showing a plan layout example of a memory according to a twelfth variation of the first embodiment.

[0049] Fig.40 is a schematic diagram showing an example of a planar layout of a memory according to a thirteenth variation of the first embodiment.

[0050] Fig.41 is a schematic diagram showing an example of a planar layout of a memory according to a fourteenth variation of the first embodiment.

[0051] Fig.42 is a schematic diagram showing an example of a plan layout of a memory according to a fifteenth variation of the first embodiment.

[0052] Fig.43 is a schematic diagram showing an example of a plan layout of a memory according to a sixteenth variation of the first embodiment.

[0053] Fig.44 It is a diagram for explaining the difference in the amount of accumulated charge between the memories generated in the comparative example.

[0054] Fig.45It is a diagram for explaining the effect of eliminating the characteristic difference between the memories according to the first embodiment.

[0055] Fig.46 is a timing chart showing a readout operation of a depth frame in the case of using a unit pixel not having an FD sharing structure according to the first embodiment.

[0056] Fig.47 is a timing chart showing a readout operation of a depth frame in the case of using a unit pixel having an FD sharing structure (for example, the unit pixel according to the first to third configuration examples described above) according to the first embodiment.

[0057] Fig.48 is a timing chart showing a readout operation of a depth frame in the case of using a unit pixel having an FD sharing structure (for example, the unit pixel according to the fourth configuration example described above) according to the first embodiment.

[0058] Fig.49 1 is a waveform diagram for explaining an example of a first driving pulse according to the first embodiment.

[0059] Fig.50 : is a schematic diagram showing an example of a connection relationship according to a modification example of the first embodiment.

[0060] Fig.51 is a schematic diagram showing another example of the connection relationship according to the modification example of the first embodiment.

[0061] Fig.52 is a schematic diagram showing still another example of the connection relationship according to the modification example of the first embodiment.

[0062] Fig.53 is a schematic diagram showing still another example of the connection relationship according to the modification example of the first embodiment.

[0063] Fig.54 is a schematic diagram showing still another example of the connection relationship according to the modification example of the first embodiment.

[0064] Fig.55 is a schematic diagram showing still another example of the connection relationship according to the modification example of the first embodiment.

[0065] Fig.56 2 is a waveform diagram for explaining an example of the second driving pulse according to the first embodiment.

[0066] Fig.57 This is a diagram for explaining noise generated by background light as interference light.

[0067] Fig.58: is a diagram for explaining a case where reflected light (interference light) from another ToF sensor is incident in a non-integration period.

[0068] Fig.59 : is a diagram for explaining a case where reflected light (interference light) from another ToF sensor is incident during the accumulation period.

[0069] Fig.60 is a diagram for explaining noise cancellation according to the first embodiment in a case where the modulation frequency of interference light from another ToF sensor is different from the modulation frequency of its own illumination light.

[0070] Fig.61 is a diagram for explaining noise cancellation according to the first embodiment in a case where the modulation frequency of interference light from another ToF sensor is the same as the modulation frequency of its own illumination light.

[0071] Fig.62 is a diagram for explaining noise cancellation according to the first embodiment in a case where the modulation frequency and phase of interference light from another ToF sensor are the same as those of its own illumination light.

[0072] Fig.63 is a waveform diagram showing a case where a ToF sensor and an object are in contact with each other.

[0073] Fig.64 is a waveform diagram showing a case where the ToF sensor and the object are separated from each other.

[0074] Fig.65 : is a waveform diagram (2-tap type) for explaining an example of the noise canceling operation at the time of phase switching according to the first embodiment.

[0075] Fig.66 2 is a waveform diagram for explaining an example of a noise canceling operation at the time of phase switching according to a modification of the first embodiment.

[0076] Fig.67 : is a waveform diagram (multi-tap type) for explaining an example of the noise canceling operation at the time of phase switching according to the first embodiment.

[0077] Fig.68 is a circuit diagram showing a circuit configuration example of a unit pixel according to a first configuration example of the second embodiment.

[0078] Fig.69 : is a circuit diagram showing a circuit configuration example of a unit pixel according to a second configuration example of the second embodiment.

[0079] Fig.70 is a circuit diagram showing a circuit configuration example of a unit pixel according to a third configuration example of the second embodiment.

[0080] Fig.71 This is a diagram schematically showing a configuration example of a non-stacked solid-state imaging device to which the technology according to the present disclosure can be applied.

[0081] Fig.72 This is a diagram showing an overview of a configuration example of a stacked solid-state imaging device to which the technology according to the present disclosure can be applied (Part 1).

[0082] Fig.73 This is a diagram showing an overview of a configuration example of a stacked solid-state imaging device to which the technology according to the present disclosure can be applied (part 2).

[0083] Fig.74 is a schematic diagram (front side) showing an example of an electronic device to which the technology according to the present disclosure can be applied.

[0084] Fig.75 is a schematic diagram showing an example of an electronic device to which the technology according to the present disclosure can be applied (latter).

[0085] Fig.76 is a schematic diagram showing a situation where the technology according to the present disclosure can be applied.

[0086] Fig.77 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0087] Fig.78 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0088] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the following embodiments, the same parts are denoted by the same reference numerals, and thus repeated descriptions will be omitted.

[0089] In addition, the present disclosure will be described in the following item order.

[0090] 1. First Implementation Method

[0091] 1.1 Distance measuring device (ToF sensor)

[0092] 1.2 Configuration Example of Solid-State Image Pickup Device

[0093] 1.3 Basic structure example of unit pixel

[0094] 1.4 Basic layout example of unit pixel

[0095] 1.5 Overview of Indirect ToF Methods

[0096] 1.6 Example of unit pixel structure

[0097] 1.6.1 First Configuration Example

[0098] 1.6.2 Second Configuration Example

[0099] 1.6.3 Example of the third structure

[0100] 1.6.4 Example of the fourth structure

[0101] 1.6.5 Example of the fifth structure

[0102] 1.6.6 Example of the sixth structure

[0103] 1.6.7 Example 7

[0104] 1.7 Pixel Separation Structure

[0105] 1.7.1 First layout example

[0106] 1.7.2 Second layout example

[0107] 1.7.3 Third layout example

[0108] 1.8 Example of cross-sectional structure of a unit pixel

[0109] 1.8.1 Example of the first section structure

[0110] 1.8.2 Second Section Structure Example

[0111] 1.8.3 Example of the third section structure

[0112] 1.8.4 Example of the fourth section structure

[0113] 1.9 FD shared layout

[0114] 1.9.1 First variant

[0115] 1.9.2 Second variant

[0116] 1.9.3 Third variant

[0117] 1.9.4 Fourth variant

[0118] 1.9.5 Fifth variant

[0119] 1.9.6 Sixth variant

[0120] 1.9.7 Seventh variant

[0121] 1.9.8 Eighth variant

[0122] 1.9.9 Ninth variant

[0123] 1.9.10 The tenth variant

[0124] 1.9.11 Eleventh Variant

[0125] 1.9.12 Twelfth variant

[0126] 1.9.13 Thirteenth Variant

[0127] 1.9.14 Fourteenth variant

[0128] 1.9.15 Fifteenth variant

[0129] 1.9.16 Sixteenth variant

[0130] 1.10 Elimination of characteristic differences

[0131] 1.11 Example of Reading Operation of Ranging Image (Depth Frame)

[0132] 1.12 Driving Pulse Example

[0133] 1.12.1 Example of the first drive pulse

[0134] 1.12.1.1 Variations

[0135] 1.12.2 Second drive pulse example

[0136] 1.13 Coding of accumulation periods

[0137] 1.13.1 Noise caused by interference

[0138] 1.13.1.1 Interference caused by background light

[0139] 1.13.1.2 Interference from another ToF sensor

[0140] 1.13.1.2.1 During the non-integration period, when reflected light from another ToF sensor is incident

[0141] 1.13.1.2.2 During the accumulation period, when the reflected light from another ToF sensor is incident

[0142] 1.13.2 Eliminating Noise Caused by Interference

[0143] 1.13.2.1 Example of noise removal by encoding the accumulation period

[0144] 1.13.2.1.1 Case where the modulation frequency of the interference light from another ToF sensor is different from the modulation frequency of its own illumination light

[0145] 1.13.2.1.2 When the modulation frequency of the interference light from another ToF sensor is the same as the modulation frequency of its own illumination light

[0146] 1.13.2.1.3 The case where the modulation frequency and phase of the interference light from another ToF sensor are the same as the modulation frequency and phase of its own illumination light

[0147] 1.13.3 Noise Generated During Phase Switching

[0148] 1.13.3.1 Example of noise cancellation operation at phase switching (in the case of 2-tap type)

[0149] 1.13.3.2 Modification of Noise Cancellation Operation During Phase Switching

[0150] 1.13.3.3 Modification of the noise cancellation operation at the time of phase switching (in the case of a multi-tap type with 3 or more taps)

[0151] 1.14 Function and Effect

[0152] 2. Second Implementation Method

[0153] 2.1 First Configuration Example

[0154] 2.2 Second Configuration Example

[0155] 2.3 Example of the third structure

[0156] 3. Configuration Example of a Stacked Solid-State Image Capturing Device to Which the Technology of the Present Disclosure Can Be Applied

[0157] 4. Examples of electronic devices to which the technology according to the present disclosure can be applied

[0158] 5. Various application examples

[0159] 6. Application examples for mobile objects

[0160] 1. First Implementation Method

[0161] First, the first embodiment will be described in detail below with reference to the drawings. Note that in the first embodiment, for example, a solid-state imaging device and a distance measuring device that measure the distance to an object using an indirect ToF method will be exemplified.

[0162] The solid-state imaging device and the distance measuring device according to the present embodiment and the following exemplary embodiments can be applied to, for example, the following equipment: an in-vehicle system that is mounted on a vehicle and measures the distance to an object outside the vehicle; a gesture recognition system that measures the distance to an object (for example, a user's hand, etc.) and recognizes the user's gesture based on the measurement result, etc. In this case, the result of the gesture recognition can also be used for the operation of a car navigation system, for example.

[0163] 1.1 Distance measuring device (ToF sensor)

[0164] Figure 11 is a block diagram showing a schematic configuration example of a ToF sensor as a distance measuring device according to the first embodiment. Figure 1 As shown, the ToF sensor 1 includes a control unit 11 , a light emitting unit 13 , a light receiving unit 14 , a calculation unit 15 , and an external interface (I / F) 19 .

[0165] The control unit 11 includes, for example, an information processing device such as a central processing unit (CPU), and controls each unit of the ToF sensor 1 .

[0166] The external I / F 19 can be, for example, a communication adapter for establishing communication with an external host 80 via a communication network that complies with any standard. In addition to a wireless LAN (local area network) or a wired LAN, the communication network can also be, for example, CAN (controller area network), LIN (local interconnectnetwork), FlexRay (registered trademark), MIPI (mobile industry processorinterface) or LVDS (low voltage differential signaling), etc.

[0167] Here, for example, when the ToF sensor 1 is installed in a car or the like, the host 80 may be an engine control unit (ECU) installed in the car or the like. In addition, in the case where the ToF sensor 1 is installed in an autonomous mobile robot (e.g., a domestic pet robot) or an autonomous mobile body (e.g., a cleaning robot, a drone, or a follow-up transport robot), the host 80 may be a control device for controlling the autonomous mobile body, etc. In addition, in the case where the ToF sensor 1 is installed in an electronic device such as a mobile phone, a smartphone, or a tablet terminal, the host 80 may be a CPU included in the electronic device or a server (including a cloud server, etc.) connected to the electronic device via a network, etc.

[0168] The light emitting unit 13 includes, for example, one or more semiconductor laser diodes as a light source, and the light emitting unit 13 emits a pulse laser (hereinafter referred to as irradiation light) L1 having a predetermined time width at a predetermined cycle (also referred to as a light emitting cycle). The light emitting unit 13 emits the irradiation light L1 at least toward an angle range equal to or greater than the viewing angle of the light receiving unit 14. In addition, the light emitting unit 13 emits the irradiation light L1 having a time width of several ns (nanoseconds) to 5 ns at a cycle of 100 MHz (megahertz), for example. For example, in the case where an object 90 exists within the ranging range, the irradiation light L1 emitted from the light emitting unit 13 is reflected by the object 90 and is incident on the light receiving unit 14 as reflected light L2.

[0169] Although details will be described later, the light receiving unit 14 includes, for example, a plurality of pixels arranged in a two-dimensional lattice pattern, and outputs signal intensity (hereinafter also referred to as a pixel signal) detected in each pixel after the light emitting unit 13 emits light.

[0170] The calculation unit 15 generates a depth image within the viewing angle of the light receiving unit 14 based on the pixel signal output from the light receiving unit 14. At this time, the calculation unit 15 can perform predetermined processing such as noise removal on the generated depth image. For example, the depth image generated by the calculation unit 15 can be output to the host 80 or the like via the external I / F 19.

[0171] 1.2 Configuration Example of Solid-State Image Pickup Device

[0172] Figure 2 is a block diagram showing a schematic configuration example of a solid-state imaging device as a light receiving unit according to the first embodiment.

[0173] Figure 2 The solid-state imaging device 100 shown is a back-illuminated indirect ToF sensor, and is provided in a distance measuring device having a distance measuring function.

[0174] The solid-state imaging device 100 includes a pixel array section 101 and peripheral circuits. The peripheral circuits may include, for example, a vertical drive circuit 103, a column processing circuit 104, a horizontal drive circuit 105, and a system control unit 102.

[0175] The solid-state imaging device 100 further includes a signal processing unit 106 and a data storage unit 107. Note that the signal processing unit 106 and the data storage unit 107 may be mounted on the same substrate as the solid-state imaging device 100, or may be arranged on a different substrate from the solid-state imaging device 100 in the distance measuring device.

[0176] The pixel array unit 101 has a structure in which pixels (hereinafter also referred to as unit pixels) 20 are arranged in row and column directions, i.e., in a matrix (also referred to as a two-dimensional grid shape), and the pixels 20 generate charges corresponding to the amount of light received and output signals corresponding to the charges.

[0177] Here, the row direction refers to the arrangement direction of the unit pixels 20 in the pixel row (lateral direction in the figure), and the column direction refers to the arrangement direction of the unit pixels 20 in the pixel column (vertical direction in the figure).

[0178] In the pixel array section 101, for a pixel array in a matrix form, a pixel drive line LD is arranged in the row direction for each pixel row, and two vertical signal lines VSL are arranged in the column direction for each pixel column. The pixel drive line LD transmits a drive signal for driving when a signal is read out from the unit pixel 20. Note that Figure 2 In the embodiment of the present invention, although the pixel drive line LD is shown as one wiring, it is not limited to one. One end of the pixel drive line LD is connected to the output end of the vertical drive circuit 103 corresponding to each row.

[0179] The vertical driving circuit 103 includes a shift register, an address decoder, and the like, and drives each unit pixel 20 of the pixel array section 101 simultaneously for all pixels or drives each unit pixel 20 of the pixel array section 101 in row units. That is, the vertical driving circuit 103 constitutes a driving unit that controls the operation of each unit pixel 20 of the pixel array section 101 together with the system control unit 102 that controls the vertical driving circuit 103.

[0180] Note that in the distance measurement using the indirect ToF method, the number of elements to be driven at high speed connected to one pixel drive line LD affects the controllability and driving accuracy of the high-speed drive. Here, in most cases, the pixel array portion of the solid-state imaging device used for distance measurement by the indirect ToF method is a rectangular area that is longer in the row direction. Therefore, in this case, as the pixel drive line LD of the element to be driven at high speed, a vertical signal line VSL or other control lines extending in the column direction can be used. In the case of such a configuration, for example, a plurality of unit pixels 20 arranged in the column direction are connected to the vertical signal line VSL and other control lines extending in the column direction, and through the vertical signal line VSL or other control lines, the driving of the unit pixel 20, that is, the driving of the solid-state imaging device 100, is performed by a driving unit and a horizontal driving circuit 105 that are separately provided from the vertical driving circuit 103.

[0181] The signal output from each unit pixel 20 of the pixel row according to the drive control of the vertical drive circuit 103 is input to the column processing circuit 104 through the vertical signal line VSL. The column processing circuit 104 performs predetermined signal processing on the signal output from each unit pixel 20 through the vertical signal line VSL, and temporarily holds the pixel signal after the signal processing.

[0182] Specifically, the column processing circuit 104 performs noise removal processing, analog-to-digital (AD) conversion processing, and the like as signal processing.

[0183] The horizontal driving circuit 105 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing circuit 104. Through the selective scanning of the horizontal driving circuit 105, pixel signals subjected to signal processing for each unit circuit in the column processing circuit 104 are sequentially output.

[0184] The system control unit 102 includes a timing generator for generating various timing signals and the like, and performs drive control of the vertical drive circuit 103 , the column processing circuit 104 , the horizontal drive circuit 105 and the like based on the various timing signals generated by the timing generator.

[0185] The signal processing unit 106 has at least an arithmetic processing function, performs various types of signal processing such as arithmetic processing based on the pixel signal output from the column processing circuit 104, and outputs the distance information of each pixel calculated thereby to the outside. The data storage unit 107 temporarily stores data required for the signal processing in the signal processing unit 106.

[0186] 1.3 Basic structure example of unit pixel

[0187] Here, a basic configuration example of the unit pixel 20 according to the present embodiment will be described using the circuit configuration of the unit pixel 920 as a basis. Figure 3 : is a circuit diagram showing a circuit configuration example of a unit pixel which is a basis of the unit pixel according to the first embodiment.

[0188] like Figure 3 As shown, the unit pixel 920 has a so-called 2-tap type circuit configuration, which includes a photodiode 21, an OFG (over flow gate) transistor 22, and two readout circuits 920A and 920B. Note that the 2-tap type may be a configuration in which two transfer gate transistors (also called taps) 23A and 23B are provided for one photodiode 21.

[0189] The photodiode 21 may be a photoelectric conversion element that performs photoelectric conversion on incident light to generate charge. The source of the OFG transistor 22 is connected to the cathode of the photodiode 21. The drain of the OFG transistor 22 is connected to the power supply line VDD, for example. In addition, the gate of the OFG transistor 22 is connected to the vertical drive circuit 103 via a pixel drive line LD (not shown).

[0190] The readout circuit 920A includes, for example, a transfer gate transistor 23A, a memory (also referred to as a tap) 24A, a transfer transistor 25A, a reset transistor 26A, an amplifier transistor 28A, and a selection transistor 29A.

[0191] In this specification, the transfer gate transistor, the memory, and the transfer transistor in each readout circuit are also referred to as a transfer circuit that transfers the charge generated in the photodiode 21 to the floating diffusion region 27, for example.

[0192] The source of the transfer gate transistor 23A is connected to the cathode of the photodiode 21, and the drain is connected to the memory 24A.

[0193] The memory 24A is, for example, a MOS (metal-oxide-semiconductor) type memory including a transistor and a capacitor, and temporarily holds the charge flowing in from the photodiode 21 via the transfer gate transistor 23A in the capacitor under the control of the vertical drive circuit 103 .

[0194] The transfer transistor 25A has a source connected to the memory 24A, a drain connected to the gate of the amplification transistor 28A, and a gate connected to the vertical drive circuit 103 via a pixel drive line LD (not shown).

[0195] A node connecting the drain of the transfer transistor 25A and the gate of the amplification transistor 28A forms a floating diffusion region (FD) 27A that converts the charge into a voltage having a voltage value corresponding to the amount of the charge.

[0196] The source of the amplifier transistor 28A is connected to the power supply line VDD, and the drain is connected to the vertical signal line VSLA via the selection transistor 29A. The amplifier transistor 28A causes the voltage value of the voltage applied to the gate, that is, the voltage value corresponding to the amount of charge accumulated in the floating diffusion region 27A, to appear in the vertical signal line VSLA as a pixel signal.

[0197] The source of the selection transistor 29A is connected to the drain of the amplification transistor 28A, the drain is connected to the vertical signal line VSLA, and the gate is connected to the vertical drive circuit 103 via a pixel drive line LD (not shown). Under the control of the vertical drive circuit 103, the selection transistor 29A causes a pixel signal having a voltage value corresponding to the amount of charge accumulated in the floating diffusion region 27A to appear in the vertical signal line VSLA.

[0198] The source of the reset transistor 26A is connected to a node connecting the drain of the transfer transistor 25A and the gate of the amplification transistor 28A, that is, connected to the floating diffusion region 27A. The drain of the reset transistor 26A is connected to the power supply line VDD, and the gate is connected to the vertical drive circuit 103 via the pixel drive line LD (not shown). The reset transistor 26A releases the charge accumulated in the floating diffusion region 27A under the control of the vertical drive circuit 103. That is, the reset transistor 26A initializes (resets) the floating diffusion region 27A according to the control of the vertical drive circuit 103.

[0199] On the other hand, the readout circuit 920B similarly includes a transfer gate transistor 23B, a memory 24B, a transfer transistor 25B, a reset transistor 26B, an amplifier transistor 28B, and a selection transistor 29B. The connection relationship and function of each circuit element may be the same as those of the readout circuit 920A.

[0200] 1.4 Basic layout example of unit pixel

[0201] Figure 4 It is shown Figure 3 The plan view of the layout example of the unit pixel shown. Note that Figure 4 An example of a planar layout of an element formation surface of a semiconductor substrate on which the photodiode 21 of the unit pixel 920 is formed is shown.

[0202] like Figure 4 As shown, each unit pixel 920 has a layout in which the photodiode 21, the OFG transistor 22, and two readout circuits 920A and 920B are arranged in a rectangular area when the element formation surface of the semiconductor substrate is viewed from the vertical direction.

[0203] A rectangular area (hereinafter also referred to as a pixel area) on the element formation surface of the semiconductor substrate is allocated to each unit pixel 920. For example, the photodiode 21 is arranged at the center of the pixel area. The OFG transistor 22 is arranged on two opposite sides of the four sides of the photodiode 21, and the transfer gate transistors 23A and 23B of the two readout circuits 920A and 920B are arranged on the remaining two sides.

[0204] The remaining circuit elements of each of the readout circuits 920A and 920B are arranged around the photodiode 21 to surround the photodiode 21. In this case, by arranging the memory 24A of the readout circuit 920A and the memory 24B of the readout circuit 920B to be point-symmetrical or line-symmetrical with the photodiode 21 as the center (hereinafter, referred to as "ensuring symmetry"), the characteristic difference between the two memories 24A and 24B can be reduced. Similarly, by arranging the remaining circuit elements of the readout circuit 920A and the remaining circuit elements of the readout circuit 920B to be point-symmetrical or line-symmetrical with the photodiode 21 as the center, the characteristic difference between the readout circuits 920A and 920B can be reduced.

[0205] 1.5 Overview of Indirect ToF Methods

[0206] Here, an outline of a distance measurement method using an indirect ToF method will be described. Figure 5 and Figure 6 Each of them is a diagram for explaining an overview of a distance measurement method using an indirect ToF method.

[0207] like Figure 5 As shown, in the indirect ToF method, the light receiving unit 14 detects the light amount Q0 of the reflected light L2 having a phase angle (also called a phase difference) of 0° with respect to the irradiation light L1 emitted from the light emitting unit 13, the light amount Q1 of the reflected light L2 having a phase angle of 90°, and the light amount Q2 of the reflected light L2 having a phase angle of 90°. 90 , the light quantity Q of the reflected light L2 having a phase angle of 180° 180 And the light quantity Q of the reflected light L2 having a phase angle of 270° 270 The phase here is the phase angle between the pulse of the irradiating light L1 and the pulse of the reflected light L2.

[0208] The phase angle α of the pulse of the reflected light L2 relative to the irradiated light L1 can be determined using, for example, Figure 6 The circle shown is used to represent this. Figure 6 In the figure, the horizontal axis represents the light quantity Q0 of the reflected light L2 having a phase angle of 0° and the light quantity Q 180 The vertical axis represents the light quantity Q of the reflected light L2 having a phase angle of 90°. 90 and the light quantity Q of the reflected light L2 having a phase angle of 270° 270 The difference between.

[0209] Then, the phase angle α can be obtained by, for example, converting the light quantities Q0, Q 90 , Q 180 and Q 270 Substitute into the following formula (1) to obtain.

[0210]

[0211] Here, the phase angle α of the pulse of the reflected light L2 relative to the irradiated light L1 corresponds to the round trip distance D from the ToF sensor 1 to the object 90. Therefore, the distance D from the ToF sensor 1 to the object 90 can be calculated by substituting the phase angle α calculated by equation (1) into the following equation (2). In equation (2), Δt is the time difference from the emission of the irradiated light L1 to the reception of the reflected light L2, and ω is the modulation frequency f mod is the angular frequency, and c is the speed of light.

[0212]

[0213] However, in the above method, since the uncertainty of the phase angle of 360° degenerates, the distance D to the object 90 whose phase angle α exceeds 360° cannot be accurately measured. fmod In the case of 100 MHz (megahertz), considering the distance to and from the object 90, the distance D cannot be obtained for the object 90 existing at a position exceeding about 1.5 m (meters).

[0214] Therefore, in this case, a different modulation frequency f is used mod to measure the distance to the object 90. Therefore, since the degradation can be resolved based on the result, the distance D to the object 90 existing at a certain distance or longer can be specified.

[0215] As described above, in the ToF sensor 1 , a distance image is created by acquiring four types of phase information of 0°, 90°, 180°, and 270°.

[0216] Then, as the pixel architecture, it is usually as mentioned above Figure 3 and Figure 4 The unit pixel includes a 2-tap pixel architecture in which two memories are provided. In this case, four sub-frames are required to obtain a ranging image (hereinafter referred to as a depth map or depth frame).

[0217] Specifically, four subframes of 0° / 180°, 90° / 270°, 180° / 0°, and 270° / 90° are required. Note that the 0° / 180° subframe is obtained by subtracting the light quantity Q1 at 180° from the light quantity Q0 at 0°. 180 Similarly, the 90° / 270° subframe is obtained by taking the light quantity Q from the phase angle α of 90° 90 Subtract the light Q at 270° from 270 The obtained subframe, the 180° / 0° subframe is obtained by the light quantity Q from the phase angle α of 180° 180The subframe of 270° / 90° is obtained by subtracting the light quantity Q0 at 0° from the phase angle α. 270 Subtract the light Q at 90° from 90 The obtained subframe.

[0218] Here, for example, the reason why a subframe of 0° / 180° and a subframe of 180° / 0° as inverted data of the subframe are required is that the charges accumulated in the two memories of each unit pixel differ (hereinafter referred to as characteristic difference) due to the arrangement of the readout circuit (including wiring distance, etc.) and the incident angle of incident light (i.e., image height), etc. That is, in order to obtain an accurate depth frame, the characteristic difference occurring in the two memories must be offset by acquiring inverted data and adding or subtracting the inverted data.

[0219] As described above, in the 2-tap type pixel architecture, there is a problem that the number of subframes required to acquire one depth frame increases due to a characteristic difference occurring in two memories.

[0220] Therefore, in the following description, some examples will be used to illustrate a structure that can more efficiently acquire subframes.

[0221] 1.6 Example of unit pixel structure

[0222] Hereinafter, a configuration example of the unit pixel 20 according to the first embodiment will be described by way of some examples.

[0223] 1.6.1 First Configuration Example

[0224] Figure 7 is a circuit diagram showing a circuit configuration example of a unit pixel according to a first configuration example of the first embodiment. Figure 8 : is a plan view showing an example of a plan layout of a unit pixel according to a first configuration example of the first embodiment. Note that Figure 8 An example of a planar layout of an element formation surface of a semiconductor substrate on which the photodiodes 211 and 212 of the unit pixel 20 - 1 are formed is shown. In the following description, when the photodiodes 211 and 212 are not distinguished, their reference numerals are 21 .

[0225] like Figure 7 As shown, the unit pixel 20-1 according to the first configuration example includes two groups of 2-tap type circuit configurations, and has a circuit configuration in which four readout circuits 20A1, 20A2, 20B1, and 20B2 constituting the circuit share one floating diffusion region 27. In the following description, when the readout circuits 20A1 and 20A2 are not distinguished, they are referred to as readout circuit A, and when the readout circuits 20B1 and 20B2 are not distinguished, they are referred to as readout circuit B.

[0226] The readout circuit 20A1 includes a transfer gate transistor 23A1, a memory 24A1, a transfer transistor 25A1, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29. Similarly, the readout circuit 20A2 includes a transfer gate transistor 23A2, a memory 24A2, a transfer transistor 25A2, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29, the readout circuit 20B1 includes a transfer gate transistor 23B1, a memory 24B1, a transfer transistor 25B1, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29, and the readout circuit 20B2 includes a transfer gate transistor 23B2, a memory 24B2, a transfer transistor 25B2, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29.

[0227] The cathode of the photodiode 211 is connected to the readout circuits 20A1 and 20B1 , and the cathode of the photodiode 212 is connected to the readout circuits 20A2 and 20B2 .

[0228] Furthermore, the OFG transistor 221 is connected to the cathode of the photodiode 211 , and the OFG transistor 222 is connected to the cathode of the photodiode 212 .

[0229] Among the four readout circuits 20A1, 20A2, 20B1, and 20B2, the readout circuit A is configured to detect the light quantity Q0 or Q1 of the component having the phase angle α of 0° or 90° with respect to the irradiation light L1 in the reflected light L2. 90 The readout circuit B is configured to detect the light quantity Q of the component having a phase angle α of 180° or 270° with respect to the irradiation light L1 in the reflected light L2. 180 or Q 270 Note that the light quantity Q of the component with a phase angle α of 90° 90 and the light quantity Q of the component having a phase angle α of 270° 270 The light quantity Q0 of the component with a phase angle α of 0° and the light quantity Q of the component with a phase angle α of 180° 180 For example, readout can be performed in time division by alternately switching readout from the same unit pixel 20 - 1 .

[0230] Furthermore, two readout circuits A are connected to the cathode of the photodiode 211 , and the remaining two readout circuits B are connected to the cathode of the photodiode 212 .

[0231] In addition, the four readout circuits 20A1, 20A2, 20B1, and 20B2 share the floating diffusion region 27, the reset transistor 26, the amplification transistor 28, and the selection transistor 29. The connection relationship of the circuit elements in each of the readout circuits 20A1, 20A2, 20B1, and 20B2 can be the same as that described above with reference to FIG. Figure 3 The connection relationship of the circuit elements in the readout circuits 20A and 20B of the unit pixel 920 is similar.

[0232] like Figure 8 As shown, in the planar layout of the unit pixel 20-1, the readout circuits A and B for detecting components having the same phase angle α are arranged in a pixel area assigned to one unit pixel 20-1, with point symmetry or line symmetry relative to the center of the pixel area or a straight line passing through the center as an axis. For example, the readout circuits 20A1 and 20A2 are arranged diagonally in the pixel area assigned to one unit pixel 20-1, and the readout circuits 20B1 and 20B2 are also arranged diagonally in the pixel area assigned to one unit pixel 20-1.

[0233] Specifically, in Figure 8 In the example shown, the readout circuit 20A1 is arranged at the upper left in the pixel area, and the readout circuit 20A2 is arranged at the lower right in the pixel area. On the other hand, among the readout circuits 20B1 and 20B2, the readout circuit 20B1 is arranged at the upper right in the pixel area, and the readout circuit 20B2 is arranged at the lower left in the pixel area.

[0234] As described above, in the first configuration example, the four readout circuits 20A1 , 20A2 , 20B1 , and 20B2 are arranged such that the readout circuits for detecting the light amount Q of the same phase angle α are arranged in a crossed manner.

[0235] Note that the photodiodes 211 and 212 may be arranged between readout circuits for generating the same subframe. For example, the photodiode 211 may be arranged between the readout circuits 20A1 and 20B1, and the photodiode 212 may be arranged between the readout circuits 20A2 and 20B2.

[0236] In this configuration, when the light quantity Q0 or Q1 at a phase angle α of 0° or 90° is detected, 90 When the phase angle α is 180° or 270°, the charge stored in the memory 24A1 of the readout circuit 20A1 and the charge stored in the memory 24A2 of the readout circuit 20A2 are both transferred to the floating diffusion region 27. Similarly, when the light quantity Q having a phase angle α of 180° or 270° is detected 180 or Q 270At this time, both the charge stored in the memory 24B1 of the readout circuit 20B1 and the charge stored in the memory 24B2 of the readout circuit 20B2 are transferred to the floating diffusion region 27.

[0237] As described above, in one unit pixel 20-1, the readout circuits for detecting components of the same phase angle α are diagonally positioned, and the charges stored in the memory are simultaneously transferred to the common floating diffusion region 27 at the time of readout, so that the difference in the amount of accumulated charge due to the difference in characteristics caused by the position of the readout circuit (image height), etc., can be reduced. As a result, a high-quality depth frame can be generated without acquiring inverted data, so that a high-quality depth frame can be generated at a high frame rate.

[0238] In addition, by sharing the structure downstream of the floating diffusion region 27 (reset transistor 26, amplification transistor 28, selection transistor 29, vertical signal line VSL, AD converter in column processing circuit 104, etc.) between each of the readout circuits 20A1, 20A2, 20B1, and 20B2, the characteristic difference caused by the downstream structure can be eliminated, so that a higher quality depth frame can be generated. Note that downstream refers to the downstream in the signal and data flow.

[0239] 1.6.2 Second Configuration Example

[0240] Fig. 9 is a circuit diagram showing a circuit configuration example of a unit pixel according to a second configuration example of the first embodiment. Fig.10 : is a plan view showing an example of a plan layout of a unit pixel according to a second configuration example of the first embodiment. Note that Fig.10 An example of a planar layout of an element formation surface of a semiconductor substrate on which the photodiodes 211 to 214 of the unit pixel 20 - 2 are formed is shown.

[0241] like Fig. 9 As shown, the unit pixel 20-2 according to the second configuration example includes four groups of 2-tap type circuit configurations, and includes a circuit configuration in which eight readout circuits 20A1 to 20A4 and 20B1 to 20B4 constituting the circuit share one floating diffusion region 27. In the following description, when the readout circuits 20A1 to 20A4 are not distinguished, they are referred to as readout circuits A, and when the readout circuits 20B1 to 20B4 are not distinguished, they are referred to as readout circuits B.

[0242] The circuits of the readout circuits 20A1, 20A2, 20B1, and 20B2 can be the same as those in the first configuration example. Figure 7The circuit configurations described are similar. In addition, the readout circuit 20A3 includes a transfer gate transistor 23A3, a memory 24A3, a transfer transistor 25A3, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29, the readout circuit 20A4 includes a transfer gate transistor 23A4, a memory 24A4, a transfer transistor 25A4, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29, the readout circuit 20B3 includes a transfer gate transistor 23B3, a memory 24B3, a transfer transistor 25B3, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29, and the readout circuit 20B4 includes a transfer gate transistor 23B4, a memory 24B4, a transfer transistor 25B4, a reset transistor 26, a floating diffusion region 27, an amplifier transistor 28, and a selection transistor 29.

[0243] The cathode of the photodiode 211 is connected to the readout circuits 20A1 and 20B1, the cathode of the photodiode 212 is connected to the readout circuits 20A2 and 20B2, the cathode of the photodiode 213 is connected to the readout circuits 20A3 and 20B3, and the cathode of the photodiode 214 is connected to the readout circuits 20A4 and 20B4.

[0244] Furthermore, the OFG transistor 221 is connected to the cathode of the photodiode 211 , the OFG transistor 222 is connected to the cathode of the photodiode 212 , the OFG transistor 223 is connected to the cathode of the photodiode 213 , and the OFG transistor 224 is connected to the cathode of the photodiode 214 .

[0245] In the eight readout circuits 20A1 to 20A4 and 20B1 to 20B4, the readout circuit A is configured to detect the light quantity Q0 or Q1 of the component having the phase angle α of 0° or 90° with respect to the irradiation light L1 in the reflected light L2. 90 The readout circuit B is configured to detect the light quantity Q of the component having a phase angle α of 180° or 270° with respect to the irradiation light L1 in the reflected light L2. 180 or Q 270 .

[0246] In addition, the eight readout circuits 20A1 to 20A4 and 20B1 to 20B4 share the floating diffusion region 27, the reset transistor 26, the amplification transistor 28, and the selection transistor 29. The connection relationship of the circuit elements in each of the readout circuits 20A1 to 20A4 and 20B1 to 20B4 can be the same as that described above with reference to FIG. Figure 3 The connection relationship of the circuit elements in the readout circuits 20A and 20B of the described unit pixel 920 is similar.

[0247] like Fig.10As shown, in the planar layout of the unit pixel 20-2, the readout circuit A or B for detecting components having the same phase angle α is arranged in a pixel area assigned to a unit pixel 20-2, with point symmetry or line symmetry relative to the center of the pixel area or a straight line passing through the center as an axis.

[0248] At this time, among the eight readout circuits 20A1 to 20A4 and 20B1 to 20B4, the readout circuits for generating the same subframe are arranged to be adjacent to each other across the photodiodes connected thereto. For example, the readout circuits 20A1 and 20B1 are adjacent to each other across the photodiode 211, the readout circuits 20A2 and 20B2 are adjacent to each other across the photodiode 212, the readout circuits 20A3 and 20B3 are adjacent to each other across the photodiode 213, and the readout circuits 20A4 and 20B4 are adjacent to each other across the photodiode 214.

[0249] exist Fig.10 In the example shown, in the readout circuits 20A1 to 20A4 for detecting the light amount Q0 of the component having the phase angle α of 0° or 90°, the readout circuit 20A1 is arranged at the upper left in the pixel area, the readout circuit 20A3 is arranged at the upper right in the pixel area, and the readout circuits 20A2 and 20A4 are arranged at the lower side near the center of the pixel area. On the other hand, in the readout circuits for detecting the light amount Q0 of the component having the phase angle α of 180° or 270°, 180 Among the readout circuits 20B1 to 20B4, the readout circuit 20B1 is arranged at the lower left in the pixel area, the readout circuit 20B3 is arranged at the lower right in the pixel area, and the readout circuits 20B2 and 20B4 are arranged on the upper side close to the center of the pixel area.

[0250] That is, in Fig.10 In the example shown, the layout is as follows: Figure 8 The two arrangements shown are a crosshanging arrangement and an arrangement obtained by inverting the crosshanging arrangement.

[0251] In this configuration, when the light quantity Q0 at the phase angle α of 0° or 90° is detected, the charges stored in the memories 24A1 to 24A4 of the readout circuits 20A1 to 20A4 are simultaneously transferred to the floating diffusion region 27. Similarly, when the light quantity Q0 at the phase angle α of 180° or 270° is detected, 180 At the same time, the charges stored in the memories 24B1 to 24B4 of the readout circuits 20B1 to 20B4 are simultaneously transferred to the floating diffusion region 27.

[0252] By such operation, in addition to the effect obtained in the first configuration example, the difference in the amount of accumulated charge caused by the characteristic difference caused by the position of the readout circuit (image height), etc. can be further reduced compared to the first configuration example. Therefore, a higher quality depth frame can be generated without acquiring inverted data.

[0253] 1.6.3 Example of the third structure

[0254] For example, the circuit configuration example of the unit pixel 20-3 according to the third configuration example can be the same as that of the reference numeral 20-3 in the second configuration example. Fig. 9 The circuit configuration example described is similar. Fig.11 : is a plan view showing an example of a plan layout of a unit pixel according to a third configuration example of the first embodiment. Note that Fig.11 An example of a planar layout of an element formation surface of a semiconductor substrate on which the photodiodes 211 to 214 of the unit pixel 20 - 3 are formed is shown.

[0255] By comparison Fig.10 and Fig.11 It can be seen that in the second configuration example, the reset transistor 26, the amplifying transistor 28 and the selecting transistor 29 are respectively arranged in separate diffusion regions 26a, 28a and 29a, while in the third configuration example, the reset transistor 26, the amplifying transistor 28 and the selecting transistor 29 are arranged in the common diffusion region 26b.

[0256] According to this configuration, the circuit area in each unit pixel 20-3 can be reduced. As a result, the light receiving area of ​​the photodiodes 211 to 214 can be increased, the storage capacity of the memories 24A1 to 24A4 and the memories 24B1 to 24B4 can be increased, and thus, in addition to the effects obtained in the second configuration example, a higher quality depth frame can be generated.

[0257] 1.6.4 Example of the fourth structure

[0258] In the first to third configuration examples described above, by alternately switching and using one unit pixel 20, the light quantity Q of the component having the phase angle α of 90° is read out in a time division manner. 90 and the light quantity Q of the component having a phase angle α of 270° 270 And the light quantity Q0 of the component having a phase angle α of 0° and the light quantity Q of the component having a phase angle α of 180° 180 .

[0259] On the other hand, in the fourth configuration example, the light quantity Q of the component having the phase angle α of 90° can be read out simultaneously from one unit pixel 20 will be described by way of example. 90 and the light quantity Q of the component with a phase angle α of 270° 270And the light quantity Q0 of the component having a phase angle α of 0° and the light quantity Q of the component having a phase angle α of 180° 180 situation.

[0260] Fig.12 is a circuit diagram showing a circuit configuration example of a unit pixel according to a fourth configuration example of the first embodiment. Fig.13 : is a plan view showing an example of a plan layout of a unit pixel according to a fourth configuration example of the first embodiment. Note that Fig.13 An example of a planar layout of an element formation surface of a semiconductor substrate on which the photodiodes 211 to 214 of the unit pixel 20 - 4 are formed is shown.

[0261] like Fig.12 As shown, the unit pixel 20-4 according to the fourth configuration example has, for example, the same configuration as that in the second configuration example. Fig. 9 However, in the fourth configuration example, among the eight readout circuits 20A1 to 20A4 and 20B1 to 20B4 in the second configuration example, two readout circuits 20A1 and 20A4 are used as readout circuit A for reading out the light quantity Q0 of the component having a phase angle α of 0°, and two readout circuits 20B1 and 20B4 are used as readout circuit A for reading out the light quantity Q0 of the component having a phase angle α of 180°. 180 Then, among the remaining readout circuits 20A2, 20A3, 20B2, and 20B3 in the second configuration example, the readout circuits 20A2 and 20B3 are used for reading the light quantity Q of the component having the phase angle α of 90°. 90 The readout circuits 20C1 and 20C2 are used as the light quantity Q of the component having the readout phase angle α of 270°. 270 In the following description, when the readout circuits 20C1 and 20C2 are not distinguished, they are referred to as a readout circuit C, and when the readout circuits 20D1 and 20D2 are not distinguished, they are referred to as a readout circuit D.

[0262] In this way, the light quantities Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q212, Q223, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q223, Q23, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q10, Q20 ...3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q3, Q4, Q5 90 , Q 180 and Q 270, four subframes of 0° / 180°, 90° / 270°, 180° / 0°, and 270° / 90° can be acquired at one time. In other words, by spatially dividing the components of the eight readout circuits 20A1, 20A4, 20B1, 20B4, 20C1, 20C2, 20D1, and 20D2 with respect to the phase angle α of 0°, 90°, 180°, and 270°, four subframes of 0° / 180°, 90° / 270°, 180° / 0°, and 270° / 90° can be acquired at one time.

[0263] As a result, the readout operation when generating a range image can be significantly shortened, thereby enabling high-quality depth frames to be generated at a high frame rate.

[0264] Note that Fig.13 As shown, in the fourth configuration example, in the planar layout of the unit pixel 20-4, by arranging a readout circuit for detecting components having the same phase angle α in the pixel area allocated to a unit pixel 20-4 so that the readout circuit is point-symmetrical or line-symmetrical with respect to the center of the pixel area or a straight line passing through the center as an axis, the difference in the amount of accumulated charge caused by the difference in characteristics caused by the position of the readout circuit (image height) etc. can be reduced, thereby generating high-quality depth frames at a high frame rate.

[0265] 1.6.5 Example of the fifth structure

[0266] In the fifth configuration example, a basic configuration of a two-tap type unit pixel 20 that shares one floating diffusion region 27 will be described as an example.

[0267] Fig.14 is a circuit diagram showing a circuit configuration example of a unit pixel according to a fifth configuration example of the first embodiment. Fig.14 As shown, the unit pixel 20 - 5 according to the fifth configuration example has a circuit configuration in which two readout circuits 20A and 20B are connected to one photodiode 21 , and the two readout circuits 20A and 20B share one floating diffusion region 27 .

[0268] According to this circuit configuration, as described above, by simultaneously transferring the charges stored in the memory at the time of reading to the common floating diffusion region 27, the difference in the amount of stored charge due to the difference in characteristics caused by the position of the readout circuit (image height), etc. can be reduced. As a result, a high-quality depth frame can be generated without acquiring inverted data, so that a high-quality depth frame can be generated at a high frame rate.

[0269] In addition, by sharing the structure downstream of the floating diffusion region 27 (reset transistor 26, amplification transistor 28, selection transistor 29, vertical signal line VSL, AD converter in the column processing circuit 104, etc.) between each of the readout circuits 20A and 20B, the characteristic differences caused by the downstream structure can be eliminated, thereby generating higher quality depth frames.

[0270] 1.6.6 Example of the sixth structure

[0271] In the first to fifth configuration examples described above, a so-called two-tap circuit configuration in which two readout circuits share one photodiode 21 is described, but the present invention is not limited to this configuration. For example, a so-called three-tap circuit configuration in which three readout circuits share one photodiode 21 may also be adopted.

[0272] Fig.15 is a circuit diagram showing a circuit configuration example of a unit pixel according to a sixth configuration example of the first embodiment. Fig.15 As shown, the unit pixel 20 - 6 according to the sixth configuration example has a circuit configuration in which three readout circuits 20A, 20B, and 20C are connected to one photodiode 21 , and the three readout circuits 20A, 20B, and 20C share one floating diffusion region 27 .

[0273] Even in such a three-tap type unit pixel 20 - 6 , similarly to the above-described configuration example, a high-quality depth frame can be generated without acquiring inverted data, and thus a high-quality depth frame can be generated at a high frame rate.

[0274] In addition, by sharing the structure downstream of the floating diffusion region 27 (reset transistor 26, amplification transistor 28, selection transistor 29, vertical signal line VSL, and AD converter in the column processing circuit 104, etc.) between each of the readout circuits 20A, 20B and 20C, the characteristic differences caused by the downstream structure can be eliminated, thereby generating higher quality depth frames.

[0275] 1.6.7 Example 7

[0276] Furthermore, a so-called four-tap type circuit configuration in which four readout circuits share one photodiode 21 may also be employed.

[0277] Fig.16 is a circuit diagram showing a circuit configuration example of a unit pixel according to a seventh configuration example of the first embodiment. Fig.16As shown, the unit pixel 20 - 7 according to the seventh configuration example has a circuit configuration in which four readout circuits 20A, 20B, 20C, and 20D are connected to one photodiode 21 , and the four readout circuits 20A, 20B, 20C, and 20D share one floating diffusion region 27 .

[0278] Even in such a four-tap type unit pixel 20 - 7 , similarly to the above-described configuration example, a high-quality depth frame can be generated without acquiring inverted data, and thus a high-quality depth frame can be generated at a high frame rate.

[0279] In addition, by sharing the structure downstream of the floating diffusion region 27 (reset transistor 26, amplification transistor 28, selection transistor 29, vertical signal line VSL and AD converter in column processing circuit 104, etc.) between each of the readout circuits 20A, 20B, 20C and 20D, the characteristic differences caused by the downstream structure can be eliminated, thereby generating higher quality depth frames.

[0280] 1.7 Pixel Separation Structure

[0281] Next, a structure for optically separating a plurality of unit pixels 20 arranged adjacent to each other in the pixel array section 101 will be described.

[0282] By optically separating adjacent unit pixels 20 , crosstalk caused by light incident on a certain unit pixel 20 being incident on another adjacent unit pixel 20 can be reduced, and thus a depth frame with higher accuracy can be generated.

[0283] For optical separation of adjacent unit pixels 20 , for example, a pixel separation portion formed by forming a groove in a semiconductor substrate on which the photodiode 21 is formed and embedding a predetermined material in the groove can be used.

[0284] Therefore, a planar layout example of the pixel separation portion will be described by way of some examples. Note that it is assumed that the planar layout example in the following description is a planar layout example on the element formation surface of the semiconductor substrate on which the photodiode 21 is formed.

[0285] 1.7.1 First layout example

[0286] Fig.17 1 is a plan view showing a plan layout example of a pixel separation unit according to a first layout example of the first embodiment. Note that in the first layout example, the use of the pixel separation unit to optically separate the reference pixel will be described. Figure 7 and Figure 8 The case of the unit pixel 20 - 1 according to the first configuration example is described.

[0287] like Fig.17As shown, for the unit pixels 20-1 arranged in a matrix form in the pixel array section 101, a pixel separation section 31 is provided along a boundary section 30 between adjacent unit pixels 20-1. Therefore, each unit pixel 20-1 is surrounded by the pixel separation section 31 from all directions.

[0288] 1.7.2 Second layout example

[0289] Fig.18 1 is a plan view showing a plan layout example of a pixel separation unit according to a second layout example of the first embodiment. Note that in the second layout example, the use of the pixel separation unit to optically separate the reference pixel will be described. Fig. 9 and Fig.10 The case of the unit pixel 20 - 2 according to the second configuration example is described.

[0290] like Fig.18 As shown, for the unit pixels 20-2 arranged in a matrix form in the pixel array section 101, Fig.17 Similar to the first layout example shown, a pixel separation section 31 is provided along a boundary section 30 between adjacent unit pixels 20-2. Therefore, each unit pixel 20-2 is surrounded by the pixel separation section 31 from all directions.

[0291] Furthermore, in the second layout example, in the pixel region surrounded by the pixel separating section 31 , the boundary sections 30 of the pairs of readout circuits 20A1 and 20B1 , 20B2 and 20A2 , 20B3 and 20A3 , and 20A4 and 20B4 are optically separated by the element separating section 32 .

[0292] Specifically, the element separation unit 32 is respectively arranged between the readout circuits 20A1 and 20B1 and the readout circuits 20B2 and 20A2, between the readout circuits 20A1 and 20B1 and the readout circuits 20B3 and 20A3, between the readout circuits 20B2 and 20A2 and the readout circuits 20A4 and 20B4, and between the readout circuits 20B3 and 20A3 and the readout circuits 20A4 and 20B4.

[0293] By optically separating the paired readout circuits, crosstalk of light between the plurality of photodiodes 211 to 214 included in the unit pixel 20 may be reduced, and thus a depth frame with higher accuracy may be generated.

[0294] Note that the structure of the element separation section 32 may be similar to that of the pixel separation section 31 , for example.

[0295] 1.7.3 Third layout example

[0296] Fig.191 is a plan view showing a plan layout example of a pixel separation unit according to a third layout example of the first embodiment. Note that in the third layout example, the use of the pixel separation unit to optically separate the reference pixel will be described. Fig. 9 and Fig.11 The above description is based on the case of the unit pixel 20-3 according to the third configuration example, but a similar structure can also be applied to the reference Fig.12 and Fig.13 The unit pixel 20 - 4 according to the fourth configuration example is described.

[0297] like Fig.19 As shown, the pixel separation section 31 and the element separation section 32 according to the third layout example have a structure similar to the pixel separation section 31 and the element separation section 32 illustrated in the second layout example. However, in the third layout example, the element separation section 32 is divided at the center portion of the pixel area divided by the pixel separation section 31.

[0298] The reset transistor 26, the floating diffusion region 27, the amplification transistor 28, and the selection transistor 29 shared by the plurality of readout circuits 20A1 to 20A4 and 20B1 to 20B4 are arranged in the central portion of the pixel region divided by the pixel separation section 31. This is because by arranging these circuit elements in the central portion of the pixel region, it is possible to minimize the variation in the wiring distance from each of the photodiodes 211 to 214 to the circuit elements.

[0299] Even with this structure, since the paired readout circuits are optically separated, it is possible to reduce crosstalk and generate a depth frame with higher accuracy.

[0300] 1.8 Example of cross-sectional structure of a unit pixel

[0301] Next, the cross-sectional structure of the unit pixel 20 will be described by way of some examples. Fig.17 The cross-sectional structure of the section taken along line II in Fig.17 However, in the cross-sectional structure of the cross section taken along the line II-II, in order to simplify the description, the structure around one of the two photodiodes 211 and 212 and the diffusion region between the amplifier transistor 28 and the reset transistor 26 are omitted.

[0302] 1.8.1 Example of the first section structure

[0303] Fig. 20 is a cross-sectional view taken along line II showing an example of a cross-sectional structure of a unit pixel according to a first cross-sectional structure example of the first embodiment, Fig.21: is a cross-sectional view taken along line II-II showing an example of a cross-sectional structure of a unit pixel according to a first cross-sectional structure example of the first embodiment.

[0304] like Fig. 20 and Fig.21 As shown, the unit pixel 20 has, for example, a configuration in which a photodiode 211 (and a photodiode 212 ) is formed in a region partitioned by a pixel separation section 31 in a semiconductor substrate 40 .

[0305] The photodiode 211 (and the photodiode 212) includes, for example, an n-type semiconductor region 42 in which donors are diffused at a low concentration, an n-type semiconductor region 43 in which the donor concentration is higher than that of the n-type semiconductor region 42, and an n+ type semiconductor region 44 in which donors are diffused at a high concentration. Charges generated by photoelectric conversion in the n-type semiconductor regions 42 and 43 are taken into the n+ type semiconductor region 44 having a deep potential along the potential gradient, and are transferred to the memory 24A or 24B at the moment when the transfer gate 23A or 23B having the dug-out portion is opened.

[0306] refer to Figure 7 and Figure 8 The illustrated circuit elements, namely, the OFG transistor 221 (and 222), the transfer gate transistors 23A1, 23A2, 23B1, and 23B2, the memories 24A1, 24A2, 24B1, and 24B2, the transfer transistors 25A1, 25A2, 25B1, and 25B2, the reset transistor 26, the floating diffusion region 27, the amplification transistor 28, and the selection transistor 29 are formed on the element formation surface (in the figure, the lower surface) of the semiconductor substrate 40. Among them, Fig. 20 Pass gate transistors 23A1 and 23B1, memories 24A1 and 24B1, pass transistors 25A1 and 25B1, and floating diffusion region 27 are shown. Fig.21 OFG transistors 221 (and 222) are shown. Note that although Fig. 20 Floating diffusion regions 27 are shown separately in FIG. 1 , but the floating diffusion regions may be connected by wirings 52 in a wiring layer 50 described later.

[0307] like Fig. 20 As shown, the transfer gate transistors 23A1 and 23B1 (and 23A2 and 23B2) may be vertical transistors having a vertical structure formed in the substrate thickness direction of the semiconductor substrate 40. Fig.21As shown, the OFG transistor 221 (and 222) may be a dual vertical transistor formed in the substrate thickness direction of the semiconductor substrate 40. In addition, the transfer gate transistors 23A1 and 23B1 (and 23A2 and 23B2) and the OFG transistor 221 (and 222) may be vertical transistors having a dual structure including the above-mentioned two vertical structures. However, these are merely examples, and various modifications may be made. Note that, Fig. 20 and Fig.21 The insulating film 51 in FIG. 4 is a gate insulating film of each circuit element formed on the semiconductor substrate 40 .

[0308] On the element forming surface of the semiconductor substrate 40 , a wiring layer 50 including wirings 52 connected to each circuit element formed on the semiconductor substrate 40 is formed.

[0309] For example, a concave-convex structure 45 is formed on the back side (upper surface in the figure) of the semiconductor substrate 40, that is, on the light incident surface. In this way, by providing the concave-convex structure 45 on the light incident surface, the incident surface can have a structure in which the refractive index gradually changes. As a result, the incident light is effectively diffracted to extend the optical path length of the incident light in the semiconductor substrate 40, and the reflectivity of the incident light is reduced, so that more light can be incident on the photodiode 211 (and 212). As a result, since the quantum efficiency of the photodiode 211 (and 212) is improved, a depth frame with higher accuracy can be generated. Note that the period of the periodic concave-convex structure 45 can be, for example, more than 300 nm.

[0310] On the back surface of the semiconductor substrate 40 , an insulating film 61 , a planarizing film 63 on the insulating film 61 , and an on-chip lens 64 on the planarizing film 63 are provided.

[0311] Furthermore, a light shielding film 62 for preventing color mixing between adjacent pixels is provided at the boundary portion 30 between adjacent unit pixels 20 on the planarization film 63. For the light shielding film 62, for example, a material having a light shielding property such as tungsten (W) can be used.

[0312] As the semiconductor substrate 40, for example, a p-type silicon substrate or the like can be used, and its substrate thickness can be reduced to, for example, a thickness of 20 μm (micrometers) or less. Note that the thickness of the semiconductor substrate 40 can be 20 μm or more, and the thickness can be appropriately determined according to the target characteristics of the light receiving unit 14, etc.

[0313] In addition to the function of pinning the incident surface of the semiconductor substrate 40, the insulating film 61 also has the function of an anti-reflection film for incident light. The insulating film 61 is composed of, for example, silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2) or tantalum oxide (Ta2O5). The thickness of the insulating film 61 is an optical thickness of about a quarter wave plate with respect to near infrared rays, and can be, for example, 50 nm or more and 150 nm or less. The flattening film 63 can be, for example, a film formed using an insulating material such as silicon oxide (SiO2) or silicon nitride (SiN).

[0314] For the on-chip lens 64 , for example, silicon oxide (SiO 2 ) or a transparent resin or the like can be used, and the curvature of the on-chip lens 64 is set so that incident light converges near the center of the photodiode 211 (or 212 ).

[0315] The pixel separation portion 31 according to the first cross-sectional structure example has a so-called FFTI (full front trench isolation) type structure formed by embedding an insulating material such as silicon oxide (SiO2) in a trench penetrating from the element formation surface to the back surface of the semiconductor substrate 40.

[0316] 1.8.2 Second Section Structure Example

[0317] Fig. 22 is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a second cross-sectional structural example of the first embodiment, Fig.23 : is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a second cross-sectional structural example of the first embodiment.

[0318] By Fig. 20 and Fig.21 and Fig. 22 and Fig.23 By comparison, it can be seen that the unit pixel 20 according to the second cross-sectional structure example has a cross-sectional structure similar to that of the unit pixel 20 according to the first cross-sectional structure example, in which the FFTI type pixel separation portion 31 is replaced by the so-called RDTI (reverse deep trench isolation) type pixel separation portion 33.

[0319] The RDTI type pixel separation section 33 can be formed, for example, by embedding an insulating material such as silicon oxide (SiO 2 ) in a groove engraved from the element formation surface of the semiconductor substrate 40 to such an extent that the semiconductor substrate 40 is not penetrated.

[0320] Note that the configuration of the pixel separation section 33 can also be applied to the element separation section 32 .

[0321] 1.8.3 Example of the third section structure

[0322] Fig.24 is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a third cross-sectional structural example of the first embodiment, Fig.25 is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a third cross-sectional structural example of the first embodiment.

[0323] By Fig. 20 and Fig.21 and Fig.24 and Fig.25 By comparison, it can be seen that the unit pixel 20 according to the third cross-sectional structure example has a cross-sectional structure similar to that of the unit pixel 20 according to the first cross-sectional structure example, in which the FFTI type pixel separation part 31 is replaced by the FFTI type pixel separation part 34.

[0324] The pixel separation portion 34 includes, for example, an insulating film 341 covering the inner surface of a groove penetrating the front and back surfaces of the semiconductor substrate 40 , and a light shielding portion 342 embedded in the groove formed by the insulating film 341 .

[0325] For example, an insulating material such as silicon oxide (SiO 2 ) can be used for the insulating film 341 . On the other hand, for example, tungsten (W) or aluminum (Al) can be used for the light shielding portion 342 .

[0326] In this way, by providing the light shielding portion 342 inside the pixel separation portion 34 , adjacent unit pixels 20 can be optically separated better, so that a depth frame with higher accuracy can be generated.

[0327] Note that the configuration of the pixel separation section 34 can also be applied to the element separation section 32 .

[0328] 1.8.4 Example of the fourth section structure

[0329] Fig.26 is a cross-sectional view taken along line II showing a cross-sectional structural example of a unit pixel according to a fourth cross-sectional structural example of the first embodiment, Fig. 27 : is a cross-sectional view taken along line II-II showing a cross-sectional structural example of a unit pixel according to a fourth cross-sectional structural example of the first embodiment.

[0330] By Fig.24 and Fig.25 and Fig.26 and Fig. 27By comparison, it can be seen that the unit pixel 20 according to the fourth cross-sectional structure example has a cross-sectional structure similar to that of the unit pixel 20 according to the third cross-sectional structure example, in which the FFTI type pixel separation portion 34 is replaced by the RDTI type pixel separation portion 35.

[0331] The RDTI type pixel separation portion 35 includes, for example: an insulating film 351 that covers the inner surface of a groove engraved from the element forming surface of the semiconductor substrate 40 to a degree that does not penetrate the semiconductor substrate 40; and a shading portion 352 that is embedded in the groove formed by the insulating film 351.

[0332] For example, an insulating material such as silicon oxide (SiO 2 ) can be used for the insulating film 351 . On the other hand, for example, tungsten (W) or aluminum (Al) can be used for the light shielding portion 352 .

[0333] Note that the configuration of the pixel separation section 35 can also be applied to the element separation section 32 .

[0334] 1.9FD shared layout

[0335] Next, it will be described whether or not each variation of the arrangement of the readout circuit can share the FD (share the floating diffusion region 27). Note that in the following description, the H direction represents the row direction in the matrix array of the unit pixel 20, and the V direction represents the column direction. In addition, in the drawings mentioned in the following description, the readout circuits A and B or the readout circuits C and D forming a pair for acquiring one subframe are surrounded by solid lines and / or dotted lines. The area separated by the solid lines indicates the case where the FD sharing cannot be achieved, and the area separated by the dotted lines indicates the case where the FD sharing can be achieved.

[0336] Furthermore, in the first to sixteenth variations exemplified below, the pixel region 70 of each unit pixel 20 is divided into four regions (hereinafter, referred to as divided regions) 71 to 74 of 2×2. In each of the divided regions 71 to 74, in addition to the two readout circuits A and B or C and D in pairs, a photodiode 21 (not shown) and an OFG transistor 22 (not shown) are arranged.

[0337] 1.9.1 First variant

[0338] Fig.28 1 is a schematic diagram showing an example of a planar layout of a memory according to a first variation of the first embodiment. Fig.28 As shown, in the first variation, in each of the divided areas 71 to 74, the light quantity Q0 (or Q 90 ) is arranged on the left side, and is used to detect the light quantity Q of the component having a phase angle α of 180° (or 270°) 180(or Q 270 ) is arranged on the right side. That is, in the first variant, the above reference Figure 3 The unit pixels 920 of the illustrated basic configuration are arranged in a matrix form.

[0339] In this layout, since the symmetry of the memories 24A and 24B cannot be ensured in the H direction, that is, in each of the total four read-out circuits A and B arranged in the divided areas 71 and 73 and the total four read-out circuits A and B arranged in the divided areas 72 and 74, a floating diffusion area 27 cannot be shared.

[0340] In addition, similarly in the V direction, since the symmetry of the memories 24A and 24B cannot be ensured in each of the total four read-out circuits A and B arranged in the divided areas 71 and 72 and the total four read-out circuits A and B arranged in the divided areas 73 and 74, a floating diffusion area 27 cannot be shared.

[0341] 1.9.2 Second variant

[0342] Fig.29 1 is a schematic diagram showing an example of a planar layout of a memory according to a second variation of the first embodiment. Fig.29 As shown, in the second variation, in the divided areas 71 and 73, the readout circuit A is arranged on the left, and the readout circuit B is arranged on the right. On the other hand, in the divided areas 72 and 74, the readout circuit A is arranged on the right, and the readout circuit B is arranged on the left.

[0343] In this layout, since the symmetry of the memory in the H direction cannot be ensured, a total of four readout circuits A and B arranged in the divided areas 71 and 73 and a total of four readout circuits A and B arranged in the divided areas 72 and 74 cannot share a floating diffusion area 27.

[0344] On the other hand, in the V direction, since the symmetry of the memory is ensured, a total of four readout circuits A and B arranged in the divided areas 71 and 72 and a total of four readout circuits A and B arranged in the divided areas 73 and 74 can each share one floating diffusion area 27.

[0345] 1.9.3 Third variant

[0346] Fig.30 1 is a schematic diagram showing an example of a planar layout of a memory according to a third variation of the first embodiment. Fig.30 As shown, in the third variation, in the divided areas 71 and 72, the readout circuit A is arranged on the left, and the readout circuit B is arranged on the right. On the other hand, in the divided areas 73 and 74, the readout circuit A is arranged on the right, and the readout circuit B is arranged on the left.

[0347] In this layout, since the symmetry of the memory in the H direction is ensured, a total of four readout circuits A and B arranged in the divided areas 71 and 73 and a total of four readout circuits A and B arranged in the divided areas 72 and 74 can each share one floating diffusion area 27.

[0348] On the other hand, since the symmetry of the memory in the V direction cannot be ensured, a total of four readout circuits A and B arranged in the divided areas 71 and 72 and a total of four readout circuits A and B arranged in the divided areas 73 and 74 cannot share one floating diffusion area 27.

[0349] 1.9.4 Fourth variant

[0350] Fig.31 1 is a schematic diagram showing an example of a planar layout of a memory according to a fourth variation of the first embodiment. Fig.31 As shown, in the fourth variation, in the divided areas 71 and 74, the readout circuit A is arranged on the left, and the readout circuit B is arranged on the right. On the other hand, in the divided areas 72 and 73, the readout circuit A is arranged on the right, and the readout circuit B is arranged on the left.

[0351] In this layout, since the symmetry of the memory in the H direction is ensured, a total of four readout circuits A and B arranged in the divided areas 71 and 73 and a total of four readout circuits A and B arranged in the divided areas 72 and 74 can each share one floating diffusion area 27.

[0352] Furthermore, similarly in the V direction, since the symmetry of the memory is ensured, a total of four readout circuits A and B arranged in the divided regions 71 and 72 and a total of four readout circuits A and B arranged in the divided regions 73 and 74 can each share one floating diffusion region 27 .

[0353] 1.9.5 Fifth variant

[0354] Fig.32 1 is a schematic diagram showing an example of a planar layout of a memory according to a fifth variation of the first embodiment. Fig.32 As shown, in the fifth variation, in each of the divided regions 71 to 74, the readout circuit A is arranged on the upper side, and the readout circuit B is arranged on the lower side.

[0355] In this layout, similarly to the first variation, since the symmetry of the memory cannot be ensured in both the H direction and the V direction, the floating diffusion region 27 cannot be shared.

[0356] 1.9.6 Sixth variant

[0357] Fig.33 1 is a schematic diagram showing an example of a planar layout of a memory according to a sixth variation of the first embodiment. Fig.33 As shown, in the sixth variation, in the divided regions 71 and 73, the readout circuit A is arranged on the upper side and the readout circuit B is arranged on the lower side. On the other hand, in the divided regions 72 and 74, the readout circuit A is arranged on the lower side and the readout circuit B is arranged on the upper side.

[0358] In this layout, similar to the second variation, since the symmetry of the memory cannot be ensured in the H direction, the floating diffusion region 27 cannot be shared. However, since the symmetry of the memory is ensured in the V direction, the floating diffusion region 27 can be shared.

[0359] 1.9.7 Seventh variant

[0360] Fig.34 1 is a schematic diagram showing an example of a planar layout of a memory according to a seventh variation of the first embodiment. Fig.34 As shown, in the seventh variation, in the divided regions 71 and 72, the readout circuit A is arranged on the upper side and the readout circuit B is arranged on the lower side. On the other hand, in the divided regions 73 and 74, the readout circuit A is arranged on the lower side and the readout circuit B is arranged on the upper side.

[0361] In this layout, similarly to the third variation, since the symmetry of the memory is ensured in the H direction, one floating diffusion region 27 can be shared, but since the symmetry of the memory is not ensured in the V direction, the floating diffusion region 27 cannot be shared.

[0362] 1.9.8 Eighth variant

[0363] Fig.35 1 is a schematic diagram showing an example of a planar layout of a memory according to an eighth variation of the first embodiment. Fig.35 As shown, in the eighth variation, in the divided areas 71 and 74, the readout circuits 20A1 and 20A4 are arranged on the upper side, and the readout circuits 20B1 and 20B4 are arranged on the lower side. On the other hand, in the divided areas 72 and 73, the readout circuits 20A2 and 20A3 are arranged on the lower side, and the readout circuits 20B2 and 20B3 are arranged on the upper side.

[0364] In this layout, similarly to the fourth variation, since the symmetry of the memory is ensured in both the H direction and the V direction, the floating diffusion region 27 can be shared in each direction.

[0365] 1.9.9 Ninth variant

[0366] Fig.36 1 is a schematic diagram showing an example of a planar layout of a memory according to a ninth variation of the first embodiment. Fig.36 As shown, in the ninth variation, in each of the divided areas 71 to 74, the light quantity Q0 or Q1 of the component having the phase angle α of 0° or 90° is detected. 90 The readout circuits A and C are arranged on the left side to detect the light quantity Q of the component having a phase angle α of 180° or 270° 180 or Q 270 The readout circuits B and D are arranged on the right side.

[0367] In this layout, not only the symmetry of the memory in the H direction and the V direction cannot be ensured, but also the symmetry of the memory with respect to the center of the pixel area 70 or a straight line passing through the center cannot be ensured. Therefore, the characteristic difference of the memory cannot be eliminated or the difference in effect cannot be eliminated.

[0368] 1.9.10 The tenth variant

[0369] Fig.37 1 is a schematic diagram showing an example of a planar layout of a memory according to a tenth variation of the first embodiment. Fig.37 As shown, in the tenth variation, in the divided areas 71 and 73, the readout circuits A and C are arranged on the left, and the readout circuits B and D are arranged on the right. On the other hand, in the divided areas 72 and 74, the readout circuits A and C are arranged on the right, and the readout circuits B and D are arranged on the left.

[0370] In this layout, since the symmetry of the memory in the H direction and the V direction cannot be ensured, the floating diffusion region 27 cannot be shared in both the H direction and the V direction. However, since the symmetry of the memory relative to the center of the pixel area 70 or with a straight line passing through the center as an axis can be ensured, the characteristic differences of the memory can be eliminated.

[0371] 1.9.11 Eleventh Variant

[0372] Fig.38 1 is a schematic diagram showing an example of a planar layout of a memory according to an eleventh variation of the first embodiment. Fig.38 As shown, in the eleventh variation, in the divided areas 71 and 72, the readout circuits A and C are arranged on the left, and the readout circuits B and D are arranged on the right. On the other hand, in the divided areas 73 and 74, the readout circuits A and C are arranged on the right, and the readout circuits B and D are arranged on the left.

[0373] In this layout, since the symmetry of the memory in the H direction is ensured, the floating diffusion region 27 can be shared, but since the symmetry of the memory in the V direction is not ensured, the floating diffusion region 27 cannot be shared.

[0374] Note that since the symmetry of the memory about the straight line passing through the center of the pixel region 70 is ensured, the characteristic variation of the memory can be eliminated.

[0375] 1.9.12 Twelfth variant

[0376] Fig.39 1 is a schematic diagram showing an example of a planar layout of a memory according to a twelfth variation of the first embodiment. Fig.39 As shown, in the twelfth variation, in divided areas 71 and 74, readout circuit A is arranged on the left and readout circuit B is arranged on the right. On the other hand, in divided areas 72 and 73, readout circuit C is arranged on the right and readout circuit D is arranged on the left.

[0377] In this layout, not only the symmetry of the memory in the H direction and the V direction cannot be ensured, but also the symmetry of the memory with respect to the center of the pixel area 70 or a straight line passing through the center cannot be ensured. Therefore, the characteristic difference of the memory cannot be eliminated or the effect thereof is poor.

[0378] 1.9.13 Thirteenth Variant

[0379] Fig.40 1 is a schematic diagram showing an example of a planar layout of a memory according to a thirteenth variation of the first embodiment. Fig.40 As shown, in the thirteenth variation, in each of the divided areas 71 to 74, the readout circuits A and C are arranged on the upper side, and the readout circuits B and D are arranged on the lower side.

[0380] In this layout, similar to the ninth variation, not only the symmetry of the memory in the H direction and the V direction cannot be ensured, but also the symmetry of the memory with respect to the center of the pixel area 70 or a straight line passing through the center cannot be ensured. Therefore, the characteristic difference of the memory cannot be eliminated or the effect thereof is poor.

[0381] 1.9.14 Fourteenth variant

[0382] Fig.41 1 is a schematic diagram showing an example of a planar layout of a memory according to a fourteenth variation of the first embodiment. Fig.41 As shown, in the fourteenth variation, in the divided areas 71 and 73, the readout circuits A and C are arranged on the upper side, and the readout circuits B and D are arranged on the lower side. On the other hand, in the divided areas 72 and 74, the readout circuits A and C are arranged on the lower side, and the readout circuits B and D are arranged on the upper side.

[0383] In this layout, similar to the tenth variation, since the symmetry of the memory in the H direction and the V direction cannot be ensured, the floating diffusion region 27 cannot be shared in both the H direction and the V direction, but since the symmetry of the memory relative to the center of the pixel area 70 or with a straight line passing through the center as an axis is ensured, the characteristic differences of the memory can be eliminated.

[0384] 1.9.15 Fifteenth variant

[0385] Fig.42 1 is a schematic diagram showing an example of a planar layout of a memory according to a fifteenth variation of the first embodiment. Fig.42 As shown, in the fifteenth variation, in the divided areas 71 and 73, the readout circuits A and C are arranged on the upper side, and the readout circuits B and D are arranged on the lower side. On the other hand, in the divided areas 72 and 74, the readout circuits A and C are arranged on the lower side, and the readout circuits B and D are arranged on the upper side.

[0386] In this layout, contrary to the eleventh variation, since the symmetry of the memory in the H direction cannot be ensured, the floating diffusion region 27 cannot be shared, but since the symmetry of the memory in the V direction can be ensured, the floating diffusion region 27 can be shared.

[0387] Note that since the symmetry of the memory about the straight line passing through the center of the pixel region 70 can be ensured, the characteristic variation of the memory can be eliminated.

[0388] 1.9.16 Sixteenth variant

[0389] Fig.43 1 is a schematic diagram showing an example of a planar layout of a memory according to a sixteenth variation of the first embodiment. Fig.43 As shown, in the sixteenth variation, in the divided areas 71 and 74, the readout circuit A is arranged on the upper side and the readout circuit B is arranged on the lower side. On the other hand, in the divided areas 72 and 73, the readout circuit C is arranged on the lower side and the readout circuit D is arranged on the upper side.

[0390] In this layout, similar to the twelfth variation, not only the symmetry of the memory in the H direction and the V direction cannot be ensured, but also the symmetry of the memory with respect to the center of the pixel area 70 or a straight line passing through the center cannot be ensured. Therefore, the characteristic difference of the memory cannot be eliminated or the effect thereof is poor.

[0391] 1.10 Elimination of characteristic differences

[0392] Next, elimination of characteristic differences according to the present embodiment will be described by way of example.

[0393] Note that in this specification, as a comparative example, Fig.28The first variant shown or Fig.32 The fifth variation shown (FD sharing in the H direction and the V direction cannot be achieved) is cited as an example for explaining the effect of eliminating the characteristic difference according to the present embodiment. Fig.31 The fourth variant shown or Fig.35 The eighth variation shown (enabling FD sharing in H and V directions).

[0394] In addition, in this specification, reference will be made to Figure 3 and Figure 4 The comparative example is described with reference to the unit pixel 920. Figure 7 and Figure 8 This embodiment is described based on the unit pixel 20 - 1 of the first configuration example.

[0395] Fig.44 It is a diagram for explaining the difference in the amount of accumulated charge of each memory cell generated in the comparative example. Fig.45 1 is a diagram for explaining the effect of eliminating the characteristic differences among the memories according to the first embodiment.

[0396] like Fig.44 As shown, in the comparative example, the floating diffusion region 27 cannot be shared in both the H direction and the V direction (see Fig.28 or Fig.32 ). Therefore, the charges 81A accumulated in each floating diffusion region 27A and the charges 81B accumulated in the floating diffusion region 27B respectively become charges transferred from one memory 24A or 24B, and the effect of eliminating the characteristic difference by accumulating the charges read out from the plurality of memories ensuring symmetry in the common floating diffusion region 27 cannot be obtained.

[0397] Since the two memories 24A and 24B are arranged symmetrically with respect to the optical center of the on-chip lens 64 in the unit pixel 920M belonging to the region with low image height (ie, the region near the center of the pixel array section 101 ), no large difference in characteristics appears.

[0398] On the other hand, in an area where the optical axis of the incident light is greatly inclined and the image height is high, that is, in the unit pixels 920UL, 920UR, 920LL and 920LR belonging to the peripheral area of ​​the pixel array unit 101, due to pupil correction, the two memories 24A and 24B are arranged to be greatly eccentric relative to the optical center of the on-chip lens 64, and thus a large difference in characteristics occurs.

[0399] Therefore, if Fig.45As shown, by adopting a structure in which charge is transferred from two memories (corresponding to memories 24A1 and 24A2 or memories 24B1 and 24B2) ensuring symmetry to a shared floating diffusion region 27, the difference in the amount of accumulated charge caused by the difference in characteristics accumulated in the floating diffusion region 27 can be reduced.

[0400] For example, in the unit pixels 20UL (two blocks surrounded by dotted lines) sharing one floating diffusion region 27 in the upper left region of the pixel array section 101, when the light quantity Q0 (or Q 90 ), the charges A81 and A82 accumulated in the two memories 24A1 and 24A2 ensuring symmetry are transferred to the shared floating diffusion region 27, and when the light amount Q of the component having the phase angle α of 180° (or 270°) is detected 180 (or Q 270 ), the charges B81 and B82 accumulated in the two memories 24B1 and 24B2 ensuring symmetry are transferred to the shared floating diffusion region 27.

[0401] Similarly, in the unit pixels 20LL sharing a floating diffusion region 27 in the lower left region of the pixel array portion 101, the unit pixels 20UR sharing a floating diffusion region 27 in the upper right region of the pixel array portion 101, the unit pixels 20LR sharing a floating diffusion region 27 in the lower right region of the pixel array portion 101, and the unit pixels 20M sharing a floating diffusion region 27 in the central region of the pixel array portion 101, the charges A81 and A82 or the charges B81 and B82 accumulated in the two memories 24A1 and 24A2 or 24B1 and 24B2 ensuring symmetry are transferred to the shared floating diffusion region 27.

[0402] As a result, a sub-frame with higher accuracy can be generated because a difference in the charge accumulation amount caused by a difference in the characteristics of the memory is eliminated in the floating diffusion region 27. As a result, a depth frame with higher accuracy can be obtained.

[0403] 1.11 Example of Reading Operation of Ranging Image (Depth Frame)

[0404] Next, the readout operation of the distance measurement image (depth frame) according to the present embodiment will be described by way of example.

[0405] Fig.46 1 is a timing chart showing a readout operation of a depth frame in the case of using a unit pixel not including an FD sharing structure according to the first embodiment. Note that the unit pixel not including an FD sharing structure according to the first embodiment may be, for example, the unit pixel described above with reference to Figure 3 Unit pixel 920 is illustrated.

[0406] on the other hand, Fig.47 is a timing chart showing a readout operation of a depth frame in the case of using a unit pixel having an FD sharing structure (for example, the unit pixel according to the first to third configuration examples described above) according to the first embodiment. Fig.48 is a timing chart showing a readout operation of a depth frame in the case of using a unit pixel having an FD sharing structure (for example, the unit pixel according to the fourth configuration example described above) according to the first embodiment.

[0407] like Figure 46 to Figure 48 As shown, the readout operation for reading out one subframe includes resetting each unit pixel 20, accumulating the charge generated by the photoelectric conversion in each unit pixel 20 in the memories 24A and 24B, reading out the charge accumulated in the memories 24A and 24B, and a dead period (dead time) when switching the phase. Note that the phase may be the phase of the pulse cycle of distributing the charge generated in the photodiode 21 to the memory 24A and the memory 24B based on the pulse cycle of the irradiation light L1, and the phase switching may be an operation of switching the phase (corresponding to the phase angle α).

[0408] In addition, if Fig.46 As shown, in the case where the unit pixel 20 does not have the FD sharing structure, as described above, in order to eliminate the characteristic difference, four subframes must be acquired: subframe #1 of 0° / 180°, subframe #2 of 90° / 270°, subframe #3 of 180° / 0°, and subframe #4 of 270° / 90°. Therefore, the time required to acquire one depth frame is approximately four times the time required to acquire four subframes.

[0409] On the other hand, Fig.47 As shown, in the first to third structure examples where the unit pixel 20 has the FD sharing structure, since the difference in the amount of accumulated charge based on the characteristic difference in the floating diffusion region 27 is reduced, as shown in FIG. Fig.47 As shown, it is not necessary to obtain the inverted subframes #3 and #4. Therefore, the time required to obtain a depth frame is twice the time required to obtain two subframes, that is, Fig.46 Half the time shown.

[0410] In addition, if Fig.48 As shown, in the fourth structural example, the unit pixel 20 has an FD sharing structure, and the light quantity Q0 of the component with a phase angle α of 0°, the light quantity Q1 of the component with a phase angle α of 90°, and the light quantity Q2 of the component with a phase angle α of 90° can be read out in one readout operation. 90 , the light quantity Q of the component having a phase angle α of 180° 180 and the light quantity Q of the component having a phase angle α of 270° 270Therefore, the time required to acquire a depth frame is equal to the time required to acquire a subframe, that is, Fig.46 1 / 4 of the time illustrated.

[0411] As described above, according to the present embodiment, a high-quality ranging image (depth frame) can be obtained in a short time.

[0412] 1.12 Driving Pulse Example

[0413] Next, the driving pulse when the charge generated in the photodiode 21 is distributed to each memory will be described by some examples. In the following description, it is assumed that the distance from the light emitting unit 13 and the light receiving unit 14 to the object 90 is 1m (meter), and the distance (2m) from the light emitting unit 13 to the light receiving unit 14 via the object 90 corresponds to one pulse cycle of the irradiation light L1 emitted from the light emitting unit 13. In addition, in the drawings used in the following description, the shaded area superimposed on the driving pulses VGA to VGD represents an example of the amount of charge accumulated in the memory to which the driving pulse is applied.

[0414] 1.12.1 Example of the first drive pulse

[0415] First, the driving pulse examples of the unit pixel 20 exemplified as the second to fourth variations and the sixth to eighth variations will be described as the first driving pulse example. Fig.49 1 is a waveform diagram for explaining an example of a first driving pulse according to the first embodiment.

[0416] exist Figure 29 to Figure 31 as well as Figure 33 to Figure 35 In the second to fourth variants and the sixth to eighth variants shown, the memories 24A1 to 24A4 in the readout circuits 20A1 to 20A4 are connected to a common drive line to which a drive pulse VGA is applied (the reference numeral for the drive line is also VGA), and the memories 24B1 to 24B4 in the readout circuits 20B1 to 20B4 are connected to a common drive line to which a drive pulse VGB is applied (the reference numeral for the drive line is also VGB).

[0417] like Fig.49 As shown, the driving pulse VGA for acquiring the light quantity Q0 of the component having a phase angle α of 0° relative to the illumination light L1 can be a pulse having the same frequency and the same phase as the illumination light L1 emitted from the light emitting unit 13 (ie, the driving pulse for driving the light emitting unit 13).

[0418] On the other hand, for obtaining the light quantity Q of the component having a phase angle α of 180° with respect to the irradiation light L1 180The driving pulse VGB may be a pulse having the same frequency as the illumination light L1 emitted from the light emitting unit 13 (ie, a driving pulse for driving the light emitting unit 13 ) and having a phase shift of 180°.

[0419] like Fig.49 As shown, in this embodiment, when acquiring a subframe, multiple times ( Fig.49 2 times in the example) to perform multiple ( Fig.49 In this specification, the charge generated in the photodiode 21 is allocated to the operation of the memories 24A1 to 24A4 and the memories 24B1 to 24B4 (for example, time T10 to T11 and time T20 to T21). Fig.49 The period (for example, time T10 to T11 and time T20 to T21) allocated to the memories 24A1 to 24A4 and the memories 24B1 to 24B4 is referred to as a charge transfer period.

[0420] exist Fig.49 In the example shown, first, after the charge transfer period (T10 to T11) in which the charges generated in the photodiode 21 are distributed to the memories 24A1 to 24A4 and the memories 24B1 to 24B4, the non-light emitting period (time T11 to T20) of the irradiation light L1 passes. Then, next, in a state where the irradiation light L1 and the driving pulses VGA and VGB are phase-inverted, after the charge transfer period (time T20 to T21) in which the charges generated in the photodiode 21 are distributed to the memories 24A1 to 24A4 and the memories 24B1 to 24B4, the non-light emitting period (time T21 to T30) of the irradiation light L1 passes.

[0421] By performing the charge transfer to each memory in such a flow, it is possible to accumulate charges of each component having a phase angle α (= 0° and 180°, or 90° and 270°) with respect to the irradiation light L1 in each memory. Note that the point at which the phase of the irradiation light L1 and the drive pulses VGA and VGB are inverted in different charge transfer periods will be described in the "Encoding of the accumulation period" described later.

[0422] Furthermore, as described above, in the present embodiment, a non-distribution period (time T11 to T20 and time T21 to T30) in which a subframe is not acquired is provided between the period in which a subframe is acquired (for example, the period between time T10 to T11 and time T20 to T21).

[0423] In the non-distribution period (time T11 to T20 and time T21 to T30), the drive pulse OFG applied to the gate of the OFG transistor 22 (221 to 222 or 221 to 224) is set to high level. As a result, the charge generated in the photodiode 21 in the non-distribution period is discharged via the OFG transistor 22.

[0424] 1.12.1.1 Variations

[0425] Notice, Fig.49 The drive pulse according to the first drive pulse example shown is not limited to the second to fourth variations and the sixth to eighth variations. Figure 29 to Figure 31 as well as Figure 33 to Figure 35 The connection relationship shown in FIG. 1 and the driving pulse can also be applied to Figure 50 to Figure 55 Other connections shown.

[0426] exist Figure 50 to Figure 55 In the illustrated example, as the driving lines to which the driving pulse VGA is applied, two driving lines VGA1 and VGA2 are provided, and as the driving lines to which the driving pulse VGB is applied, two driving lines VGB1 and VGB2 are provided.

[0427] Each of the memories 24A1 to 24A4 and the memories 24B1 to 24B4 is connected to one of the driving lines VGA1, VGA2, VGB1, and VGB2, so that the memories sharing the floating diffusion region 27 are connected to different driving lines. However, in the fourth and eighth variations (see FIG. 1 ) in which eight memories 24A1 to 24A4 and memories 24B1 to 24B4 share one floating diffusion region 27, Fig.49 and Fig.55 ), each drive line connects two memories without being restricted by this condition.

[0428] Even in such a connection relationship, it is possible to apply the reference Fig.49 The first drive pulse example is illustrated to acquire a sub-frame.

[0429] 1.12.2 Second drive pulse example

[0430] Next, the driving pulse examples of the unit pixel 20 exemplified as the tenth to twelfth variations and the fourteenth to sixteenth variations will be described as second driving pulse examples. Fig.56 2 is a waveform diagram for explaining an example of the second driving pulse according to the first embodiment.

[0431] exist Figure 37 to Figure 39 as well as Figure 41 to Figure 43In the tenth to twelfth variations and the fourteenth to sixteenth variations shown, the memories 24A1 and 24A2 are connected to a common drive line VGA to which a drive pulse VGA is applied, the memories 24B1 and 24B2 are connected to a common drive line VGB to which a drive pulse VGB is applied, the memories 24C1 and 24C2 are connected to a common drive line VGC to which a drive pulse VGC is applied, and the memories 24D1 and 24D2 are connected to a common drive line VGD to which a drive pulse VGD is applied.

[0432] like Fig.56 As shown, the driving pulses VGA and VGB may be similar to the driving pulses VGA and VGB in the first driving pulse example.

[0433] For obtaining the light quantity Q of the component having a phase angle α of 90° with respect to the irradiation light L1 90 The driving pulse VGC may be a pulse having the same frequency as the illumination light L1 emitted from the light emitting unit 13 (ie, a driving pulse for driving the light emitting unit 13 ) and having a phase shift of 90°.

[0434] In addition, for obtaining the light quantity Q of the component having a phase angle α of 270° with respect to the irradiation light L1 270 The driving pulse VGD of may be a pulse having the same frequency as the illumination light L1 emitted from the light emitting unit 13 (ie, a driving pulse for driving the light emitting unit 13 ) and having a phase shift of 270°.

[0435] like Fig.56 As shown, with the first drive pulse example reference Fig.49 Similar to the charge transfer described, the charge transfer to each memory using each of the driving pulses VGA to VGD can be an operation of alternatingly repeating multiple times of charge distribution (time T10 to T11 and time T20 to T21) and charge discharge (time T11 to T20 and time T21 to T30).

[0436] By performing charge transfer to each memory in such a flow, charges of each component having a phase angle α (=0°, 90°, 180°, and 270°) with respect to the irradiation light L1 can be accumulated in each memory.

[0437] 1.13 Coding of accumulation periods

[0438] Next, the encoding of the accumulation period will be explained in detail with reference to the drawings.

[0439] The ToF method is a method of measuring the distance to an object by receiving reflected light of irradiation light emitted from a light-emitting unit included in the ToF method. Therefore, when light other than the reflected light (hereinafter referred to as interference light) is incident on the light-receiving unit, the light appears as noise, thereby hindering accurate distance measurement.

[0440] 1.13.1 Noise caused by interference

[0441] Here, the noise generated by interference light will be explained by example. In the following description, similar to the description of the "drive pulse example", it is assumed that the distance from the light emitting unit 13 and the light receiving unit 14 to the object 90 is 1m (meter), and the distance (2m) from the light emitting unit 13 to the light receiving unit 14 via the object 90 corresponds to one pulse cycle of the illumination light L1 emitted from the light emitting unit 13. In addition, in the drawings used in the following description, the shaded area superimposed on the drive pulses VGA and VGB represents an example of the amount of charge accumulated in the memory to which the drive pulses are applied. In addition, in this specification, the noise generated by interference will be explained by taking the unit pixel 20 illustrated as the second variant to the fourth variant and the sixth variant to the eighth variant as an example.

[0442] 1.13.1.1 Interference caused by background light

[0443] One of the interferences to which the ToF sensor 1 is subjected is interference caused by background light (also referred to as disturbance light) such as sunlight or illumination light being incident on the light receiving unit 14 . Fig.57 This is a diagram for explaining noise generated by background light as interference light.

[0444] like Fig.57 As shown in (a) of FIG. 1 , when considering the span of acquiring a depth frame, the background light can generally be regarded as light with a constant intensity (i.e., light with a DC component). In this case, as Fig.57 As shown in (b), the charges accumulated in the memories 24A1 to 24A4 include charges 91A generated by photoelectric conversion of the reflected light L2 (hereinafter referred to as charges of the reflected light L2) and charges 92A generated by photoelectric conversion of the background light (hereinafter referred to as charges of the background light). On the other hand, only charges 92B of the background light are accumulated in the memories 24B1 to 24B4 in which the components of the reflected light L2 are not accumulated.

[0445] Here, as described above, since the background light is a light of a DC component, the charges 92A in the memories 24A1 to 24A4 and the charges 92B in the memories 24B1 to 24B4 have the same charge amount. Fig.57As shown in (b), by subtracting the charge amount of charge 92B in memories 24B1 to 24B4 from the total charge amount in memories 24A1 to 24A4 (the total amount of charge 91A and charge 92A), the charge amount of charge 91A of only reflected light L2 can be obtained, that is, the noise caused by interference light (background light) can be eliminated.

[0446] 1.13.1.2 Interference from another ToF sensor

[0447] Another example of interference to which the ToF sensor 1 is subjected is interference caused by reflected light of illumination light emitted from a light emitting unit of another ToF sensor different from the ToF sensor 1 being incident on the light receiving unit 14 of the ToF sensor 1 (this is referred to as “interference from another ToF sensor”).

[0448] In the case of receiving interference from another ToF sensor, whether or not the interference appears as noise depends on whether or not the reflected light (interference light) from the other ToF sensor is incident on the light receiving unit 14 during a period (hereinafter referred to as an accumulation period) during which charge transfer is performed to the memories 24A1 to 24A4 or the memories 24B1 to 24B4. Note that in the following description, a period during which charge transfer is not performed to the memories 24A1 to 24A4 or the memories 24B1 to 24B4 is referred to as a non-accumulation period.

[0449] 1.13.1.2.1 When reflected light from another ToF sensor is incident during the non-integration period

[0450] Fig.58 3 is a diagram for explaining a case where reflected light (interference light) from another ToF sensor is incident during a non-integration period.

[0451] like Fig.58 As shown in (a), during the non-accumulation period, when interference light is incident on the light receiving unit 14, the charge generated in the photodiode 21 by photoelectric conversion of the interference light is not transmitted to the memories 24A1 to 24A4 and the memories 24B1 to 24B4, and the charge is discharged via the OFG transistors 221 and 222 or the OFG transistors 221 to 224.

[0452] Therefore, if Fig.58 As shown in (b), only the charge 91A of the reflected light L2 is accumulated in the memories 24A1 to 24A4, and no charge is accumulated in the memories 24B1 to 24B4 in which the component of the reflected light L2 is not accumulated.

[0453] Therefore, if Fig.58As shown in (b), when the charge amount of the charges in the memories 24B1 to 24B4 is subtracted from the charge amount of the charges in the memories 24A1 to 24A4 (charges 91A and 92A), the charge amount is the charge amount of the charge 91A of the reflected light L2. This means that the interference light does not generate noise.

[0454] 1.13.1.2.2 When reflected light from another ToF sensor is incident during the integration period

[0455] Fig.59 : is a diagram for explaining a case where reflected light (interference light) from another ToF sensor is incident within the accumulation period. Fig.59 The case where the pulse period of the irradiation light L1 coincides with the pulse period of the interference light and the phase of the irradiation light L1 coincides with the phase of the interference light is exemplified.

[0456] like Fig.59 As shown in (a), during the accumulation period, when interference light is incident on the light receiving unit 14, the charge generated in the photodiode 21 by photoelectric conversion of both the reflected light L2 and the interference light is transferred to the memories 24A1 to 24A4 and the memories 24B1 to 24B4.

[0457] In this case, if Fig.59 As shown in (b), the charges accumulated in the memories 24A1 to 24A4 include charges 91A generated by photoelectric conversion of the reflected light L2 (hereinafter referred to as charges of the reflected light L2) and charges 93A generated by photoelectric conversion of the interference light (hereinafter referred to as charges of the interference light). On the other hand, no charges are accumulated in the memories 24B1 to 24B4 in which the components of the reflected light L2 are not accumulated.

[0458] Therefore, if Fig.59 As shown in (b), when the charge amount of the charges in the memories 24B1 to 24B4 is subtracted from the charge amount of the charges (charges 91A and 93A) in the memories 24A1 to 24A4, the charge amount is the total charge amount of the charge 91A of the reflected light L2 and the charge 93A of the interference light. This means that, during the accumulation period, when the reflected light from another ToF sensor is incident, unless the charge amount of the interference light accumulated in the memories 24A1 to 24A4 matches the charge amount of the interference light accumulated in the memories 24B1 to 24B4, the noise caused by the interference light cannot be eliminated.

[0459] 1.13.2 Elimination of Interference Noise

[0460] As described above, in the distance measurement sensor of the indirect ToF method, noise may be generated due to the incidence of interference light, so that the distance measurement accuracy may be reduced.

[0461] Therefore, in this embodiment, during the period of acquiring one subframe, the phase of the irradiation light L1 (and the drive pulses VGA and VGB) in another accumulation period is opposite to the phase of the irradiation light L1 (and the drive pulses VGA and VGB) in a certain accumulation period. In this specification, this is referred to as encoding of the accumulation period.

[0462] For example, it is possible to manage the encoding of the accumulation period by associating one accumulation period with one bit. In this case, for example, the phase of the irradiation light L1 (and the drive pulses VGA and VGB) may not be reversed in the accumulation period associated with bit '0' (hereinafter referred to as code 0), while the phase of the irradiation light L1 (and the drive pulses VGA and VGB) may be reversed in the accumulation period associated with bit '1' (hereinafter referred to as code 1).

[0463] Specifically, when eight accumulation periods are performed to acquire one subframe, as a code for encoding the accumulation period, 8-bit codes such as '01010101' and '00101011' can be used. The code encoding the accumulation period is preferably a code with a duty ratio of 50:50 between code 0 and code 1.

[0464] Note that as a code string for encoding the accumulation period, for example, a pseudo-random number generated using a pseudo-random number generator or the like, a code string prepared in advance, or the like can be used.

[0465] 1.13.2.1 Example of noise removal by encoding the accumulation period

[0466] Here, an example will be given to eliminate noise by encoding the accumulation period. In the following description, similar to the description of the "drive pulse example", it is assumed that the distance from the light emitting unit 13 and the light receiving unit 14 to the object 90 is 1m (meter), and the distance (2m) from the light emitting unit 13 to the light receiving unit 14 via the object 90 corresponds to one pulse cycle of the illumination light L1 emitted from the light emitting unit 13. In addition, in the drawings used in the following description, the shaded area superimposed on the drive pulses VGA and VGB represents an example of the amount of charge accumulated in the memory to which the drive pulse is applied. In addition, in this specification, the noise generated by interference will be explained by taking the unit pixel 20 illustrated as the second variant to the fourth variant and the sixth variant to the eighth variant as an example. However, here, it is assumed that the non-accumulation period is not set.

[0467] 1.13.2.1.1 Case where the modulation frequency of the interference light from another ToF sensor is different from the modulation frequency of its own illumination light

[0468] Fig.60: is a diagram for explaining noise elimination according to the first embodiment when the modulation frequency of interference light from another ToF sensor is different from the modulation frequency of its own illumination light. Note that, Fig.60 FIG. 4 shows a case where four accumulation periods are repeated when acquiring one subframe. Fig.60 In , the code for encoding the four accumulation periods is set to '0101'.

[0469] like Fig.60 As shown in (a), when the modulation frequency of the reflected light from another ToF sensor is different from the modulation frequency of its own illuminating light L1, by encoding four accumulation periods using codes with the same duty cycle, the charges generated by photoelectric conversion of the interference light (reflected light) from another ToF sensor can be basically evenly distributed to memories 24A1 to 24A4 and memories 24B1 to 24B4.

[0470] Results, such as Fig.60 As shown in (b), the charge amount of the interference light charge 94A included in the charges accumulated in the memories 24A1 to 24A4 and the charge amount of the interference light charge 94B included in the charges accumulated in the memories 24B1 to 24B4 become substantially equal.

[0471] Therefore, if Fig.60 As shown in (b), when the charge amount of the charge 94B in the memories 24B1 to 24B4 is subtracted from the charge amount of the charge 91A and 94A in the memories 24A1 to 24A4, the charge amount is substantially equal to the charge amount of the charge 91A of the reflected light L2. This means that the noise generated by the interference light has been eliminated to a negligible degree.

[0472] 1.13.2.1.2 When the modulation frequency of the interference light from another ToF sensor is the same as the modulation frequency of its own illumination light

[0473] Fig.61 is a diagram for explaining noise elimination according to the first embodiment when the modulation frequency of interference light from another ToF sensor is the same as the modulation frequency of its own illumination light. Fig.60 similar, Fig.61 A case where four accumulation periods are repeated when one subframe is acquired, and a code (code) for encoding the four accumulation periods is '0101' is shown.

[0474] like Fig.61As shown in (a), when the modulation frequency of the reflected light from another ToF sensor is the same as the modulation frequency of its own illuminating light L1, four accumulation periods are encoded using codes with the same duty cycle, and among the charges generated by photoelectric conversion of the interference light (reflected light) from another ToF sensor, the total amount of charge 94A0 transferred to the memories 24A1 to 24A4 in the accumulation period of code 0 and the total amount of charge 94A1 transferred to the memories 24A1 to 24A4 in the accumulation period of code 1 is equal to the total amount of charge 94B0 transferred to the memories 24B1 to 24B4 in the accumulation period of code 0 and the total amount of charge 94B1 transferred to the memories 24B1 to 24B4 in the accumulation period of code 1.

[0475] Therefore, if Fig.61 As shown in (b), when the charge amount of the charges in the memories 24B1 to 24B4 (charges 94B0 and 94B1) is subtracted from the charge amount of the charges in the memories 24A1 to 24A4 (charges 91A, 94A0, and 94A1), the charge amount is the charge amount of the charge 91A of the reflected light L2. This means that the noise generated by the interference light is eliminated.

[0476] 1.13.2.1.3 The case where the modulation frequency and phase of the interference light from another ToF sensor are the same as the modulation frequency and phase of its own illumination light

[0477] Fig.62 : is a diagram for explaining noise elimination according to the first embodiment in the case where the modulation frequency and phase of interference light from another ToF sensor are the same as the modulation frequency and phase of its own illumination light. Fig.60 or Fig.61 Like in Fig.62 A case where four accumulation periods are repeated when one subframe is acquired, and a code (code) for encoding the four accumulation periods is '0101' is shown.

[0478] like Fig.62 As shown in (a), when the modulation frequency and phase of the reflected light from another ToF sensor are the same as the modulation frequency and phase of its own irradiation light L1, in the accumulation period of code 0, the charge generated by photoelectric conversion of the interference light (reflected light) from another ToF sensor is transferred to the memories 24A1 to 24A4, and in the accumulation period of code 1, the charge generated by photoelectric conversion of the interference light (reflected light) from another ToF sensor is transferred to the memories 24B1 to 24B4.

[0479] Therefore, by encoding four accumulation periods using codes having the same duty ratio, charges generated by photoelectrically converting interference light (reflected light) from another ToF sensor can be equally distributed to the memories 24A1 to 24A4 and the memories 24B1 to 24B4.

[0480] Results, such as Fig.62 As shown in (b), the charge amount of the interference light charge 94A included in the charges accumulated in the memories 24A1 to 24A4 and the charge amount of the interference light charge 94B included in the charges accumulated in the memories 24B1 to 24B4 become substantially equal.

[0481] Therefore, if Fig.62 As shown in (b), when the charge amount of charge 94B in memories 24B1 to 24B4 is subtracted from the charge amount of charge (charges 91A and 94A) in memories 24A1 to 24A4, the charge amount is the charge amount of charge 91A of reflected light L2. This means that the noise generated by the interference light is eliminated.

[0482] 1.13.3 Noise Generated During Phase Switching

[0483] However, in the encoding of the accumulation period as described above, when the non-accumulation period is not provided between the accumulation periods, a phenomenon occurs in which, after the phase switching is performed by the encoding of the accumulation period, a part of the reflected light L2 of the irradiation light L1 emitted before the phase switching is incident on the light receiving unit 14. As a result, a part of the charge that should have been transferred to the memories 24A1 to 24A4 or the memories 24B1 to 24B4 is transferred to the memories 24B1 to 24B4 or the memories 24A1 to 24A1, so that the ranging accuracy may be reduced.

[0484] Fig.63 is a waveform diagram showing a case where the ToF sensor and the object are in contact with each other, that is, the distance from the ToF sensor to the object is 0, Fig.64 : is a waveform diagram showing a case where the ToF sensor and the object are separated from each other (as an example, the distance from the ToF sensor to the object is a distance corresponding to one pulse cycle of the irradiated light). Note that Fig.63 and Fig.64 Both show the case where no non-accumulation period is set between the accumulation periods.

[0485] like Fig.63As shown in (a), when the ToF sensor 1 is in contact with the object 90, before the phase of the light receiving unit 14 is switched, that is, before the phases of the driving pulses VGA and VGB are switched according to the encoding of the accumulation period, all the reflected light L2 of the irradiation light L1 emitted before the phase switching is incident on the light receiving unit 14. Therefore, part of the charge that should have been transferred to the memories 24A1 to 24A4 or the memories 24B1 to 24B4 is not transferred to the memories 24B1 to 24B4 or the memories 24A1 to 24A1. Fig.63 As shown in (b) of FIG. 1 , the charge amount of the charge 96 obtained by subtracting the charge accumulated in the memories 24B1 to 24B4 from the charge 95A accumulated in the memories 24A1 to 24A4 is a true charge amount corresponding to the amount of the reflected light L2 .

[0486] On the other hand, Fig.64 As shown in (a) of FIG. 1 , in a case where the ToF sensor 1 and the object 90 are separated from each other, for example, in a case where the distance from the ToF sensor 1 to the object 90 is a distance corresponding to one pulse cycle of the irradiation light L1 (for example, 2 m), after the phases of the drive pulses VGA and VGB are switched based on the encoding of the accumulation period, the last pulse of the reflected light L2 is incident on the light receiving unit 14. Therefore, a part of the charge that should have been transferred to the memories 24A1 to 24A4 or the memories 24B1 to 24B4 is transferred to the memories 24B1 to 24B4 or the memories 24A1 to 24A1, and as shown in FIG. Fig.64 As shown in (b), the charge amount of charge 96 obtained by subtracting the charge 95B accumulated in the memories 24B1 to 24B4 from the charge 95A accumulated in the memories 24A1 to 24A4 is a charge amount including an error relative to the true charge amount corresponding to the amount of reflected light L2.

[0487] 1.13.3.1 Example of noise cancellation operation during phase switching (in the case of 2-tap type)

[0488] Therefore, in this embodiment, if Fig.65 As shown in (a) of FIG. 1 , a non-accumulation period is provided between the accumulation periods. In the non-accumulation period, a high-level driving pulse OFG is applied to the gates of the OFG transistors 221 to 224. As a result, the charge generated by a portion of the reflected light L2 of the irradiation light L1 emitted before the phase switching is incident on the light receiving unit 14 after the phase switching through the encoding of the accumulation period is discharged via the OFG transistors 221 to 224, thereby avoiding the phenomenon that a portion of the charge that should have been transferred to the memories 24A1 to 24A4 or the memories 24B1 to 24B4 is transferred to the memories 24B1 to 24B4 or the memories 24A1 to 24A1. As a result, as Fig.65As shown in (b) of FIG. 1 , the charge amount of the charge 96 obtained by subtracting the charge accumulated in the memories 24B1 to 24B4 from the charge 95A accumulated in the memories 24A1 to 24A4 becomes a true charge amount corresponding to the light amount of the reflected light L2 .

[0489] 1.13.3.2 Modification of Noise Cancellation Operation During Phase Switching

[0490] Fig.65 FIG. 2 shows a case where the two OFG transistors 221 and 222 are always turned on during the non-accumulation period, but the present disclosure is not limited to such operation. Fig.66 As shown in (a), the driving pulse OFG1 supplied to the gate of the OFG transistor 221 and the driving pulse OFG2 supplied to the gate of the OFG transistor 222 in the non-accumulation period may be pulses having the same cycle as the driving pulses VGA and VGB.

[0491] As a result, the vertical driving circuit 103 that supplies the driving pulses VGA, VGB, OFG1, and OFG2 can continue the same operation in the accumulation period and the non-accumulation period, and thus can maintain uniform the state of the voltage drop (IR drop) in each of the readout circuit A and the readout circuit B. As a result, the noise generated at the time of phase switching is reduced, and thus a depth frame with higher accuracy can be obtained.

[0492] 1.13.3.3 Modification of the noise cancellation operation during phase switching (in the case of a multi-tap type with 3 or more taps)

[0493] Furthermore, in the case where the readout circuit connected to one photodiode 21 is a 3-tap or more multi-tap type having 3 or more readout circuits, readout circuits other than the 2 readout circuits of the 3-tap or more may be used for resetting (discharging charge) of the photodiode 21. For example, Fig.15 The readout circuit 20C or Fig.16 The readout circuits 20C and 20D in FIG. 20A can be used to reset the photodiode 21 (discharge the electric charge).

[0494] In this case, for example, Fig.67 As shown in (a), in the non-accumulation period, a high-level drive pulse VGC (or VGC and VGD) is applied to the gate of the transfer gate transistor 23C (or 23C and 23D) of the readout circuit 20C (or 20C and 20D).

[0495] As a result, the charges generated in the photodiode 21 in the non-accumulation period can be efficiently discharged, and thus a more accurate depth frame can be acquired.

[0496] 1.14 Function and Effect

[0497] As described above, according to the present embodiment, since the charge stored in the memory is transferred to the common floating diffusion region 27 at the time of reading, the difference in the amount of accumulated charge due to the characteristic difference of each readout circuit can be reduced. As a result, a high-quality depth frame can be generated without acquiring inverted data, so that a high-quality depth frame can be generated at a high frame rate.

[0498] In addition, according to this embodiment, since multiple readout circuits share the structure downstream of the floating diffusion region 27 (reset transistor 26, amplification transistor 28, selection transistor 29, vertical signal line VSL, and AD converter in the column processing circuit 104, etc.), the characteristic differences caused by the downstream structure can be eliminated, thereby generating higher quality depth frames.

[0499] Furthermore, according to the present embodiment, since a plurality of accumulation periods when acquiring one subframe are encoded, noise generated due to interference with other ToF sensors can be reduced, thereby obtaining a depth frame with higher accuracy.

[0500] In addition, according to the present embodiment, a non-accumulation period is set between the accumulation period and the accumulation period, and the charge generated in the photodiode 21 in the non-accumulation period is discharged via the OFG transistors 221 and 222 or 221 to 224. Therefore, the noise generated at the time of phase switching can be reduced, and a higher-precision depth frame can be acquired.

[0501] 2. Second Implementation Method

[0502] Next, the second embodiment will be described in detail with reference to the accompanying drawings. In the following description, the same configuration and operation as those of the above-described embodiment are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0503] In the first embodiment, the unit pixel 20 having a configuration in which the charges generated in the photodiode 21 are temporarily accumulated in the memory and then the charges in the memory are transferred to the shared floating diffusion region 27 is exemplified. On the other hand, in the second embodiment, a unit pixel configured to directly transfer the charges generated in the photodiode 21 to the floating diffusion region will be exemplified.

[0504] 2.1 First Configuration Example

[0505] Fig.68 1 is a circuit diagram showing a circuit configuration example of a unit pixel according to a first configuration example of the second embodiment. Fig.68 As shown, the unit pixel 120-1 according to the first configuration example has the same structure as that in the first embodiment. Fig.14The unit pixel 20-5 according to the fifth configuration example described above is similar in structure to that in which the transfer gate transistors 23A and 23B and the memories 24A and 24B in the readout circuits 20A and 20B are omitted. In addition, in the unit pixel 120-1, separate reset transistors 26A and 26B, floating diffusion regions 27A and 27B, amplification transistors 28A and 28B, and selection transistors 29A and 29B are provided for the readout circuits 20A and 20B, respectively.

[0506] For example, the driving pulse supplied to the unit pixel 120-1 having such a circuit configuration may be the same as that in the first embodiment. Fig.65 or Fig.66 The drive pulses described are similar.

[0507] As a result, in encoding the accumulation period, the charge generated in the photodiode 21 in the non-accumulation period is discharged via the OFG transistors 221 and 222 or 221 to 224, so the noise generated at the time of phase switching can also be reduced and a depth frame with higher accuracy can be obtained.

[0508] 2.2 Second Configuration Example

[0509] Fig.69 1 is a circuit diagram showing a circuit configuration example of a unit pixel according to a second configuration example of the second embodiment. Fig.69 As shown, the unit pixel 120-2 according to the second configuration example has the same structure as that in the first embodiment. Fig.15 The unit pixel 20-6 according to the sixth configuration example described above is similar in structure to that in which the transfer gate transistors 23A, 23B, and 23C and the memories 24A, 24B, and 24C in the readout circuits 20A, 20B, and 20C are omitted. In addition, in the unit pixel 120-2, a separate reset transistor 26A, 26B, or 26C, a floating diffusion region 27A, 27B, or 27C, an amplification transistor 28A, 28B, or 28C, and a selection transistor 29A, 29B, or 29C are provided for the readout circuits 20A, 20B, and 20C, respectively.

[0510] For example, the driving pulse supplied to the unit pixel 120-2 having such a circuit configuration may be the same as that in the first embodiment. Fig.67 The drive pulses described are similar.

[0511] As a result, the charges generated in the photodiode 21 in the non-accumulation period can be efficiently discharged through the OFG transistor 22 and the readout circuit 20C, so that a more accurate depth frame can be obtained.

[0512] 2.3 Example of the third structure

[0513] Fig.701 is a circuit diagram showing a circuit configuration example of a unit pixel according to a third configuration example of the second embodiment. Fig.70 As shown, the unit pixel 120-3 according to the third configuration example has the same structure as that in the first embodiment. Fig.16 The unit pixel 20-7 according to the seventh configuration example described above is similar in structure to that in which the transfer gate transistors 23A, 23B, 23C, and 23D and the memories 24A, 24B, 24C, and 24D in the readout circuits 20A, 20B, 20C, and 20D are omitted. In addition, in the unit pixel 120-3, separate reset transistors 26A, 26B, 26C, or 26D, floating diffusion regions 27A, 27B, 27C, or 27D, amplification transistors 28A, 28B, 28C, or 28D, and selection transistors 29A, 29B, 29C, or 29D are provided for the readout circuits 20A, 20B, 20C, and 20D, respectively.

[0514] For example, the driving pulse supplied to the unit pixel 120-3 having such a circuit configuration may be the same as that in the first embodiment. Fig.67 The drive pulses described are similar.

[0515] As a result, the charges generated in the photodiode 21 in the non-accumulation period can be efficiently discharged through the OFG transistor 22 and the readout circuits 20C and 20D, so that a more accurate depth frame can be obtained.

[0516] Other configurations, operations, and effects may be similar to those of the above-described embodiments, and thus detailed descriptions are omitted here.

[0517] 3. Configuration example of a stacked solid-state imaging device to which the technology disclosed herein can be applied

[0518] Fig.71 This is a diagram schematically showing a configuration example of a non-stacked solid-state imaging device to which the technology of the present disclosure can be applied. Fig.72 and Fig.73 This is a diagram schematically showing a configuration example of a stacked solid-state imaging device to which the technology of the present disclosure can be applied.

[0519] Fig.71 FIG. 2 shows a schematic configuration example of a non-stacked solid-state imaging device. Fig.71 As shown, the solid-state imaging device 23010 includes a bare chip (semiconductor substrate) 23011. The bare chip 23011 has mounted thereon: a pixel region 23012 in which pixels are arranged in an array; a control circuit 23013 that performs various controls such as driving of pixels; and a logic circuit 23014 for signal processing.

[0520] Fig.72 and Fig.73FIG. 2 shows a schematic configuration example of a stacked solid-state imaging device. Fig.72 and Fig.73 As shown, the solid-state imaging device 23020 is constructed as one semiconductor chip in which two dies of a sensor die 23021 and a logic die 23024 are stacked and electrically connected.

[0521] exist Fig.72 In the embodiment, a pixel region 23012 and a control circuit 23013 are mounted on a sensor die 23021, and a logic circuit 23014 including a signal processing circuit that performs signal processing is mounted on a logic die 23024.

[0522] exist Fig.73 In the embodiment, a pixel region 23012 is mounted on a sensor die 23021 , and a control circuit 23013 and a logic circuit 23014 are mounted on a logic die 23024 .

[0523] 4. Examples of electronic devices to which the technology of the present disclosure can be applied

[0524] Fig.74 and Fig.75 Schematic diagram showing an example of an electronic device to which the technology according to the present disclosure can be applied. Note that in this specification, a smartphone is taken as an example of an electronic device to which the technology according to the present disclosure can be applied.

[0525] Fig.74 FIG. 2 shows an example of the front structure of a smart phone. Fig.74 As shown, the smartphone 1000 includes an active infrared (IR) light source 1131 as the light emitting unit 13 and front cameras 1141 and 1142 as the light receiving unit 14 on the front side where the display 1001 is provided.

[0526] In addition, if Fig.75 As shown, the smartphone 1000 includes an active IR light source 1133 as the light emitting unit 13 and rear cameras 1143 and 1144 as the light receiving unit 14 at the rear side opposite to the front side where the display 1001 is provided.

[0527] 5. Various application examples

[0528] Next, application examples of the present technology will be described.

[0529] For example, Fig.76 As shown, the present technology can be applied to various situations of sensing light such as visible light, infrared light, ultraviolet light, and X-rays.

[0530] · Devices used to capture images for viewing, such as digital cameras or portable devices with camera functions

[0531] · Devices used for transportation, such as on-vehicle sensors that capture images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping and for identifying the driver's status; surveillance cameras for monitoring moving vehicles and roads; and distance sensors for measuring the distance between vehicles, etc.

[0532] Devices for home appliances such as televisions, refrigerators, and air conditioners that capture images of user gestures and operate the device based on the gestures

[0533] Devices used in medical care, such as endoscopes or devices for angiography by receiving infrared light, etc.

[0534] ・Devices used for security, such as surveillance cameras for crime prevention or cameras for personal authentication, etc.

[0535] ・Device used for beauty treatment, such as a skin measuring instrument for photographing the skin or a microscope for photographing the scalp, etc.

[0536] ・Devices for sports, such as action cameras or wearable cameras for sports, etc.

[0537] Devices used in agriculture, such as cameras used to monitor the condition of fields and crops

[0538] 6. Application examples for mobile objects

[0539] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0540] Fig.77 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0541] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig.77 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0542] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; a braking device for generating a braking force for the vehicle, etc.

[0543] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for the following devices: a keyless entry system, a smart key system, a power window device, and various lights such as headlights, rear lights, brake lights, turn signal lights, and fog lights. In this case, radio waves sent from a portable device that replaces the key or signals of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

[0544] The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle in which the vehicle control system 12000 is installed. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 enables the camera unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing on a person, a vehicle, an obstacle, a sign, or characters on a road surface, etc. based on the received image.

[0545] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light or may be invisible light such as infrared rays.

[0546] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that photographs the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or can determine whether the driver is dozing off.

[0547] The microcomputer 12051 calculates the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and outputs a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the functions of an advanced driver assistance system (ADAS), which includes collision avoidance or collision mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, speed maintenance driving, collision warning of the vehicle, and lane departure warning of the vehicle.

[0548] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism or braking device, etc. based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control such as automatic driving aimed at achieving autonomous driving of the vehicle without relying on the driver's operation.

[0549] In addition, the microcomputer 12051 can output a control instruction to the body system control unit 12020 based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control to prevent glare by controlling the headlights, such as switching the high beam to the low beam, etc., according to the position of the front vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0550] The sound and image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually and auditorily notify information to the passengers of the vehicle or the outside of the vehicle. Fig.77 In the example of , as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0551] Fig.78 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0552] exist Fig.78 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0553] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the front nose, side mirrors, rear bumper or rear door and the upper part of the windshield in the vehicle 12100. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly obtain the front image of the vehicle 12100. The camera units 12102 and 12103 arranged at the side mirrors mainly obtain the image of the side of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains the image of the back of the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0554] Notice, Fig.78 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above can be obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0555] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0556] For example, the microcomputer 12051 obtains the distance to each three-dimensional object in the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting a three-dimensional object (particularly, the closest three-dimensional object) traveling in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h) on the driving path of the vehicle 12100 as the front vehicle. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be ensured between the front vehicle and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control) and the like. As described above, cooperative control such as automatic driving aimed at achieving autonomous driving of the vehicle without relying on the operation of the driver can be performed.

[0557] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as electric poles based on the distance information obtained from the camera units 12101 to 12104, extract the three-dimensional object data, and use the three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that cannot be visually recognized by the driver. Then, the microcomputer 12051 determines the collision risk representing the risk of collision with each obstacle, and when the collision risk is a set value or higher than the set value and there is a possibility of collision, the microcomputer 12051 can perform driving assistance for collision avoidance by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062 or performing forced deceleration or evasive steering through the drive system control unit 12010.

[0558] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by a process of extracting feature points in the captured images of the camera units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the contour of an object and determining whether it is a pedestrian. For example, when the microcomputer 12051 determines that there is a pedestrian in the captured images of the camera units 12101 to 12104 and identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 to superimpose and display a square contour line for emphasizing the identified pedestrian. In addition, the sound image output unit 12052 may cause the display unit 12062 to display an icon representing a pedestrian light at a desired position.

[0559] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the camera unit 12031 and the driver state detection unit 12041 in the above-mentioned configuration, etc. Specifically, the ToF sensor 1 according to the present disclosure can be applied to the camera units 12101, 12102, 12103, 12104, and 12105, etc. As a result, the situation around the vehicle 12100 can be detected more accurately, and therefore, more accurate control in autonomous driving, etc. and more accurate grasp of the driver's state, etc. can be achieved.

[0560] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments, and various changes can be made within the scope that does not depart from the gist of the present disclosure. In addition, the configurations of different embodiments and modified examples can also be appropriately combined.

[0561] Furthermore, the effects of the embodiments described in this specification are merely examples and are not limiting, and other effects may be provided.

[0562] Furthermore, each of the above-described embodiments may be used alone or in combination with other embodiments.

[0563] Note that the present technology can also have the following configurations.

[0564] (1) A solid-state imaging device comprising:

[0565] A pixel array section, in which a plurality of pixels are arranged in a matrix, wherein:

[0566] Each of the pixels comprises:

[0567] A plurality of photoelectric conversion units, each of which performs photoelectric conversion on incident light to generate electric charge;

[0568] a floating diffusion region, which accumulates charge;

[0569] a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region; and

[0570] A first transistor causes a pixel signal having a voltage value corresponding to a charge amount of the charges accumulated in the floating diffusion region to appear on a signal line.

[0571] (2) The solid-state imaging device according to (1), wherein:

[0572] Each of the plurality of pixels is arranged in a pixel area individually allocated on a first surface of the semiconductor substrate,

[0573] The plurality of transmission circuits include:

[0574] a plurality of first transfer circuits, the plurality of first transfer circuits being arranged point-symmetrically or line-symmetrically with respect to a center of the pixel region or a straight line passing through the center as an axis; and

[0575] a plurality of second transmission circuits, wherein the plurality of second transmission circuits are arranged in point symmetry or line symmetry with respect to the center or with the straight line as an axis; and

[0576] The respective photoelectric conversion units are provided one-to-one with respect to a combination of the first transfer circuit and the second transfer circuit arranged in a predetermined direction in the matrix-like arrangement.

[0577] (3) The solid-state imaging device according to (2), wherein each of the transfer circuits includes a second transistor having a vertical structure reaching from the first surface of the semiconductor substrate to the photoelectric conversion unit arranged in the semiconductor substrate.

[0578] (4) The solid-state imaging device according to (3), wherein the second transistor has two of the vertical structures.

[0579] (5) The solid-state imaging device according to any one of (2) to (4), further comprising:

[0580] a driving unit configured to drive the transmission of the charges of the plurality of transmission circuits, wherein:

[0581] The driving unit drives the first transfer circuit and the second transfer circuit so that a transfer timing of the charge via the first transfer circuit is different from a transfer timing of the charge via the second transfer circuit.

[0582] (6) The solid-state imaging device according to (5), wherein:

[0583] The drive unit

[0584] inputting a first drive pulse having a first phase angle with respect to a pulse of a predetermined period and having the predetermined period to the first transmission circuit, and,

[0585] A second drive pulse having a phase shifted by 180° with respect to the first drive pulse is input to the second transmission circuit.

[0586] (7) The solid-state imaging device according to (6), wherein:

[0587] The drive unit

[0588] driving the plurality of first transmission circuits in the same phase, and

[0589] The plurality of second transmission circuits are driven in the same phase.

[0590] (8) The solid-state imaging device according to (7), wherein the plurality of first transfer circuits and the plurality of second transfer circuits are arranged point-symmetrically or line-symmetrically with respect to the center or the straight line as an axis.

[0591] (9) The solid-state imaging device according to (7) or (8), wherein:

[0592] The plurality of transmission circuits further include a plurality of third transmission circuits and a plurality of fourth transmission circuits, and

[0593] The drive unit

[0594] A third driving pulse having a phase shifted by 90° with respect to the first driving pulse is input to each of the plurality of third transmission circuits, and the third driving pulse is driven with the same phase, and,

[0595] A fourth driving pulse having a phase shifted by 180° with respect to the third driving pulse is input to each of the plurality of fourth transfer circuits, and the fourth driving pulse is driven with the same phase.

[0596] (10) The solid-state imaging device according to (9), wherein:

[0597] The first driving pulse has the first phase angle of 0° relative to the pulse of the predetermined period,

[0598] The second driving pulse has a second phase angle of 180° relative to the pulse of the predetermined period,

[0599] The third driving pulse has a third phase angle of 90° relative to the pulse of the predetermined period, and

[0600] The fourth driving pulse has a fourth phase angle of 270° with respect to the pulse of the predetermined period.

[0601] (11) A solid-state imaging device according to (9) or (10), wherein the plurality of first transfer circuits, the plurality of second transfer circuits, the plurality of third transfer circuits, and the plurality of fourth transfer circuits are arranged point-symmetrically or line-symmetrically with respect to the center or with the straight line as an axis.

[0602] (12) The solid-state imaging device according to any one of (9) to (11), wherein

[0603] Each of the transfer circuits includes a memory that holds the charge generated in the photoelectric conversion unit, and

[0604] The drive unit

[0605] inputting a first drive pulse having a phase angle of 0° with respect to a pulse of the predetermined period and having the predetermined period to the plurality of first transfer circuits to accumulate the charge in the memory of each of the plurality of first transfer circuits,

[0606] inputting a second drive pulse having a phase angle of 180° with respect to a pulse of the predetermined period and having the predetermined period to the plurality of second transfer circuits to accumulate the charge in the memory of each of the plurality of second transfer circuits,

[0607] inputting a third driving pulse having a phase angle of 90° with respect to a pulse of the predetermined period and having the predetermined period to the plurality of third transfer circuits to accumulate the charge in the memory of each of the plurality of third transfer circuits, and

[0608] A fourth driving pulse having a phase angle of 270° with respect to a pulse of the predetermined period and having the predetermined period is input to the plurality of fourth transfer circuits to accumulate the charges in the memory of each of the plurality of fourth transfer circuits.

[0609] (13) The solid-state imaging device according to (12), wherein the memory is a MOS (metal-oxide-semiconductor) type memory.

[0610] (14) The solid-state imaging device according to any one of (9) to (13) further includes a signal processing unit, which generates distance information based on the ratio of the difference between the charge transmitted via the first transfer circuit and the charge transmitted via the second transfer circuit to the difference between the charge transmitted via the third transfer circuit and the charge transmitted via the fourth transfer circuit.

[0611] (15) The solid-state imaging device according to (2), wherein each of the pixels further includes a third transistor that discharges the charge generated in the photoelectric conversion unit.

[0612] (16) The solid-state imaging device according to (15), wherein the third transistor has a vertical structure reaching from the first surface of the semiconductor substrate to the photoelectric conversion unit arranged in the semiconductor substrate.

[0613] (17) The solid-state imaging device according to (16), wherein the third transistor has two of the vertical structures.

[0614] (18) The solid-state imaging device according to (6), wherein:

[0615] The driving unit divides the charges generated in the respective photoelectric conversion units into a plurality of accumulation periods and transfers the divided charges to the floating diffusion region, and

[0616] The driving unit inverts a phase of each of the first driving pulse and the second driving pulse for each of the accumulation periods.

[0617] (19) The solid-state imaging device according to (18), wherein:

[0618] Each of the pixels further includes a third transistor that discharges the charge generated in the photoelectric conversion unit,

[0619] The driving unit sets a non-accumulation period in which the charges generated in each of the photoelectric conversion units are not transferred to the floating diffusion region during the accumulation period, and

[0620] The drive unit discharges the charge generated in the photoelectric conversion unit via the third transistor in the non-accumulation period.

[0621] (20) The solid-state imaging device according to any one of (2) to (19), further including a pixel separation unit which is provided along a boundary portion of the pixel region and optically separates adjacent pixels from each other.

[0622] (21) The solid-state imaging device according to (20), wherein the pixel separation portion is provided in a groove which penetrates the semiconductor substrate from the first surface to a second surface opposite to the first surface or reaches a middle portion of the semiconductor substrate from the first surface.

[0623] (22) The solid-state imaging device according to (20) or (21), wherein the pixel separation unit includes at least one of a dielectric having silicon oxide as a main component and a metal having an optical property of reflecting near infrared rays.

[0624] (23) The solid-state imaging device according to any one of (20) to (22) further includes an element separation unit, which is arranged in at least a portion between the plurality of photoelectric conversion elements in the pixel region and optically separates adjacent photoelectric conversion elements from each other.

[0625] (24) The solid-state imaging device according to (23), wherein the element separation portion is provided in a groove which penetrates the semiconductor substrate from the first surface to a second surface opposite to the first surface or reaches a middle portion of the semiconductor substrate from the first surface.

[0626] (25) The solid-state imaging device according to (23) or (24), wherein the element separation portion includes at least one of a dielectric having silicon oxide as a main component and a metal having an optical property of reflecting near infrared rays.

[0627] (26) The solid-state imaging device according to any one of (1) to (25), wherein a periodic concavo-convex structure is provided on a light receiving surface of each of the photoelectric conversion units.

[0628] (27) The solid-state imaging device according to (26), wherein a period of the periodic concavo-convex structure is greater than or equal to 300 nm (nanometers).

[0629] (28) A distance measuring device comprising:

[0630] a light receiving unit including a pixel array section in which a plurality of pixels are arranged in a matrix; and

[0631] A light emitting unit, wherein the light emitting unit emits pulsed illumination light of a predetermined period, wherein:

[0632] Each of the pixels comprises:

[0633] A plurality of photoelectric conversion units, each of which performs photoelectric conversion on incident light to generate electric charge;

[0634] a floating diffusion region, which accumulates charge;

[0635] a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region; and

[0636] A first transistor causes a pixel signal having a voltage value corresponding to a charge amount of the charges accumulated in the floating diffusion region to appear on a signal line.

[0637] Reference numerals list

[0638] 1 ToF sensor

[0639] 11 Control Unit

[0640] 13 Lighting Unit

[0641] 14 Light receiving unit

[0642] 15 Computational Units

[0643] 19 External I / F

[0644] 20,20-1 to 20-7,120-1,120-2,120-3,920 unit pixels

[0645] 20A,20A1 to 20A4,20B,20B1 to 20B4,20C,20C1,20C2,20D1,20D2,120A,120B,120C,120D,920A,920B Readout Circuit

[0646] 21,211 to 214 Photodiode

[0647] 22,221 to 224 OFG transistors

[0648] 23A, 23A1 to 23A4, 23B, 23B1 to 23B4, 23C1, 23C2, 23D1, 23D2 Transmission gate transistors

[0649] 24A,24A1 to 24A4,24B,24B1 to 24B4,24C,24C1,24C2,24D,24D1,24D2 Memory

[0650] 25A, 25A1 to 25A4, 25B, 25B1 to 25B4, 25C, 25C1, 25C2, 25D, 25D1, 25D2 Pass transistors

[0651] 26,26A,26B Reset transistor

[0652] 27,27A,27B Floating diffusion area

[0653] 28,28A,28B Amplifier transistor

[0654] 29,29A,29B Select transistor

[0655] 30 Boundary Department

[0656] 31,33,34,35 Pixel separation unit

[0657] 32 Component separation unit

[0658] 40 Semiconductor substrate

[0659] 42 n-type semiconductor region

[0660] 43 n-type semiconductor region

[0661] 44 n+ type semiconductor region

[0662] 45 Concave and convex structure

[0663] 50 wiring layers

[0664] 51 Insulation film

[0665] 52 Wiring

[0666] 61 Insulation film

[0667] 62 shading film

[0668] 63 Flattening film

[0669] 64 On-chip lens

[0670] 70 pixel area

[0671] 71 to 74 Division area

[0672] 80 Host

[0673] 90 Objects

[0674] 100 Solid-state imaging device

[0675] 101 Pixel array unit

[0676] 102 System control unit

[0677] 103 Vertical drive circuit

[0678] 104 Column Processing Circuit

[0679] 105 Horizontal drive circuit

[0680] 106 Signal Processing Unit

[0681] 107 Data storage unit

[0682] 341,351 Insulation film

[0683] 342,352 Shading part

[0684] LD pixel drive line

[0685] VGA, VGB, VGC, VGD drive lines (drive pulses)

[0686] VSL,VSLA,VSLB vertical signal lines

Claims

1. A solid-state imaging device, comprising: A pixel array section, in which a plurality of pixels are arranged in a matrix, wherein: Each of the pixels comprises: A plurality of photoelectric conversion units, each of which performs photoelectric conversion on incident light to generate electric charge; a floating diffusion region, which accumulates charge; a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region; a first transistor that causes a pixel signal having a voltage value corresponding to the charge amount of the charges accumulated in the floating diffusion region to appear on a signal line, wherein Each of the plurality of pixels is arranged in a pixel area individually allocated on a first surface of the semiconductor substrate, The plurality of transmission circuits include: a plurality of first transfer circuits, the plurality of first transfer circuits being arranged point-symmetrically or line-symmetrically with respect to a center of the pixel region or a straight line passing through the center as an axis; and a plurality of second transmission circuits, the plurality of second transmission circuits being arranged point-symmetrically or line-symmetrically with respect to the center or with the straight line as an axis, wherein each of the photoelectric conversion units is provided one-to-one with respect to a combination of the first transmission circuit and the second transmission circuit arranged in a predetermined direction in the matrix-like arrangement; and a driving unit configured to drive the transmission of the charges of the plurality of transmission circuits, wherein: The driving unit drives the first transmission circuit and the second transmission circuit so that a transmission time of the charge via the first transmission circuit is different from a transmission time of the charge via the second transmission circuit. The driving unit inputs a first driving pulse having a first phase angle with respect to a pulse of a predetermined period and having the predetermined period to the first transmission circuit, and inputs a second driving pulse having a phase shifted by 180° with respect to the first driving pulse to the second transmission circuit, and The driving unit drives the plurality of first transmission circuits in the same phase, and drives the plurality of second transmission circuits in the same phase.

2. The solid-state imaging device according to claim 1, wherein Each of the transfer circuits includes a second transistor having a vertical structure reaching from the first surface of the semiconductor substrate to the photoelectric conversion unit arranged in the semiconductor substrate.

3. The solid-state imaging device according to claim 1, wherein The plurality of first transmission circuits and the plurality of second transmission circuits are arranged in point symmetry or line symmetry with respect to the center or with the straight line as an axis.

4. The solid-state imaging device according to claim 1, wherein The plurality of transmission circuits further include a plurality of third transmission circuits and a plurality of fourth transmission circuits, and The drive unit A third driving pulse having a phase shifted by 90° with respect to the first driving pulse is input to each of the plurality of third transmission circuits, and the third driving pulse is driven with the same phase, and, A fourth driving pulse having a phase shifted by 180° with respect to the third driving pulse is input to each of the plurality of fourth transfer circuits, and the fourth driving pulse is driven with the same phase.

5. The solid-state imaging device according to claim 4, wherein: The first driving pulse has the first phase angle of 0° relative to the pulse of the predetermined period, The second driving pulse has a second phase angle of 180° relative to the pulse of the predetermined period, The third driving pulse has a third phase angle of 90° relative to the pulse of the predetermined period, and The fourth driving pulse has a fourth phase angle of 270° with respect to the pulse of the predetermined period.

6. The solid-state imaging device according to claim 4, wherein: The plurality of first transmission circuits, the plurality of second transmission circuits, the plurality of third transmission circuits, and the plurality of fourth transmission circuits are arranged in point symmetry or line symmetry with respect to the center or with the straight line as an axis.

7. The solid-state imaging device according to claim 4, wherein: Each of the transfer circuits includes a memory that holds the charge generated in the photoelectric conversion unit, and The drive unit inputting a first drive pulse having a phase angle of 0° with respect to a pulse of the predetermined period and having the predetermined period to the plurality of first transfer circuits to accumulate the charge in the memory of each of the plurality of first transfer circuits, inputting a second drive pulse having a phase angle of 180° with respect to a pulse of the predetermined period and having the predetermined period to the plurality of second transfer circuits to accumulate the charge in the memory of each of the plurality of second transfer circuits, inputting a third driving pulse having a phase angle of 90° with respect to a pulse of the predetermined period and having the predetermined period to the plurality of third transfer circuits to accumulate the charge in the memory of each of the plurality of third transfer circuits, and A fourth driving pulse having a phase angle of 270° with respect to a pulse of the predetermined period and having the predetermined period is input to the plurality of fourth transfer circuits to accumulate the charges in the memory of each of the plurality of fourth transfer circuits.

8. The solid-state imaging device according to claim 4 further includes a signal processing unit, which generates distance information based on the ratio of the difference between the charge transmitted via the first transfer circuit and the charge transmitted via the second transfer circuit and the difference between the charge transmitted via the third transfer circuit and the charge transmitted via the fourth transfer circuit.

9. A solid-state imaging device, comprising: A pixel array section, in which a plurality of pixels are arranged in a matrix, wherein: Each of the pixels comprises: A plurality of photoelectric conversion units, each of which performs photoelectric conversion on incident light to generate electric charge; a floating diffusion region, which accumulates charge; a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region; a first transistor that causes a pixel signal having a voltage value corresponding to a charge amount of the charges accumulated in the floating diffusion region to appear on a signal line, in, Each of the plurality of pixels is arranged in a pixel area individually allocated on a first surface of the semiconductor substrate, The plurality of transmission circuits include: a plurality of first transfer circuits, the plurality of first transfer circuits being arranged point-symmetrically or line-symmetrically with respect to a center of the pixel region or a straight line passing through the center as an axis; and a plurality of second transmission circuits, the plurality of second transmission circuits being arranged point-symmetrically or line-symmetrically with respect to the center or with the straight line as an axis, wherein each of the photoelectric conversion units is provided one-to-one with respect to a combination of the first transmission circuit and the second transmission circuit arranged in a predetermined direction in the matrix-like arrangement; and a driving unit configured to drive the transmission of the charge of the plurality of transmission circuits, wherein the driving unit drives the first transmission circuit and the second transmission circuit so that the transmission timing of the charge via the first transmission circuit is different from the transmission timing of the charge via the second transmission circuit, the driving unit inputs a first driving pulse having a first phase angle with respect to a pulse of a predetermined period and having the predetermined period to the first transmission circuit, and inputs a second driving pulse having a phase shifted by 180° with respect to the first driving pulse to the second transmission circuit, The driving unit divides the charges generated in the respective photoelectric conversion units into a plurality of accumulation periods and transfers the divided charges to the floating diffusion region, and The driving unit inverts a phase of each of the first driving pulse and the second driving pulse for each of the accumulation periods.

10. The solid-state imaging device according to claim 9, wherein: Each of the pixels further includes a third transistor that discharges charges generated in the photoelectric conversion unit.

11. The solid-state imaging device according to claim 10, wherein: The driving unit sets a non-accumulation period in which the charges generated in each of the photoelectric conversion units are not transferred to the floating diffusion region during the accumulation period, and The drive unit discharges the charge generated in the photoelectric conversion unit via the third transistor in the non-accumulation period. 12 . The solid-state imaging device according to claim 1 , further comprising a pixel separation section which is provided along a boundary portion of the pixel region and optically separates adjacent pixels from each other. 13 . The solid-state imaging device according to claim 12 , further comprising an element separation section which is provided in at least a portion between the plurality of photoelectric conversion units in the pixel region and optically separates adjacent photoelectric conversion units from each other.

14. The solid-state imaging device according to any one of claims 1 to 11, wherein: A periodic concavo-convex structure is provided on the light receiving surface of each of the photoelectric conversion units.

15. A distance measuring device, comprising: a light receiving unit including a pixel array section in which a plurality of pixels are arranged in a matrix; and A light emitting unit, wherein the light emitting unit emits pulsed illumination light of a predetermined period, wherein Each of the pixels comprises: A plurality of photoelectric conversion units, each of which performs photoelectric conversion on incident light to generate electric charge; a floating diffusion region, which accumulates charge; a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region; a first transistor that causes a pixel signal having a voltage value corresponding to a charge amount of the charges accumulated in the floating diffusion region to appear on a signal line, in, Each of the plurality of pixels is arranged in a pixel area individually allocated on a first surface of the semiconductor substrate, The plurality of transmission circuits include: a plurality of first transfer circuits, the plurality of first transfer circuits being arranged point-symmetrically or line-symmetrically with respect to a center of the pixel region or a straight line passing through the center as an axis; and a plurality of second transmission circuits, the plurality of second transmission circuits being arranged point-symmetrically or line-symmetrically with respect to the center or with the straight line as an axis, wherein each of the photoelectric conversion units is provided one-to-one with respect to a combination of the first transmission circuit and the second transmission circuit arranged in a predetermined direction in the matrix-like arrangement; and A driving unit configured to drive the transmission of the charge of the plurality of transmission circuits, wherein the driving unit drives the first transmission circuit and the second transmission circuit so that the transmission timing of the charge via the first transmission circuit is different from the transmission timing of the charge via the second transmission circuit, the driving unit inputs a first driving pulse having a first phase angle relative to a pulse of a predetermined period and having the predetermined period to the first transmission circuit, and inputs a second driving pulse having a phase shifted by 180° relative to the first driving pulse to the second transmission circuit, the driving unit drives the plurality of first transmission circuits with the same phase, and drives the plurality of second transmission circuits with the same phase.

16. A distance measuring device, comprising: a light receiving unit including a pixel array section in which a plurality of pixels are arranged in a matrix; and A light emitting unit, wherein the light emitting unit emits pulsed illumination light of a predetermined period, wherein Each of the pixels comprises: A plurality of photoelectric conversion units, each of which performs photoelectric conversion on incident light to generate electric charge; a floating diffusion region, which accumulates charge; a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region; a first transistor that causes a pixel signal having a voltage value corresponding to a charge amount of the charges accumulated in the floating diffusion region to appear on a signal line, in, Each of the plurality of pixels is arranged in a pixel area individually allocated on a first surface of the semiconductor substrate, The plurality of transmission circuits include: a plurality of first transfer circuits, the plurality of first transfer circuits being arranged point-symmetrically or line-symmetrically with respect to a center of the pixel region or a straight line passing through the center as an axis; and a plurality of second transmission circuits, the plurality of second transmission circuits being arranged point-symmetrically or line-symmetrically with respect to the center or with the straight line as an axis, wherein each of the photoelectric conversion units is provided one-to-one with respect to a combination of the first transmission circuit and the second transmission circuit arranged in a predetermined direction in the matrix-like arrangement; and a driving unit configured to drive the transmission of the charge of the plurality of transmission circuits, wherein the driving unit drives the first transmission circuit and the second transmission circuit so that the transmission timing of the charge via the first transmission circuit is different from the transmission timing of the charge via the second transmission circuit, the driving unit inputs a first driving pulse having a first phase angle with respect to a pulse of a predetermined period and having the predetermined period to the first transmission circuit, and inputs a second driving pulse having a phase shifted by 180° with respect to the first driving pulse to the second transmission circuit, The driving unit divides the charges generated in the respective photoelectric conversion units into a plurality of accumulation periods and transfers the divided charges to the floating diffusion region, and The driving unit inverts a phase of each of the first driving pulse and the second driving pulse for each of the accumulation periods.

Images