Memory device and method of operating the same

Abstract

Provided herein may be a memory device and an operating method thereof. The memory device may include a plurality of cell strings, a peripheral circuit, and a control logic. Each cell string in the cell string includes a drain select transistor, a source select transistor, and a plurality of memory cells coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a programming operation and a programming verification operation on a cell string selected from a plurality of cell strings. The control logic may be configured to control the peripheral circuit to raise the channel voltage of at least one unselected cell string among the plurality of cell strings based on a comparison between a degree of progress of the programming operation and a reference degree of progress during the programming verification operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0061155 filed on May 21, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly to a memory device and a method of operating a memory device. Background Art

[0004] A storage device is a device that stores data based on a host device such as a computer or a smart phone. A storage device may include a memory device in which data is stored and a memory controller that controls the memory device. Such memory devices are classified into volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device is a memory device in which data is stored only when power is supplied and the stored data is lost when power is interrupted. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] A nonvolatile memory device is a memory device in which stored data is retained even when power is interrupted. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the invention

[0007] An embodiment of the present disclosure may provide a memory device. The memory device may include a plurality of cell strings, a peripheral circuit, and a control logic. Each of the plurality of cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells coupled in series between the drain select transistor and the source select transistor. The peripheral circuit is configured to perform a programming operation and a programming verification operation on a cell string selected from the plurality of cell strings. The control logic is configured to control the peripheral circuit to increase the channel voltage of at least one unselected cell string among the plurality of cell strings based on a comparison between a degree of progress of the programming operation and a reference degree of progress during the programming verification operation.

[0008] An embodiment of the present disclosure may provide a memory device. The memory device may include a first cell string to a fourth cell string, a peripheral circuit, and a control logic. Each of the first cell string to the fourth cell string includes a drain select transistor, a source select transistor, and a plurality of memory cells coupled in series between the drain select transistor and the source select transistor. The peripheral circuit is configured to perform a programming operation and a programming verification operation on the memory cells in the first cell string. The control logic is configured to control the peripheral circuit to increase the channel voltage of the third cell string and the fourth cell string based on a comparison between the progress degree of the programming operation and the reference progress degree during the programming verification operation, wherein the corresponding source select transistors included in the first cell string and the second cell string are coupled to the first source select line, and wherein the corresponding source select transistors included in the third cell string and the fourth cell string are coupled to the second source select line.

[0009] An embodiment of the present disclosure may provide a method for operating a memory device, the memory device including a plurality of cell strings, each cell string including a drain selection transistor, a source selection transistor, and a plurality of memory cells coupled in series between the drain selection transistor and the source selection transistor. The method may include: performing a programming operation on a cell string selected from the plurality of cell strings, and during a programming verification operation performed on the selected cell string, controlling the increase of a channel voltage of at least one unselected cell string among the plurality of cell strings based on a comparison between a progress degree of the programming operation and a reference progress degree. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 Diagram of the structure of a memory device.

[0012] Figure 3 It is shown Figure 2 Diagram of a memory cell array.

[0013] Figure 4 It is shown Figure 2 A diagram of one embodiment of a memory cell array.

[0014] Figure 5 It is shown Figure 4 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0015] Figure 6 It is shown Figure 4 A circuit diagram of an example of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0016] Figure 7 It is shown Figure 2 A diagram of a programming operation of a memory device.

[0017] Figure 8 is a diagram illustrating the degree of progress of a programming operation according to one embodiment.

[0018] Fig. 9 is a circuit diagram of a cell string according to one embodiment.

[0019] Fig.10 It means that Fig. 9 FIG. 1 is a diagram of control of raising a channel voltage of a non-selected cell string during a program verification operation performed on a cell string of FIG.

[0020] Fig.11 is a circuit diagram of a cell string according to one embodiment.

[0021] Fig.12 It means that Fig.11 FIG. 1 is a diagram of control of raising a channel voltage of a non-selected cell string during a program verification operation performed on a cell string of FIG.

[0022] Fig.13A is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0023] Fig. 13B is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0024] Fig. 13C is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0025] Fig.13D is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0026] Fig.14 is a flow chart illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0027] Fig.15 It is shown Fig.14 Flowchart of an embodiment of the present invention.

[0028] Fig.16 It is shown Fig.14Flowchart of an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are exemplified to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0030] Various embodiments of the present disclosure are directed to a memory device having improved program verification operation performance, and a method of operating the memory device.

[0031] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0032] refer to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device. The storage device 50 may be a device that stores data based on a host, such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet PC, or an in-vehicle infotainment system.

[0033] The storage device 50 may be manufactured as any of various types of storage devices, depending on the host interface used to communicate with the host. The storage device 50 may be implemented as any of various types of storage devices, such as a solid state drive (SSD), a multimedia card (such as MMC, embedded MMC (eMMC), reduced size MMC (RS-MMC) or micro MMC), a secure digital card (such as SD, mini SD or micro SD), a universal storage bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI Express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0034] The memory device 50 may be manufactured in any of various types of packaging forms. For example, the memory device 50 may be manufactured and packaged as a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabrication package (WFP), and a wafer-level stacked package (WSP).

[0035] The memory device 100 may store data. The memory device 100 may operate based on the memory controller 200. The memory device 100 may include a memory cell array having a plurality of memory cells storing data.

[0036] Each of the memory cells may be implemented as a single-level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0037] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In one embodiment, a page may be a unit of measurement for storing data in the memory device 100 or reading data stored in the memory device 100.

[0038] A memory block may be a unit of measurement for erasing data. In one embodiment, the memory device 100 may take many alternative forms, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM). In this specification, for ease of description, the memory device 100 will be described under the assumption that it is a NAND flash memory.

[0039] The memory device 100 can receive commands and addresses from the memory controller 200, and can access the area of ​​the memory cell array selected by the address. That is, the memory device 100 can perform the operation indicated by the command on the area selected by the address. For example, the memory device 100 can perform a write operation (i.e., a programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 can program data to the area selected by the address. During the read operation, the memory device 100 can read data from the area selected by the address. During the erase operation, the memory device 100 can erase the data stored in the area selected by the address.

[0040] The memory controller 200 may control overall operations of the memory device 50 .

[0041] The memory controller 200 may run firmware (FW) when power is applied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 may run firmware such as a flash translation layer (FTL) for controlling communication between the host and the memory device 100.

[0042] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from a host, and may convert the logical block address (LBA) into a physical block address (PBA) indicating an address of a memory cell included in the memory device 100 and in which data is to be stored.

[0043] The memory controller 200 may control the memory device 100 so that a programming operation, a read operation, or an erase operation is performed based on a request received from a host. During a programming operation, the memory controller 200 may provide a write command, a physical block address (PBA), and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a physical block address (PBA) to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a physical block address (PBA) to the memory device 100.

[0044] In one embodiment, regardless of whether a request from the host is received, the memory controller 200 may autonomously generate commands, addresses, and data, and may transmit them to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0045] In one embodiment, the memory controller 200 may control at least two memory devices 100. In this case, the memory controller 200 may control the memory devices 100 by using an interleaving scheme to improve operation performance. The interleaving scheme may be an operation mode in which operation cycles of at least two memory devices 100 are overlapped with each other.

[0046] The host may communicate with the storage device 50 by using at least one of various communication methods, such as universal serial bus (USB), serial AT attachment (SATA), serial attached SCSI (SAS), high-speed inter-chip (HSIC), small computer system interface (SCSI), peripheral component interconnect (PCI), PCI Express (PCIe), non-volatile memory express (NVMe), universal flash storage (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM) and load reduced DIMM (LRDIMM) communication methods.

[0047] Figure 2 It is shown Figure 1 Diagram of the structure of a memory device.

[0048] refer to Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0049] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be coupled to the address decoder 121 via the row line RL. The memory blocks BLK1 to BLKz are coupled to the read-write circuit 123 via the bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells are nonvolatile memory cells. Among the plurality of memory cells, the memory cells coupled to the same word line are defined as a single physical page. That is, the memory cell array 110 may be composed of a plurality of physical pages. According to one embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. One or more dummy cells may be coupled in series between the drain select transistor and the memory cell, and between the source select transistor and the memory cell.

[0050] Each of the memory cells of the memory device 100 may be implemented as a single-level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0051] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a read and write circuit 123 , a data input / output circuit 124 , and a sensing circuit 125 .

[0052] The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 so that a program operation, a read operation, and an erase operation are performed.

[0053] The address decoder 121 may be coupled to the memory cell array 110 via a row line RL. The row line RL may include a drain selection line, a word line, a source selection line, and a common source line. According to one embodiment of the present disclosure, the word line may include a normal word line and a dummy word line. According to one embodiment of the present disclosure, the row line RL may also include a pipeline selection line.

[0054] The address decoder 121 may operate based on the control logic 130. The address decoder 121 may receive an address ADDR from the control logic 130.

[0055] The address decoder 121 may decode the block address among the received address ADDR. The address decoder 121 may select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. The address decoder 121 may decode the row address among the received address ADDR. The address decoder 121 may select at least one of the word lines of the selected memory block based on the decoded row address. The address decoder 121 may apply the operating voltage Vop supplied from the voltage generator 122 to the selected word line.

[0056] During a program operation, the address decoder 121 may apply a program voltage to a selected word line and may apply a pass voltage to unselected word lines, the level of the pass voltage being lower than the level of the program voltage. During a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line and apply a verification pass voltage to unselected word lines, the level of the verification pass voltage being higher than the level of the verification voltage.

[0057] During a read operation, the address decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage to unselected word lines, the level of the read pass voltage being higher than that of the read voltage.

[0058] According to one embodiment of the present disclosure, the erase operation of the memory device 100 can be performed based on the unit of the memory block. During the erase operation, the address ADDR input to the memory device 100 may include a block address. The address decoder 121 may decode the block address and select a single memory block based on the decoded block address. During the erase operation, the address decoder 121 may apply a ground voltage to a word line coupled to the selected memory block.

[0059] According to an embodiment of the present disclosure, the address decoder 121 may decode the column address in the received address ADDR. The decoded column address may be transmitted to the read / write circuit 123. In an embodiment, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0060] The voltage generator 122 may generate a plurality of operating voltages Vop by using an external supply voltage supplied to the memory device 100. The voltage generator 122 may operate based on the control logic 130.

[0061] In one embodiment, the voltage generator 122 may generate an internal supply voltage by regulating an external supply voltage. The internal supply voltage generated by the voltage generator 122 may be used as an operating voltage for the memory device 100.

[0062] In one embodiment, the voltage generator 122 can generate a plurality of operating voltages Vop by using an external supply voltage or an internal supply voltage. The voltage generator 122 can generate various voltages required by the memory device 100. For example, the voltage generator 122 can generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselect read voltages.

[0063] The voltage generator 122 may include a plurality of pumping capacitors for receiving an internal supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and may generate the plurality of operating voltages Vop by selectively enabling the plurality of pumping capacitors based on the control logic 130 .

[0064] The generated operating voltage Vop may be supplied to the memory cell array 110 through the address decoder 121 .

[0065] The read / write circuit 123 may include first to m-th page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm may be coupled to the memory cell array 110 through first to m-th bit lines BL1 to BLm, respectively. The first to m-th page buffers PB1 to PBm may operate based on the control logic 130 .

[0066] The first to mth page buffers PB1 to PBm may perform data communication with the data input / output circuit 124. During a program operation, the first to mth page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0067] During a programming operation, when a programming pulse is applied to a selected word line, the first page buffer PB1 to the mth page buffer PBm can transmit data DATA to be stored to the selected memory cell through the bit lines BL1 to BLm, and the data DATA is received through the data input / output circuit 124. The memory cells in the selected page can be programmed based on the received data DATA. The memory cells coupled to the bit lines to which a programming permission voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells coupled to the bit lines to which a programming inhibition voltage (e.g., a supply voltage) is applied can be maintained. During a programming verification operation, the first page buffer PB1 to the mth page buffer PBm can read the data DATA stored in the selected memory cell from the selected memory cell through the bit lines BL1 to BLm.

[0068] During a read operation, the read and write circuit 123 may read data DATA from memory cells in a selected page through the bit lines BL1 to BLm, and may store the read data DATA in the first to mth page buffers PB1 to PBm.

[0069] During an erase operation, the read and write circuit 123 may allow the bit lines BL1 to BLm to float. In one embodiment, the read and write circuit 123 may include a column selection circuit.

[0070] The data input / output circuit 124 may be coupled to the first to m-th page buffers PB1 to PBm through the data lines DL The data input / output circuit 124 may operate based on the control logic 130 .

[0071] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. During a program operation, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 may output data DATA received from the first page buffer PB1 to the mth page buffer PBm included in the read / write circuit 123 to the external controller.

[0072] During a read operation or a verification operation, the sensing circuit 125 can generate a reference current based on an enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a fail signal to the control logic 130 by comparing the sensing voltage VPB received from the read-write circuit 123 with a reference voltage generated by the reference current.

[0073] The control logic 130 may be coupled to the address decoder 121, the voltage generator 122, the read / write circuit 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may control the overall operation of the memory device 100. The control logic 130 may operate based on a command CMD transmitted from an external device.

[0074] The control circuit 130 may control the peripheral circuit 120 by generating various types of signals based on the command CMD and the address ADDR. For example, the control logic 130 may generate an operation signal OPSIG, an address ADDR, a read / write circuit control signal PBSIGNALS, and an enable bit VRYBIT based on the command CMD and the address ADDR. The control logic 130 may output the operation signal OPSIG to the voltage generator 122, may output the address ADDR to the address decoder 121, may output the read / write circuit control signal PBSIGNALS to the read / write circuit 123, and may output the enable bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 may determine whether the verification operation passes or fails based on the pass signal PASS or the fail signal FAIL output from the sensing circuit 125.

[0075] In one embodiment, the control logic 130 may include a program progress information storage device 131 , a reference progress information storage device 132 , and a program operation controller 133 .

[0076] The program progress information storage device 131 may store information about the degree of progress of the program operation performed by the memory device 100. In one embodiment, as will be described later, Fig.10 As described above, the progress of the programming operation can be a programming loop count for the programming operation. Figure 8 As mentioned above, the progress degree of the programming operation may be a program verification level for the programming operation.

[0077] The reference progress information storage device 132 may store information about a reference progress degree (ie, a reference progress degree) of a programming operation. Fig.10 As described above, the reference progress level may be a reference programming cycle count. Figure 8 As mentioned above, the reference progress level may be a reference program verify level.

[0078] The program operation controller 133 may control the peripheral circuit 120 so that a program operation and a program verification operation are performed on a cell string selected from among a plurality of cell strings included in the memory cell array 110 .

[0079] The program operation controller 133 may control the increase of the channel voltage of at least one unselected cell string among the plurality of cell strings during the program verification operation. The program operation controller 133 may determine whether the progress degree of the program operation is equal to or higher than the reference progress degree based on the information about the progress degree of the program operation and the information about the reference progress degree. The program operation controller 133 may control the increase of the channel voltage of at least one unselected cell string based on the comparison result between the progress degree of the program operation and the reference progress degree.

[0080] For example, when the progress degree of the programming operation is lower than the reference progress degree, the programming operation controller 133 may increase the channel voltage of the unselected cell string when performing the programming verification operation on the selected cell string. When the channel voltage of the unselected cell string is increased, the difference between the voltage of the word line and the voltage of the channel may be reduced. When the difference between the voltage of the word line and the voltage of the channel is reduced, the capacitance component between the word line and the channel may be reduced, and thus the time required for the programming verification operation may be shortened.

[0081] For example, when the degree of progress of the programming operation is equal to or higher than the reference degree of progress, the programming operation controller 133 can mitigate the increase of the channel voltage of the unselected cell string when performing the program verification operation on the selected cell string. The channel voltage of the unselected cell string that appears when the degree of progress of the programming operation is equal to or higher than the reference degree of progress can be increased to be higher than the channel voltage of the unselected cell string that appears when the degree of progress of the programming operation is lower than the reference degree of progress. In this case, due to the highly increased channel voltage, the memory cell to which the program verification voltage or the program pass voltage is applied can be slightly erased. Therefore, when the degree of progress of the programming operation is equal to or higher than the reference degree of progress, the increase of the channel voltage of the unselected cell string can be mitigated, and thus the phenomenon of slightly erasing the memory cell can be improved.

[0082] Figure 3 It is shown Figure 2 Diagram of a memory cell array.

[0083] refer to Figure 3 , the first to z-th memory blocks BLK1 to BLKz may be commonly coupled to the first to m-th bit lines BL1 to BLm. Figure 3 , for ease of description, elements included in the first memory block BLK1 among the plurality of memory blocks BLK1 to BLKz are shown, and illustration of elements included in each of the remaining memory blocks BLK2 to BLKz is omitted. It will be understood that each of the remaining memory blocks BLK2 to BLKz has the same configuration as the first memory block BLK1.

[0084] The memory block BLK1 may include a plurality of cell strings CS1_1 to CS1_m (where m is a positive integer). The first to m-th cell strings CS1_1 to CS1_m may be coupled to the first to m-th bit lines BL1 to BLm, respectively. Each of the first to m-th cell strings CS1_1 to CS1_m may include a drain select transistor DST, a plurality of memory cells MC1 to MCn (where n is a positive integer) coupled in series, and a source select transistor SST.

[0085] A gate terminal of a drain select transistor DST included in each of the first to m-th cell strings CS1_1 to CS1_m may be coupled to a drain select line DSL1. Gate terminals of first to n-th memory cells MC1 to MCn included in each of the first to m-th cell strings CS1_1 to CS1_m may be coupled to first to n-th word lines WL1 to WLn, respectively. A gate terminal of a source select transistor SST included in each of the first to m-th cell strings CS1_1 to CS1_m may be coupled to a source select line SSL1.

[0086] For ease of description, the structure of each cell string will be described based on the first cell string CS1_1 among the plurality of cell strings CS1_1 to CS1_m. However, it will be understood that each of the remaining cell strings CS1_2 to CS1_m is configured in the same manner as the first cell string CS1_1.

[0087] A drain terminal of a drain select transistor DST included in the first cell string CS1_1 may be coupled to a first bit line BL1. A source terminal of a drain select transistor DST included in the first cell string CS1_1 may be coupled to a drain terminal of a first memory cell MC1 included in the first cell string CS1_1. The first memory cell MC1 to the nth memory cell MCn may be coupled in series. A drain terminal of a source select transistor SST included in the first cell string CS1_1 may be coupled to a source terminal of an nth memory cell MCn included in the first cell string CS1_1. A source terminal of a source select transistor SST included in the first cell string CS1_1 may be coupled to a common source line CSL. In one embodiment, the common source line CSL may be commonly coupled to the first memory block BLK1 to the zth memory block BLKz.

[0088] The drain selection line DSL1, the first to n-th word lines WL1 to WLn, and the source selection line SSL1 may be included in Figure 2The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 may be controlled by the address decoder 121. The common source line CSL may be controlled by the control logic 130. The first to mth bit lines BL1 to BLm may be controlled by the read / write circuit 123.

[0089] Figure 4 It is shown Figure 2 A diagram of one embodiment of a memory cell array.

[0090] refer to Figure 4 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional (3D) structure. Each memory block may include a plurality of memory cells stacked on a substrate. Such memory cells may be arranged in a positive X (+X) direction, a positive Y (+Y) direction, and a positive Z (+Z) direction. The structure of each memory block will be described below with reference to Figure 5 and Figure 6 Detailed description.

[0091] Figure 5 It is shown Figure 4 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0092] refer to Figure 5 , the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in a row direction (ie, a positive (+) X direction). Figure 5 , two cell strings are shown to be arranged in the column direction (ie, the positive (+) Y direction). However, this illustration is made for convenience of description, and it will be understood that three or more cell strings may be arranged in the column direction.

[0093] In one embodiment, a single memory block may include a plurality of sub-blocks. A single sub-block may include cell strings arranged in a single column in a "U" shape.

[0094] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0095] The selection transistors SST and DST and the memory cells MC1 to MCn may have similar structures. In one embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a column for providing a channel layer may be provided in each cell string. In one embodiment, a column for providing at least one of a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0096] The source selection transistor SST of each cell string may be coupled between the common source line CSL and the memory cells MC1 to MCp.

[0097] In one embodiment, source selection transistors of cell strings arranged in the same row may be coupled to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows may be coupled to different source selection lines. Figure 5 , source selection transistors of cell strings CS11 to CS1m in a first row may be coupled to a first source selection line SSL1. Source selection transistors of cell strings CS21 to CS2m in a second row may be coupled to a second source selection line SSL2.

[0098] In one embodiment, source select transistors of cell strings CS11 to CS1m and CS21 to CS2m may be commonly coupled to a single source select line.

[0099] The first to nth memory cells MC1 to MCn in each cell string may be coupled between a source select transistor SST and a drain select transistor DST.

[0100] The first to nth memory cells MC1 to MCn may be divided into: the first to pth memory cells MC1, and the p+1th to nth memory cells MCp+1. The first to pth memory cells MCp may be sequentially arranged in a direction opposite to the positive (+) Z direction, and may be coupled in series between the source selection transistor SST and the pipe transistor PT. The p+1th to nth memory cells MCp+1 may be sequentially arranged in the +Z direction, and may be coupled in series between the pipe transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 and the p+1th to nth memory cells MCn may be coupled to each other through the pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string may be coupled to the first to nth word lines WL1 to WLn, respectively.

[0101] A gate of the pipe transistor PT of each cell string may be coupled to the pipe line PL.

[0102] The drain selection transistor DST of each cell string may be coupled between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings in the row direction may be coupled to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m in the first row may be coupled to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m in the second row may be coupled to the second drain selection line DSL2.

[0103] The cell strings arranged in the column direction may be coupled to the bit lines extending in the column direction. Figure 5 , the cell strings CS11 and CS21 in the first column may be coupled to the first bit line BL1. The cell strings CS1m and CS2m in the mth column may be coupled to the mth bit line BLm.

[0104] Memory cells coupled to the same word line in the cell strings arranged in the row direction may form a single page. For example, memory cells coupled to the first word line WL1 among the cell strings CS11 to CS1m in the first row may form a single page. Memory cells coupled to the first word line WL1 among the cell strings CS21 to CS2m in the second row may form an additional page. The cell strings arranged in the direction of a single row may be selected by selecting any one of the drain selection lines DSL1 and DSL2. By selecting any one of the word lines WL1 to WLn, a single page may be selected from the selected cell string.

[0105] In one embodiment, instead of the first to m-th bit lines BL1 to BLm, even bit lines and odd bit lines may be provided. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to corresponding even bit lines. Odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to corresponding odd bit lines.

[0106] In one embodiment, one or more of the first to nth memory cells MC1 to MCn may be used as dummy memory cells. For example, one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKa may be improved, while the size of the memory block BLKa may increase. As fewer memory cells are provided, the size of the memory block BLKa may be reduced, while the reliability of the operation of the memory block BLKa may deteriorate.

[0107] In order to efficiently control one or more dummy memory cells, each of the dummy memory cells may have a desired threshold voltage. Before or after performing an erase operation on the memory block BLKa, a programming operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation has been performed, the threshold voltage of the dummy memory cell may control the voltage applied to the dummy word line coupled to the corresponding dummy memory cell, and therefore, the dummy memory cell may have a desired threshold voltage.

[0108] Figure 6 It is shown Figure 4 A circuit diagram of an example of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0109] refer to Figure 6 , the memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' may extend in the positive (+) Z direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0110] In one embodiment, a single memory block may include a plurality of sub-blocks. A single sub-block may include cell strings arranged in a single column in an "I" shape.

[0111] The source select transistor SST of each cell string may be coupled between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row may be coupled to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row may be coupled to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row may be coupled to the second source select line SSL2. In one embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be coupled together to a single source select line.

[0112] First to nth memory cells MC1 to MCn in each cell string may be coupled in series between source select transistors SST and drain select transistors DST. Gates of first to nth memory cells MC1 to MCn may be coupled to first to nth word lines WL1 to WLn, respectively.

[0113] The drain selection transistor DST of each cell string may be coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the cell strings arranged in the row direction may be coupled to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11' to CS1m' in the first row may be coupled to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21' to CS2m' in the second row may be coupled to the second drain selection line DSL2.

[0114] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 6 The memory block BLKb has Figure 5 The equivalent circuit of the memory block BLKa is similar.

[0115] In one embodiment, instead of the first to m-th bit lines BL1 to BLm, even bit lines and odd bit lines may be provided. In addition, even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be coupled to corresponding even bit lines. Odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be coupled to corresponding odd bit lines.

[0116] In one embodiment, one or more of the first memory cell MC1 to the nth memory cell MCn may be used as a dummy memory cell. For example, one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. As the number of dummy memory cells provided increases, the reliability of the operation of the memory block BLKb may be improved, and the size of the memory block BLKb may increase. As the number of dummy memory cells provided decreases, the size of the memory block BLKb may be reduced, and the reliability of the operation of the memory block BLKb may deteriorate.

[0117] In order to efficiently control one or more dummy memory cells, the corresponding dummy memory cells may have a desired threshold voltage. Before or after the erase operation is performed on the memory block BLKb, a programming operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after the programming operation has been performed, the dummy memory cells may have a desired threshold voltage by controlling the voltage to be applied to the dummy word line coupled to the corresponding dummy memory cell.

[0118] Figure 7 It is shown Figure 2 A diagram of a programming operation of a memory device.

[0119] exist Figure 7 In the present invention, for ease of description, it is assumed that the memory cell is a multi-level cell (MLC) storing 2-bit data. However, the scope of the present disclosure is not limited thereto, and the memory cell may be a triple-level cell (TLC) storing 3-bit data or a quad-level cell (QLC) storing 4-bit data. The number of data bits stored in each memory cell may be one or more.

[0120] The memory device may perform a program operation such that each of the selected memory cells has a threshold voltage corresponding to any one of a plurality of program states P1 , P2 , and P3 by performing a plurality of program loops PL1 to PLn.

[0121] Each of the program loops PL1 to PLn may include: a program voltage applying step (PGM step) of applying a program voltage to a selected word line coupled to a selected memory cell; and a verification step of determining whether the memory cell has been programmed by applying a verification voltage.

[0122] For example, when the first programming loop PL1 is performed, the first programming pulse Vpgm1 may be applied, and thereafter, the first verification voltage V_vfy1 to the third verification voltage V_vfy3 may be sequentially applied to verify the programming state of the selected memory cell. Here, the memory cell whose target programming state is the first programming state P1 may be verified by using the first verification voltage V_vfy1. The memory cell whose target programming state is the second programming state P2 may be verified by using the second verification voltage V_vfy2. And, the memory cell whose target programming state is the third programming state P3 may be verified by using the third verification voltage V_vfy3.

[0123] Memory cells that have passed verification (i.e., verification passed) via corresponding verification voltages V_vfy1 to V_vfy3 may be determined to have a target program state and may then be program-inhibited in the second programming loop PL2. In other words, from the second programming loop PL2, a program-inhibit voltage may be applied to the bit lines coupled to the memory cells that have passed verification.

[0124] In order to program memory cells other than the program-inhibited memory cells in the second programming loop PL2, a second programming pulse Vpgm2 higher by a unit voltage (step voltage) ΔVpgm than the first programming pulse Vpgm1 may be applied to the selected word line. Thereafter, a verification operation may be performed in the same manner as the verification operation in the first programming loop PL1. In one example, the term "verification passed" may indicate that a memory cell is read as an off cell by a corresponding verification voltage.

[0125] As described above, when the memory device programs a multi-level cell (MLC) storing 2 bits, the memory device may individually verify memory cells with corresponding program states as target program states by using first to third verification voltages V_vfy1 to V_vfy3 .

[0126] During a verify operation, a verify voltage may be applied to a selected word line, which is a word line coupled to a selected memory cell, and Figure 2 The page buffer may determine whether the selected memory cells have passed verification based on currents or voltages flowing through bit lines respectively coupled to the selected memory cells.

[0127] Figure 8 is a diagram illustrating the degree of progress of a programming operation according to one embodiment.

[0128] refer to Figure 8 , the horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells.

[0129] exist Figure 8 In the embodiment, the description is made assuming that the memory cell is a triple level cell (TLC), in which each memory cell stores 3 bits. The number of data bits stored in one memory cell is not limited to the present embodiment.

[0130] Each of the memory cells may be programmed to any one of an erase state E and a plurality of program states P1 to P7. A program operation may be performed while a program verification level sequentially increases from the erase state E to the highest program state P7.

[0131] The program verification level may be the level of the program state in which the program verification operation is performed. For example, when a program verification operation is currently being performed on a cell to be programmed to the first program state P1, the program verification level for the current program operation may be the first program verification level. When the program verification operation on the cell to be programmed to the first program state P1 has been completed, and a program verification operation is currently being performed on a cell to be programmed to the second program state P2, the program verification level for the current program operation may be the second program verification level. Similarly, when a program verification operation is currently being performed on a cell to be programmed to the seventh program state P7, the program verification level for the current program operation may be the seventh program verification level.

[0132] In one embodiment, the degree of progress of the programming operation may be a programming verification level. The reference degree of progress may be a reference programming verification level. The reference programming verification level may be a programming verification level set to determine whether the degree of progress of the programming operation is high or low. That is, based on the comparison result between the programming verification level and the reference programming verification level, the degree to which the programming operation has progressed may be determined. In various embodiments, the reference programming verification level may be changed based on a request from the memory controller 200.

[0133] The reference program verification level may be a reference based on which a lower program state and an upper program state are distinguished from each other. Figure 8 In the embodiment, the reference program verification level may be a fourth program verification level. The reference program verification level is not limited to this embodiment.

[0134] For example, when the program verification level is lower than the reference program verification level, the program verification level may be a program verification level corresponding to lower program states P1 to P3. For example, when the program verification level is equal to or higher than the reference program verification level, the program verification level may be a program verification level corresponding to higher program states P4 to P7.

[0135] Fig. 9 is a circuit diagram of a cell string according to one embodiment.

[0136] refer to Fig. 9, the memory device may include a first cell string ST1 and a second cell string ST2. The number of cell strings included in the memory device is not limited by this embodiment.

[0137] The first cell string ST1 may be a selected cell string SelST on which a program operation and a program verification operation are performed. The second cell string ST2 may be an unselected cell string Unsel ST.

[0138] The drain select transistor DST1 in the first cell string ST1 may be coupled to the first drain select line DSL1. The plurality of memory cells in the first cell string ST1 may be coupled to the plurality of word lines, respectively. The source select transistor SST1 of the first cell string ST1 may be coupled to the first source select line SSL1.

[0139] The drain select transistor DST2 in the second cell string ST2 may be coupled to the second drain select line DSL2. The plurality of memory cells in the second cell string ST2 may be coupled to the plurality of word lines, respectively. The source select transistor SST2 of the second cell string ST2 may be coupled to the second source select line SSL2.

[0140] The source select transistor SST1 of the first cell string ST1 and the source select transistor SST2 of the second cell string ST2 may be coupled to a common source line CSL.

[0141] When performing a program verification operation, a program verification voltage Vvfy may be applied to a word line Sel WL selected from among a plurality of word lines. A program pass voltage Vpass may be applied to an unselected word line Unsel WL among a plurality of word lines. A ground voltage may be applied to a common source line CSL.

[0142] Fig.10 It means that Fig. 9 FIG. 1 is a diagram of control of raising a channel voltage of a non-selected cell string during a program verification operation performed on a cell string of FIG.

[0143] refer to Fig.10 , PLk (where k is a natural number of 2 or more) may be a reference programming loop. The reference programming loop count k may be a programming loop count set to determine whether the degree of progress of the programming operation is high or low. PLn (where n is a natural number less than k) may be a lower programming loop. PLm (where m is a natural number equal to or greater than k) may be a higher programming loop.

[0144] During the program verification operation in the lower programming loop, the program verification voltage Vvfy can be applied to the selected word line. The program pass voltage Vpass can be applied to the unselected word line. The turn-on voltage Von can be applied to the drain selection line coupled to the drain selection transistor of the selected cell string. The turn-on voltage Von can be applied to the source selection line coupled to the source selection transistor of the selected cell string. The ground voltage can be applied to the drain selection line coupled to the drain selection transistor of the unselected cell string. The ground voltage can be applied to the source selection line coupled to the source selection transistor of the unselected cell string. In a state where both the drain selection transistor and the source selection transistor of the unselected cell string are turned off, the channel voltage of the unselected cell string can be increased due to the program pass voltage Vpass applied to the unselected word line. When the channel voltage of the unselected cell string is increased, the difference between the voltage of the word line and the voltage of the channel of the unselected cell string can be reduced, and the capacitive component between the word line and the channel can be reduced. When the capacitance component is reduced, the time required to drive the unselected cell strings can be reduced, and thus, the total time required for the entire program verification operation can be shortened.

[0145] During a program verification operation in a higher programming loop, a program verification voltage Vvfy' may be applied to a selected word line. A program pass voltage Vpass may be applied to an unselected word line. A turn-on voltage Von may be applied to a drain select line coupled to a drain select transistor of a selected cell string. A turn-on voltage Von may be applied to a source select line coupled to a source select transistor of a selected cell string. A ground voltage may be applied to a drain select line coupled to a drain select transistor of an unselected cell string. A ground voltage may be applied to a source select line coupled to a source select transistor of an unselected cell string, and then a turn-on voltage Von may be applied thereto.

[0146] In a state in which both the drain selection transistor and the source selection transistor of the unselected cell string are turned off, the channel voltage of the unselected cell string can be raised due to the programming pass voltage Vpass' applied to the unselected word line. In this case, because the pass voltage Vpass' of the higher programming cycle is higher than the pass voltage Vpass of the lower programming cycle, the amplitude by which the channel voltage is raised in the higher programming cycle can be higher than the amplitude by which the channel voltage is raised in the lower programming cycle. Therefore, due to the excessively raised channel voltage, the memory cell to which the programming verification voltage Vvfy' is applied can be slightly erased. Therefore, after the channel voltage of the unselected cell string has been raised by turning off the drain selection transistor, the excessively raised channel voltage can be reduced to a suitable level by turning on the drain selection transistor, and the phenomenon of slightly erasing the memory cell can be improved.

[0147] Fig.11is a circuit diagram of a cell string according to one embodiment.

[0148] refer to Fig.11 , the memory device may include first to fourth cell strings ST1 to ST4. The number of cell strings included in the memory device is not limited to the present embodiment.

[0149] The first cell string ST1 may be a selected cell string SelST on which a program operation and a program verification operation are performed. The second cell string ST2 may be a shared cell string Shared ST. The shared cell string may be a cell string that shares a source selection line with the selected cell string. The third cell string ST3 and the fourth cell string ST4 may be unselected cell strings Unsel ST.

[0150] The drain select transistor DST1 of the first cell string ST1 may be coupled to the first drain select line DSL1. The plurality of memory cells of the first cell string ST1 may be coupled to the plurality of word lines, respectively. The source select transistor SST1 of the first cell string ST1 may be coupled to the first source select line SSL1.

[0151] The drain select transistor DST2 of the second cell string ST2 may be coupled to the second drain select line DSL2. The plurality of memory cells of the second cell string ST2 may be coupled to the plurality of word lines, respectively. The source select transistor SST2 of the second cell string ST2 may be coupled to the first source select line SSL1.

[0152] The drain selection transistor DST3 of the third cell string ST3 may be coupled to the third drain selection line DSL3. The plurality of memory cells of the third cell string ST3 may be coupled to the plurality of word lines, respectively. The source selection transistor SST3 of the third cell string ST3 may be coupled to the second source selection line SSL2.

[0153] The drain select transistor DST4 of the fourth cell string ST4 may be coupled to the fourth drain select line DSL4. The plurality of memory cells of the fourth cell string ST4 may be coupled to the plurality of word lines, respectively. The source select transistor SST4 of the fourth cell string ST4 may be coupled to the second source select line SSL2.

[0154] Respective source selection transistors SST1 to SST4 of the first to fourth cell strings ST1 to ST4 may be coupled to a common source line CSL.

[0155] When performing a program verification operation, a program verification voltage Vvfy may be applied to a word line selected from among a plurality of word lines. A program pass voltage Vpass may be applied to unselected word lines among the plurality of word lines. A ground voltage may be applied to the common source line CSL.

[0156] Fig.12 It means that Fig.11 FIG. 1 is a diagram of control of raising a channel voltage of a non-selected cell string during a program verification operation performed on a cell string of FIG.

[0157] refer to Fig.12 , can be used with Fig.10 The operations of the selected cell string and the unselected cell string are described in a manner similar to that of FIG.

[0158] During the program verification operation in all programming loops, a ground voltage may be applied to the drain selection line coupled to the drain selection transistor of the shared cell string. A turn-on voltage Von may be applied to the source selection line coupled to the source selection transistor of the shared cell string. Because the shared cell string is a cell string on which the program verification operation is not performed, the drain selection transistor of the shared cell string may be turned off during the program verification operation, similar to the unselected cell string. However, because the shared cell string shares the source selection line with the selected cell string, the source selection transistor of the shared cell string may be turned on during the program verification operation.

[0159] Fig.13A is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0160] refer to Fig.13A , a program verification operation may be performed during a period from ta1 to ta2.

[0161] During the period from ta1 to ta2 , a program verification voltage Vvfy may be applied to a selected word line.

[0162] During a period from ta1 to ta2, a first turn-on voltage Von1 may be applied to a source selection line coupled to a source selection transistor of a selected cell string. The first turn-on voltage Von1 may be a voltage that completely turns on the source selection transistor.

[0163] During a period from ta1 to ta2 , a first on voltage Von1 may be applied to a source selection line coupled to source selection transistors of unselected cell strings.

[0164] A period p1 during which the first turn-on voltage Von1 is applied to a source select line coupled to a source select transistor of an unselected cell string may be identical to a period p1 during which the first turn-on voltage Von1 is applied to a source select line coupled to a source select transistor of a selected cell string.

[0165] Fig. 13Bis a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0166] refer to Fig. 13B , a program verification operation may be performed during a period from tb1 to tb3.

[0167] During the period from tb1 to tb3 , a program verification voltage Vvfy may be applied to a selected word line.

[0168] During the period from tb1 to tb3, a first turn-on voltage Von1 may be applied to a source selection line coupled to a source selection transistor of a selected cell string. The first turn-on voltage Von1 may be a voltage that completely turns on the source selection transistor.

[0169] During the period from tb1 to tb2, a ground voltage may be applied to a source selection line coupled to a source selection transistor of an unselected cell string. During the period from tb2 to tb3, a first on-voltage Von1 may be applied to a source selection line coupled to a source selection transistor of an unselected cell string. The time point at which the first on-voltage Von1 is applied to a source selection line coupled to a source selection transistor of an unselected cell string is not limited to the present embodiment.

[0170] A period p2 during which the first turn-on voltage Von1 is applied to a source select line coupled to a source select transistor of an unselected cell string may be shorter than a period p1 during which the first turn-on voltage Von1 is applied to a source select line coupled to a source select transistor of a selected cell string.

[0171] Fig. 13C is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0172] refer to Fig. 13C , a program verification operation may be performed during a period from tc1 to tc2.

[0173] During the period from tc1 to tc2 , a program verification voltage Vvfy may be applied to a selected word line.

[0174] During the period from tc1 to tc2, a first turn-on voltage Von1 may be applied to a source selection line coupled to a source selection transistor of a selected cell string. The first turn-on voltage Von1 may be a voltage that completely turns on the source selection transistor.

[0175] During the period from tc1 to tc2, a second on-voltage Von2 may be applied to a source select line coupled to a source select transistor of an unselected cell string. The second on-voltage Von2 may be a voltage that slightly turns on the source select transistor. The second on-voltage Von2 may be lower than the first on-voltage Von1.

[0176] A period p1 during which the second turn-on voltage Von2 is applied to the source selection line coupled to the source selection transistor of the unselected cell string may be completely identical to a period p1 during which the first turn-on voltage Von1 is applied to the source selection line coupled to the source selection transistor of the selected cell string.

[0177] Fig.13D is a timing diagram illustrating voltages applied to a source select line coupled to source select transistors of an unselected cell string during a program verification operation according to one embodiment.

[0178] refer to Fig.13D , during the period from td1 to td3, a program verification voltage Vvfy may be applied to the selected word line.

[0179] During the period from td1 to td3, a first turn-on voltage Von1 may be applied to a source selection line coupled to a source selection transistor of a selected cell string. The first turn-on voltage Von1 may be a voltage that completely turns on the source selection transistor.

[0180] During the period from td1 to td2, a ground voltage may be applied to a source selection line coupled to a source selection transistor of an unselected cell string. During the period from td2 to td3, a second on-voltage Von2 may be applied to a source selection line coupled to a source selection transistor of an unselected cell string. The second on-voltage Von2 may be a voltage that slightly turns on the source selection transistor. The second on-voltage Von2 may be lower than the first on-voltage Von1. The point in time at which the second on-voltage Von2 is applied to a source selection line coupled to a source selection transistor of an unselected cell string is not limited to the present embodiment.

[0181] A period p2 during which the second turn-on voltage Von2 is applied to the source selection line coupled to the source selection transistor of the unselected cell string may be shorter than a period p1 during which the first turn-on voltage Von1 is applied to the source selection line coupled to the source selection transistor of the selected cell string.

[0182] Fig.14 is a flow chart illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0183] refer to Fig.14, in step S1401, the memory device may perform a program operation on the selected cell string.

[0184] In step S1403 , the memory device may control the increase of the channel voltage of the unselected cell strings based on a comparison result between the progress degree of the program operation and the reference progress degree during the program verification operation performed on the selected cell string.

[0185] In one embodiment, when the progress degree of the programming operation is lower than the reference progress degree, the memory device may increase the channel voltage of the unselected cell string. When the progress degree of the programming operation is equal to or higher than the reference progress degree, the memory device may increase the channel voltage of the unselected cell string, and thereafter may mitigate the increased channel voltage to a suitable level.

[0186] In one embodiment, the degree of progress of the programming operation may be a program verification level for the currently executing programming operation, and the reference degree of progress may be a reference program verification level. In other embodiments, the degree of progress of the programming operation may be a program loop count for the currently executing programming operation, and the reference degree of progress may be a reference program loop count.

[0187] Fig.15 It is shown Fig.14 Flowchart of an embodiment of the present invention.

[0188] refer to Fig.15 , in step S1501, the memory device may initiate a program operation on a selected cell string.

[0189] In step S1503, the memory device may determine whether the program loop count for the program operation is equal to or greater than the reference program loop count. When it is determined that the program loop count is equal to or greater than the reference program loop count, the process proceeds to step S1505, and when it is determined that the program loop count is less than the reference program loop count, the process proceeds to step S1509.

[0190] In step S1505, the memory device may mitigate the increase of the channel voltage of the unselected cell string during the program verification operation performed on the selected cell string. For example, after the channel voltage of the unselected cell string has been increased during the program verification operation, the memory device may mitigate the increased channel voltage to a suitable level. As a result, the phenomenon that the memory cell to which the program verification voltage is applied is slightly erased among the memory cells in the unselected cell string due to excessive increase in the channel voltage can be improved.

[0191] In step S1507, the memory device may determine whether the program operation on the selected cell string has been completed. When it is determined that the program operation has been completed, the process terminates, and when it is determined that the program operation has not been completed, the process returns to step S1503.

[0192] In step S1509, during the program verification operation performed on the selected cell string, the memory device may raise the channel voltage of the unselected cell string. As a result, the difference between the voltage of the word line coupled to the unselected cell string and the voltage of the channel of the unselected cell string may be reduced, and thus the capacitance between the word line and the channel may be reduced. When the capacitance of the unselected cell string is reduced, the time required to drive the unselected cell string may be reduced, and thus the total time required for the entire program verification operation may be shortened.

[0193] Fig.16 It is shown Fig.14 Flowchart of an embodiment of the present invention.

[0194] refer to Fig.16 , in step S1601, the memory device may initiate a program operation on a selected cell string.

[0195] In step S1603, the memory device may determine whether the program verification level for the program operation is equal to or higher than the reference program verification level. When it is determined that the program verification level is equal to or higher than the reference program verification level, the process proceeds to step S1605, and when it is determined that the program verification level is lower than the reference program verification level, the process proceeds to step S1609.

[0196] In step S1605, the memory device may mitigate the increase of the channel voltage of the unselected cell string during the program verification operation performed on the selected cell string. For example, after the channel voltage of the unselected cell string has been increased during the program verification operation, the memory device may mitigate the increased channel voltage to a suitable level. As a result, the phenomenon that the memory cell to which the program verification voltage is applied is slightly erased among the memory cells in the unselected cell string due to the excessive increase of the channel voltage can be improved.

[0197] In step S1607, the memory device may determine whether the program operation on the selected cell string has been completed. When it is determined that the program operation has been completed, the process is terminated, and when it is determined that the program operation has not been completed, the process returns to step S1603.

[0198] In step S1609, during the program verification operation performed on the selected cell string, the memory device can increase the channel voltage of the unselected cell string. As a result, the difference between the voltage of the word line coupled to the unselected cell string and the voltage of the channel of the unselected cell string can be reduced, and thus the capacitance between the word line and the channel can be reduced. When the capacitance of the unselected cell string is reduced, the time required to drive the unselected cell string can be reduced, and thus the total time required for the entire program verification operation can be shortened.

[0199] According to the present disclosure, a memory device having improved program verification operation performance and a method of operating the memory device are provided.

Claims

1. A memory device, comprising: a plurality of cell strings, each cell string comprising a drain select transistor, a source select transistor, and a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; a peripheral circuit configured to perform a program operation and a program verification operation on a cell string selected from among the plurality of cell strings; as well as a control logic configured to control the peripheral circuit to increase a channel voltage of at least one unselected cell string among the plurality of cell strings based on a comparison between a progress degree of the programming operation and a reference progress degree during the program verification operation, Wherein during the program verification operation, when the progress degree of the program operation is equal to or higher than the reference progress degree, the control logic controls the peripheral circuit to mitigate the increase of the channel voltage of the at least one unselected cell string.

2. The memory device of claim 1, wherein: The degree of progress of the programming operation is based on a programming loop count for the programming operation, and The reference progress level is a reference programming loop count.

3. The memory device of claim 1 , wherein: The degree of progress of the programming operation is based on a program verify level for the programming operation, and The reference degree of progress is a reference program verify level.

4. The memory device of claim 1, wherein: Respective source selection transistors included in the plurality of cell strings are coupled to a common source line, and During the program verification operation, a ground voltage is applied to the common source line.

5. The memory device of claim 1 , wherein during the programming verification operation, when the progress degree of the programming operation is lower than the reference progress degree, the control logic controls the peripheral circuit to apply a first turn-on voltage to a first source selection line coupled to a source selection transistor included in the selected cell string, and to apply a ground voltage to a second source selection line coupled to a source selection transistor included in the at least one unselected cell string.

6. The memory device of claim 1 , wherein during the programming verification operation, when the degree of progress of the programming operation is equal to or higher than the reference degree of progress, the control logic controls the peripheral circuit to apply a first turn-on voltage to a first source selection line coupled to a source selection transistor included in the selected cell string, and to apply a second turn-on voltage to a second source selection line coupled to a source selection transistor included in the at least one unselected cell string. The memory device of claim 6 , wherein the second turn-on voltage is lower than or equal to the first turn-on voltage. 8 . The memory device of claim 6 , wherein a period during which the second turn-on voltage is applied to the second source select line is shorter than or equal to a period during which the first turn-on voltage is applied to the first source select line.

9. A memory device comprising: a first cell string, a second cell string, a third cell string, and a fourth cell string, each cell string comprising a drain select transistor, a source select transistor, and a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; a peripheral circuit configured to perform a program operation and a program verification operation on the memory cells in the first cell string; as well as a control logic configured to control the peripheral circuit to increase the channel voltages of the third cell string and the fourth cell string based on a comparison between a progress degree of the programming operation and a reference progress degree during the program verification operation, wherein respective source selection transistors included in the first cell string and the second cell string are coupled to a first source selection line, wherein respective source selection transistors included in the third cell string and the fourth cell string are coupled to a second source selection line, and Wherein during the program verification operation, when the progress degree of the program operation is equal to or higher than the reference progress degree, the control logic controls the peripheral circuit to mitigate the increase of the channel voltage of the third cell string and the fourth cell string.

10. The memory device of claim 9, wherein: The degree of progress of the programming operation is based on a programming loop count for the programming operation, and The reference progress level is a reference programming loop count.

11. The memory device of claim 9, wherein: The degree of progress of the programming operation is based on a program verify level for the programming operation, and The reference degree of progress is a reference program verify level.

12. The memory device of claim 9, wherein: Respective source selection transistors included in the first to fourth cell strings are coupled to a common source line, and During the program verification operation, a ground voltage is applied to the common source line.

13. The memory device of claim 9, wherein during the programming verification operation, when the progress degree of the programming operation is lower than the reference progress degree, the control logic controls the peripheral circuit to apply a first turn-on voltage to the first source selection line and to apply a ground voltage to the second source selection line.

14. The memory device of claim 9, wherein during the programming verification operation, when the progress degree of the programming operation is equal to or higher than the reference progress degree, the control logic controls the peripheral circuit to apply a first turn-on voltage to the first source selection line and a second turn-on voltage to the second source selection line. 15 . The memory device of claim 14 , wherein a period during which the second turn-on voltage is applied to the second source select line is shorter than or equal to a period during which the first turn-on voltage is applied to the first source select line.

16. A method of operating a memory device, the memory device comprising a plurality of cell strings, each cell string comprising a drain select transistor, a source select transistor, and a plurality of memory cells coupled in series between the drain select transistor and the source select transistor, the method comprising: performing a program operation on a cell string selected from among the plurality of cell strings; as well as During a program verification operation performed on the selected cell string, controlling a rise in a channel voltage of at least one unselected cell string among the plurality of cell strings based on a comparison between a progress degree of the program operation and a reference progress degree, Wherein controlling the increase of the channel voltage involves: when the progress degree of the program operation is equal to or higher than the reference progress degree, mitigating the increase of the channel voltage of the at least one unselected cell string.

17. A method according to claim 16, wherein controlling the increase of the channel voltage involves: when the progress level of the programming operation is lower than the reference progress level, applying a first turn-on voltage to a first source selection line coupled to a source selection transistor included in the selected cell string, and applying a ground voltage to a second source selection line coupled to a source selection transistor included in the at least one unselected cell string.

18. A method according to claim 16, wherein controlling the increase of the channel voltage involves: when the progress degree of the programming operation is equal to or higher than the reference progress degree, applying a first turn-on voltage to a first source selection line coupled to a source selection transistor included in the selected cell string, and applying a second turn-on voltage to a second source selection line coupled to a source selection transistor included in the at least one unselected cell string, wherein the second turn-on voltage is lower than or equal to the first turn-on voltage. 19 . The method of claim 18 , wherein a period during which the second turn-on voltage is applied to the second source select line is shorter than or equal to a period during which the first turn-on voltage is applied to the first source select line.

20. The method of claim 16, wherein a result of the comparison between the degree of progress of the programming operation and the reference degree of progress is determined based on a result of a comparison between a programming verification level for the programming operation and a reference programming verification level, or is determined based on a result of a comparison between a programming loop count for the programming operation and a reference programming loop count.

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