Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor package device and a manufacturing method thereof, the semiconductor package device comprising: a circuit layer having a first surface, the circuit layer comprising conductive traces, the conductive traces being at least partially exposed at the first surface; a protective layer disposed on the first surface and contacting the conductive traces, the protective layer having a coefficient of thermal expansion less than that of the conductive traces; by disposing a protective layer having a coefficient of thermal expansion less than that of the conductive traces on one side of the conductive traces, the risk of breakage of the conductive traces is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular, to a semiconductor packaging device and a manufacturing method thereof. BACKGROUND

[0002] Fan Out Chip on Substrate (FOCoS) products have thermal stress generated in the process of thermal cycling due to the difference in the thermal expansion coefficients of various materials. The stress borne by the conductive traces located between two chips is affected by the difference between the thermal expansion coefficients of the material itself and the surrounding material, i.e., the thermal expansion coefficient of the dielectric material surrounding the conductive traces is greater than the thermal expansion coefficient of the copper of the conductive traces. In the process of thermal cycling, the conductive traces are prone to rupture due to the tensile strain or elongation they bear. SUMMARY

[0003] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0004] a circuit layer having a first surface, the circuit layer comprising a conductive trace, the conductive trace being at least partially exposed on the first surface;

[0005] a protective layer disposed on the first surface and in contact with the conductive trace, the protective layer having a thermal expansion coefficient less than that of the conductive trace.

[0006] In some optional embodiments, the device further comprises:

[0007] a first chip and a second chip disposed on the first surface, the first chip being electrically connected to the second chip via the conductive trace.

[0008] In some optional embodiments, the first chip is disposed on the first surface with its active surface or non-active surface facing the first surface.

[0009] In some optional embodiments, the second chip is disposed on the first surface with its active surface or non-active surface facing the first surface.

[0010] In some optional embodiments, the circuit layer further comprises a dielectric layer, and the conductive trace is disposed on the dielectric layer;

[0011] The contact area between the protective layer and the conductive trace is greater than the contact area between the dielectric layer and the conductive trace.

[0012] In some optional embodiments, the first surface is provided with a groove, and the conductive trace is at least partially disposed at the bottom of the groove and exposed on the first surface via the groove;

[0013] The protective layer is disposed at least partially in the groove.

[0014] In some optional embodiments, the protective layer covers the conductive trace.

[0015] In some optional embodiments, the protective layer comprises underfill glue.

[0016] In some optional embodiments, the device further comprises:

[0017] A packaging material is disposed on the first surface and covers the first chip and the second chip.

[0018] In some optional embodiments, the non-active surface of the first chip and / or the non-active surface of the second chip is substantially coplanar with an upper surface of the packaging material.

[0019] In some optional embodiments, the circuit layer has a second surface opposite to the first surface; the device further comprises:

[0020] An electrical connector is disposed on the second surface.

[0021] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0022] Providing a circuit layer having a first surface, the circuit layer embedding a conductive trace;

[0023] Removing at least part of the circuit layer through the first surface to expose the conductive trace at least partially on the first surface;

[0024] Providing a protective layer on the first surface to contact the conductive trace, the protective layer having a thermal expansion coefficient smaller than that of the conductive trace.

[0025] In the semiconductor packaging device and the method for manufacturing the same provided by the present disclosure, the semiconductor packaging device comprises: a circuit layer having a first surface, the circuit layer embedding a conductive trace, the conductive trace being exposed at least partially on the first surface; and a protective layer disposed on the first surface and contacting the conductive trace, the protective layer having a thermal expansion coefficient smaller than that of the conductive trace. In this way, one side of the conductive trace is in contact with the protective layer having a thermal expansion coefficient smaller than that of the conductive trace itself. In a thermal process, the tension on the side of the conductive trace in the circuit layer can be transferred to the side of the protective layer, thereby reducing the risk of rupture of the conductive trace due to deformation caused by the tension of the circuit layer in the thermal process. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings:

[0027] FIG. 1A is a longitudinal cross-sectional structure schematic diagram of one embodiment of a semiconductor package device according to the present disclosure;

[0028] FIG. 1B is a longitudinal cross-sectional structure schematic diagram of one embodiment of a semiconductor package device according to the present disclosure; FIG. 1A is a partial enlarged schematic diagram of the dashed line part in

[0029] FIG. 1C-1E is a longitudinal cross-sectional structure schematic diagram of one embodiment of a semiconductor package device according to the present disclosure; FIG. 1A is a partial longitudinal cross-sectional enlarged schematic diagram of the dashed line part in FIG. 1A corresponding to the direction perpendicular to the longitudinal cross-section in different embodiments;

[0030] FIG. 2A-2G is a longitudinal cross-sectional structure schematic diagram of different embodiments of a semiconductor package device according to the present disclosure;

[0031] FIG. 3A-3I is a longitudinal cross-sectional structure schematic diagram of a semiconductor package device manufactured at various stages according to one embodiment of the present disclosure.

[0032] Symbol explanation:

[0033] 11 - circuit layer; 11a - first surface; 11b - second surface; 110 - sub-circuit layer; 12 - protective layer; 13 - first chip; 14 - second chip; 111 - conductive trace; 112 - dielectric layer; 1121 - protrusion; 113 - groove; 1131 - groove extension; 15 - packaging material; 16 - electrical connection; 17 - wire; 18 - substrate; 181 - substrate conductive trace; 182 - substrate protective layer; 21 - first carrier plate; 22 - second carrier plate. DETAILED DESCRIPTION

[0034] The specific embodiments of the present disclosure will be described below with reference to the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the content recorded in the present specification. It can be understood that the specific embodiments described herein are only used to explain the related invention, and not to limit the invention. In addition, only the parts related to the invention are shown in the drawings for ease of description.

[0035] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content described in the specification for understanding and reading by those skilled in the art, and do not serve to define the limiting conditions for the implementation of the present disclosure, so they do not have technical substantive significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the present disclosure, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and not to limit the scope of the implementation of the present disclosure. The change or adjustment of the relative relationship without substantially changing the technical content should also be considered as the implementation scope of the present disclosure.

[0036] It should also be noted that the longitudinal cross-section of the embodiments of the present disclosure can correspond to the front view direction cross-section, the transverse cross-section can correspond to the right view direction cross-section, and the horizontal cross-section can correspond to the upper view direction cross-section.

[0037] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0038] Reference FIG. 1A and FIG. 1B , FIG. 1A is a longitudinal cross-sectional structure schematic diagram of one embodiment of the semiconductor packaging device of the present disclosure, FIG. 1B is FIG. 1A a local enlarged schematic diagram of the dashed portion in

[0039] As shown in FIG. 1A and FIG. 1B , the semiconductor packaging device 100A can include a circuit layer 11 and a protective layer 12. Wherein:

[0040] The circuit layer 11 has a first surface 11a, and the circuit layer 11 includes a conductive trace 111, which is at least partially exposed at the first surface 11a.

[0041] The circuit layer 11 can be a circuit layer composed of a conductive material and a dielectric material. Here, the dielectric material can include an organic material and / or an inorganic material, where the organic material can be, for example, polyamide (PA), polyimide (PI), poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, a semi-cured resin or prepreg), ABF (Ajinomoto Build-up Film), etc., and the inorganic material can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

[0042] The conductive trace 111 can be at least part of the conductive material that composes the circuit layer 11.

[0043] The protective layer 12 is disposed on the first surface 11a and contacts the conductive trace 111, and the thermal expansion coefficient of the protective layer 12 is less than the thermal expansion coefficient of the conductive trace 111.

[0044] The present disclosure does not make a specific limitation on the material of the protective layer 12, and the thermal expansion coefficient of the protective layer 12 is only required to be less than the thermal expansion coefficient of the conductive trace 111. For example, the protective layer 12 can include an underfill adhesive, where the underfill adhesive can be, for example, an epoxy resin.

[0045] One side of the conductive trace 111 contacts the dielectric material of the circuit layer 11, and the other side at least partially contacts the protective layer 12, and the thermal expansion coefficient of the protective layer 12 is less than the thermal expansion coefficient of the conductive trace 111. Therefore, in a thermal process, the tension generated by the thermal expansion of the dielectric material of the circuit layer 11 is transmitted to the protective layer 12 through the conductive trace 111, thereby avoiding the concentration of tensile stress on the conductive trace 111 and reducing the risk of breakage of the conductive trace 111.

[0046] In some optional embodiments, the protective layer 12 covers the conductive trace 111.

[0047] In some optional embodiments, as shown in FIG. 1B, the device 100B further includes: FIG. 1A

[0048] The first chip 13 and the second chip 14 are disposed on the first surface 11a, and the first chip 13 is electrically connected to the second chip 14 through the conductive trace 111. ​

[0049] This disclosure does not specifically limit the types of the first chip 13 and the second chip 14. The first chip 13 and the second chip 14 may include, for example, a die, an ASIC (Application Specific Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip. Here, the first chip 13 and the second chip 14 may be the same chip or different chips.

[0050] In some alternative implementations, such as FIG. 1A and 1B As shown, the first chip 13 has its active surface facing the first surface 11a, and the second chip 14 has its active surface facing the first surface 11a.

[0051] In some alternative implementations, such as FIG. 1A and 1B As shown, the circuit layer 11 also includes a dielectric layer 112, and conductive traces 111 are disposed on the dielectric layer 112.

[0052] FIG. 1C for FIG. 1A The middle dashed line corresponds to the perpendicular to FIG. 1A A partially enlarged schematic diagram of the longitudinal section, showing its direction. FIG. 1C As shown, the contact area between the protective layer 12 and the conductive trace 111 is greater than the contact area between the dielectric layer 112 and the conductive trace 111.

[0053] In some alternative implementations, such as FIG. 1A and FIG. 1B As shown, the first surface 11a is provided with a groove 113, and the conductive trace 111 is at least partially provided at the bottom of the groove 113 and exposed on the first surface 11a through the groove 113.

[0054] Here, the groove 113 can be formed by removing the dielectric material covering the conductive trace 111.

[0055] The protective layer 12 is at least partially disposed in the groove 113.

[0056] FIG. 1D for FIG. 1A The middle dashed line corresponds to the perpendicular to FIG. 1A The orientation of the longitudinal section is shown in a partial enlarged schematic diagram of the longitudinal section in some alternative embodiments, such as... FIG. 1D As shown, in some optional embodiments, there are multiple corresponding conductive traces 111 and grooves 113, and a protrusion 1121 is provided between two adjacent grooves 113, which can increase the contact area between the protective layer 12 and the groove 113 and improve the adhesion.

[0057] FIG. 1E For FIG. 1A The middle dotted line portion corresponds to the direction perpendicular to FIG. 1A The longitudinal section in some optional embodiments of the partial longitudinal section enlarged schematic view, as FIG. 1E As shown in some optional embodiments, the groove 113 at least partially extends to the circuit layer 11 through the plane where the conductive trace 111 is located to form a groove extension 1131, which can increase the contact area between the protective layer 12 and the groove 113 and improve the adhesion.

[0058] In some optional embodiments, as FIG. 1A shown, the semiconductor package device 100A further includes:

[0059] The encapsulation material 15 is disposed on the first surface 11a and covers the first chip 13 and the second chip 14.

[0060] The encapsulation material 15 can be formed of various molding compounds. For example, the molding compound can include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0061] In some optional embodiments, the non-active surface of the first chip 13 and / or the non-active surface of the second chip 14 is substantially coplanar with the upper surface of the encapsulation material 15.

[0062] Here, the two surfaces being substantially coplanar can be considered as: the height difference between the two surfaces is not greater than 5 microns, not greater than 2 microns, not greater than 1 micron or not greater than 0.5 microns.

[0063] In some optional embodiments, as FIG. 1A shown, the circuit layer 11 has a second surface 11b opposite to the first surface 11a; the semiconductor package device 100A further includes:

[0064] The electrical connector 16 is disposed on the second surface 11b.

[0065] The electrical connection 16 can be, for example, a solder ball, a solder bump, a conductive pillar, a solder pad, or the like.

[0066] The substrate 18 has its upper surface electrically connected to the second surface lib via the electrical connection 16.

[0067] The substrate 18 can be various types of substrates, which are not specifically limited by the present disclosure. The substrate 18 can include organic and / or inorganic materials, where the organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, or semi-cured resin, prepreg), ABF (Ajinomoto Build-up Film), or the like, and the inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, or the like.

[0068] The substrate 18 can also be, for example, a printed circuit board such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate, or the like.

[0069] The substrate 18 can also include interconnection structures such as conductive traces, conductive vias, or the like. Here, the conductive vias can be through-holes, buried holes, or blind holes, and the through-holes, buried holes, or blind holes can be filled with a conductive material such as a metal or a metal alloy, where the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

[0070] The structure of the conductive traces 111 of the circuit layer 11 and the protective layer 12 shown in FIG. 1A can be applied to both the circuit layer and the substrate. Referring to FIG. 2A , FIG. 2A The semiconductor package device 200A shown in FIG. 1A is similar to the semiconductor package device 100A shown in FIG. 2B , except that the substrate 18 is provided with substrate conductive traces 181 at the dashed line locations, and the substrate 18 is provided with a substrate protective layer 182 on the conductive traces.

[0071] Continuing to refer to FIG. 2B ,FIG. 1A The semiconductor package device 200B shown is similar to the semiconductor package device 100A shown in FIG. 2C , except that the semiconductor package device 200B does not include the encapsulant 15.

[0072] With reference back to FIG. 2C , FIG. 1A The semiconductor package device 200C shown is similar to the semiconductor package device 100A shown in FIG. 2D , except that the encapsulant 15 is partially disposed between the first chip 13 and the circuit layer 11 and between the second chip 14 and the circuit layer 11, and the protective layer 12 does not contact the first chip 13 and the second chip 14.

[0073] With reference back to FIG. 2D , FIG. 2C The semiconductor package device 200D shown is similar to the semiconductor package device 200C shown in FIG. 2E , except that the encapsulant 15 covers the upper surface of the substrate 18, and the encapsulant 15 is partially disposed between the substrate 18 and the circuit layer 11.

[0074] With reference back to FIG. 2E , FIG. 1A The semiconductor package device 200E shown is similar to the semiconductor package device 100A shown in FIG. 2F , except that the protective layer 12 is partially disposed between the first chip 13 and the second chip 14.

[0075] With reference back to FIG. 2F , FIG. 1A The semiconductor package device 200F shown is similar to the semiconductor package device 100A shown in FIG. 2G , except that the protective layer 12 is partially disposed between the first chip 13 and the circuit layer 11, and the encapsulant 15 is partially disposed between the second chip 14 and the circuit layer 11.

[0076] With reference back to FIG. 2G , FIG. 1A The semiconductor package device 200G shown is similar to the semiconductor package device 100A shown in FIG. 3A to FIG. 3I , except that the first chip 13 is disposed with its active surface facing the first surface 11a, and the second chip 14 is disposed with its non-active surface facing the first surface 11a, and the active surface of the second chip 14 is electrically connected to the circuit layer 11 by the wire 17.

[0077] In some alternative embodiments, the first chip 13 is disposed with its non-active surface facing the first surface 11a, and the second chip 14 is disposed with its non-active surface facing the first surface 11a.

[0078] Reference will now be made toFIG. 3A to FIG. 3I , FIG. 3A is a longitudinal sectional structure schematic diagram of a semiconductor package device manufactured according to one embodiment of the present disclosure at various stages.

[0079] Referring to FIG. 3B , a carrier plate 21 is provided, and a sub-circuit layer 110 is disposed on the carrier plate 21, the sub-circuit layer 110 including a dielectric layer 112 and a conductive trace 111 disposed on the dielectric layer 112.

[0080] Referring to FIG. 3C , a dielectric material is disposed on the sub-circuit layer 110 to form a circuit layer 11, the circuit layer 11 having a first surface 11a facing away from the carrier plate 21.

[0081] Referring to FIG. 3D , the circuit layer 11 is provided with a groove 113 corresponding to the conductive trace 111 through the first surface 11a, and the conductive trace 111 is at least partially disposed at the bottom of the groove 113 and exposed on the first surface 11a through the groove 113.

[0082] Here, the groove 113 can be formed on the circuit layer 11 by photolithography, etching or the like.

[0083] Referring to FIG. 3E , first, a first chip 13 and a second chip 14 are provided.

[0084] Then, the first chip 13 and the second chip 14 are bonded to the circuit layer 11, respectively, so that the first chip 13 and the second chip 14 are electrically connected to the first surface 11a.

[0085] Then, a bottom filling glue is disposed between the first chip 13 and the second chip 14 and the first surface 11a to form a protective layer 12, the protective layer 12 contacting the conductive trace 111, and the protective layer 12 having a thermal expansion coefficient less than that of the conductive trace 111.

[0086] Here, the bottom filling glue can be disposed between the first chip 13 and the second chip 14 and the first surface 11a by Capillary Underfill (CUF) to form the protective layer 12.

[0087] Referring to FIG. 3F , a mold is sealed to form a packaging material 15, the packaging material 15 being disposed on the first surface 11a and covering the first chip 13 and the second chip 14.

[0088] The upper surface of the packaging material 15 is ground so that the upper surface of the first chip 13 and the upper surface of the second chip 14 are substantially coplanar with the upper surface of the packaging material 15.

[0089] Referring to FIG. 3G , a second carrier plate 22 is disposed on the upper surface of the packaging material 15.

[0090] After turning over, the first carrier plate 21 is removed.

[0091] Referring to FIG. 3H The electrical connections 16 are provided on the second surface 11b of the circuit layer 11.

[0092] Here, the electrical connections 16 can be placed on the second surface 11b using a Controlled Collapsed Chip Connection (C4) method.

[0093] After turning over, the substrate 18 is disposed under the second surface 11b, and is bonded so that the substrate 18 is electrically connected to the second surface 11b through the electrical connections 16.

[0094] On the electrical connection process, for example, Flip Chip Bonding (FCB), Thermal Compression Bonding (TCB), or similar techniques can be used.

[0095] Referring to FIG. 3I The second carrier plate 22 is removed.

[0096] Referring to ​ After turning over, the tin block is placed on top of the substrate 18.

[0097] Here, the tin block can be placed on top of the substrate 18 using a C4 method.

[0098] The method for manufacturing a semiconductor structure provided by the present disclosure can achieve similar technical effects as the aforementioned semiconductor structure, which will not be repeated here.

[0099] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not intended to be limiting. Those skilled in the art can readily devise various changes and modifications without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The drawings are not necessarily to scale. There can be differences between the technical reproduction and actual implementation in the present disclosure due to variables in the manufacturing process, etc. There can be other embodiments of the present disclosure that are not specifically described. The specification and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be appreciated that these operations can be combined, subdivided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated otherwise, the order and grouping of operations are not a limitation of the present disclosure.

Claims

1. A semiconductor packaging device, comprising: a circuit layer having a first surface, the circuit layer comprising conductive traces, the conductive traces being at least partially exposed at the first surface; a protective layer disposed on the first surface and contacting the conductive traces, the protective layer having a coefficient of thermal expansion less than that of the conductive traces; the device further comprising: a first chip and a second chip disposed on the first surface, the first chip being electrically connected to the second chip via the conductive traces; wherein the circuit layer further comprises a dielectric layer, the conductive traces being disposed on the dielectric layer; the protective layer having a contact area with the conductive traces greater than that of the dielectric layer with the conductive traces. 2.The device of claim 1, wherein: the first chip has an active side or a non-active side facing the first surface; the second chip has an active side or a non-active side facing the first surface.

3. The apparatus of claim 1, wherein, the first surface is provided with a recess, the conductive traces being at least partially disposed at the bottom of the recess and exposed at the first surface via the recess; the protective layer is at least partially disposed in the recess.

4. The apparatus of claim 1, wherein, the protective layer covers the conductive traces.

5. The apparatus of claim 1, wherein, the protective layer comprises underfill adhesive.

6. The apparatus of claim 1, wherein, the device further comprising: an encapsulant disposed on the first surface and covering the first chip and the second chip.

7. The apparatus of claim 6, wherein, the non-active side of the first chip and / or the non-active side of the second chip is substantially coplanar with an upper surface of the encapsulant.

8. The apparatus of claim 1, wherein, the circuit layer has a second surface opposite to the first surface; the device further comprising: an electrical connector disposed on the second surface.

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