Method for manufacturing structure and intermediate structure

Abstract

The method for manufacturing a structure has the following steps: a step of preparing a treatment object, wherein the treatment object includes: an etching object having an etching surface composed of a conductive group III nitride, and an etching region is arranged on the etching surface; a conductive member, which is arranged in a manner of contacting at least a portion of the surface of the conductive region of the etching object that is electrically connected to the etching region; and a mask, which is formed on the etching surface and is composed of a non-conductive material; and a step of irradiating the etching surface with light through the etching solution while the treatment object is immersed in an alkaline or acidic etching solution containing peroxydisulfate ions as an electron-accepting oxidant and the etching region and the conductive member are in contact with the etching solution, thereby etching the group III nitride constituting the etching region, wherein the edge of the etching region is defined by the edge of the mask, excluding the edge of the conductive member.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a structure and an intermediate structure. Background Art

[0002] Group III nitrides such as gallium nitride (GaN) are used as materials for manufacturing semiconductor devices such as light-emitting elements and transistors.

[0003] As an etching technique for forming various structures on group III nitrides such as GaN, photoelectrochemical (PEC) etching has been proposed (see, for example, non-patent document 1). PEC etching is a wet etching that causes less damage than general dry etching, and is preferred in terms of simplicity of apparatus compared to special dry etching that causes less damage, such as neutral particle beam etching (see, for example, non-patent document 2) and atomic layer etching (see, for example, non-patent document 3).

[0004] Prior art literature

[0005] Non-patent literature

[0006] Non-patent document 1: J.Murata et al., "Photo-electrochemical etching of free-standing GaN wafer surfaces grown by hydride vapor phase epitaxy", Electrochimica Acta 171 (2015) 89-95

[0007] Non-patent document 2: S. Samukawa, JJAP, 45 (2006) 2395.

[0008] Non-patent document 3: T. Faraz, ECS J. Solid Stat. Scie. & Technol., 4, N5023 (2015). Summary of the invention

[0009] Problem that the invention aims to solve

[0010] One object of the present invention is to provide a technique for performing good PEC etching on group III nitrides.

[0011] Solutions for solving problems

[0012] According to one embodiment of the present invention, there is provided a method for manufacturing a structure, which comprises the following steps:

[0013] A step of preparing a treatment object, the treatment object comprising: an etching object having an etching surface composed of a conductive group III nitride, an etching region being arranged on the etching surface; a conductive member provided in contact with at least a portion of a surface of a conductive region of the etching object electrically connected to the etching region; and a mask formed on the etching surface and composed of a non-conductive material; and

[0014] The process of immersing the object to be processed in an alkaline or acidic etching solution containing peroxydisulfate ions as an electron-accepting oxidant, and irradiating the surface to be etched with light through the etching solution while the etching solution is in contact with the etching region and the conductive member, thereby etching the group III nitride constituting the etching region.

[0015] The edge defining the etched region does not include the edge of the conductive member, but is constituted by the edge of the mask.

[0016] According to another aspect of the present invention, there is provided an intermediate structure comprising:

[0017] An etching object having an etching surface composed of a conductive group III nitride, wherein an etching region is arranged on the etching surface;

[0018] a conductive member provided in contact with at least a portion of a surface of a conductive region of the etching object that is electrically connected to the etched region; and

[0019] A mask is formed on the etched surface and is made of a non-conductive material.

[0020] The intermediate structure is immersed in an etchant containing peroxodisulfate ions as an electron-accepting oxidant in a state where the etched region and the conductive member are in contact with the etchant.

[0021] The edge defining the etched region does not include the edge of the conductive member, but is constituted by the edge of the mask.

[0022] Effects of the Invention

[0023] Techniques for performing good PEC etches on Group III nitrides are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 (a) is a schematic cross-sectional view illustrating an object to be processed according to the first embodiment of the present invention, Figure 1 (b) is a schematic cross-sectional view showing an example of an etching object according to the first embodiment, Figure 1(c) is a schematic diagram of a PEC etching apparatus for illustrating the PEC etching step of the first embodiment.

[0025] Figure 2 (a)~ Figure 2 (c) is a schematic cross-sectional view showing a first example of a method for forming a cathode pad.

[0026] Figure 3 (a)~ Figure 3 (c) is a schematic cross-sectional view showing a second example of the method for forming the cathode pad.

[0027] Figure 4 (a)~ Figure 4 (f) is a photograph showing the first to sixth processed objects of the experimental example of PEC etching according to the first embodiment.

[0028] Figure 5 (a) and Figure 5 (b) is a graph showing the results of PEC etching in the experimental example.

[0029] Figure 6 (a) is a schematic cross-sectional view illustrating a structure of the second embodiment, Figure 6 (b) is a schematic cross-sectional view showing an example of an etching object according to the second embodiment.

[0030] Figure 7 (a) and Figure 7 (b) are respectively a schematic cross-sectional view and a schematic plan view illustrating an object to be processed according to the second embodiment, Figure 7 (c) is a schematic diagram of a PEC etching apparatus for illustrating the PEC etching step of the second embodiment.

[0031] Figure 8 (a) and Figure 8 (b) is a schematic plan view of the object to be etched, showing an example in which cathode pads are arranged along the outer periphery of the object to be etched.

[0032] Fig. 9 This is a schematic cross-sectional view conceptually illustrating a method of providing a cathode pad on an etching object having a conductive substrate.

[0033] Fig.10 (a)~ Fig.10 (d) is a schematic cross-sectional view showing an object to be processed in a preliminary experiment.

[0034] Fig.11 This is a graph showing the results of PEC etching in a preliminary experiment.

[0035] Fig.12 (a) and Fig.12 (b) is a schematic cross-sectional view and a plan view illustrating a mode in which the cathode pad is arranged so that the edge of the cathode pad becomes the edge of the mask that defines the etching area.

[0036] Fig.13 (a) and Fig.13 (b) is a schematic cross-sectional view and a plan view illustrating a mode in which the non-conductive mask and the cathode pad are arranged so that the edge of the non-conductive mask becomes the edge of the mask defining the etching area.

[0037] Fig.14 This is a photograph showing the results of PEC etching using a Ti mask.

[0038] Fig.15 (a) is a photograph showing a processing object formed with a non-conductive mask and a cathode pad. Fig.15 (b) and Fig.15 (c) is to Fig.15 This is a photograph in which a part of the region indicated by the upper right circle in (a) is enlarged. DETAILED DESCRIPTION

[0039] <First Embodiment>

[0040] A method for manufacturing a structure according to a first embodiment of the present invention is described. The manufacturing method includes an etching step (hereinafter also referred to as a PEC etching step) of an etching object 10 (hereinafter also referred to as a wafer 10) that is a material of the structure using photoelectrochemical (PEC) etching. Hereinafter, PEC etching is referred to simply as etching.

[0041] The wafer 10 includes a substrate 11 and a group III nitride layer 12 (hereinafter also referred to as an epitaxial layer 12) formed on the substrate 11 (see Figure 1 (a)). The upper surface of the epitaxial layer 12 constitutes an etched surface 20 to be etched. The etched surface 20 is composed of a conductive group III nitride. An etched region 21 to be etched is arranged on the etched surface 20.

[0042] The object to be processed by PEC etching, that is, the object immersed in (contacting) the etching solution 201 is referred to as the processing object 100. The processing object 100 can be regarded as a structure (intermediate structure) in the intermediate stage for obtaining the final structure. The processing object 100 has at least a wafer 10, and further, as a member required for PEC etching processing, it can have a mask 50 and the like. The mask 50 is formed in the form of a pattern with an opening in the etched area 21 on the etched surface 20 of the wafer 10. That is, the mask 50 is arranged at a position to define the etched area 21.

[0043] Before describing the details of the method for manufacturing the structure of the present embodiment, first, an experiment conducted for preliminary research (hereinafter also referred to as preliminary experiment) is described. In the preliminary experiment, it is studied how the progress of PEC etching will change by changing the structure and configuration of the processing object 100. For details of the PEC etching process (see Figure 1 The details of (c)) and the mechanism of PEC etching (refer to (Chemical Formula 1) to (Chemical Formula 7)) will be described later.

[0044] Fig.10 (a)~ Fig.10 (d) is a schematic cross-sectional view showing the object 100 in the preliminary experiment. In the preliminary experiment, the object 100 was immersed in the etching solution 201 contained in the container 210, and PEC etching was performed.

[0045] As the etching solution 201, an acidic etching solution obtained by mixing a 0.1M phosphoric acid (H3PO4) aqueous solution and a 0.05M K2S2O8 aqueous solution at a ratio of 1:1 was used. Ultraviolet (UV) light 221 was irradiated on the etched surface 20 through the etching solution 201. The irradiation wavelength of the UV light 221 was set to 260nm, and the irradiation intensity (I) was set to 4mW / cm 2 The distance L (d electrolyte ) is set to 5 mm. The mask 50 is formed of silicon oxide (SiO 2 ) which is a non-conductive material.

[0046] Fig.10 (a)~ Fig.10 (d) respectively represent the conditions of the first to fourth preliminary experiments. In the first, second and fourth preliminary experiments, a gallium nitride (GaN) substrate with n-type conductivity was used as the substrate 11 of the wafer 10. In the third preliminary experiment, a semi-insulating sapphire substrate was used as the substrate 11 of the wafer 10. Here, "conductivity" means, for example, a resistivity of less than 10 5 Ωcm state, "semi-insulating" means that, for example, the resistivity is 10 5 In the first to fourth preliminary experiments, as the epitaxial layer 12 , an n-type conductive GaN layer was grown on the substrate 11 .

[0047] An etched region 21 is defined as a portion exposed in the etching solution 201 in the upper surface of the epitaxial layer 12, that is, in the etched surface 20. It is considered that the etched region 21 functions as an anode in PEC etching as described later.

[0048] It is considered that the portion of the surface of the conductive region of the object 100 that is electrically connected to the etched region 21 and that is exposed in the etching solution 201 can function as a cathode of PEC etching as described later. Hereinafter, the region that can function as a cathode of PEC etching is referred to as cathode region 40. Fig.10 (a)~ Fig.10 In (d), the cathode region 40 is shown by a thick line. Figure 1 (a) and Fig. 9 Similarly, the cathode region 40 is indicated by a thick line in FIG.

[0049] Reference Fig.10 In the first preliminary experiment, the object 100 was placed on the support member (spacer) 240 so that the bottom surface of the conductive GaN substrate 11 was exposed to the etching solution 201. In the first preliminary experiment, the side surfaces of the substrate 11 and the epitaxial layer 12 and the bottom surface of the substrate 11 constituted the cathode region 40.

[0050] Reference Fig.10 In the second preliminary experiment, the object 100 was placed on the bottom surface of the container 210 so that the bottom surface of the conductive GaN substrate 11 was not exposed in the etching solution 201 . In the second preliminary experiment, the side surfaces of the substrate 11 and the epitaxial layer 12 constituted the cathode region 40 .

[0051] Reference Fig.10 In the third preliminary experiment, the object 100 was placed on the bottom surface of the container 210 in the same manner as in the second preliminary experiment. In the third preliminary experiment, a semi-insulating sapphire substrate 11 was used. Therefore, even if the surface of the substrate 11 was exposed in the etching solution 201, it would not become the cathode region 40, and only the side surface of the epitaxial layer 12 constituted the cathode region 40.

[0052] Reference Fig.10 (d). In the fourth preliminary experiment, the object to be processed 100 is arranged on the bottom surface of the container 210 in the same manner as in the second preliminary experiment. The object to be processed 100 of the fourth preliminary experiment has a resist coating 60 in addition to the wafer 10 and the mask 50. The resist coating 60 is formed in a manner covering the side surfaces of the wafer 10, i.e., the side surfaces of the substrate 11 and the epitaxial layer 12, and the bottom surface of the wafer 10, i.e., the bottom surface of the substrate 11. It should be noted that if an alkaline etching solution 201 is used, the resist coating 60 will peel off, and therefore, an acidic etching solution 201 was used in this preliminary experiment.

[0053] In the fourth preliminary experiment, the conductive GaN substrate 11 was used similarly to the first and second preliminary experiments, but since the resist coating 60 was formed, the side surfaces of the substrate 11 and the epitaxial layer 12, and the bottom surface of the substrate 11 were not exposed in the etching solution 201. Therefore, in the fourth preliminary experiment, the cathode region 40 did not exist.

[0054] In the first, second and fourth preliminary experiments, a GaN substrate 11 with a size of 6 mm square and a thickness of 0.4 mm was used, and a GaN substrate with an n-type impurity concentration of 1×10 16 / cm 3 A GaN layer (n-GaN) with a thickness of 10 μm was used as the epitaxial layer 12. The area of ​​the cathode region 40 in each of the first, second, and fourth preliminary experiments was 0.456 cm 2 、0.096cm 2 and 0cm 2 It should be noted that here, the epitaxial layer 12 is very thin compared to the GaN substrate 11, so the area of ​​the cathode region 40 based on the side of the epitaxial layer 12 is approximated to 0. In the third preliminary experiment, a 6 mm square 0.4 mm thick sapphire substrate 11 was used to form a 3 μm thick GaN layer (un-GaN) without doping and an n-type impurity concentration of 1.2×10 16 / cm 3 A stack of GaN layers (n-GaN) with a thickness of 2 μm is used as the epitaxial layer 12 (described later). Figure 1 The area of ​​the cathode region 40 in the third preliminary experiment is 0.00048 cm 2 (The area of ​​the side surface of n-GaN which is the conductive portion in the epitaxial layer 12).

[0055] By irradiating the etched surface 20 with UV light 221 through the etching solution 201, sulfate ion radicals (SO4 -* Free radicals). It can be inferred that: SO4 -* The free radicals diffuse from the etched surface 20 to a certain extent in the etching solution 201. It is believed that SO4 -* The radical region becomes a region that effectively functions as a cathode (effective cathode region).

[0056] In the first and second preliminary experiments, it can be considered that the side of the epitaxial layer 12 and the side of the substrate 11 are effective cathode regions. In addition, in the third preliminary experiment, it can be considered that the side of the epitaxial layer 12 is an effective cathode region. Among them, in the first preliminary experiment, it can be inferred that SO4 -*The free radicals do not reach the center of the bottom surface of the substrate 11, but exist at the periphery of the bottom surface of the substrate 11. That is, in the first preliminary experiment, it can be inferred that the effective cathode area in the bottom surface of the substrate 11 is the periphery of the bottom surface of the substrate 11. Fig.11 The results shown in FIG. 1 show that in the first preliminary experiment, the outer peripheral portion of the bottom surface of the substrate 11 with a width of about 0.4 mm is the effective cathode region. The area of ​​the effective cathode region in the first preliminary experiment is estimated to be 0.192 cm 2 The effective cathode regions in the second to fourth preliminary experiments have an area equal to the area of ​​the cathode region 40, which is 0.096 cm. 2 、0.00048cm 2 and 0cm 2 .

[0057] Fig.11 This is a graph showing the results of PEC etching in preliminary experiments. The horizontal axis represents the area of ​​the effective cathode region (Cathode area), and the vertical axis represents the etching rate. The results of the first preliminary experiment are shown as "with spacer", the results of the second preliminary experiment are shown as "w / o spacer", the results of the third preliminary experiment are shown as "on SAP", and the results of the fourth preliminary experiment are shown as "Side & back resist coat".

[0058] From this result, it can be seen that the wider the area of ​​the effective cathode region, the higher the etching rate. In addition, it can be considered that in order to perform PEC etching of the etched area 21 as the anode well, in order to improve the electrical balance, it is preferred to widen the area of ​​the effective cathode region, and therefore, it is preferred to set the area that can function as the cathode, that is, the cathode region 40, to be wider in advance.

[0059] In the first and second preliminary experiments, by using a conductive substrate 11, the cathode region 40 can be set wider by using the side or bottom surface of the substrate 11, so that the etching rate can be easily increased. In contrast, in the third preliminary experiment, by using a semi-insulating substrate 11, the cathode region 40 is composed of a narrow region only on the side of the epitaxial layer 12, so it is difficult to increase the etching rate. Fig.11 It is found that in the third preliminary experiment, etching hardly proceeds, similar to the fourth preliminary experiment in which the cathode region 40 does not exist.

[0060] It should be noted that even when a semi-insulating substrate 11 is used, when the mask 50 is formed of a conductive material, the surface of the mask 50 also functions as the cathode region 40. This is because the mask 50 is electrically connected to the etched region 21. In this case, the etching rate can be increased compared to the case where the mask 50 is formed of a non-conductive material.

[0061] As a material for manufacturing a semiconductor device using a group III nitride, it is sometimes desirable to use a wafer 10 obtained by growing an epitaxial layer 12 on a semi-insulating substrate 11 such as a sapphire substrate, a silicon carbide (SiC) substrate, or a semi-insulating GaN substrate. In this case, it is sometimes desirable to form a mask 50 using a non-conductive material such as a resist or silicon oxide.

[0062] The results of the third preliminary experiment show that it is difficult to perform PEC etching satisfactorily when a semi-insulating substrate 11 is used and the mask 50 is formed of a non-conductive material. The inventors of the present application have proposed a technique that enables PEC etching to be performed satisfactorily even in such a case.

[0063] Hereinafter, the method for producing the structured body according to the first embodiment will be described in detail. Figure 1 (a) is a schematic cross-sectional view illustrating the processing object 100 of the first embodiment. Figure 1 As shown in (a) of FIG. 1 , the object to be processed 100 is prepared. The object to be processed 100 of the present embodiment includes a cathode pad (conductive member) 30 in addition to the wafer 10 and the mask 50 .

[0064] In this embodiment, a semi-insulating substrate such as a sapphire substrate, a SiC substrate, or a (semi-insulating) GaN substrate is used as the substrate 11. The mask 50 is formed of a non-conductive material such as a resist, silicon oxide, etc. The shape, width, and etching depth of the etched region 21 can be appropriately selected as needed. The mask 50 is arranged at a position that defines the etched region 21 (the edge that defines the etched region 21 includes the edge of the mask 50).

[0065] The cathode pad 30 is a conductive member formed of a conductive material and is provided so as to be in contact with at least a portion of the surface of the conductive region of the wafer 10 which is electrically connected to the etched region 21 . Figure 1 The cathode pad 30 illustrated in (a) is preferably arranged in a state of contact with the mask 50 (in a state where the etched surface 20 is not exposed in a gap between the mask 50 and the cathode pad 30) in an area on the etched surface 20 that is enclosed in the mask 50 when viewed from above. The cathode pad 30 is not arranged at a position that defines the etched area 21.

[0066] The cathode pad 30 is “not configured at a position defining the etched area 21” means that at least a portion of the cathode pad 30 is “not configured at a position defining the etched area 21”, that is, the cathode pad 30 has a portion that does not function as a mask defining the etched area 21 (the etched area 21 does not define the cathode pad 30 only as a mask, and the edge defining the etched area 21 is not constituted by only the edge of the cathode pad 30). It should be noted that the configuration of the cathode pad 30 can be appropriately adjusted as needed. For example, the cathode pad 30 can sometimes be configured in an area that is not included in the mask 50 when viewed from above. The edge of the cathode pad 30 may have a portion included in the edge defining the etched area 21, or may have a portion not included in the edge defining the etched area 21.

[0067] As the material of the cathode pad 30, it is preferred to use a material that has a low Schottky barrier height to the etched surface 20 and is resistant to the etching solution 201 (alkali or acid). Specifically, a metal such as titanium (Ti) can be preferably used. In addition to Ti, for example, Ti / Au in which gold (Au) is stacked on Ti, nickel (Ni), platinum (Pt), a single layer of Au, etc. can also be used.

[0068] When the object 100 is immersed in the etching solution 201, the upper surface of the cathode pad 30 is exposed in the etching solution 201. Therefore, the upper surface of the cathode pad 30 functions as the cathode region 40. As described above, in the present embodiment, the upper surface of the cathode pad 30 also constitutes the cathode region 40 in addition to the side surface of the epitaxial layer 12.

[0069] In the present embodiment, by providing the cathode pad 30, the cathode region 40 becomes wider than when the cathode pad 30 is not provided. Thus, PEC etching can be performed more favorably than when the cathode pad 30 is not provided.

[0070] The cathode pad 30 of the present embodiment can use the upper surface of the cathode pad 30 as the cathode region 40, so it is easy to set the cathode region 40 to be wider. In addition, by providing the cathode pad 30 on the etched surface 20, the SO4 generated by irradiating the UV light 221 on the etched surface 20 can be made larger. -* The radicals are more surely present near the upper surface of the cathode pad 30. Thus, the upper surface of the cathode pad 30 can be easily used as an effective cathode region.

[0071] Figure 1(b) is a schematic cross-sectional view showing an example of the structure of the wafer 10 (a structure used in the experimental examples described later). The substrate 11 is a sapphire substrate. The epitaxial layer 12 is composed of a GaN layer (un-GaN) with a thickness of 3 μm without doping and a GaN layer with n-type doping and a carrier concentration (substantial dopant concentration) of 1.2×10 16 / cm 3 , a stacked structure of GaN layers (n-GaN) with a thickness of 2 μm.

[0072] Figure 1 (c) is a schematic cross-sectional view of a PEC etching apparatus 200 showing a PEC etching process. The PEC etching apparatus 200 includes a container 210 for containing an etching solution 201 and a light source 220 for emitting ultraviolet (UV) light 221 .

[0073] In the PEC etching process, while the object 100 is immersed in the etching solution 201 and the etched region 21 and the cathode pad 30 are in contact with the etching solution 201, UV light 221 is irradiated to the etched surface 20 through the etching solution 201, thereby etching the group III nitride constituting the etched region 21. Details of the etching solution 201, UV light 221, and the mechanism of PEC etching will be described later.

[0074] In addition, the method for producing a structure may include, as other steps, steps such as electrode formation and protective film formation, as necessary.

[0075] Next, a method for forming the cathode pad 30 will be described by way of example. Figure 2 (a)~ Figure 2 (c) is a schematic cross-sectional view showing a first example of a method for forming the cathode pad 30. In the first example, the cathode pad 30 is formed before forming the mask 50. As a material of the mask 50, a resist can be exemplified.

[0076] First, if Figure 2 As shown in (a) of FIG. 1 , a cathode pad 30 is formed on the etched surface 20 of the wafer 10 by lift-off or the like, for example, from Ti. Figure 2 As shown in (b) of FIG. 1 , a resist film 51 is formed on the entire surface of the etched surface 20 so as to cover the cathode pad 30. Figure 2 As shown in (c) of FIG. 1 , the resist film 51 is patterned to form a mask 50 . The mask 50 has an opening for exposing the etched region 21 and an opening for exposing the upper surface of the cathode pad 30 .

[0077] Figure 3 (a)~ Figure 3(c) is a schematic cross-sectional view showing a second example of the method for forming the cathode pad 30. In the second example, the cathode pad 30 is formed after forming the mask 50. As a material of the mask 50, silicon oxide can be exemplified.

[0078] First, if Figure 3 As shown in (a), after forming a silicon oxide film on the entire surface of the etched surface 20 of the wafer 10, the silicon oxide film is patterned by photolithography and etching to form a mask 50. The mask 50 has an opening that exposes the etched area 21 and has an opening in the area where the cathode pad 30 is to be formed.

[0079] Then, if Figure 3 As shown in (b) of FIG. 1 , a resist pattern 70 for lift-off is formed so as to cover the etching region 21 and expose the region where the cathode pad 30 is to be formed. Then, a Ti film 31 is formed on the entire surface of the etching surface 20 .

[0080] Then, if Figure 3 As shown in (c) of FIG. 1 , by lift-off, that is, by removing the resist pattern 70 together with the unnecessary portion of the Ti film 31 , the cathode pad 30 is formed (remains) in the region where the cathode pad 30 is to be formed.

[0081] For example, when the mask 50 is formed using silicon oxide, hydrofluoric acid is preferably used in the etching when forming the mask 50. Therefore, if the mask 50 is formed after the cathode pad 30 is formed, there is a concern that the cathode pad 30 may be etched. By forming the cathode pad 30 after the mask 50 is formed as in the second example, such unnecessary etching of the cathode pad 30 can be avoided.

[0082] Next, the details of the etching solution 201, the UV light 221, and the mechanism of PEC etching are described. GaN can be exemplified as the group III nitride to be etched.

[0083] As the etching solution 201, an alkaline or acidic etching solution 201 containing oxygen for generating an oxide of the group III element contained in the group III nitride constituting the etching area 21 and further containing an oxidant that accepts electrons can be used. Examples of the oxidant include persulfate ions (S2O8 2- ).

[0084] As a first example of the etching solution 201, there can be cited an etching solution obtained by mixing a potassium hydroxide (KOH) aqueous solution with a potassium persulfate (K2S2O8) aqueous solution, which exhibits alkalinity at the start time of etching. Such an etching solution 201 is prepared, for example, by mixing a 0.01M KOH aqueous solution with a 0.05M K2S2O8 aqueous solution in a ratio of 1:1. The concentration of the KOH aqueous solution, the concentration of the K2S2O8 aqueous solution, and the mixing ratio of these aqueous solutions can be appropriately adjusted as needed. It should be noted that the etching solution 201 mixed with the KOH aqueous solution and the K2S2O8 aqueous solution can also exhibit acidity at the start time of etching, for example, by reducing the concentration of the KOH aqueous solution.

[0085] The PEC etching mechanism when the etching solution 201 of the first example is used is described. By irradiating the etched surface 20 with UV light 221 having a wavelength of less than 365 nm, holes and electrons are generated in pairs in the GaN constituting the etched area 21. The generated holes decompose the GaN into Ga 3+ and N2 (chemical formula 1), and further, Ga 3+ The hydroxide ion (OH - ) is oxidized to generate gallium oxide (Ga2O3) (chemical formula 2). The generated Ga2O3 is dissolved in an alkali or acid. In this way, PEC etching of GaN is performed. It should be noted that the generated holes react with water, and the water is decomposed, thereby generating oxygen (chemical formula 3).

[0086] [Chemical formula 1]

[0087]

[0088] [Chemical formula 2]

[0089]

[0090] [Chemical formula 3]

[0091]

[0092] In addition, peroxydisulfate ions (S2O8) are generated by dissolving K2S2O8 in water. 2- )(chemical formula 4), by S2O8 2- UV light 221 is irradiated to generate sulfate ion radicals (SO4 -* Free radicals) (chemical formula 5). The electrons and holes generated in pairs and SO4 -* The free radicals react with water, and the water is decomposed, thereby generating hydrogen (chemical formula 6). -*The free radicals can consume the electrons generated in pairs with holes in GaN, so PEC etching can be performed well. It should be noted that as shown in (chemical formula 6), as PEC etching proceeds, sulfate ions (SO4 2- ) will increase, thereby, the acidity of the etching solution 201 gradually becomes stronger (the pH gradually decreases).

[0093] [Chemical formula 4]

[0094]

[0095] [Chemical formula 5]

[0096]

[0097] [Chemical formula 6]

[0098]

[0099] As a second example of the etching solution 201, an etching solution obtained by mixing a phosphoric acid (H3PO4) aqueous solution with a potassium persulfate (K2S2O8) aqueous solution, which exhibits acidity at the start time of etching, can be cited. This etching solution 201 is prepared, for example, by mixing a 0.01M H3PO4 aqueous solution with a 0.05M K2S2O8 aqueous solution in a ratio of 1:1. The concentration of the H3PO4 aqueous solution, the concentration of the K2S2O8 aqueous solution, and the mixing ratio of these aqueous solutions can be appropriately adjusted as needed. Both the H3PO4 aqueous solution and the K2S2O8 aqueous solution are acidic, and therefore, the etching solution 201 mixed with the H3PO4 aqueous solution and the K2S2O8 aqueous solution exhibits acidity at any mixing ratio. It is preferred that the etching solution 201 is acidic from the perspective of facilitating the use of a resist mask as a mask 50.

[0100] The PEC etching mechanism when the etching solution 201 of the second example is used can be presumed to be that (Chemical Formula 1) to (Chemical Formula 3) described for the case of using the etching solution 201 of the first example are replaced with (Chemical Formula 7). That is, GaN, holes generated by irradiation with UV light 221, and water react to generate Ga2O3, hydrogen ions (H + ) and N2 (chemical formula 7). And the generated Ga2O3 is dissolved in acid. In this way, PEC etching of GaN is performed. It should be noted that the electrons generated in pairs with holes as shown in (chemical formula 4) to (chemical formula 6) are removed by S2O8 2- The mechanism of consumption is the same as that in the case of using the etching solution 201 of the first example.

[0101] [Chemical formula 7]

[0102]

[0103] As can be understood from (Chemical Formula 1) and (Chemical Formula 2) or (Chemical Formula 7), the etched region 21 where PEC etching of GaN occurs is considered to function as an anode that consumes holes. In addition, as can be understood from (Chemical Formula 6), the portion of the surface of the conductive region of the object 100 that is electrically connected to the etched region 21 and exposed to the etching solution 201 is considered to function as a cathode that consumes (releases) electrons.

[0104] As shown in (chemical formula 5), ​​as S2O8 2- Generate SO4 -* The free radical method may use at least one of irradiation with UV light 221 and heating. When irradiation with UV light 221 is used, in order to increase the S2O8 2- The light absorption can efficiently generate SO4 -* The wavelength of the UV light 221 is preferably 200 nm or more and less than 310 nm. That is, the UV light 221 is irradiated to efficiently generate holes in the III-nitride in the wafer 10 and to generate S2O8 in the etching solution 201. 2- Generate SO4 -* From the perspective of free radicals, it is preferred that the wavelength of UV light 221 be greater than 200 nm and less than 310 nm. 2- Generate SO4 -* In the case of free radicals, the wavelength of the UV light 221 can be set to (365 nm or less and) 310 nm or more.

[0105] By irradiation of UV light 221, S2O8 2- Generate SO4 -* When the free radical is generated, the distance L from the etched surface 20 of the wafer 10 to the upper surface 202 of the etching liquid 201 is preferably set to 5 mm or more and 100 mm or less. If the distance L is too short, for example, less than 5 mm, the SO4 generated in the etching liquid 201 above the wafer 10 -* The amount of free radicals may become unstable due to the change in the distance L. In addition, if the distance L is too long, for example, more than 100 mm, SO4 that does not participate in PEC etching and increases uselessly is generated in the etching solution 201 above the wafer 10. -* Free radicals are generated, and therefore, the utilization efficiency of the etching solution 201 is reduced.

[0106] It should be noted that PEC etching can also be performed on group III nitrides other than the exemplified GaN. The group III element contained in the group III nitride is at least one of aluminum (Al), gallium (Ga) and indium (In). The concept of PEC etching of the Al component or the In component in the group III nitride is the same as the concept described for the Ga component with reference to (chemical formula 1) and (chemical formula 2) or (chemical formula 7). That is, holes are generated by irradiating UV light 221, thereby generating Al oxides or In oxides, and these oxides are dissolved in alkali or acid, thereby enabling PEC etching. The wavelength (below 365nm) of the UV light 221 can be appropriately changed according to the composition of the group III nitride to be etched. Taking the PEC etching of GaN as a benchmark, when Al is contained, UV light with a shorter wavelength can be used, and when In is contained, UV light with a longer wavelength can also be used.

[0107] Next, the experimental example of the PEC etching described in the first embodiment is described. In this experimental example, the following is studied: Figure 1 (b) shows how the progress of PEC etching changes when a mask 50 and a cathode pad 30 are formed on the etched surface 20 of a 6 mm square wafer 10 of a stacked structure and the area of ​​the cathode pad 30 is changed.

[0108] As the etching solution 201, a solution obtained by mixing a 0.01M KOH aqueous solution and a 0.05M K2S2O8 aqueous solution at a ratio of 1:1 was used. UV light 221 was irradiated on the etched surface 20 through the etching solution 201. The irradiation wavelength of the UV light 221 was set to 260nm, and the irradiation intensity (I) was set to 4mW / cm 2 The distance L (d electrolyte ) is set to 5mm.

[0109] Figure 4 (a)~ Figure 4 (e) are photographs showing the patterns of the mask 50 and the cathode pad 30 formed on the first to fifth processing objects (hereinafter also referred to as the first to fifth samples) of this experimental example. The first to fifth samples use silicon oxide (SiO2) to form the mask 50 having the same shape of the opening area. Figure 4 (a)~ Figure 4 In (e), the region where the mask 50 is formed is shown as a dark region.

[0110] Figure 4 (a)~ Figure 4 In (e), the bright area represents the opening area of ​​the mask 50, that is, the etched area 21. Figure 4 (a)~ Figure 4 In the bright area of ​​(e), the portion marked as "Ti" indicates the cathode pad 30 formed of Ti. The area of ​​the portion marked as "Ti", that is, the area of ​​the cathode pad 30, is increased in the order of the first to fifth samples. Figure 4 (a)~ Figure 4 In (e), the numerical value shown in the upper part indicates the area of ​​the upper surface of the cathode pad 30 relative to the total area of ​​the etched surface 20 of 6 mm square (36 mm 2 The cathode ratios of the first to fifth samples were 0.0056 (0.6%), 0.011 (1.1%), 0.022 (2.2%), 0.044 (4.4%), and 0.078 (7.8%), respectively.

[0111] Figure 4 (f) is a photograph showing the pattern of the mask 50 of the sixth processing object (hereinafter also referred to as the sixth sample). The sixth sample uses Ti to form a mask 50 having an opening area of ​​the same shape as the first to fifth samples. In addition, the sixth sample does not form a cathode pad 30. The sixth sample does not have a cathode pad 30, but the mask 50 itself is formed of Ti and functions as a cathode area 40, so it corresponds to a case where the area of ​​the cathode pad 30 is expanded to the limit in the mask 50 having an opening area of ​​the same shape as the first to fifth samples. In the sixth sample, as a cathode ratio, it corresponds to 0.504 (50.4%).

[0112] Figure 5 (a) and Figure 5 (b) is a graph showing the results of this experimental example. Figure 5 (a) shows the dependency of the etching depth of the first to sixth samples on the etching time. Figure 5 (b) shows the dependency of the etching rate of the first to sixth samples on the cathode area (the value obtained by converting the cathode ratio into the area). The etching rate is an average value within the etching time of 120 minutes.

[0113] Depend on Figure 5 (a) and Figure 5 (b) shows that the etching depth per unit time, that is, the etching rate can be increased by forming the cathode pad 30. It is also found that the etching rate can be increased by increasing the cathode ratio (increasing the cathode area).

[0114] The reference of the preferred area of ​​the cathode pad 30 can be, for example, as follows: The cathode ratio, that is, the ratio of the cathode area (the area where the cathode pad 30 contacts the etching solution 201) to the overall area of ​​the etched surface 20 is preferably set to 1% or more, more preferably 2% or more, further preferably 4% or more, and further preferably 8% or more.

[0115] The reference for the preferred area of ​​the cathode pad 30 may be, for example, as follows: The cathode area (the area where the cathode pad 30 contacts the etching solution 201) is preferably larger than the area of ​​the cathode region 40 when the cathode pad 30 is not provided, that is, the entire area of ​​the side surface (conductive portion) of the epitaxial layer 12.

[0116] <Second Embodiment>

[0117] Next, a method for manufacturing the structure body according to the second embodiment will be described. In the second embodiment, a high electron mobility transistor (HEMT) can be exemplified as the structure body 150 to be manufactured.

[0118] Figure 6 (a) is a schematic cross-sectional view illustrating a structure 150 (hereinafter also referred to as HEMT150) according to the second embodiment. Figure 6 (b) is a schematic cross-sectional view illustrating a wafer 10 used as a material for the HEMT 150 .

[0119] As the substrate 11, for example, a semi-insulating SiC substrate is used. As the epitaxial layer 12, for example, a stacked structure of a nucleation layer 12a composed of aluminum nitride (AlN), a channel layer 12b composed of GaN with a thickness of 1.2 μm, a barrier layer 12c composed of aluminum gallium nitride (AlGaN) with a thickness of 24 nm, and a cap layer 12d composed of GaN with a thickness of 5 nm is used. A two-dimensional electron gas (2DEG) that becomes a channel of the HEMT 150 is generated in the stacked portion of the channel layer 12b and the barrier layer 12c.

[0120] The source electrode 151, the gate electrode 152, and the drain electrode 153 of the HEMT 150 are formed on the upper surface of the cap layer 12d. A protective film 154 is formed to have openings on the upper surfaces of the source electrode 151, the gate electrode 152, and the drain electrode 153.

[0121] The HEMT 150 has an element isolation trench 160 for isolating adjacent elements. The element isolation trench 160 is provided so that its bottom surface is located deeper than the upper surface of the channel layer 12 b , that is, so that 2DEG is disconnected between adjacent elements by the element isolation trench 160 .

[0122] In this embodiment, a method of forming the element isolation groove 160 of the HEMT 150 by PEC etching is exemplified. Figure 7 (a) is a schematic cross-sectional view illustrating an example of the object 100 to be processed when PEC etching is performed to form the element isolation groove 160 . Figure 7 (b) is a schematic top view of the processing object 100. Figure 7(c) is a schematic cross-sectional view of the PEC etching apparatus 200 showing the PEC etching process.

[0123] The processing object 100 of this example has a structure in which a PEC etching mask 50 is formed on a member at a stage where a source electrode 151 and a drain electrode 153 are formed on a wafer 10. The source electrode 151 and the drain electrode 153 are used as a cathode pad 30. The cathode pad 30 (source electrode 151 and drain electrode 153) is formed of, for example, Ti / Al / Au in which aluminum (Al) is stacked on Ti and Au is stacked on Al.

[0124] The mask 50 is formed on the etched surface 20 which is the upper surface of the cap layer 12d, and has an opening for exposing the etched region 21 and an opening for exposing the upper surface of the cathode pad 30 (source electrode 151 and drain electrode 153). The etched region 21 is a region where the element separation groove 160 is to be formed, and is arranged in a grid pattern, for example, so as to surround each HEMT element in a plan view.

[0125] The mask 50 is formed of, for example, a resist. As the etching solution 201, an acidic etching solution is preferably used (from the etching start time point). By etching the III-nitride constituting the etched region 21 to a position deeper than the upper surface of the channel layer 12b, a recessed portion used as the element separation groove 160 is formed. After the recessed portion (element separation groove 160) is formed, the mask 50 is removed, the gate electrode 152 is formed, and the protective film 154 is formed. In this way, the HEMT 150 is manufactured.

[0126] According to the second embodiment, even when the wafer 10 having the semi-insulating substrate 11 such as a SiC substrate is used and the mask 50 formed of a non-conductive material such as a resist is used, the element isolation trench 160 of the HEMT 150 can be easily formed by PEC etching.

[0127] <Third Embodiment>

[0128] Next, a method for manufacturing a structured body according to the third embodiment will be described. In the third embodiment, a preferred arrangement of the cathode pad 30 is described in order to improve the shape controllability of the recessed portion formed by PEC etching.

[0129] As described in the first and second embodiments, by providing the cathode pad 30 , PEC etching can be performed favorably even when the mask 50 formed of a non-conductive material (hereinafter also referred to as a non-conductive mask 50 ) is used.

[0130] From the viewpoint of promoting the progress of PEC etching, a portion of the edge of the mask defining the etched area 21 may be constituted by the edge of the cathode pad 30. However, as described below, based on the findings obtained by the inventors of the present application, from the viewpoint of improving the shape controllability of the recess formed by PEC etching, it is preferred that all portions of the edge of the mask defining the etched area 21 do not include the edge of the cathode pad 30, but are constituted by the edge of the non-conductive mask 50.

[0131] This configuration is obtained, for example, by arranging the cathode pad 30 on the inner side (the side opposite to the etched region 21) of the non-conductive mask 50 in a plan view. In other words, the cathode pad 30 is arranged so that the entire periphery of the cathode pad 30 is surrounded by the non-conductive mask 50 (see, for example, Figure 7 (b)).

[0132] Fig.12 (a) and Fig.12 (b) is a schematic cross-sectional view and a top view (a view showing a portion where edge 85 of mask 80 is formed by edge 35 of cathode pad 30) illustrating a manner in which cathode pad 30 is configured so that edge 35 of cathode pad 30 becomes edge 85 of mask 80 that defines etched area 21.

[0133] By utilizing the cathode pad 30 to promote the progress of PEC etching, it is possible to form the recess 22 in the etched region 21. Ideally, the edge of the recess 22 is formed along the edge 85 of the mask 80, that is, the edge 35 of the cathode pad 30 (the edge 23a of the recess 22 in the ideal case is indicated by a dotted line). However, it is known that, by the PEC etching of this method, the edge 23 of the recess 22 is actually formed in a position deviated from the edge 35 of the cathode pad 30 to the outside (the etched region 21 side) in a disorderly shape with an irregular distance from the edge 35. It is inferred that the reason for this is that since the cathode pad 30 is conductive, a depletion layer is formed on the etched surface 20 near the cathode pad 30.

[0134] Fig.13 (a) and Fig.13 (b) is a schematic cross-sectional view and a top view illustrating a method in which the non-conductive mask 50 and the cathode pad 30 are arranged in such a manner that the edge 55 of the non-conductive mask 50 becomes the edge 85 of the mask 80 that defines the etched region 21. In this example, the cathode pad 30 is arranged on the inner side of the non-conductive mask 50 (the side opposite to the etched region 21).

[0135] The (shortest) distance between the edge 85 of the mask 80, that is, the edge 55 of the non-conductive mask 50 and the edge 35 of the cathode pad 30 (hereinafter referred to as the offset distance) is denoted as D OFFThe inventors of the present application have obtained the following knowledge: off By extending the distance D to a certain extent or more, the influence of the depletion layer caused by the cathode pad 30 can be suppressed and the edge 23 of the recess 22 can be formed at a position along the edge 85 of the mask 80 (the edge 55 of the non-conductive mask 50). OFF It is preferably 5 μm or more, and more preferably 10 μm or more. OFF There is no particular upper limit.

[0136] As described above, by configuring the edge 85 of the mask 80 that defines the etching target region 21 with the edge 55 of the non-conductive mask 50 , it is possible to improve the shape controllability of the edge 23 of the recess 22 formed by the PEC etching.

[0137] It should be noted that in Figure 7 In the configuration illustrated in (b), the cathode pad 30 is disposed inside the edge of the closed shape defining the etched region 21 of the non-conductive mask 50, but as required (depending on the element structure to be manufactured, etc.), the cathode pad 30 may be disposed outside the edge (for example, see the configuration described later). Fig.15 (a)). In this method, it is easier to ensure the offset distance D from the edge of the non-conductive mask 50 defining the etched area 21 to the cathode pad 30. OFF long.

[0138] Hereinafter, the results of the experimental example described in the third embodiment will be described. Fig.14 : is a photograph showing the result of PEC etching using a Ti mask. In the square-shaped area shown in the photograph, the bright areas on the upper side and the right side represent the Ti mask. The slightly dark area outside the Ti mask (lower side or left side) represents the etched area 21 defined by the Ti mask. The edge 23 with a chaotic shape of the formed concave portion 22 is observed in the etched area 21.

[0139] Fig.15 (a) is a photograph showing the object 100 on which the non-conductive mask 50 and the cathode pad 30 are formed. The cathode pad 30 is shown as a bright area, and the non-conductive mask 50 is shown as an area darker than the cathode pad 30. The etching area is demarcated by the non-conductive mask 50 and is shown as a (linear) area darker than the non-conductive mask 50. Fig.15 (a)~ Fig.15 The experimental conditions in the experimental example described in (c) are the same as those in the first embodiment except that a K2S2O8 aqueous solution is used as the etching solution. Figure 4 (a)~ Figure 4The experimental conditions (irradiation wavelength, irradiation intensity, and distance L) in the experimental example described in (f) are the same. The non-conductive mask 50 is formed of SiO2, and the cathode pad 30 is formed of Ti.

[0140] Fig.15 (b) and Fig.15 (c) is to Fig.15 The photograph is a magnified image of a portion of the area shown in the upper right circle of (a). Within the circle, a square ring-shaped etched area 21 is defined by a non-conductive mask 50. Fig.15 (b) and Fig.15 In (c), the upper right corner of the etched area 21 is shown. Fig.15 (b) is a photo before PEC etching. Fig.15 (c) is a photo after PEC etching. Fig.15 As shown in (b), the width of the portion of the etched region 21 extending in the horizontal direction of the paper surface is 76 μm, and the width of the portion of the etched region 21 extending in the vertical direction of the paper surface is 45 μm.

[0141] The edge of the mask defining the etched region 21 does not include the edge of the cathode pad 30, but is formed by the edge of the non-conductive mask 50. That is, the cathode pad 30 is not arranged at the position defining the etched region 21. In addition, the edge of the non-conductive mask 50 defining the etched region 21 is spaced a sufficient distance (more than 5 μm or more than 10 μm) from the cathode pad 30 (refer to Fig.15 (a)).

[0142] Will Fig.15 (b) and Fig.15 By comparing with (c), it can be seen that in this experimental example, the recess 22 is formed in a shape substantially consistent with the opening shape of the non-conductive mask 50, and the edge 23 of the recess 22 can be formed along the edge of the non-conductive mask 50. In this way, by making the edge defining the etched area 21 not include the edge of the cathode pad 30 but consist of the edge of the non-conductive mask 50, PEC etching that improves the shape controllability of the recess 22 can be performed.

[0143] <Other Implementation Methods>

[0144] The embodiments of the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiments, and various changes, improvements, combinations, etc. can be made without departing from the spirit and scope of the present invention.

[0145] For example, the shape, size, configuration, number, etc. of the cathode pad 30 can be adjusted in various ways as needed.

[0146] Figure 8(a) and Figure 8 (b) is a schematic plan view of the object 100 showing an example in which the cathode pads 30 are arranged along the outer periphery of the wafer 10. The edge of the wafer 10 is indicated by a thick line.

[0147] Generally speaking, there are many cases where no element is formed on the periphery of the wafer 10. Therefore, by using the periphery of the wafer 10 to arrange the cathode pad 30, it is easy to use the wide area inside the wafer 10 for element formation. In addition, by arranging the cathode pad 30 along the periphery of the wafer 10, it is easy to form the cathode pad 30 longer, that is, to form the cathode pad 30 wider.

[0148] Figure 8 (a) shows an example in which the cathode pad 30 is arranged inside the wafer 10 along the outer circumference of the wafer 10 in a plan view. Figure 8 (b) shows an example in which the cathode pad 30 is arranged along the outer periphery of the wafer 10 in a manner extending to the outside of the wafer 10 (protruding into a brim shape) in a plan view. Figure 8 By placing the cathode pad 30 outside the wafer 10, as in the example shown in (b), the area where the cathode pad 30 contacts the etching liquid 201 can be expanded, so that the cathode region 40 can be set wider. This structure is formed, for example, by bonding (or making it contact) the separately prepared cathode pad 30 to the wafer 10.

[0149] In the first and second embodiments, the case where the substrate 11 of the wafer 10 is semi-insulating is exemplified, but the substrate 11 may be conductive. That is, when the substrate 11 is conductive, the cathode pad 30 may be provided. When the substrate 11 is conductive, the cathode pad 30 may be arranged at any position on the surface of the substrate 11.

[0150] Fig. 9 1 is a schematic cross-sectional view conceptually illustrating a method of providing a cathode pad 30 on a wafer 10 having a conductive substrate 11. When the substrate 11 is conductive, the cathode pad 30 can be arranged not only on the upper surface of the wafer 10 (i.e., on the etched surface 20), but also on the side surface of the wafer 10 (of the substrate 11), and also on the bottom surface of the wafer 10 (of the substrate 11). It should be noted that in this case, only the substrate 11 will also be conductive, so it is also possible to consider using the substrate 11 itself without the epitaxial layer 12 as the wafer 10, and arranging the cathode pad 30 on the upper surface of the wafer 10 (of the substrate 11). Where on the surface of the conductive substrate 11 to arrange the cathode pad 30 can be appropriately selected according to needs.

[0151] As the etching liquid 201, for example, only a K2S2O8 aqueous solution may be used as the etching liquid 201 which is acidic at the start of etching. In this case, the concentration of the K2S2O8 aqueous solution may be set to 0.025M, for example.

[0152] In the above description, potassium persulfate (K2S2O8) is used as an example to supply S2O8. 2- But S2O8 2- It can be supplied by other substances such as sodium peroxodisulfate (Na2S2O8), ammonium peroxodisulfate (ammonium persulfate, (NH4)2S2O8), etc.

[0153] When performing PEC etching, the etching liquid 201 may be stationary or circulated (flowing). In the case of circulating the etching liquid 201, the same etching liquid 201 may be circulated (without replacing the etching liquid 201) or a new etching liquid 201 may be continuously supplied (without replacing the etching liquid 201).

[0154] <Preferred Mode of the Invention>

[0155] Hereinafter, preferred embodiments of the present invention will be described.

[0156] (Note 1)

[0157] A method for manufacturing a structure, comprising the following steps:

[0158] A step of preparing a processing object, the processing object comprising: an etching object having an etching surface composed of a conductive group III nitride, an etching region being arranged on the etching surface; and a conductive member provided in contact with at least a portion of a surface of a conductive region of the etching object electrically connected to the etching region; and

[0159] The process of immersing the object to be processed in an alkaline or acidic etching solution containing an electron-accepting oxidant and irradiating the surface to be etched with ultraviolet light through the etching solution while the etching solution is in contact with the etching region and the conductive member, thereby etching the group III nitride constituting the etching region.

[0160] The edge defining the region to be etched is not constituted only by the edge of the conductive member (the conductive member is not arranged at a position defining the region to be etched).

[0161] (Note 2)

[0162] The method for manufacturing a structure according to Supplementary Note 1, wherein the object to be processed includes a mask formed on the surface to be etched and made of a non-conductive material,

[0163] The edge defining the region to be etched includes the edge of the mask (the mask is arranged at a position defining the region to be etched).

[0164] (Note 3)

[0165] The method for manufacturing a structure according to Supplement 2, wherein the mask is composed of a resist,

[0166] The aforementioned etching solution is acidic.

[0167] (Note 4)

[0168] The method for producing a structure according to any one of Supplementary Notes 1 to 3, wherein the etching solution is acidic.

[0169] (Note 5)

[0170] The method for producing a structure according to any one of Supplementary Notes 1 to 4, wherein the Group III nitride is etched in a state where an upper surface of a portion of the conductive member provided on the surface to be etched is in contact with the etching solution.

[0171] (Note 6)

[0172] The method for manufacturing a structure according to any one of Supplementary Notes 1 to 5, wherein the etching object is used as a material for a high electron mobility transistor.

[0173] The conductive member is used as an electrode of the high electron mobility transistor.

[0174] (Note 7)

[0175] The method for manufacturing a structure according to Supplementary Note 6, wherein the recessed portion formed by etching the etched region is used as a device isolation trench of the high electron mobility transistor.

[0176] (Note 8)

[0177] The method for producing a structure according to any one of Supplementary Notes 1 to 7, wherein the conductive member is arranged along the outer periphery of the etching object in a plan view.

[0178] (Note 9)

[0179] The method for producing a structure according to any one of Supplementary Notes 1 to 8, wherein the conductive member is arranged so as to extend to a position outside the etching object in a plan view.

[0180] (Note 10)

[0181] The method for producing a structure according to any one of Supplementary Notes 1 to 9, wherein the etching object includes a semi-insulating substrate.

[0182] (Note 11)

[0183] The method for manufacturing a structure according to Supplementary Note 10, wherein the conductive member is provided on a Group III nitride layer formed on the semi-insulating substrate.

[0184] (Note 12)

[0185] A method for manufacturing a structure according to Note 11, wherein the area in which the conductive component is in contact with the etching solution is preferably 1% or more, more preferably 2% or more, further preferably 4% or more, and further preferably 8% or more, relative to the entire area of ​​the etched surface which is the upper surface of the Group III nitride layer.

[0186] (Note 13)

[0187] The method for manufacturing a structure according to Appendix 11 or 12, wherein an area where the conductive member is in contact with the etching solution is wider than an entire area of ​​a side surface of the Group III nitride layer.

[0188] (Note 14)

[0189] The method for producing a structure according to any one of Supplementary Notes 1 to 9, wherein the etching object includes a conductive substrate.

[0190] (Note 15)

[0191] The method for producing a structure according to Supplementary Note 14, wherein the conductive member is disposed on a surface of a group III nitride layer formed on the conductive substrate.

[0192] (Note 16)

[0193] The method for producing a structure according to Appendix 14 or 15, wherein the conductive member is arranged on a surface of the conductive substrate.

[0194] (Note 17)

[0195] An intermediate structure comprising:

[0196] An etching object having an etching surface composed of a conductive group III nitride, wherein an etching region is arranged on the etching surface; and

[0197] a conductive member disposed in contact with at least a portion of a surface of a conductive region of the etching object that is electrically connected to the etched region;

[0198] The intermediate structure is immersed in an etchant containing an oxidant that accepts electrons, in a state where the etched region and the conductive member are in contact with the etchant.

[0199] The edge defining the region to be etched is not constituted only by the edge of the conductive member (the conductive member is not arranged at a position defining the region to be etched).

[0200] (Note 18)

[0201] The intermediate structure according to Supplementary Note 17, comprising a mask formed on the surface to be etched and made of a non-conductive material,

[0202] The edge defining the region to be etched includes the edge of the mask (the mask is arranged at a position defining the region to be etched).

[0203] (Note 19)

[0204] The intermediate structure according to Supplementary Note 17 or 18, wherein the mask is made of a resist.

[0205] (Note 20)

[0206] The intermediate structure according to any one of Supplementary Notes 17 to 19, wherein the etching object is used as a material for a high electron mobility transistor.

[0207] The conductive member is used as an electrode of the high electron mobility transistor.

[0208] (Note 21)

[0209] The intermediate structure according to any one of Supplementary Notes 17 to 20, wherein the conductive member is arranged along the outer periphery of the etching object in a plan view.

[0210] (Note 22)

[0211] The intermediate structure according to Supplementary Note 21, wherein the conductive member is arranged so as to extend to the outside of the etching object in a plan view.

[0212] (Note 23)

[0213] The intermediate structure according to any one of Supplementary Notes 17 to 22, wherein the etching object includes a semi-insulating substrate.

[0214] (Note 24)

[0215] The intermediate structure according to any one of Supplementary Notes 17 to 22, wherein the etching object includes a conductive substrate.

[0216] (Note 25)

[0217] The intermediate structure according to Supplementary Note 24, wherein the conductive member is arranged on a surface of the conductive substrate.

[0218] (Note 26)

[0219] The intermediate structure according to any one of Supplementary Notes 17 to 25, wherein the surface to be etched is irradiated with ultraviolet light via the etching solution.

[0220] (Note 27)

[0221] A method for processing a group III nitride crystal, characterized in that it is a method for electrochemically etching a crystal composed of a group III nitride in a state of being immersed in an etching solution, and comprises the following steps:

[0222] A step of defining an etched region and a region other than the etched region on the surface of the group III nitride; and

[0223] a step of etching the group III nitride by irradiating the surface with ultraviolet light via the etching solution,

[0224] A part of the region other than the region to be etched is connected (brought into contact) with a conductive member that functions as a cathode for releasing electrons into the etching solution.

[0225] (Note 28)

[0226] The method for manufacturing a structure according to Supplementary Note 2, wherein the edge defining the etching region does not include an edge of the conductive member, and is constituted by an edge of the mask.

[0227] (Note 29)

[0228] The method for producing a structure according to Supplementary Note 28, wherein the distance between the edge of the mask and the edge of the conductive member is preferably 5 μm or more, more preferably 10 μm or more.

[0229] (Note 30)

[0230] The method for manufacturing a structure according to Supplementary Note 28 or 29, wherein the conductive member is arranged so that the entire periphery of the conductive member is surrounded by the mask in a plan view.

[0231] (Note 31)

[0232] The intermediate structure according to Supplementary Note 18, wherein the edge defining the etched region does not include an edge of the conductive member, and is constituted by an edge of the mask.

[0233] (Note 32)

[0234] The intermediate structure according to Supplementary Note 31, wherein the distance between the edge of the mask and the edge of the conductive member is preferably 5 μm or more, more preferably 10 μm or more.

[0235] (Note 33)

[0236] The intermediate structure according to Supplementary Note 31 or 32, wherein the conductive member is arranged so that the entire periphery of the conductive member is surrounded by the mask in a plan view.

[0237] Description of Reference Numerals

[0238] 10 ... etching object, 20 ... etching surface, 21 ... etching region, 30 ... cathode pad, 50 ... mask, 100 ... processing object, 150 ... structure, 200 ... PEC etching device, 201 ... etching solution, 202 ... upper surface of etching solution, 210 ... container, 220 ... light source, 221 ... UV light

Claims

1. A method for manufacturing a structure, comprising the following steps: A step of preparing a processing object, the processing object comprising: an etching object having an etching surface composed of a conductive group III nitride, wherein an etching region is arranged on the etching surface; a conductive member provided in contact with at least a portion of a surface of a conductive region of the etching object electrically connected to the etching region; and a mask formed on the etching surface and composed of a non-conductive material; and The process of immersing the object to be processed in an alkaline or acidic etching solution containing peroxydisulfate ions as an electron-accepting oxidant, and irradiating the etched surface with light through the etching solution while the etched region and the conductive member are in contact with the etching solution, thereby etching the group III nitride constituting the etched region, The edge defining the etched area does not include the edge of the conductive member and is formed by the edge of the mask, wherein: The distance between the edge of the mask defining the etched region and the edge of the conductive member is 5 μm or more.

2. The method for manufacturing a structure according to claim 1, wherein: In the step of etching the group III nitride constituting the etched region, the etching is performed so that an edge of a recessed portion caused by the etching is formed at a position along an edge defining the etched region.

3. The method for manufacturing a structure according to claim 1 or 2, wherein: The mask is composed of a resist, The etching solution is acidic.

4. The method for manufacturing a structure according to claim 1 or 2, wherein: The group III nitride is etched in a state where the upper surface of the portion of the conductive member provided on the surface to be etched is in contact with the etching liquid.

5. The method for manufacturing a structure according to claim 1 or 2, wherein: The etching object is used as a material of a high electron mobility transistor, The conductive member is used as an electrode of the high electron mobility transistor.

6. The method for manufacturing a structure according to claim 5, wherein: The recessed portion formed by etching the etched region is used as an element isolation groove of the high electron mobility transistor.

7. The method for manufacturing a structure according to claim 1 or 2, wherein: The conductive member is arranged along the outer periphery of the etching object in a plan view.

8. The method for manufacturing a structure according to claim 1 or 2, wherein: The etching object includes a semi-insulating substrate.

9. The method for manufacturing a structure according to claim 8, wherein: The conductive member is provided on a Group III nitride layer formed on the semi-insulating substrate.

10. The method for manufacturing a structure according to claim 9, wherein: An area of ​​the conductive member in contact with the etching solution is 1% or more relative to an entire area of ​​the etched surface which is an upper surface of the group III nitride layer.

11. The method for manufacturing a structure according to claim 1 or 2, wherein: The etching object includes a conductive substrate.

12. The method for manufacturing a structure according to claim 11, wherein: The conductive member is disposed on a surface of the conductive substrate.

13. An intermediate structure comprising: An etching object having an etched surface composed of a conductive group III nitride, wherein an etched region is arranged on the etched surface; a conductive member provided in contact with at least a portion of a surface of a conductive region of the etching object that is electrically connected to the etched region; and a mask formed on the etched surface and made of a non-conductive material, The intermediate structure is immersed in an etchant containing peroxodisulfate ions as an electron-accepting oxidant in a state where the etched region and the conductive member are in contact with the etchant. The edge defining the etched area does not include the edge of the conductive member and is formed by the edge of the mask, wherein: The distance between the edge of the mask defining the etched region and the edge of the conductive member is 5 μm or more.

14. The intermediate structure according to claim 13, wherein: The mask is composed of resist.

15. The intermediate structure according to claim 13 or 14, wherein: The etching object is used as a material of a high electron mobility transistor, The conductive member is used as an electrode of the high electron mobility transistor.

16. The intermediate structure according to claim 13 or 14, wherein: The conductive member is arranged along the outer periphery of the etching object in a plan view.

17. The intermediate structure according to claim 13 or 14, wherein: The etching object includes a semi-insulating substrate.

18. The intermediate structure according to claim 13 or 14, wherein: The etching object includes a conductive substrate.

19. The intermediate structure according to claim 18, wherein: The conductive member is disposed on a surface of the conductive substrate.

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