Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises: a base substrate, a conductive strip and an interlayer insulating layer. The base substrate comprises a bonding area; a plurality of conductive strips are located in the bonding area on the base substrate, each conductive strip comprises a first sub-conductive strip and a second sub-conductive strip which are stacked, and the second sub-conductive strip is located on a side of the first sub-conductive strip away from the base substrate; and the interlayer insulating layer is located between the first sub-conductive strip and the second sub-conductive strip. The interlayer insulating layer comprises a strip hole extending along the extension direction of the conductive strip, and the strip hole is configured to expose the first sub-conductive strip so that the second sub-conductive strip is electrically connected to the first sub-conductive strip. By arranging the strip hole exposing the first sub-conductive strip in the interlayer insulating layer, it is possible to ensure that the first sub-conductive strip has a larger contact area with the second sub-conductive strip, and it is also possible to reduce the probability of the second sub-conductive strip located at the edge of the strip hole being broken, thereby improving the yield of the display substrate.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] Currently, ultra-thin, ultra-narrow borders or even borderless displays are gaining more and more attention, so many manufacturers are developing towards the direction of producing ultra-narrow borders or even borderless displays. Organic light-emitting diode display devices can achieve narrow borders by using technologies such as chip on film (COF) or chip on plastic (COP). Summary of the invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device.

[0004] The embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a display area and a bonding area located at least on one side of the display area; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and connected to the plurality of sub-pixels to provide data signals to the plurality of sub-pixels; a plurality of data leads located in the bonding area and electrically connected to the plurality of data lines; at least one group of conductive strips located in the bonding area and located on a side of the plurality of data leads away from the display area, the at least one group of conductive strips comprising a plurality of conductive strips, at least one of the plurality of conductive strips comprising a first sub-conductive strip and a second sub-conductive strip, the second sub-conductive strip being located on a side of the first sub-conductive strip away from the base substrate; an interlayer insulating layer located between the first sub-conductive strip and the second sub-conductive strip. The first sub-conductive strip is electrically connected to one of the plurality of data leads; the interlayer insulating layer comprises a strip-shaped hole extending along the extension direction of the plurality of conductive strips, and the strip-shaped hole is configured to expose the first sub-conductive strip so that the second sub-conductive strip is electrically connected to the first sub-conductive strip.

[0005] For example, in an embodiment of the present disclosure, the aspect ratio of the strip-shaped hole is not less than 5.

[0006] For example, in an embodiment of the present disclosure, the width of the strip-shaped holes is in the range of 3 to 5 micrometers.

[0007] For example, in an embodiment of the present disclosure, the slope angle between the inner surface of the strip-shaped hole and the base substrate ranges from 30° to 40°.

[0008] For example, in an embodiment of the present disclosure, along the extension direction of at least one of the plurality of conductive strips, the length of the strip-shaped hole is 1-10 micrometers smaller than the length of the second sub-conductive strip in the extension direction.

[0009] For example, in an embodiment of the present disclosure, the strip-shaped hole is a continuous strip-shaped hole extending along an extension direction of at least one of the plurality of conductive strips.

[0010] For example, in an embodiment of the present disclosure, the strip-shaped hole includes a plurality of sub-strip-shaped holes arranged along the extension direction of at least one of the plurality of conductive strips, there is a gap between two adjacent sub-strip-shaped holes in the plurality of sub-strip-shaped holes, and a length of at least one of the plurality of sub-strip-shaped holes is in the range of 15 to 30 microns.

[0011] For example, in an embodiment of the present disclosure, the plurality of sub-strip-shaped holes are uniformly arranged along an extension direction of at least one of the plurality of conductive strips.

[0012] For example, in an embodiment of the present disclosure, the second sub-conductive strip includes a first conductive layer, a second conductive layer, and a third conductive layer which are stacked in sequence.

[0013] For example, in an embodiment of the present disclosure, the materials of the first conductive layer and the third conductive layer include titanium, and the material of the second conductive layer includes aluminum.

[0014] For example, in an embodiment of the present disclosure, the at least one group of conductive strips includes two groups of conductive strips, and the two groups of conductive strips are arranged in a direction away from the display area.

[0015] For example, in an embodiment of the present disclosure, at least one of the multiple sub-pixels includes a pixel circuit and a light-emitting element, and the pixel circuit is located between the substrate and the light-emitting element; the light-emitting element includes a first electrode, a light-emitting layer and a second electrode stacked in sequence, and the second electrode is located on the side of the light-emitting layer facing the substrate; the pixel circuit includes at least one thin film transistor, and the thin film transistor includes a gate located on the substrate, and a source and a drain located on the side of the gate away from the substrate, and the source or drain of the thin film transistor is electrically connected to the second electrode; the gate is arranged on the same layer as the first sub-conductive strip.

[0016] For example, in an embodiment of the present disclosure, the plurality of data lines extend along a first direction, the display substrate further comprises: a plurality of gate lines extend along a second direction, the plurality of data lines are located on a side of the plurality of gate lines away from the base substrate, the first direction intersects with the second direction, and the second sub-conductive strip is disposed in the same layer as the plurality of data lines, the source electrode or the drain electrode.

[0017] For example, in an embodiment of the present disclosure, at least one of the multiple sub-pixels also includes a storage capacitor, the storage capacitor includes two capacitor electrodes, and at least one of the multiple data leads and one of the two capacitor electrodes of the storage capacitor are arranged in the same layer as the gate.

[0018] For example, in an embodiment of the present disclosure, an extension direction of at least one of the plurality of conductive strips is not parallel to the first direction and the second direction.

[0019] For example, in an embodiment of the present disclosure, along the second direction, the maximum width of the first sub-conductive strip is smaller than the maximum width of the second sub-conductive strip, and the maximum width of the strip-shaped hole in the second direction is smaller than the maximum width of the first sub-conductive strip.

[0020] For example, in an embodiment of the present disclosure, the two groups of conductive strips include a first conductive strip group and a second conductive strip group, the first conductive strip group and the second conductive strip group each include a row of conductive strips arranged along the second direction, and the first conductive strip group is located on a side of the second conductive strip group close to the display area.

[0021] For example, in an embodiment of the present disclosure, the plurality of data leads include a plurality of first data leads connected to the first conductive stripe group and a plurality of second data leads connected to the second conductive stripe group, the plurality of first data leads and the plurality of second data leads are arranged alternately, and each of the plurality of second data leads passes through a gap between adjacent conductive strips in the first conductive stripe group.

[0022] An embodiment of the present disclosure provides a display device, comprising a circuit structure and the above display substrate. The circuit structure comprises a third sub-conductive strip, and the third sub-conductive strip is electrically connected to the second sub-conductive strip through a conductive adhesive to write a signal to the second sub-conductive strip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1 A schematic diagram of a local planar structure of a strip electrode in a bonding area of ​​a display substrate;

[0025] Figure 2 For along Figure 1 A schematic diagram of a local cross-sectional structure taken along line AA' shown;

[0026] Figure 3 A schematic diagram of a planar structure of a display substrate provided in an embodiment of the present disclosure;

[0027] Figure 4 for Figure 3 A partial enlarged schematic diagram of a bonding area in a display substrate shown;

[0028] Figure 5 for Figure 4 The enlarged view of the part C shown in one example;

[0029] Figure 6 For along Figure 5 A schematic diagram of the local cross-sectional structure taken along line BB' is shown;

[0030] Figure 7 for Figure 3 A schematic diagram of a partial cross-sectional structure of a display area in a display substrate shown;

[0031] Figure 8 for Figure 3 An enlarged view of the illustrated section C in another example; and

[0032] Fig. 9 It is a schematic diagram of a partial cross-sectional structure of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0035] Figure 1 It is a schematic diagram of the local planar structure of a strip electrode in a bonding area of ​​a display substrate. Figure 2 For along Figure 1 The schematic diagram of the local cross-section structure cut by the AA' line shown in FIG. Figure 1 and Figure 2As shown, the bonding area (non-display area) of the display substrate includes a plurality of strip electrodes (contact pads), each of which includes a first sub-conductive strip 10 and a second sub-conductive strip 20 that are electrically connected, the second sub-conductive strip 20 is located on a side of the first sub-conductive strip 10 away from the base substrate 40, the extension direction of the first sub-conductive strip 10 is the same as the extension direction of the second sub-conductive strip 20, and an interlayer insulating layer 30 is provided between the first sub-conductive strip 10 and the second sub-conductive strip 20. The interlayer insulating layer 30 is provided with a via 31 for exposing the first sub-conductive strip 10 so that the via 31 located in the interlayer insulating layer 30 ( Figure 2 Only the second sub-conductive strip 20 on the interlayer insulating layer 30 between the first sub-conductive strip 10 and the second sub-conductive strip 20 is shown to be electrically connected to the first sub-conductive strip 10 through the via 31. A passivation layer 50 and a flat layer 60 are provided on the side of the second sub-conductive strip 20 away from the first sub-conductive strip 10, and the strip electrodes are configured to be bonded to the electrodes of a circuit structure such as a chip on film (COF) through anisotropic conductive adhesive.

[0036] For example, Figure 2 As shown, the second sub-conductive strip 20 includes a first metal layer 21, a second metal layer 22 and a third metal layer 23 which are stacked. The materials of the first metal layer 21 and the third metal layer 23 may include titanium, and the material of the second metal layer 22 may include aluminum.

[0037] In the research, the inventor of the present application found that the dimension of the via hole 31 parallel to the substrate 40 is 2.1 microns to 2.5 microns, which is relatively small. Therefore, in the process of forming the via hole 31 by etching, exposure and other processes, the inner side surface of the via hole 31 is formed into a slope, and the angle a1 ( Figure 2 The angle of the slope formed on the inner side of the via hole 31 is greater than 50°, that is, the slope angle a1 of the slope formed on the inner side of the via hole 31 is greater than 50°, for example, 70° to 80°. Under certain stress, the via hole 31 with a smaller size mentioned above is prone to fracture at the edge of the via hole 31 due to the larger slope angle of the slope, that is, the steeper slope. For example, the first metal layer 21 of the second sub-conductive strip 20, which is farthest from the substrate 40, is prone to fracture at the edge of the via hole 31, resulting in the exposure of the second metal layer 22, for example, the metal aluminum layer.

[0038] exist Figure 1-Figure 2In the manufacturing process of the display substrate shown, after the patterned flat layer 60 forms an opening 61 exposing the second sub-conductive strip 20, an anode film layer of the organic light-emitting element is formed on the side of the flat layer 60 away from the base substrate 40, and the anode film layer is formed in both the display area and the non-display area. In the process of etching the anode film layer in the non-display area by a wet etching process to form an anode pattern in the display area, the acidic etching solution for etching the anode film layer will be recycled, and a large amount of silver ions will exist in the acidic etching solution. When the first metal layer 21 in the second sub-conductive strip 20 at the edge of the via 31 is broken and the second metal layer 22 is exposed, the aluminum in the second metal layer 22 will undergo a substitution reaction with the silver ions in the above-mentioned acidic etching solution to precipitate silver. In the subsequent cleaning process, the precipitated silver will flow irregularly, resulting in the formation of silver particles on the display substrate. The silver particles may cause a short circuit between two adjacent strip electrodes, affecting the normal lighting of the panel including the above-mentioned display substrate, and will also cause a Mura phenomenon, reducing the yield of the product.

[0039] The embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes: a base substrate, a plurality of sub-pixels located on the base substrate, a plurality of data lines, a plurality of data leads, at least one group of conductive strips, and an interlayer insulating layer. The base substrate includes a display area and a bonding area located at least on one side of the display area; a plurality of sub-pixels are located in the display area; a plurality of data lines are located in the display area and are connected to the plurality of sub-pixels to provide data signals to the plurality of sub-pixels; a plurality of data leads are located in the bonding area and are electrically connected to the plurality of data lines; at least one group of conductive strips is located in the bonding area and is located on a side of the plurality of data leads away from the display area, at least one group of conductive strips includes a plurality of conductive strips, at least one of the plurality of conductive strips includes a first sub-conductive strip and a second sub-conductive strip, the second sub-conductive strip is located on a side of the first sub-conductive strip away from the base substrate; an interlayer insulating layer is located between the first sub-conductive strip and the second sub-conductive strip. The first sub-conductive strip is electrically connected to one of the plurality of data leads; the interlayer insulating layer includes a strip-shaped hole extending along the extension direction of the plurality of conductive strips, and the strip-shaped hole is configured to expose the first sub-conductive strip so that the second sub-conductive strip is electrically connected to the first sub-conductive strip. In the embodiment of the present disclosure, by providing the strip-shaped hole exposing the first sub-conductive strip in the interlayer insulating layer, a larger contact area between the first sub-conductive strip and the second sub-conductive strip can be ensured, and the probability of the second sub-conductive strip located at the edge of the strip-shaped hole being broken can be reduced, thereby improving the yield of the display substrate.

[0040] The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0041] Figure 3 is a schematic diagram of a planar structure of a display substrate provided according to an embodiment of the present disclosure, Figure 4 for Figure 3The partially enlarged schematic diagram of the bonding area in the display substrate shown in FIG. Figure 5 for Figure 4 The enlarged view of the part C shown in one example, Figure 6 For along Figure 5 The schematic diagram of the local cross-section structure cut by BB' is shown in FIG. Figure 3-Figure 6 As shown, the display substrate provided by the embodiment of the present disclosure includes a base substrate 100 and a plurality of conductive strips 200 located on the base substrate 100, each conductive strip 200 includes a first sub-conductive strip 210 and a second sub-conductive strip 220 arranged in a stacked manner, the second sub-conductive strip 220 is located on a side of the first sub-conductive strip 210 away from the base substrate 100, the first sub-conductive strip 210 and the second sub-conductive strip 220 extend in the same direction, and an interlayer insulating layer 301 is provided between the first sub-conductive strip 210 and the second sub-conductive strip 220. The base substrate 100 includes a display area 110 and a peripheral area located around the display area 110, the peripheral area includes a bonding area 120 for bonding the display substrate to a circuit structure such as a chip on film (COF). The conductive strip 200 including the first sub-conductive strip 210 and the second sub-conductive strip 220 is located in the bonding area 120, and the orthographic projection of the second sub-conductive strip 220 on the base substrate 100 overlaps with the orthographic projection of the first sub-conductive strip on the base substrate 100. As shown Figure 3-Figure 6 As shown, the interlayer insulating layer 301 includes a strip-shaped hole 310 extending along the extension direction of the conductive strip 200, and the strip-shaped hole 310 is configured to expose the first sub-conductive strip 210, so that the second sub-conductive strip 220 is electrically connected to the first sub-conductive strip 210. In the embodiment of the present disclosure, by providing the strip-shaped hole exposing the first sub-conductive strip in the interlayer insulating layer, a larger contact area between the first sub-conductive strip and the second sub-conductive strip can be ensured, and the probability of the second sub-conductive strip located at the edge of the strip-shaped hole being broken can be reduced, thereby improving the yield of the display substrate.

[0042] The plane shape of the conductive strip parallel to the substrate is a strip shape, and the extension direction of the conductive strip is the extension direction of the long side of the plane shape. The plane shape of the strip hole parallel to the substrate is a strip shape, and the length and width of the subsequent strip hole refer to the length and width of the plane shape parallel to the substrate.

[0043] A plurality of strip-shaped holes are arranged in the interlayer insulating layer, and the plurality of strip-shaped holes correspond to the plurality of conductive strips one by one, and each strip-shaped hole is used to expose the first sub-conductive strip in each conductive strip.

[0044] For example, the material of the interlayer insulating layer 301 may include insulating materials such as silicon oxide or silicon nitride.

[0045] For example, Figure 3As shown, the display area 110 is provided with a data line 400 extending along a first direction (Y direction) and a gate line 500 extending along a second direction (X direction). The data line 400 is located on a side of the gate line 500 away from the base substrate 100, and an interlayer insulating layer 301 can be provided between the data line 400 and the gate line 500.

[0046] For example, the first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular. The first direction and the second direction in the embodiment of the present disclosure can be interchangeable.

[0047] For example, Figure 3-Figure 6 As shown, the extension direction of the conductive strip 200 is not parallel to the first direction and the second direction. For example, the extension direction of the conductive strip 200 and the first direction may have an angle of, for example, 8° to 10°. For example, the end of the conductive strip 200 close to the display area 110 is closer to the center line of the display substrate extending along the first direction than the end of the conductive strip 200 away from the display area, so as to facilitate connection with the data line. For example, the conductive strips 200 located on both sides of the center line of the display substrate extending along the first direction may be symmetrically distributed relative to the center line.

[0048] For example, the bonding area 120 is located on one side of the display area 110 and is used to electrically connect the external circuit to the display substrate through a bonding process. For example, the external circuit may include a flexible circuit board (e.g., Chip On Film, COF for short) on which a chip is mounted, and a control chip or a driver chip is arranged on the flexible circuit board. The bonding area may also be used to directly electrically connect to the chip.

[0049] For example, the conductive strip 200 located in the bonding area 120 may be a contact pad directly bonded to the driver chip, and the substrate 100 may be a flexible substrate. By bending the flexible substrate at the bonding area 120 toward the back of the flexible substrate away from the data line 400, a narrow frame may be achieved. For example, the conductive strip 200 located in the bonding area 120 may also be a contact pad for bonding to a chip-on-film.

[0050] For example, the data line 400 can be connected to the plurality of conductive strips 200 in a one-to-one correspondence through the plurality of data leads 410 located in the bonding area 120 , so that the data line 400 is electrically connected to a circuit structure such as a driving chip or a flexible circuit board.

[0051] For example, Figure 3-Figure 4As shown, the plurality of conductive strips 200 include a first conductive strip group 2201 and a second conductive strip group 2202. The first conductive strip group 2201 and the second conductive strip group 2202 both include a row of conductive strips 200 arranged along the second direction. The first conductive strip group 2201 is located on a side of the second conductive strip group 2202 close to the display area 110. The embodiment of the present disclosure takes the conductive strips arranged in two rows along the second direction as an example, but is not limited thereto. It may also be one row or more rows, that is, the conductive strips may be arranged in one or more conductive strip groups.

[0052] For example, in order to reduce the size of the bonding area along the Y direction, a row of conductive strips, ie, a conductive strip group, may be provided.

[0053] For example, Figure 3-Figure 4 As shown, the plurality of data leads 410 include a plurality of first data leads 411 connected to the first conductive stripe group 2201 and a plurality of second data leads 412 connected to the second conductive stripe group 2202. The plurality of first data leads 411 and the plurality of second data leads 412 are alternately arranged along the second direction, that is, the first data leads 411 may be connected to the odd-numbered data lines 400, and the second data leads 412 may be connected to the even-numbered data lines 400. The disclosed embodiment is not limited thereto, and the first data leads may be connected to the even-numbered data lines, and the second data leads may be connected to the odd-numbered data lines.

[0054] For example, Figure 3-Figure 4 As shown, a gap is provided between two adjacent conductive strips 200 in each conductive strip group, and each second data lead 412 passes through the gap between adjacent conductive strips 200 in the first conductive strip group 2201 to be connected to the data line 400. In the embodiment of the present disclosure, by providing two conductive strip groups, and each second data lead passes through the gap between adjacent conductive strips in the first conductive strip group to be connected to the data line, the distance between two adjacent data leads can be reduced, and the fan-shaped wiring area can be avoided as much as possible, so as to achieve a narrow frame design.

[0055] For example, a third data lead (not shown in the figure) may also be arranged on the side of the first conductive strip group facing the second conductive strip group, and the third data lead extends from the side of the conductive strips in the first conductive strip group away from the display area to pass through the interval between two adjacent conductive strips in the second conductive strip group, that is, along the second direction, the third data lead and the second data lead are alternately arranged to ensure that the data leads between the first conductive strip group and the second conductive strip group are evenly arranged. The third data lead is only connected to the conductive strips in the first conductive strip group.

[0056] For example, when an active semiconductor layer is arranged on a side of the first conductive strip away from the base substrate, an antistatic portion can be arranged on a side of each conductive strip away from the display area. The antistatic portion includes a portion of the first conductive strip away from the display area and the active semiconductor layer. The portion is connected to the active semiconductor layer to increase resistance and play an antistatic role.

[0057] For example, Figure 3-Figure 6 As shown, the second sub-conductive strip 220 and the data line 400 are in the same layer. For example, the second sub-conductive strip 220 and the data line 400 can be arranged in the same layer and made of the same material. Here and in the following, "same layer" refers to the relationship between multiple film layers formed by the same material after the same step (for example, one-step patterning process). Here, "same layer" does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0058] For example, the first sub-conductive strip 210 and the gate line 500 may be in the same layer and made of the same material.

[0059] For example, at least a portion of the first data lead lines 411 may be disposed in the same layer as the first sub-conductive stripes 210 of the conductive stripes 200 in the first conductive stripe group 2201, and at least a portion of the second data lead lines 412 may be disposed in the same layer as the first sub-conductive stripes 210 of the conductive stripes 200 in the second conductive stripe group 2202. That is, each conductive strip 200 may be connected to the corresponding data line 400 through the first sub-conductive strips 210 connected to the data lead lines 410, so that the circuit structure provides data signals for the data lines.

[0060] For example, Figure 3-Figure 6 As shown, a passivation layer 610 and a planarization layer 620 are provided on the side of the second sub-conductive strip 220 away from the base substrate 100. An opening 621 for exposing the second sub-conductive strip 220 is provided in the passivation layer 610 and the planarization layer 620, and an electrode strip in a circuit structure such as a chip on film (COF) is bonded to the second sub-conductive strip 220 through the opening 621.

[0061] For example, the passivation layer 610 and the planarization layer 620 cover the edges around the second sub-conductive strips 220 to prevent the edges around the second sub-conductive strips 220 from being damaged in the subsequent process of manufacturing the display substrate.

[0062] For example, Figure 5-Figure 6As shown, along the second direction, the size of the first sub-conductive strip 210 is smaller than the size of the second sub-conductive strip 220, that is, along the second direction, the width of the first sub-conductive strip 210 is smaller than the width of the second sub-conductive strip 220. Along the second direction, the second sub-conductive strip 220 covers the edge of the first sub-conductive strip 210, reducing the overlap area of ​​the passivation layer 610 and the planarization layer 630 located at the edge of the second sub-conductive strip 220 and the first sub-conductive strip 210, thereby preventing the thickness of the film layer covered by the passivation layer 610 and the planarization layer 620 located at the edge of the second sub-conductive strip 220 from being too large and affecting the thickness of the display substrate.

[0063] For example, Figure 7 for Figure 3 A schematic diagram of a partial cross-sectional structure of a display area in a display substrate is shown in FIG. Figure 7 As shown, the display substrate also includes a light-emitting element 700 located in the display area 110 of the base substrate 100 and a pixel circuit 1120 for driving the light-emitting element 700. For example, the pixel circuit is located between the light-emitting element and the base substrate. For example, the pixel circuit may include a thin film transistor, a storage capacitor, etc., and may be implemented in various different types, such as a 2T1C type (i.e., including two thin film transistors and a storage capacitor), and may further include more transistors and / or capacitors on the basis of the 2T1C type to have functions such as compensation, reset, light emission control, and detection. The embodiments of the present disclosure do not limit the pixel circuit. For example, in some embodiments, the thin film transistor directly electrically connected to the light-emitting element may be a driving transistor or a light emission control transistor, etc.

[0064] For example, Figure 6-Figure 7 As shown, the display substrate further includes a buffer layer 1121 located on the base substrate 100, and the pixel circuit 1120 includes an active layer 1122 located on the buffer layer 1121, a first gate insulating layer 1128 located on the side of the active layer 1122 away from the base substrate 100, and a gate 11211 located on the first gate insulating layer 1128, the gate 11211 is a gate of a thin film transistor (such as a driving transistor or a light emitting control transistor) directly connected to the light emitting element, and the gate is arranged in the same layer as the first sub-conductive strip 210. Therefore, the gate 11211 and the first sub-conductive strip 210 can be formed in the same preparation process, for example, by using the same material layer through a patterning process.

[0065] For example, Figure 6-Figure 7As shown, the pixel circuit further includes a second gate insulating layer 302 located on the side of the gate electrode 11211 away from the base substrate 100, an interlayer insulating layer 301 located on the second gate insulating layer 302, and a source electrode 1125 and a drain electrode 1126 located on the interlayer insulating layer 301. The buffer layer 1121 in the display area 110 and the bonding area 120 can be an integral structure or a film layer separated from each other and located at the same layer. The first gate insulating layer 1128 in the display area 110 and the bonding area 120 can be an integral structure or a film layer separated from each other and located at the same layer; the second gate insulating layer 302 in the display area 110 and the bonding area 120 can be an integral structure or a film layer separated from each other and located at the same layer; the interlayer insulating layer 301 in the display area 110 and the bonding area 120 can be an integral structure or a film layer separated from each other and located at the same layer. The buffer layer 1121 serves as a transition layer, which can prevent harmful substances in the base substrate from invading the interior of the display substrate and increase the adhesion of the film layer in the display substrate on the base substrate.

[0066] For example, the buffer layer 1121 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The interlayer insulating layer 301, the second gate insulating layer 302, and the first gate insulating layer 1128 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the interlayer insulating layer 301, the second gate insulating layer 302, and the first gate insulating layer 1128 may be the same or different.

[0067] For example, in some examples of the above embodiments of the present disclosure, Figure 7 As shown, the active layer 1122 may include a source region 1123 and a drain region 1124, and a channel region between the source region 1123 and the drain region 1124. The interlayer insulating layer 301, the second gate insulating layer 302 and the first gate insulating layer 1128 have vias to expose the source region 1123 and the drain region 1124. The source 1125 and the drain 1126 are electrically connected to the source region 1123 and the drain region 1124 through the vias, respectively. The drain 1126 and the source 1125 are respectively the first electrode and the second electrode of the thin film transistor directly electrically connected to the light emitting element 700, for example, the drain of the thin film transistor is electrically connected to the light emitting element 700. The portion of the drain 1126 and the source 1125 located in the interlayer insulating layer 301 away from the base substrate 100 is arranged in the same layer as the second sub-conductive strip 220.

[0068] The thin film transistors in the embodiments of the present disclosure may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors. The source and drain of the thin film transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. The drain and drain of all or part of the thin film transistors in the embodiments of the present disclosure may be interchangeable according to actual needs.

[0069] For example, Figure 7 As shown, the gate 11211 overlaps with the channel region between the source region 1123 and the drain region 1124 in the active layer 1122 in a direction perpendicular to the substrate 100. The planar layer 620 and the passivation layer 610 are located above the source 1125 and the drain 1126, and are used to planarize the surface of the pixel circuit away from the substrate. A via 1131 is formed in the planar layer 620 and the passivation layer 610 to expose the source 1125 or the drain 1126 (as shown in the figure). The passivation layer can protect the source and drain of the pixel circuit from being corroded by water vapor.

[0070] For example, the material of the active layer 1122 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 11211 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium. For example, the multilayer structure may be a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti). The material of the source 1125 and the drain 1126 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium. The embodiments of the present disclosure do not specifically limit the materials of each functional layer. Figure 7 It is schematically shown that the active layer 1122 is located on the side of the gate 11211 facing the substrate, but the invention is not limited thereto. The active layer may also be located on the side of the gate away from the substrate.

[0071] For example, the material of the passivation layer 610 may include an organic insulating material or an inorganic insulating material, such as a silicon nitride material, which has a relatively high dielectric constant and good hydrophobicity, and can well protect the pixel circuit from being corroded by water vapor.

[0072] For example, Figure 6-Figure 7 As shown, a light-emitting element 700 is formed on the planarization layer 620, that is, the light-emitting element 700 is arranged on the side of the planarization layer 620 away from the base substrate 100. The light-emitting element 700 includes a first electrode 710, a light-emitting layer 730 and a second electrode 720 which are stacked in sequence. The second electrode 720 is located on the side of the light-emitting layer 730 facing the base substrate 100 and is configured to be connected to the thin film transistor. The display substrate also includes a pixel defining layer 630, and the opening of the pixel defining layer 630 exposes a portion of the second electrode 720. When the light-emitting layer 730 is formed in the opening of the pixel defining layer 630, the light-emitting layer 730 contacts the second electrode 720, so that this portion can drive the light-emitting layer 730 to emit light to form an effective light-emitting area.

[0073] In addition, the display substrate further includes a storage capacitor 1160, and the storage capacitor 1160 may include a first capacitor electrode 1161 and a second capacitor electrode 1162. The first capacitor electrode 1161 is disposed between the first gate insulating layer 1128 and the second gate insulating layer 302, and the second capacitor electrode 1162 is disposed between the second gate insulating layer 302 and the interlayer insulating layer 301. The first capacitor electrode 1161 and the second capacitor electrode 1162 are stacked and at least partially overlapped in a direction perpendicular to the base substrate 100. The first capacitor electrode 1161 and the second capacitor electrode 1162 form a storage capacitor using the second gate insulating layer 302 as a dielectric material. The first storage capacitor electrode 1161 is disposed in the same layer as the gate electrode 11211 in the pixel circuit 1120 and the first sub-conductive strip 210 in the bonding area 120. For example, the first storage capacitor electrode 1161 is disposed in the same layer as the gate electrode 11211 in the pixel circuit 1120 and at least one of the plurality of data leads. The embodiments of the present disclosure are not limited thereto. For example, the first capacitor electrode and the second capacitor electrode of the storage capacitor may also be located in other layers, thereby obtaining sub-pixels of different structures. For example, the first capacitor electrode of the storage capacitor may still be arranged in the same layer as the gate electrode, while the second capacitor electrode of the storage capacitor may be arranged in the same layer as the source and drain electrodes in the thin film transistor, thereby forming a storage capacitor with the first capacitor electrode and the second capacitor electrode using the stack of the second gate insulating layer and the interlayer insulating layer as dielectric materials.

[0074] For example, Figure 7 As shown, the display substrate may further include an encapsulation layer 1150 disposed on the light emitting element 700. The encapsulation layer 1150 seals the light emitting element 700, thereby reducing or preventing degradation of the light emitting element 700 caused by moisture and / or oxygen included in the environment. The encapsulation layer 1150 may be a single-layer structure or a composite layer structure, wherein the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. For example, the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, an organic encapsulation layer 1152, and a second inorganic encapsulation layer 1153 disposed in sequence. The encapsulation layer 1150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the conductive strips.

[0075] For example, the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to flatten the surface of the display substrate, and to relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that intrude into the interior.

[0076] For example, Figure 6-Figure 7 As shown, the film layer where the second electrode 720 is located is located on a side of the second sub-conductive strip 220 away from the base substrate 100 , that is, the second electrode 720 is located on a side of the planar layer 620 away from the second sub-conductive strip 220 .

[0077] For example, Figure 6-Figure 7 As shown, the film layer for forming the second electrode 720 of the light-emitting element 700 can be deposited on the side of the flat layer 620 away from the base substrate 100. Since the opening 621 of the flat layer 620 exposes the second sub-conductive strip 220, the film layer for forming the second electrode includes a portion deposited in the display area and the non-display area, and the portion located in the non-display area includes a portion located on the second sub-conductive strip 220. In the process of etching the film layer for forming the second electrode by a wet etching process to form an anode pattern located in the display area, the acidic etching solution for etching the film layer for forming the second electrode will be recycled, and a large amount of silver ions exist in the acidic etching solution.

[0078] For example, Figure 3-Figure 6 As shown, the second sub-conductive strip 220 includes three stacked conductive layers, and the material of the second conductive layer 222 in the three conductive layers includes aluminum. For example, the material of the first conductive layer 221 and the third conductive layer 223 in the three conductive layers includes titanium. The stacked structure of the second sub-conductive strip 220 in the embodiment of the present disclosure and the materials of each layer can be the same as Figure 1-Figure 2 The stacked structure and the materials of each layer of the second sub-conductive strips 20 in the display substrate shown are the same.

[0079] For example, Figure 3-Figure 6 As shown, the aspect ratio of the strip hole 310 is not less than 5. For example, the width of the strip hole 310 is in the range of 3 to 5 microns. The "aspect ratio" of the above-mentioned strip hole 310 may refer to the ratio of the length of the strip hole 310 along the extension direction of the conductive strip 200 to the width of the strip hole 310 along the arrangement direction of the conductive strip 200 (for example, the second direction). In the embodiment of the present disclosure, the extension direction of the conductive strip is the extension direction of the strip hole and the long side of the conductive strip, and the second direction is the extension direction of the strip hole and the short side of the conductive strip. Then, the size of the strip hole in the second direction may also be referred to as the width of the strip hole in the second direction, and the size of the conductive strip in the second direction may also be referred to as the width of the conductive strip in the second direction.

[0080] Relative to Figure 2The via hole 31 with a smaller size in the interlayer insulating layer 30 between two layers of conductive strips in the display substrate shown in the figure, in the embodiment of the present disclosure, the via hole in the interlayer insulating layer 301 between the first sub-conductive strip and the second sub-conductive strip is set as a strip hole 310, and the aspect ratio of the strip hole 310 is not less than 5, and the width of the strip hole 310 is in the range of 3 to 5 microns. Thus, while increasing the contact area between the first sub-conductive strip 210 and the second sub-conductive strip 220 to reduce the conductive strip impedance, the probability of the first conductive layer 221 being broken at the edge of the strip hole 310 can also be reduced, preventing the second conductive layer 222 from being replaced by silver ions in the subsequent acidic etching solution, which affects the yield of the display substrate.

[0081] For example, Figure 3-Figure 6 As shown, along the extension direction of the second sub-conductive strip 220, the length of the strip hole 310 is 1-10 microns smaller than the length of the second sub-conductive strip 220. For example, the length of the second sub-conductive strip 220 may be 145 microns, and the length of the strip hole 310 may be 135 microns. For example, the length of the second sub-conductive strip 220 may be 650 microns, and the length of the strip hole 310 may be 640 microns. For example, along the extension direction of the second sub-conductive strip 210, the length of the strip hole 310 is 4-6 microns smaller than the length of the second sub-conductive strip 220.

[0082] Figure 1-Figure 2 The size of the via hole 31 in the flat layer 30 shown is relatively small, which will result in the second sub-conductive strip 20 formed in the via hole 31 not being able to effectively contact with the subsequent circuit structure, so that the contact area between the second sub-conductive strip 20 and the circuit structure is small, the contact resistance is large, and the connectivity is poor. The size of the strip hole 310 in the embodiment of the present disclosure is relatively large, and the second sub-conductive strip 220 located in the strip hole 310 can achieve a better electrical connection effect with the subsequent circuit structure through anisotropic conductive adhesive. In addition, compared with Figure 2 As shown in the via hole 31, the strip hole 310 in the embodiment of the present disclosure can accommodate more anisotropic conductive adhesive, which increases the contact area between the anisotropic conductive adhesive and the second sub-conductive strip, thereby increasing the bonding strength between the anisotropic conductive adhesive and the second sub-conductive strip, thereby ensuring the quality of the display substrate.

[0083] For example, Figure 3-Figure 6 As shown, the included angle a2 ( Figure 6As shown) is in the range of 30° to 40°. For example, in the process of forming the strip hole 310 by etching, exposure and other processes, the inner surface of the strip hole 310 is formed into a slope, and the slope angle a2 of the slope is in the range of 30° to 40°. For example, the cross section of the strip hole 310 cut by the surface perpendicular to the substrate includes a hypotenuse, and the angle a2 between the hypotenuse and the substrate is in the range of 30° to 40°. The inner surface of the strip hole 310 can be a plane or a curved surface. When the inner surface of the strip hole is a plane, the hypotenuse is a straight edge; when the inner surface of the strip hole is a curved surface, the hypotenuse is a curved edge. At this time, taking the slope of the line connecting the midpoint at the position of half the height of the strip hole and the intersection of the curved edge of the strip hole and the first sub-conductive strip as an example of the slope of the hypotenuse of the strip hole, the angle between the above-mentioned line and the substrate is the inclination angle a2 of the inner surface. Relative to Figure 2 In the case where the angle between the inner side surface of the via hole 31 in the interlayer insulating layer 30 shown in the figure and the base substrate 40 is in the range of 70° to 80°, the length and width of the strip hole 310 are designed to be larger in the embodiment of the present disclosure, so that the angle between the inner side surface of the strip hole 310 and the base substrate 100 can be reduced, that is, the inclination angle of the inner side surface of the strip hole 310 becomes smaller, and the slope formed by the inner side surface of the strip hole 310 becomes gentler, which can prevent the second sub-conductive strip 220 subsequently formed in the strip hole 310 from breaking at the edge position of the strip hole 310, thereby improving the yield of the display substrate.

[0084] For example, Figure 3-Figure 6 As shown, the strip-shaped holes 310 are continuous strip-shaped holes extending along the extension direction of the first sub-conductive strip 210. That is, each first sub-conductive strip 210 corresponds to a continuous strip-shaped hole 310, and the first sub-conductive strip 210 is electrically connected to the second sub-conductive strip 220 through the continuous strip-shaped hole 310.

[0085] For example, Figure 3-Figure 6 As shown, the orthographic projection of the strip-shaped hole 310 on the base substrate 100 is located within the orthographic projection of the first sub-conductive strip 210 on the base substrate 100. For example, the orthographic projection of the strip-shaped hole 310 on the base substrate 100 is located in the middle of the orthographic projection of the second sub-conductive strip 220 on the base substrate 100, so that the second sub-conductive strip 220 located in the strip-shaped hole 310 can have a good electrical connection with the first sub-conductive strip 210.

[0086] Figure 8 for Figure 3 The shown part C is an enlarged view of another example. Figure 8 The example shown is similar to Figure 5 The example shown differs in that Figure 8The strip-shaped holes 310 shown include a plurality of sub-strip-shaped holes 311 arranged along the extension direction of the first sub-conductive strip 210, with intervals between adjacent sub-strip-shaped holes 311, and a length of at least one sub-strip-shaped hole 311 is in the range of 15 to 30 micrometers. Figure 2 In the case where a plurality of small-sized via holes are arranged in the flat layer of the display substrate shown in the figure, the plurality of sub-strip holes arranged in the flat layer in the embodiment of the present disclosure can not only increase the contact area between the first sub-conductive strip and the second sub-conductive strip to reduce the impedance of the conductive strip, but also reduce the probability of the first conductive layer of the second sub-conductive strip being broken at the edge of the sub-strip hole, thereby preventing the second conductive layer from being replaced by silver ions in the subsequent acidic etching solution.

[0087] For example, the angle between the inner surface of the sub-strip hole 311 and the base substrate 100 is in the range of 30° to 40°, that is, the inclination angle of the inner surface of the sub-strip hole 311 is 30° to 40°. In the embodiment of the present disclosure, the length of the sub-strip hole is set in the range of 15 to 30 microns, which can reduce the angle between the inner side surface of the sub-strip hole and the base substrate, that is, the inclination angle of the inner side surface of the sub-strip hole is reduced, which can prevent the second sub-conductive strip subsequently formed in the sub-strip hole from breaking at the edge of the sub-strip hole, thereby improving the yield of the display substrate.

[0088] In the embodiment of the present disclosure, the size of the sub-strip hole is relatively large, and the second sub-conductive strip located in the sub-strip hole can achieve a better electrical connection effect with the circuit structure through the anisotropic conductive adhesive. In addition, each sub-strip hole in the embodiment of the present disclosure can accommodate more anisotropic conductive adhesive, which increases the contact area between the anisotropic conductive adhesive and the second sub-conductive strip, thereby increasing the bonding strength between the anisotropic conductive adhesive and the second sub-conductive strip, thereby ensuring the quality of the display substrate.

[0089] For example, Figure 8 As shown, the plurality of sub-strip-shaped holes 311 are evenly arranged along the extension direction of the first sub-conductive strip 210 , thereby ensuring uniformity of electrical connection between the electrode strips of the circuit structure and the second sub-conductive strips.

[0090] Another embodiment of the present disclosure provides a display device, which may include a display substrate in any of the above embodiments. Fig. 9 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display device provided according to an embodiment of the present disclosure. Fig. 9 As shown, the display device includes the above display substrate and a circuit structure 800 . The circuit structure 800 includes a third sub-conductive strip 810 . The third sub-conductive strip 810 is electrically connected to the second sub-conductive strip 220 through a conductive adhesive 900 to write a signal to the second sub-conductive strip 220 .

[0091] For example, Fig. 9As shown, the circuit structure 800 includes a plurality of third sub-conductive strips 810 , and the plurality of third sub-conductive strips 810 are connected to the plurality of second sub-conductive strips 220 in a one-to-one correspondence. Fig. 9 Only the electrical connection between one third sub-conductive strip 810 and one second sub-conductive strip 220 is schematically shown.

[0092] For example, Fig. 9 As shown, the third sub-conductive strip 810 of the circuit structure 800 extends into the opening defined by the planar layer 620 to achieve electrical connection with the second sub-conductive strip 220 through the anisotropic conductive adhesive 900 .

[0093] For example, the circuit structure 800 may include a flexible circuit board. For example, the flexible circuit board may be bonded to the bonding area of ​​the display substrate, and the control chip may be mounted on the flexible circuit board, thereby being electrically connected to the display area. For example, the circuit structure may include a chip-on-film.

[0094] For example, the display device may adopt COP (Chip On Plastic) technology, and the circuit structure 800 may include a control chip, which may be directly bonded to the bonding area, thereby being electrically connected to the display area. For example, the substrate may be a flexible substrate, and by bending the flexible substrate at the bonding area toward the side of the flexible substrate away from the data line, that is, bending the flexible substrate toward the back, the occupation of the "chin" space by the display device may be minimized, thereby achieving a narrow frame.

[0095] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0096] For example, the display device provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0097] There are a few points to note:

[0098] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0099] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0100] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a bonding area located at at least one side of the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and connected to the plurality of sub-pixels to provide data signals to the plurality of sub-pixels; a plurality of data leads, located in the bonding area and electrically connected to the plurality of data lines; At least one group of conductive strips is located in the bonding area and on a side of the plurality of data leads away from the display area, the at least one group of conductive strips includes a plurality of conductive strips, at least one of the plurality of conductive strips includes a first sub-conductive strip and a second sub-conductive strip, the second sub-conductive strip is located on a side of the first sub-conductive strip away from the substrate; an interlayer insulating layer, located between the first sub-conductive strip and the second sub-conductive strip; Wherein, the first sub-conductive strip is electrically connected to one of the plurality of data lead lines; The interlayer insulating layer includes a strip-shaped hole extending along an extension direction of the plurality of conductive strips, and the strip-shaped hole is configured to expose the first sub-conductive strip so that the second sub-conductive strip is electrically connected to the first sub-conductive strip; The aspect ratio of the strip-shaped hole is not less than 5, and the slope angle between the inner surface of the strip-shaped hole and the substrate is in the range of 30° to 40°; The portion of the second sub-conductive strip located in the strip-shaped hole forms a recess, and the second sub-conductive strip is configured to be bound to the circuit structure by at least an anisotropic conductive adhesive disposed in the recess.

2. The display substrate according to claim 1, wherein: The width of the strip-shaped holes is in the range of 3 to 5 microns.

3. The display substrate according to claim 1, wherein: Along the extension direction of at least one of the plurality of conductive strips, the length of the strip-shaped hole is 1-10 micrometers smaller than the length of the second sub-conductive strip in the extension direction.

4. The display substrate according to claim 3, wherein: The strip-shaped hole is a continuous strip-shaped hole extending along an extending direction of at least one of the plurality of conductive strips.

5. The display substrate according to claim 1, wherein: The strip-shaped holes include a plurality of sub-strip-shaped holes arranged along the extension direction of at least one of the plurality of conductive strips, a gap exists between two adjacent sub-strip-shaped holes in the plurality of sub-strip-shaped holes, and a length of at least one of the plurality of sub-strip-shaped holes is in the range of 15 to 30 micrometers.

6. The display substrate according to claim 5, wherein: The plurality of sub-strip-shaped holes are uniformly arranged along an extension direction of at least one of the plurality of conductive strips.

7. The display substrate according to any one of claims 1 to 6, wherein: The second sub-conductive strip includes a first conductive layer, a second conductive layer and a third conductive layer which are stacked in sequence.

8. The display substrate according to claim 7, wherein: The materials of the first conductive layer and the third conductive layer include titanium, and the material of the second conductive layer includes aluminum.

9. The display substrate according to claim 7, wherein: The at least one group of conductive strips includes two groups of conductive strips, and the two groups of conductive strips are arranged in a direction away from the display area.

10. The display substrate according to claim 9, wherein: At least one of the plurality of sub-pixels comprises a pixel circuit and a light-emitting element, wherein the pixel circuit is located between the substrate and the light-emitting element; The light emitting element comprises a first electrode, a light emitting layer and a second electrode which are stacked in sequence, wherein the second electrode is located on a side of the light emitting layer facing the base substrate; The pixel circuit comprises at least one thin film transistor, wherein the thin film transistor comprises a gate located on the substrate, a source and a drain located on a side of the gate away from the substrate, and the source or drain of the thin film transistor is electrically connected to the second electrode; The gate is arranged in the same layer as the first sub-conductive strip.

11. The display substrate according to claim 10, wherein: The plurality of data lines extend along a first direction, and the display substrate further comprises: A plurality of gate lines extending along a second direction, the plurality of data lines being located on a side of the plurality of gate lines away from the substrate, the first direction intersecting with the second direction, Wherein, the second sub-conductive strip is arranged in the same layer as the plurality of data lines, the source electrode or the drain electrode.

12. The display substrate according to claim 11, wherein: At least one of the plurality of sub-pixels further includes a storage capacitor, wherein the storage capacitor includes two capacitor electrodes. At least one of the plurality of data leads, one of the two capacitor electrodes of the storage capacitor and the gate are arranged in the same layer.

13. The display substrate according to claim 11, wherein: An extension direction of at least one of the plurality of conductive strips is not parallel to either the first direction or the second direction.

14. The display substrate according to claim 11, wherein: Along the second direction, the maximum width of the first sub-conductive strip is smaller than the maximum width of the second sub-conductive strip, and the maximum width of the strip-shaped hole in the second direction is smaller than the maximum width of the first sub-conductive strip.

15. The display substrate according to claim 11, wherein: The two groups of conductive strips include a first conductive strip group and a second conductive strip group. The first conductive strip group and the second conductive strip group each include a row of conductive strips arranged along the second direction. The first conductive strip group is located on a side of the second conductive strip group close to the display area.

16. The display substrate according to claim 15, wherein: The plurality of data lead lines include a plurality of first data lead lines connected to the first conductive stripe group and a plurality of second data lead lines connected to the second conductive stripe group, the plurality of first data lead lines and the plurality of second data lead lines are alternately arranged, and each of the plurality of second data lead lines passes through a space between adjacent conductive stripes in the first conductive stripe group.

17. A display device comprising a circuit structure and the display substrate according to any one of claims 1 to 16, in, The circuit structure includes a third sub-conductive strip, and the third sub-conductive strip is electrically connected to the second sub-conductive strip through a conductive adhesive so as to write a signal to the second sub-conductive strip.

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