Memory device with shared read / write data line for 2-transistor vertical memory cell

Abstract

Some embodiments include devices and methods of forming the devices. One of the devices includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. A portion of the conductive line spans a portion of the first region of the first transistor and a portion of the second region of the second transistor.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 782,142, filed on December 26, 2018, which is incorporated herein by reference in its entirety. Background Art

[0003] Memory devices are widely used in computers and many other electronic items to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. Examples of volatile memory devices include dynamic random access memory (DRAM) devices. Examples of non-volatile memory devices include flash memory devices (e.g., flash memory sticks). Memory devices generally have many memory cells that store information. In volatile memory devices, if the supply power is disconnected from the memory device, the information stored in the memory cells is lost. In non-volatile memory devices, the information stored in the memory cells is retained even if the supply power is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of electric charge in a capacitor structure contained in a memory cell. As the demand for device storage density increases, many conventional technologies provide ways to reduce the size of the memory cell in order to increase the device storage density for a given device area. However, if the memory cell size shrinks to a certain size, then physical limitations and manufacturing constraints may pose challenges to such conventional technology settings. Unlike some conventional memory devices, the memory devices described herein include features that can overcome the challenges faced by conventional technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram is shown of an apparatus in the form of a memory device including volatile memory cells according to some embodiments described herein.

[0006] Figure 2 A schematic diagram illustrating a portion of a memory device including a memory array of two-transistor (2T) memory cells according to some embodiments described herein.

[0007] Figure 3 1 shows a diagram including example voltages used during a read operation of a memory device according to some embodiments described herein. Figure 2 Memory device.

[0008] Figure 4 1 shows example voltages used during a write operation of a memory device according to some embodiments described herein. Figure 2Memory device.

[0009] Figure 5 , Figure 6 , Figure 7 and Figure 8 The present invention shows some embodiments according to the present invention. Figure 2 Different views of the structure of a memory device.

[0010] FIG. 9A to FIG. 9R A process of forming a memory device according to some embodiments described herein is shown.

[0011] FIG. 10A to FIG. 10E shows a process of forming another memory device according to some embodiments described herein, FIG. 10A to FIG. 10E The process of forming a memory device shown may be to form FIG. 9A to FIG. 9R The process of storing the memory device varies.

[0012] Fig.11A , Fig. 11B and Fig. 11C Different views of a memory device structure including multiple stacks of memory cells are shown according to some embodiments described herein. DETAILED DESCRIPTION

[0013] The memory devices described herein include volatile memory cells, wherein each of the memory cells may include two transistors (2T). One of the two transistors has a charge storage structure that may form a memory element of the memory cell to store information. The memory devices described herein may have a structure that allows the size of the memory device to be relatively smaller than the size of similar conventional memory devices (e.g., a 4F2 cell footprint). The described memory devices may include signal access lines that control the two transistors of the memory cell. This may reduce power consumption and improve processing. Reference is made below to Figures 1 to 10E Other improvements and benefits of the described memory device and variations thereof are discussed.

[0014] Figure 1A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells according to some embodiments described herein is shown. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 is a volatile memory device (e.g., a DRAM device), such that the memory cells 102 are volatile memory cells. Therefore, if the supply power (e.g., the supply voltage Vcc) is disconnected from the memory device 100, the information stored in the memory cells 102 may be lost (e.g., invalid). Hereinafter, Vcc is referred to as representing some voltage level, however, it is not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator (e.g., Vcc) that generates an internal voltage based on Vcc, the memory device 100 may be disconnected from the supply power (e.g., Vcc). Figure 1 ), then such internal voltage may be used instead of Vcc.

[0015] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed in different levels (e.g., stacked on top of each other in different layers) above a substrate (e.g., a semiconductor substrate) of the memory device 100. The structure of the memory array 101 including the memory cells 102 may include the following reference Figures 2 to 10E Describes the structure of the memory array and memory cells.

[0016] like Figure 1 As shown, memory device 100 can include access lines 104 (e.g., "word lines") and data lines (e.g., bit lines) 105. Memory device 100 can use signals on access lines 104 (e.g., word line signals) to access memory cells 102 and data lines 105 to provide information (e.g., data) to be stored (e.g., written) in memory cells 102 or read (e.g., sensed) from the memory cells.

[0017] The memory device 100 may include an address register 106 to receive address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines) 107. The memory device 100 may include a row access circuit system (e.g., X-decoder) 108 and a column access circuit system (e.g., Y-decoder) 109 that may be used to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 may determine which memory cells 102 are to be accessed during a memory operation. The memory device 100 may perform a write operation to store information in the memory cells 102, and perform a read operation to read (e.g., sense) information in the memory cells 102 (e.g., previously stored information). The memory device 100 may also perform an operation (e.g., a refresh operation) to refresh (e.g., keep valid) the value of the information stored in the memory cells 102. Each of memory cells 102 may be configured to store information that may represent at most one bit (e.g., a single bit having a binary zero (“0”) or a binary one (“1”)) or more than one bit (e.g., a plurality of bits having a combination of at least two binary bits).

[0018] Memory device 100 may receive supply voltages on lines 130 and 132, respectively, including supply voltages Vcc and Vss. Supply voltage Vss may operate at ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc may include an external voltage supplied to memory device 100 from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuit.

[0019] like Figure 1 As shown, the memory device 100 may include a memory control unit 118, which includes circuit systems (e.g., hardware components) to control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on lines 120 include row access select signals RAS*, column access select signals CAS*, write enable signals WE*, chip select signals CS*, clock signals CK, and clock enable signals CKE. These signals may be part of the signals provided to the DRAM device.

[0020] like Figure 1As shown, memory device 100 can include lines (e.g., global data lines) 112 that can carry signals DQ0 through DQN. In a read operation, the value of the information (read from memory cell 102) provided to line 112 (in the form of signals DQ0 through DQN) (e.g., a "0" or a "1") can be based on the value of the signal on data line 105. In a write operation, the value of the information (e.g., a "0" or a "1") provided to data line 105 (to be stored in memory cell 102) can be based on the value of the signals DQ0 through DQN on line 112.

[0021] Memory device 100 may include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 may selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Selection circuitry 115 may respond to signals on lines 114 to select signals on data lines 105. The signals on data lines 105 may represent the value of information to be stored in memory cell 102 (e.g., during a write operation) or the value of information to be read (e.g., sensed) from memory cell 102 (e.g., during a read operation).

[0022] I / O circuitry 116 may be used to provide information read from memory cell 102 to line 112 (e.g., during a read operation) and to provide information from line 112 (e.g., provided by an external device) to data line 105 for storage in memory cell 102 (e.g., during a write operation). Line 112 may include a node within memory device 100 or a pin (or solder ball) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0023] The memory device 100 may include other components. Figure 1 100 (eg, a portion of memory array 101) may include the same memory device 100 as described below. Fig.10E Similar or identical structure and operation of any of the described memory devices.

[0024] Figure 2 Schematic diagram showing a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to Figure 1 For example, the memory array 201 may be formed Figure 1 A portion of the memory array 101. Figure 2As shown, memory device 200 may include memory cells 210-215, which are volatile memory cells (eg, DRAM cells). For simplicity, similar or identical elements among memory cells 210-215 are given the same labels.

[0025] Each of the memory cells 210 to 215 may include two transistors T1 and T2. Therefore, each of the memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of the transistors T1 and T2 may include a field effect transistor (FET). As an example, the transistor T1 may be a p-channel FET (PFET) and the transistor T2 may be an n-channel FET (NFET). The transistor T1 may include a charge storage-based structure (e.g., based on a floating gate). As shown in FIG. Figure 2 As shown, each of the memory cells 210 to 215 may include a charge storage structure 202, which may include a floating gate of a transistor T1. The charge storage structure 202 may form a memory element of a corresponding memory cell among the memory cells 210 to 215. The charge storage structure 202 may store charge. The value (e.g., "0" or "1") of the information stored in a particular memory cell among the memory cells 210 to 215 may be based on the amount of charge in the charge storage structure 202 of the particular memory cell.

[0026] like Figure 2 As shown, the transistor T2 (e.g., the channel region of the transistor T2) of a particular memory cell among the memory cells 210 to 215 may be electrically coupled to (e.g., directly coupled to) the charge storage structure 202 of the particular memory cell. Therefore, a circuit path (e.g., a current path) may be directly formed between the transistor T2 of the particular memory cell and the charge storage structure 202 of the particular memory cell during operation (e.g., a write operation) of the memory device 200.

[0027] Memory cells 210 to 215 may be arranged in memory cell groups 2010 and 2011 . Figure 2 Two memory cell groups (e.g., 2010 and 2011) are shown as an example. However, memory device 200 may include more than two memory cell groups. Memory cell groups 2010 and 2011 may include the same number of memory cells. For example, memory cell group 2010 may include memory cells 210, 212, and 214, and memory cell group 2011 may include memory cells 211, 213, and 215. Figure 2 Three memory cells in each of memory cell groups 2010 and 2011 are shown as an example. The number of memory cells in memory cell groups 2010 and 2011 may be different than three.

[0028] The memory device 200 may perform a write operation to store information in the memory cells 210 to 215, and perform a read operation to read (e.g., sense) information from the memory cells 210 to 215. The memory device 200 may be configured to be used as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container of a capacitor, the memory device 200 may store information in the form of electric charge in a charge storage structure 202 (which may be a floating gate structure). As mentioned above, the charge storage structure 202 may be a floating gate (e.g., floating gate 202) of the transistor T1. Therefore, the memory device 200 may be referred to as a floating gate-based DRAM device.

[0029] like Figure 2 As shown, the memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 that may carry corresponding signals (e.g., word line signals) WL1, WL2, and WLn. The access lines 241, 242, and 243 may be used to access both memory cell groups 2010 and 2011. Each of the access lines 241, 242, and 243 may be configured as at least one conductive line (one conductive line or multiple conductive lines that may be electrically coupled to each other (e.g., shorted)). The access lines 241, 242, and 243 may be selectively activated (e.g., activated one at a time) during an operation (e.g., a read or write operation) of the memory device 200 to access one or more selected memory cells among the memory cells 210 to 215. The selected cells may be referred to as target cells. In a read operation, information may be read from the one or more selected memory cells. In a write operation, the information may be stored information in the one or more selected memory cells.

[0030] In the memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or off) the transistors T1 and T2 of the corresponding memory cell during a read or write operation of the memory device 200. Some conventional memory devices may use multiple (e.g., two separate) access lines for controlling access to the corresponding memory cell during read and write operations. Compared to such conventional memory devices (using multiple access lines for the same memory cell), the memory device 200 uses a single access line (e.g., a common access line) in the memory device 200 to control the two transistors T1 and T2 of the corresponding memory cell to access the corresponding memory cell. This technology can save space and simplify the operation of the memory device 200.

[0031] In the memory device 200, the gate of each of the transistors T1 and T2 may be part of a corresponding access line (eg, a corresponding word line). Figure 2As shown, the gate of each of the transistors T1 and T2 of the memory cell 210 may be part of the access line 241. The gate of each of the transistors T1 and T2 of the memory cell 211 may be part of the access line 241.

[0032] The gate of each of the transistors T1 and T2 of the memory cell 212 may be part of the access line 242. The gate of each of the transistors T1 and T2 of the memory cell 213 may be part of the access line 242.

[0033] The gate of each of the transistors T1 and T2 of the memory cell 214 may be part of the access line 243. The gate of each of the transistors T1 and T2 of the memory cell 215 may be part of the access line 243.

[0034] The memory device 200 may include data lines (e.g., bit lines) 221, 221', 222, and 222', which may carry corresponding signals (e.g., bit line signals) BL1, BL1*, BL2, and BL2*. During a read operation, the memory device 200 may use the data lines 221 and 221' to obtain information read (e.g., sensed) from selected memory cells of the memory cell group 2010, and use the data lines 222 and 222' to read information from selected memory cells of the memory cell group 2011. During a write operation, the memory device 200 may use the data line 221 to provide information to be stored in selected memory cells of the memory cell group 2010, and use the data line 222 to provide information to be stored in selected memory cells of the memory cell group 2011.

[0035] The memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained via the read path coupled to the selected memory cell. In the memory cell group 2010, the read path of a particular memory cell (e.g., 210, 212, or 214) may include a current path (e.g., a read current path) through the channel region of the transistor T1 of the particular memory cell and the data lines 221 and 221'. In the memory cell group 2011, the read path of a particular memory cell (e.g., 211, 213, or 215) may include a current path (e.g., a read current path) through the channel region of the transistor T1 of the particular memory cell and the data lines 222 and 222'. In an example in which the transistor T1 is a PFET, the current may include hole conduction (e.g., hole conduction in a direction from the data line 221 to the data line 221* through the channel region (e.g., n-type semiconductor region) of the transistor T1). Since transistor T1 may be used for a read path to read information from a corresponding memory cell during a read operation, transistor T1 may be referred to as a read transistor and a channel region of transistor T1 may be referred to as a read channel region.

[0036] The memory device 200 may include a write path (e.g., a circuit path). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell via the write path coupled to the selected memory cell. In the memory cell group 2010, the write path of a particular memory cell may include the transistor T2 of the particular memory cell (e.g., may include a write current path through the channel region of the transistor T2) and the data line 221. In the memory cell group 2011, the write path of a particular memory cell (e.g., 211, 213, or 215) may include the transistor T2 of the particular memory cell (e.g., may include a write current path through the channel region of the transistor T2) and the data line 222. In an example in which the transistor T2 is an NFET, the current may include electron conduction (e.g., electron conduction in a direction from the data line 221 to the charge storage structure 202 through the channel region (e.g., n-type semiconductor region) of the transistor T2). Since transistor T2 may be used for a write path to store information in a corresponding memory cell during a write operation, transistor T2 may be referred to as a write transistor and the channel region of transistor T1 may be referred to as a write channel region.

[0037] Each of the transistors T1 and T2 may have a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values of the threshold voltages Vt1 and Vt2 may be different (unequal values). For example, the value of the threshold voltage Vt2 may be greater than the value of the threshold voltage Vt1. The difference in the values of the threshold voltages Vt1 and Vt2 allows the reading (e.g., sensing) of the information stored in the charge storage structure 202 of the transistor T1 on the read path without affecting (e.g., without turning on) the transistor T2 on the write path (e.g., the path through transistor T2). This may prevent charge leakage from the charge storage structure 202 via the transistor T2 of the write path.

[0038] In the structure of the memory device 200, the transistors T1 and T2 may be formed (e.g., engineered) such that the threshold voltage Vt1 of the transistor T1 may be less than zero volts (e.g., Vt1 < 0V) regardless of the value of the information stored in the charge storage structure 202 of the transistor T1 (e.g., "0" or "1"), and Vt1 < Vt2. When information having a value of "0" is stored in the charge storage structure 202, the charge storage structure 202 may be in state "0". When information having a value of "1" is stored in the charge storage structure 202, the charge storage structure 202 may be in state "1". Thus, in this structure, the relationship between the values of the threshold voltages Vt1 and Vt2 may be expressed as follows: Vt1 for state "0" < Vt1 for state "1" < 0V, and Vt2 = 0V (or alternatively Vt2 > 0V).

[0039] In an alternative structure of the memory device 200, the transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 for state "0" < Vt1 for state "1", where Vt1 for state "0" < 0V (or alternatively Vt1 for state "0" = 0V), Vt1 for state "1" > 0V, and Vt1 < Vt2.

[0040] In another alternative structure, the transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 (for state "0") < Vt1 (for state "1"), where Vt1 for state "0" = 0V (or alternatively Vt1 for state "0" > 0V, and Vt1 < Vt2.

[0041] During a read operation of the memory device 200, only one memory cell of the same memory cell group may be selected one at a time to read information from the selected memory cell. For example, the memory cells 210, 212, and 214 of the memory cell group 2010 may be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cells 211, 213, and 215 of the memory cell group 2011 may be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of the memory cells 211, 213, and 215 in this example).

[0042] During a read operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) may be selected in parallel (or alternatively may be selected sequentially). For example, memory cells 210 and 211 may be selected in parallel during a read operation to read (e.g., read in parallel) information from memory cells 210 and 211. Memory cells 212 and 213 may be selected in parallel during a read operation to read (e.g., read in parallel) information from memory cells 212 and 213. Memory cells 214 and 215 may be selected in parallel during a read operation to read (e.g., read in parallel) information from memory cells 214 and 215.

[0043] The value of information read from a selected memory cell of the memory cell group 2010 during a read operation may be determined based on the value of a current detected (e.g., sensed) from a read path (described above) including the transistor T1 and data lines 221 and 221' of the selected memory cell (e.g., memory cell 210, 212, or 214). The value of information read from a selected memory cell of the memory cell group 2011 during a read operation may be determined based on the value of a current detected (e.g., sensed) from a read path including the transistor T1 and data lines 222 and 222' of the selected memory cell (e.g., memory cell 211, 213, or 215).

[0044] The memory device 200 may include a detection circuit system (not shown) that can operate during a read operation to detect (e.g., sense) a current on a read path including data lines 221 and 221' (e.g., current I1, not shown), and detect a current on a read path including data lines 222 and 222' (e.g., current I2, not shown). The value of the detected current may be based on the value of the information stored in the selected memory cell. For example, depending on the value of the information stored in the selected memory cell of the memory cell group 2010, the value of the detected current between the data lines 221 and 221' (e.g., the value of the current I1) may be zero or greater than zero. Similarly, depending on the value of the information stored in the selected memory cell of the memory cell group 2011, the value of the detected current between the data lines 222 and 222' (e.g., the value of the current I2) may be zero or greater than zero. The memory device 200 may include a circuit system (not shown) that converts the value of the detected current into the value of the information stored in the selected memory cell (e.g., "0", "1", or a combination of multi-bit values).

[0045] During a write operation of the memory device 200, only one memory cell of the same memory cell group may be selected one at a time to store information in the selected memory cell. For example, the memory cells 210, 212, and 214 of the memory cell group 2010 may be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cells 211, 213, and 215 of the memory cell group 2011 may be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of the memory cells 211, 213, and 215 in this example).

[0046] During a write operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) may be selected in parallel. For example, memory cells 210 and 211 may be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 210 and 211. Memory cells 212 and 213 may be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 212 and 213. Memory cells 214 and 215 may be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 214 and 215.

[0047] Information to be stored in a selected memory cell of the memory cell group 2010 during a write operation may be provided via a write path including data line 221 and transistor T2 of a selected memory cell (e.g., memory cell 210, 212, or 214). Information to be stored in a selected memory cell of the memory cell group 2011 during a write operation may be provided via a write path including data line 222 and transistor T2 of a selected memory cell (e.g., memory cell 212, 213, or 215). As described above, the value (e.g., a binary value) of the information stored in a particular memory cell among the memory cells 210-215 may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0048] In a write operation, the amount of charge in the charge storage structure 202 of the selected memory cell may be changed (to reflect the value of the information stored in the selected memory cell) by applying a voltage on a write path including the transistor T2 of the specific memory cell and a data line (e.g., data line 221W or 222W) coupled to the specific memory cell. For example, if the information to be stored in the selected memory cell among the memory cells 210, 212, and 214 has one value (e.g., “0”), a voltage having one value (e.g., 0V) may be applied to the data line 221W (e.g., 0V is provided to the signal BL1). In another example, if the information to be stored in the selected memory cell among the memory cells 210, 212, and 214 has another value (e.g., “1”), a voltage having another value (e.g., a positive voltage) may be applied to the data line 221 (e.g., a positive voltage is provided to the signal BL1). Thus, information may be stored (eg, directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (eg, in the form of a voltage) on the write path of the particular memory cell (which includes transistor T2).

[0049] Figure 3 1 shows a diagram including example voltages V0, V1, V2, and V3 used during a read operation of the memory device 200 according to some embodiments described herein. Figure 2 A memory device 200 is provided. Figure 3 The example assumes that memory cell 210 is a selected memory cell (e.g., a target memory cell) for reading (e.g., sensing) information stored (e.g., previously stored) in memory cell 210 during a read operation. Memory cells 211 to 215 are assumed to be unselected memory cells. This means that in Figure 3 When information is read from memory cell 210 in the example of , memory cells 211 to 215 are not accessed and information stored in memory cells 211 to 215 is not read.

[0050] exist Figure 3 , voltages V0, V1, V2, and V3 may represent different voltages applied to the corresponding access lines 241, 242, and 243 and data lines 221, 221', 222, and 222' during a read operation of the memory device 200. As an example, the voltages V0, V1, V2, and V3 may have values ​​of 0V (e.g., ground), -0.3V, -0.75V, and 0.5V, respectively. The specific values ​​of the voltages used in this specification are merely example values. Different values ​​may be used.

[0051] exist Figure 3 In the read operation shown, voltage V1 may have a value (voltage value) to turn on transistor T1 of memory cell 210 (the selected memory cell in this example) and turn off (or keep off) transistor T2 of memory cell 210. This allows information to be read from memory cell 210. Voltages V0 and V2 may have values ​​such that transistors T1 and T2 of each of memory cells 211 to 215 (unselected memory cells in this example) are turned off (e.g., kept off). Voltage V3 may have a value such that a current (e.g., a read current) may be formed on a read path including data lines 221 and 221' and transistor T1 of memory cell 210. This allows current to be detected on the read path coupled to memory cell 210. Detection circuitry (not shown) of memory device 200 may be used to convert the value of the detected current (during reading of information from the selected memory cell) into the value of the information read from the selected memory cell (e.g., "0", "1", or a combination of multi-bit values). In Figure 3 In the example of , the value of the detected current on the data lines 221 and 221 ′ may be converted into the value of information read from the memory cell 210 .

[0052] exist Figure 3In the read operation shown, the voltage applied to the corresponding access lines 241, 242, and 243 may turn off (or keep off) the transistors T1 and T2 of each of the memory cells 211 to 215 except the transistor T1 of the memory cell 210. Depending on the value of the threshold voltage Vt1 of the transistor T1 of the memory cell 210, the transistor T1 of the memory cell 210 may or may not be turned on. For example, if the transistor T1 of each of the memory cells (e.g., 210 to 215) of the memory device 200 is configured (e.g., constructed) such that the threshold voltage of the transistor T1 is less than zero (e.g., Vt1<0V) regardless of the value (e.g., state) of the information stored in the corresponding memory cell 210, then the transistor T1 of the memory cell 210 in this example may be turned on and conduct current between the data lines 221 and 221' (via the transistor T1 of the memory cell 210). Memory device 200 may determine the value of information stored in memory cell 210 based on the value of the current between data lines 221 and 221'. As described above, memory device 200 may include a detection circuit that measures the value of the current between data lines 221 and 221' (or between data lines 222 and 222) during a read operation.

[0053] Figure 4 1 shows a diagram including example voltages V0, V4, V5, V6, and V7 used during a write operation of the memory device 200 according to some embodiments described herein. Figure 2 A memory device 200 is provided. Figure 4 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) for storing information in memory cells 210 and 211 during a write operation. Memory cells 212 to 215 are assumed to be unselected memory cells. This means that when information is stored in Figure 4 When the memory cells 210 and 211 in the example of FIG. 1 are accessed, the memory cells 212 to 215 are not accessed and the stored information is not stored in the memory cells 212 to 215.

[0054] exist Figure 4 , voltages V0, V4, V5, V6, and V7 may represent different voltages applied to the corresponding access lines 241, 242, and 243 and data lines 221, 221', 222, and 222' during a write operation of the memory device 200. As an example, voltages V0, V4, and V5 may have values ​​of 0V, 3.3V, and -0.75V, respectively. These values ​​are example values. Different values ​​may be used.

[0055] Depending on the value of the information stored in the memory cells 210 and 211 (e.g., "0" or "1"), the values ​​of the voltages V6 and V7 may be the same or different. For example, if the memory cells 210 and 211 are to store information having the same value, the values ​​of the voltages V6 and V7 may be the same (e.g., V6=V7). As an example, if the information to be stored in each of the memory cells 210 and 211 is "0", then V6=V7=0V, and if the information to be stored in each of the memory cells 210 and 211 is "1", then V6=V7=1V to 3V.

[0056] In another example, if memory cells 210 and 211 are to store information with different values, the values ​​of voltages V6 and V7 may be different (e.g., V6≠V7). As an example, if "0" is to be stored in memory cell 210 and "1" is to be stored in memory cell 211, then V6=0V and V7=1V to 3V. As another example, if "1" is to be stored in memory cell 210 and "0" is to be stored in memory cell 211, then V6=1V to 3V and V7=0V.

[0057] A range of voltages of 1 V to 3 V is used here as an example. Different ranges of voltages may be used. In addition, instead of applying 0 V (e.g., V6=0 V or V7=0 V) to a specific write data line (e.g., data line 221W or 222W) for storing information having a value of "0" to a memory cell (e.g., memory cell 210 or 211) coupled to the specific write data line, a positive voltage (e.g., V6>0 V or V7>0 V) may be applied to the specific data line.

[0058] exist Figure 4In a write operation of the memory device 200 of FIG. 1 , the voltage V5 may have a value such that the transistors T1 and T2 of each of the memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., remain turned off). The voltage V4 may have a value to turn on the transistors T2 of each of the memory cells 210 and 211 (selected memory cells in this example) and form a write path between the charge storage structure 202 of the memory cell 210 and the data line 221, and a write path between the charge storage structure 202 of the memory cell 211 and the data line 222. A current (e.g., a write current) may be formed between the charge storage structure 202 of the memory cell 210 and the data line 221. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 210 to reflect the value of the information to be stored in the memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of the memory cell 211 and the data line 222. This current may affect (eg, change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the value of the information to be stored in the memory cell 211 .

[0059] exist Figure 4 In the example write operation of , the value of voltage V6 may cause the charge storage structure 202 of memory cell 210 to discharge or charge, so that the resulting charge on the charge storage structure 202 of memory cell 210 (e.g., the charge remaining after the discharge or charge action) may reflect the value of the information stored in memory cell 210. Similarly, the value of voltage V7 in this example may cause the charge storage structure 202 of memory cell 211 to discharge or charge, so that the resulting charge on the charge storage structure 202 of memory cell 211 (e.g., the charge remaining after the discharge or charge action) may reflect the value of the information stored in memory cell 211.

[0060] According to some embodiments described herein, Figure 5 , Figure 6 , Figure 7 and Figure 8 Shows the X, Y and Z directions Figure 2 Different views of the structure of the memory device 200. Figure 5 A side view of the memory device 200 with respect to the XZ direction is shown. Figure 6 , Figure 7 and Figure 8 Shown along Figure 5 Views taken along lines 6-6, 7-7 and 8-8.

[0061] For simplicity, Figures 5 to 8 Focus is placed on the structures of memory cells 210 and 211 . Figure 2The structures of other memory cells (e.g., memory cells 212, 213, 214, and 215) of the memory device 200 may be similar to those of the memory devices 210, 211, 212, 213, 214, and 215. Figure 5 The structures of the memory cells 210 and 211 shown in FIG. 1 are similar or identical. Figures 5 to 8 (which illustrates the physical structure of memory device 200) and Figure 2 (which illustrates a memory device 200 in circuit schematic form), like elements are given like reference numerals.

[0062] The following description refers to Figures 5 to 8 For simplicity, Figures 5 to 8 The detailed description of the same element is not repeated in the description of FIG. Figures 5 to 8 and other figures in the drawings described herein (e.g., FIG. 9A to FIG. 10E ) are cross-sectional lines (eg, hatching) for most elements shown in FIG. 2 . Some elements of memory device 200 may be omitted from certain views in the accompanying drawings so as not to obscure the description of the elements described in the certain views. Figures 5 to 10E The dimensions of the elements shown are not to scale.

[0063] like Figure 5 As shown, the memory device 200 may include a substrate 599 over which memory cells 210 and 211 may be formed (e.g., formed vertically relative to the substrate 599). The substrate 599 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrates. The Z direction may be a direction perpendicular to the substrate 599 (e.g., a vertical direction relative to the substrate 599). The X direction and the Y direction are perpendicular to each other and perpendicular to the Z direction.

[0064] like Figures 5 to 8 As shown, each of the data lines 221, 221', 222, and 222' (associated with signals BL1, BL1*, BL2, and BL2*, respectively) may have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Each of the data lines 221, 221', 222, and 222' may include a conductive material (or a combination of materials) that may be configured as a conductive line (e.g., a conductive region). Example materials of the data lines 221, 221', 222, and 222' include metal, conductively doped polysilicon, or other conductive materials.

[0065] like Figure 5As shown, the data lines 221 and 221' may include respective conductive regions (forming a portion of the respective conductive material of the data lines 221 and 221') located at different levels (relative to the Z direction) of the memory device 200 and electrically separated from each other. Similarly, the data lines 222 and 222' may include respective conductive regions (forming a portion of the respective conductive material of the data lines 222 and 222') located at different levels of the memory device 200 and electrically separated from each other.

[0066] Data lines 221 and 221' can be bottom and top data lines, respectively (relative to substrate 599 and the Z direction). Memory cell 210 can be located between and coupled to memory cells 211. Data lines 222 and 222' can be bottom and top data lines, respectively (relative to substrate 599 and the Z direction). Memory cell 211 can be located between and coupled to memory cells 210.

[0067] Access line 241 (associated with signal WL1) may be constructed from a combination of portions 541F and 541B (e.g., a front conductive portion and a rear conductive portion with respect to the Y direction) (may include the portions). Each of portions 541F and 541B may include a conductive material (or a combination of materials) that may be constructed as a conductive line (e.g., a conductive region) having a length that extends continuously in the X direction. Figure 5 , portions 541A, 541B, 541C, and 541D are partially shown to avoid blocking portions of other elements of memory device 200.

[0068] Each of the portions 541F and 541B may include a block (eg, layer) of a conductive material (eg, metal, conductively doped polysilicon, or other conductive material). Each of the portions 541F and 541B may have a length in the X direction (eg, Figure 5 As shown in the figure), the width in the Z direction (as shown in the figure), Figure 5 ) and the thickness in the Y direction (as Figure 8 shown).

[0069] Portions 541F and 541B may be electrically coupled to each other. For example, memory device 200 may include a conductive material (e.g., not shown) that may contact (e.g., electrically couple to) portions 541F and 541B so that portions 541F and 541B (which are part of a single access line 241) may be applied in parallel by the same signal (e.g., signal WL1).

[0070] In an alternative configuration of memory device 200, portion 541F or portion 541B may be omitted, such that access line 241 may include only portion 541F or portion 541B. Figure 5In the illustrated structure, the inclusion of two portions 541F and 541B may help better control transistor T1 (eg, Figure 2 Schematically shown transistor T1).

[0071] like Figure 5 As shown, the memory device 200 may include a dielectric 590 formed on a portion of a substrate 599. The dielectric 590 may include silicon oxide. The dielectric 590 may electrically separate the data lines 221' and 222' from the substrate 599.

[0072] The charge storage structure 202 may include a block (e.g., layer) of semiconductor material (e.g., polysilicon), a block (e.g., layer) of metal, or a block of material (or multiple materials) that can capture charge. The materials used for the charge storage structure 202 and the portions 541F and 541B of the access line 241 may be the same or different. Figure 5 As shown, the charge storage structure 202 may be located above the data line 221 ′ and may be closer to (eg, extend closer in the Z direction to) the substrate 599 than each of the portions 541F and 541B of the access line 241 .

[0073] Figure 5 The top edge of the charge storage structure 202 is shown to be a certain distance (eg, a bottom edge) from the edge (eg, bottom edge) of each of the portions 541F and 541B of the access line 241. Figure 5 However, the distance between the top edge of the charge storage structure 202 and the edge (eg, bottom edge) of each of the portions 541F and 541B may vary.

[0074] Figure 5 An example is shown where portions 541F and 541B overlap (in the Z direction) the charge storage structure 202. However, portions 541F and 541B may not overlap the charge storage structure 202.

[0075] The memory device 200 may include a material 520 between the data line 221 and the charge storage structure 202. Figure 5 As shown, material 520 can be electrically coupled to data line 221 and charge storage structure 202 of memory cell 210. As described above, charge storage structure 202 of memory cell 210 can form a memory element of memory cell 210. Therefore, memory cell 210 can include a memory element (which is charge storage structure 202) located between substrate 599 and material 520 with respect to the Z direction, and the memory element contacts (e.g., is directly coupled to) material 520.

[0076] The material 520 may form a source (eg, source terminal), a drain (eg, drain terminal), and a channel region (eg, write channel region) between the source and the drain of the transistor T2 of the memory cell 210. Figure 5 As shown, the source, channel region, and drain of the transistor T2 of the memory cell 210 may be formed from a single block of the same material (or alternatively, a single block of the same material combination), such as material 520. Therefore, the source, drain, and channel region of the transistor T2 of the memory cell 210 may be formed from the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type).

[0077] The memory device 200 may include a material 521 that may form a source (eg, source terminal), a drain (eg, drain terminal), and a channel region (eg, write channel region) between the source and drain of the transistor T2 of the memory cell 211. Figure 5 As shown, the source, channel region, and drain of transistor T2 of memory cell 211 may be formed from a single identical block of material (or alternatively, a single identical block of material combination), such as material 521 .

[0078] Materials 520 and 521 may be the same. For example, each of materials 520 and 521 may include a block (e.g., layer) of semiconductor material. In an example where the transistor is a PFET (as described above), materials 520 and 521 may include p-type semiconductor material (e.g., p-type silicon).

[0079] In another example, the semiconductor material forming the material 520 or the material 521 may include a bulk oxide material. Examples of oxide materials for the materials 520 and 521 include semiconductor oxide materials, transparent conductive oxide materials, and other oxide materials.

[0080] As an example, each of the materials 520 and 521 may include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), Indium Zinc Oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Gay Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0081] The use of the above materials in the memory device 200 provides improvements and benefits to the memory device 200. For example, during a read operation to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from the charge storage structure 202 of the selected memory cell may leak to the transistor T2 of the selected memory cell. Using the above listed materials for the channel region of transistor T2 (e.g., material 520 or 521) can reduce or prevent such leakage. This improves the accuracy of the information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory devices described herein (e.g., memory device 200).

[0082] The materials listed above are examples of materials 520 and 521. However, other materials (eg, relatively high bandgap materials) other than the materials listed above may be used.

[0083] exist Figure 5 In the embodiment, the material 520 and the charge storage structure 202 of the memory cell 210 may be electrically coupled to each other (e.g., directly coupled), such that the material 520 may contact the charge storage structure 202 of the memory cell 210 without an intermediate material (e.g., no conductive material) between the charge storage structure 202 of the memory cell 210 and the material 520. In another example, the material 520 may be electrically coupled to the charge storage structure 202 of the memory cell 210, such that the material 520 is not directly coupled to (does not contact) the charge storage structure 202 of the memory cell 210, but the material 520 is electrically coupled to the charge storage structure 202 of the memory cell 210 through an intermediate material (e.g., conductive material) between the charge storage structure 202 of the memory cell 210 and the material 520. Figure 5 2. The charge storage structure 202 (not shown) is coupled to (eg, indirectly contacts) the memory cell 210.

[0084] like Figure 5 As shown, memory cell 210 may include portions 510A, 510B, and 510C electrically coupled to each other. Each of portions 510A, 510B, and 510C may include a block of semiconductor material. Example materials for each of portions 510A, 510B, and 510C include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon germanium, or other semiconductor materials.

[0085] Each of the portions 511A and 510B may have a length extending in the Z direction. The portion 510C may have a length in the X direction. Figure 5 As shown, portions 510A, 510B, and 510C may form a "U" shape (or close to a "U" shape).

[0086] As above reference Figure 2 As described above, the transistor T1 of the memory cell 210 includes a channel region (eg, a read channel region). Figure 5 , the channel region of the transistor T1 of the memory cell 210 may include portions 510A, 510B, and 510C (eg, may be formed by a combination thereof). The portions 510A, 510B, and 510C may be electrically coupled to the data lines 221 and 222. Figure 2 As described above, the memory unit 210 may include a read path. Figure 5, portions 510A, 510B, and 510C (e.g., a read channel region of transistor T1 of memory cell 210) may be part of a read path of memory cell 210 that may carry a current (e.g., a read current) during a read operation to read information from memory cell 210. For example, during a read operation, portions 510A, 510B, and 510C may conduct a current (e.g., a read current) between data lines 221 and 221' in order to read information from memory cell 210. The direction of the read current may be from data line 221 to data line 221' (through portions 510A, 510B, and 510). In an example where transistor T1 is a PFET and transistor T2 is an NFET, the material forming portions 510A, 510B, and 510C may have a different conductivity type than material 520 or 521. For example, portions 510A, 510B, and 510C may include p-type semiconductor material (eg, p-type silicon), and materials 520 and 521 may include n-type semiconductor material (eg, n-type gallium phosphide (GaP)).

[0087] Memory cell 210 may include dielectrics 515A, 515B, and 515C. Dielectrics 515A, 515B, and 515C may be gate oxide regions that electrically separate charge storage structure 202 from portions 510A, 510B, and 510C and electrically separate material 520 from portions 510A, 510B, and 510C. Example materials for dielectrics 515A, 515B, and 515C may include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0088] like Figure 5 As shown, a portion of portion 541F may span (e.g., overlap in the X direction) a portion of portions 510A and 510B and a portion of material 520. As described above, portions 510A and 510B may form a portion of the read channel region of transistor T1, and material 520 may form a portion of the write channel region of transistor T2. Figure 5 As shown, a portion of the portion 541F may span (eg, overlap) a portion of the read and write channels of the transistors T1 and T2, respectively (eg, one side (eg, front side) in the Y direction). Figure 5 Hidden in the illustrated view, a portion of portion 541B may span (e.g., overlap in the X direction) a portion of portions 510A and 510B (e.g., the other side in the Y direction (e.g., the back side as opposed to the front side)) and a portion of material 521. Figure 5As shown, access line 241 may also span (e.g., overlap in the X direction) a portion of portions 511A and 511B (e.g., a portion of the read channel region of transistor T1 of memory cell 211) and a portion of material 521 (e.g., a portion of the write channel region of transistor T2 of memory cell 211).

[0089] Access line 241 spans (e.g., overlaps) portions 510A and 510B and material 520 to allow access line 241 (a single access line) to control (e.g., turn on or off) transistors T1 and T2 of memory cell 210 and two transistors of memory cell 211. Similarly, access line 241 spans (e.g., overlaps) portions 511A and 511B and material 521 to allow access line 241 (a single access line) to control (e.g., turn on or off) two transistors T1 and T2 of memory cell 211.

[0090] like Figures 6 to 8 As shown, the memory device 200 can include dielectrics 515E and 515F (e.g., oxide regions) to electrically separate portions 541F and 541B of the access line 241 from other elements of the memory cells 210 and 211 (e.g., from portions 510A, 510B, 510C, 510D, and 510E (e.g., read channel regions) and from the charge storage structure 202). Example materials for portions 515E and 515F can include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0091] The dielectric material (or multiple dielectric materials) separating portions 510A, 510B, 510C, 511A, 511B, and 511C (read channel regions) from portions 541F and 541B of access line 214 can be the same as (or, alternatively, different from) the material (or multiple materials) separating charge storage structure 202 from portions 541F and 541B. In addition, the thickness of the dielectric material (or multiple dielectric materials) separating portions 510A, 510B, 510C, 511A, 511B, and 511C (read channel regions) from portions 541F and 541B of access line 214 can be the same as (or, alternatively, different from) the thickness of the material (or multiple materials) separating charge storage structure 202 from portions 541F and 541B of access line 214.

[0092] like Figure 8 As shown, portions 541F and 541B may be adjacent to respective sides of material 520 and charge storage structure 202 of memory cell 210. For example, portion 541F may be adjacent to a side of a portion of each of material 520 and charge storage structure 202 (e.g., Figure 8In another example, portion 541B may be adjacent to the other side of a portion of each of material 520 and charge storage structure 202 (eg, Figure 8 Adjacent to the left side in the X direction (opposite to the right side) in the view of .

[0093] The above description focuses on the structure of the memory unit 210. The memory unit 211 may include elements constructed in a manner similar to or identical to the elements of the memory unit 210 described above. Figures 5 to 7 As shown, memory cell 211 may include charge storage structure 202, channel region (e.g., write channel region) 521, portions 511A, 511B, and 511C (e.g., read channel region), and dielectrics 525A, 525B, and 525C. The material (or materials) for dielectrics 525A, 525B, and 525C may be the same as the material (or materials) for dielectrics 515A, 515B, and 515C, respectively.

[0094] FIG. 9A to FIG. 9R A cross-sectional view of elements in a process of forming a memory device 900 according to some embodiments of the present invention is shown. Some or all of the processes for forming the memory device 900 may be used to form the memory device 900 described above. Figures 2 to 8 A memory device 200 is described.

[0095] Fig. 9A Memory device 900 is shown after dielectric material 990, conductive material 927, and material 930 are formed in respective levels (e.g., layers) in the Z direction over substrate 999. The Z direction (e.g., vertical direction) is a direction perpendicular to substrate 999 (e.g., outward from the substrate). The Z direction is also perpendicular to the X direction. Dielectric material 990, conductive material 927, and material 930 may be formed in a sequential manner one material after another over substrate 999. For example, Fig. 9A The process used in may include forming (eg, depositing) a dielectric material 990 over a substrate, forming (eg, depositing) a conductive material 927 over dielectric material 990 , and forming (eg, depositing) a material 930 over conductive material 927 .

[0096] Substrate 999 can be Figure 5 The substrate 599 is similar or identical to that of the substrate 599. Fig. 9A The dielectric material 922 of the memory device 900 may include an oxide material (e.g., silicon dioxide SiO2). The conductive material 927 may include a metal, conductive doped polysilicon, or other conductive material. As described below in a subsequent process of forming the memory device 900, the conductive material 927 may be configured to form a data line of the memory device 900, which may be similar to the data lines 221' and 222' of the memory device 200 ( Figure 5 ). Material 930 may be a "sacrificial" material that may be removed at some point (in a subsequent process) during the formation of memory device 900. Material 930 may include a nitride material (e.g., silicon nitrite SiN4) or other material that is relatively easy to remove (e.g., etch away).

[0097] Fig. 9B The memory device 900 is shown after forming openings (eg, trenches) 931 , 932 , and 933 and data lines 921 ′, 922 ′, and 923 ′. Fig. 9B Also shown are signals (eg, bit line signals) BL1*, BL2*, and BL3*, which may represent signals applied to data lines 921', 922', and 923', respectively, during operation (eg, reading or writing) of memory device 900. Signals BL1* and BL2* may be similar to Figure 5 1 and 2. The memory device 500 in FIG.

[0098] exist Fig. 9B , forming openings 931, 932, and 933 may include removing (e.g., by patterning) a portion of material 930 at the locations of openings 931, 932, and 933, and leaving portions 930A, 930B, and 930C (which are remaining portions of material 930), as shown in FIG. Fig. 9B Forming data lines 921', 922', and 923' may include removing a portion of conductive material 923 (at the locations of openings 931, 932, and 933), leaving a remaining portion of conductive material 923 that forms corresponding data lines 921', 922', and 923'. Fig. 9B As shown, data lines 921', 922' and 923' are electrically separated from each other (in the X direction). Data lines 921' and 922' may be similar to Figure 5 The data lines 221 ′ and 222 ′ (eg, bottom data lines) of the memory device 200 are shown. The data line 923 ′ may be another data line of the memory device 900 .

[0099] Fig. 9C Memory device 900 is shown after dielectric materials 951 , 952 , and 953 are formed (eg, filled) in openings 931 , 932 , and 933 , respectively. Fig. 9C The process in the embodiment may include a planarization process (eg, a chemical mechanical polishing (CMP) process) after forming the dielectric materials 951, 952, and 953. Such a planarization process may make Fig. 9C The top surface of the structure of memory device 900 is shown to be smooth (eg, planarized).

[0100] Fig.9DShown are portions 930A, 930B, and 930C ( Fig. 9C ) after the memory device 900. Fig.9D The process can include Fig.9D The etching process of removing portions 930A, 930B, and 930C from the structure of the memory device 900 is shown.

[0101] Fig.9E Memory device 900 is shown after material 913 (e.g., transistor channel material) is formed (e.g., deposited) over data lines 921', 922', and 923' and over dielectric materials 951, 952, and 953. Material 913 can conduct current during operation (e.g., a read operation) of memory device 900. Examples of material 913 include semiconductor materials. Material 913 can be formed with Figure 5 The materials of the portions 510A, 510B, and 510C (eg, the read channel regions) of the corresponding transistors T1 of the memory device 500 have the same properties. As described below, in the subsequent process of forming the memory device 900 (eg, Figure 9L ), the material 913 may be configured to form a channel region (eg, a read channel region) of a transistor (eg, transistor T1) of a corresponding memory cell of the memory device 900.

[0102] Fig.9F Memory device 900 is shown after dielectric material (e.g., gate oxide material) 942 is formed (e.g., deposited) over material 913. Dielectric material 942 may include silicon dioxide. As described below, in subsequent processes (e.g., Figure 9H ), Fig.9F The material 942 may be configured to form a portion of a gate oxide of a transistor (eg, transistors T1 and T2 ) of a corresponding memory cell of the memory device 900 .

[0103] Figure 9G Memory device 900 is shown after forming (eg, filling) material (eg, charge storage material) 902A in the open spaces between portions of dielectric material 942. As described below, in the subsequent process of forming memory device 900 ( Figure 9L ), the material 902A may be configured to form a charge storage structure of a corresponding memory cell of the memory device 900. The material 902A may include the same Figure 5 ) of the charge storage structure 202 of the memory cell (eg, memory cell 210 or 211) may be made of a material similar to or the same as that of the charge storage structure 202 of the memory cell (eg, memory cell 210 or 211).

[0104] Figure 9H Shown in the removal Figure 9GMemory device 900 after a portion of each of materials 913, 942, 902A, 952, and 953 is removed. Figure 9H The process in may include a process (e.g., a CMP process) that can remove a portion of material 913 to form portions (remaining portions of material 913) 910A, 910B and 910C", 911A, 911B, 910C", and 919A. The combination of portions 910A, 910B, and 910C" may form a channel region of a transistor (e.g., transistor T1) of memory cell 910 in a subsequent process. The combination of portions 911A, 911B, and 910C" may form a channel region of a transistor (e.g., transistor T1) of memory cell 911. Portion 919A may form a portion of a channel region of a transistor of a memory cell adjacent to memory cell 911.

[0105] Figure 9H The process (e.g., a CMP process) may also remove portions of material 942 to form portions (remaining portions of material 942) 915A, 915B, 915C", 925A, 925B, 925C", and 929A. The combination of portions 915A, 915B, and 915C" may form portions of gate oxide regions of transistors (e.g., transistors T1 and T2) of memory cell 910 in a subsequent process. The combination of portions 925A, 925B, and 925C" may form portions of gate oxide regions of transistors (e.g., transistors T1 and T2) of memory cell 911 in a subsequent process. Portion 929A may form portions of gate oxide regions of transistors of memory cells adjacent to memory cell 911.

[0106] Figure 9H The process in FIG. 1 may also include a process (e.g., an etching process performed after the CMP process) that may remove a portion of the material 902A (FIG. G) to form a recess (e.g., an opening) 903 and a portion (e.g., a channel region) 902B exposed at the corresponding recess 903. The portion 902B is the remaining portion of the material 902A.

[0107] Fig.9I Memory device 900 is shown after materials 920A, 921A, and 922A are formed (eg, deposited) in respective recesses 903. Materials 920A, 921A, and 922A may include Figure 5 A portion (eg, a write channel region) 520 or 521 of the transistor T2 of the memory device 500 ( Figure 5 ) of the material. As described below, in the subsequent process of forming the memory device 900 ( Figure 9L), the material 920A may form a channel region (eg, a write channel region) of a transistor (eg, transistor T2) of a corresponding memory cell of the memory device 900.

[0108] like Fig.9I As shown, a portion of the elements of memory device 900 may form a portion of memory cells 910 and 911, which may be similar to memory cells 210 and 211 of memory device 500, respectively. Figure 5 ).

[0109] Figure 9J Show about Fig.9I For simplicity, the top view of the memory device 900 in the XY direction is not repeated. Figure 9J Description of the components shown (refer to Fig.9I Description). Figure 9J As shown, elements of memory device 900 may include strips of material having a length extending in the Y direction. In a subsequent process of forming memory device 900, material at locations 961, 962, and 963 of memory device 900 will be removed (e.g., cut in the Z direction (e.g., etched to form trenches)), and material of memory device 900 at locations 971 and 972 will remain (and will be parts of corresponding memory cells of memory device 900). Figure 9K Another view of memory device 900 along line 9K-9K is shown in FIG.

[0110] Figure 9K Show Figure 9J The memory device 900 is arranged along the YZ direction. Figure 9J Side view of the line 9K-9K. Figure 9K , positions 961, 962, 963, 971, and 972 of the memory device 900 relative to the YZ direction are also shown. The structures of the memory device 900 at the positions 961, 962, and 963 (e.g., materials 920A, 902B, 915C" and 910C") are to be removed ( Figure 9L ) and stops at data line 921' so that material of data line 921' at positions 961, 962 and 963 is not removed.

[0111] Figure 9L Memory device 900 is shown after forming openings (e.g., trenches) 961A, 962A, and 963A and portions 920, 920', 902', 915C, 915C', 910C, and 910C'. Openings 961A, 962A, and 963A may be formed by removing a portion of each of materials 920A, 902B, 915C", and 910C" at locations 961, 962, and 963 (as described above). Figure 9L In the embodiment, parts 920, 920', 902, 902', 915C, 915C', 910C and 910C' are Figure 9K The remaining portions of the corresponding materials 920A, 902B, 915C" and 910C".

[0112] Figure 9M Memory device 900 is shown after forming dielectric material 945. Dielectric material 945 may include silicon dioxide.

[0113] Figure 9N Shown in the removal Figure 9M Memory device 900 after removing a portion of dielectric material 945 from the memory device 900. Figure 9N The remainder of dielectric material 945 is shown in FIG.

[0114] Fig.9O Memory device 900 is shown after forming dielectric portions 915E, 915F, and 915G. Dielectric portions 915E, 915F, and 915G may include silicon dioxide.

[0115] Figure 9P The memory device 900 is shown after forming a conductive material 941. The conductive material 941 may include metal, conductive doped polysilicon, or other conductive materials. In a subsequent process of forming the memory device 900, the conductive material 941 may be configured to form an access line (eg, a word line) of the memory device 900.

[0116] Figure 9Q Memory device 900 is shown after forming portions 941F, 941B, 941F', and 941B'. ​​Forming portions 941F, 941B, 941F', and 941B' may include removing conductive material 941 ( Figure 9P ) (e.g., the bottom), leaving Figure 9Q 941F, 941B, 941F', and 941B' are shown as portions of conductive material 941. Removing portions of conductive material 941 can include a punch etching process to electrically separate portions of conductive material 941 from each other in the Y direction. For example, portion 941B is electrically separated from portion 941F'. Portion 941F is also electrically separated from another portion of conductive material 941 (not shown) in the Y direction. Portion 941B' is also electrically separated from another portion of conductive material 941 (not shown) in the Y direction.

[0117] Figure 9R Memory device 900 is shown after forming dielectric material 980 and data line 921 . Figure 9RAlso shown is a signal (eg, a bit line signal) BL1, which may represent a signal applied to the data line 921 during operation (eg, reading or writing) of the memory device 900. The signal BL1 may be similar to Figure 5 The signal BL1 of the memory device 500 is Figure 9R In the embodiment, the dielectric material 980 may include silicon dioxide. The data line 921 may be formed after the dielectric material 980 is formed, and may be formed of a conductive material (eg, metal, conductive doped polysilicon, or other conductive materials).

[0118] like Figure 9R As shown, data line 921 may be formed so as to be electrically coupled to portions 920 and 920' and electrically separated from portions 941F, 941B, 941F', and 941B'. Figure 9R The process may include removing a portion (eg, a top portion) of each of portions 941F, 941B, 941F′, and 941B′ before forming data line 921 so that data line 921 is electrically separated from portions 941F, 941B, 941F′, and 941B′ when data line 921 is formed.

[0119] like Figure 9R As shown, a portion of memory device 900 may form memory cells 910 and 912, which may be similar to memory cells 210 and 212 (schematically shown in FIG. 2 ) of memory device 200, respectively. Figure 2 in). Figure 9R , portions 941F and 941B may be portions of access lines (e.g., word lines and associated signals WL1) that may be used to control transistors T1 and T2 of memory cell 910 during a memory operation (e.g., a read or write operation) of memory device 900. Portions 941F′ and 941B′ may be portions of access lines (e.g., word lines and associated signals WL2) that may be used to control transistors T1 and T2 of memory cell 912 during a memory operation (e.g., a read or write operation) of memory device 900. Figure 9Q The memory unit 911 ( Fig.9I However, the memory cell 911 may be located in the X direction (eg, located Figure 9R ), and may share the same access line that includes portions 941F and 941B.

[0120] exist Figure 9R, portion 920 may form a channel portion (e.g., a write channel portion) of transistor T2 of memory cell 910, portion 902 may form a charge storage structure (e.g., a floating gate of transistor T1) of memory cell 910, portion 915C may form a portion of a gate oxide of transistors T1 and T2 of memory cell 910, and portion 910C may form a portion of a channel portion (e.g., a read channel portion) of transistor T1 of memory cell 910. Portion 920′ may form a channel portion (e.g., a write channel portion) of transistor T2 of memory cell 912, portion 902′ may form a charge storage structure (e.g., a floating gate of transistor T1) of memory cell 912, portion 915C′ may form a portion of a gate oxide of transistors T1 and T2 of memory cell 912, and portion 910C may form a portion of a channel portion (e.g., a read channel portion) of transistor T1 of memory cell 910.

[0121] FIG. 10A to FIG. 10E A cross-sectional view of elements during a process of forming memory device 1000 according to some embodiments of the present invention is shown. Some or all of the processes for forming memory device 1000 may be used to form the memory device 1000 described above. Figures 2 to 8 The process of forming the memory device 1000 may be a process of forming the memory device 900 ( FIG. 9A to FIG. 9R ). Therefore, similar elements (having the same labels) between the processes of forming memory devices 900 and 1000 are not repeated.

[0122] Fig. 10A Shows that you can use FIG. 9A to FIG. 9L The elements of memory device 1000 are formed by similar or identical processes as the elements of memory device 900. Therefore, Fig. 10A The components of the memory device 1000 shown may be similar to Figure 9L Elements of memory device 900 are shown.

[0123] Fig. 10B Memory device 900 is shown after forming dielectric portions 1015E, 1015F, and 1015G. Dielectric portions 1015E, 1015F, and 1015G may include silicon dioxide.

[0124] Fig. 10C The memory device 900 is shown after forming the conductive material 1041. The conductive material 941 may include metal, conductive doped polysilicon, or other conductive materials. In a subsequent process of forming the memory device 900, the conductive material 1041 may be configured to form an access line (eg, a word line) of the memory device 1000.

[0125] Fig. 10D Memory device 1000 is shown after forming portions 1041F, 1041B, 1041F′, and 1041B′. Forming portions 1041F, 1041B, 1041F′, and 1041B′ may include removing conductive material 1041( Fig.10E ) part (e.g., the bottom), leaving it as Fig. 10D 1041F, 1041B, 1041F', and 1041B' are shown as portions of conductive material 1041. Removing a portion of conductive material 1041 may include a punch etching process to electrically separate portions of conductive material 1041 from each other in the Y direction. For example, portion 1041B is electrically separated from portion 1041F'. Portion 1041F is also electrically separated from another portion of conductive material 1041 (not shown) in the Y direction. Portion 1041B' is also electrically separated from another portion of conductive material 1041 (not shown) in the Y direction.

[0126] Fig.10E Memory device 1000 is shown after forming dielectric material 1080 and data line 1021 . Fig.10E Also shown is a signal (eg, a bit line signal) BL1, which may represent a signal applied to the data line 1021 during operation (eg, reading or writing) of the memory device 1000. The signal BL1 may be similar to Figure 5 The signal BL1 of the memory device 500 is Fig.10E In the embodiment, the dielectric material 1080 may include silicon dioxide. The data line 1021 may be formed after the dielectric material 1080 is formed, and may be formed of a conductive material (eg, metal, conductive doped polysilicon, or other conductive materials).

[0127] like Fig.10E As shown, data line 1021 may be formed so as to be electrically coupled to portions 920 and 920' and electrically separated from portions 1041F, 1041B, 1041F', and 1041B'. Fig.10E The process may include removing a portion (e.g., a top portion) of each of portions 1041F, 1041B, 1041F', and 1041B' before forming data line 1021, so that data line 1021 is electrically separated from portions 1041F, 1041B, 1041F', and 1041B' when data line 1021 is formed.

[0128] like Fig.10E As shown, a portion of memory device 1000 may form memory cells 1010 and 1012, which may be similar to memory cells 210 and 212 (schematically shown in FIG. 1 ) of memory device 200, respectively. Figure 2 in). Fig.10E, portions 1041F and 1041B may be portions of access lines (e.g., word lines and associated signals WL1) that may be used to control transistors T1 and T2 of memory cell 1010 during a memory operation (e.g., a read or write operation) of memory device 1000. Portions 1041F′ and 1041B′ may be portions of access lines (e.g., word lines and associated signals WL2) that may be used to control transistors T1 and T2 of memory cell 1012 during a memory operation (e.g., a read or write operation) of memory device 1000.

[0129] exist Fig.10E , portion 920 may form a channel portion (e.g., a write channel portion) of transistor T2 of memory cell 1010, portion 902 may form a charge storage structure (e.g., a floating gate of transistor T1) of memory cell 1010, portion 915C may form a portion of a gate oxide of transistors T1 and T2 of memory cell 1010, and portion 910C may form a portion of a channel portion (e.g., a read channel portion) of transistor T1 of memory cell 1010. Portion 920′ may form a channel portion (e.g., a write channel portion) of transistor T2 of memory cell 1012, portion 902′ may form a charge storage structure (e.g., a floating gate of transistor T1) of memory cell 1012, portion 915C′ may form a portion of a gate oxide of transistors T1 and T2 of memory cell 1012, and portion 910C′ may form a portion of a channel portion (e.g., a read channel portion) of transistor T1 of memory cell 1012.

[0130] Fig.11A , Fig. 11B and Fig. 11C Different views of a memory device 1100 structure including multiple stacks of memory cells are shown according to some embodiments described herein. Fig.11A An exploded view (eg, in the Z direction) of memory device 1100 is shown. Fig. 11B Side views (eg, cross-sectional views) in the X-direction and the Z-direction of the memory device 1100 are shown. Fig. 11C Side views (eg, cross-sectional views) in the Y direction and the Z direction of the memory device 1100 are shown.

[0131] like Fig.11AAs shown, the memory device 1100 may include stacks (memory cell stacks) 11050, 11051, 11052, and 11053, which are shown separated from each other in an exploded view to facilitate viewing of the stack structure of the memory device 1100. In practice, the stacks 11050, 11051, 11052, and 11053 may be attached to each other in an arrangement where one stack may be formed (e.g., stacked) on top of another stack on a substrate (e.g., a semiconductor (e.g., silicon) substrate) 1199. For example, Fig.11A As shown, layers 11050 , 11051 , 11052 , and 11053 may be formed in a Z direction perpendicular to the substrate 1199 (eg, formed vertically in the Z direction relative to the substrate 1199 ).

[0132] like Fig.11A As shown, each of the stacks 11050, 11051, 11052, and 11053 may have memory cells arranged in the X direction and the Y direction (e.g., arranged in rows in the X direction and arranged in columns in the Y direction). For example, the stack 11050 may include memory cells 11100, 11110, 11120, and 11130 (e.g., arranged in rows), memory cells 11200, 11210, 11220, and 11230 (e.g., arranged in rows), and memory cells 11300, 11310, 11320, and 11330 (e.g., arranged in rows).

[0133] Stack 11051 may include memory cells 11101, 11111, 11121, and 11131 (eg, arranged in rows), memory cells 11201, 11211, 11221, and 11231 (eg, arranged in rows), and memory cells 11301, 11311, 11321, and 11331 (eg, arranged in rows).

[0134] Stack 11052 can include memory cells 11102, 11112, 11122, and 11132 (eg, arranged in rows), memory cells 11202, 11212, 11222, and 11232 (eg, arranged in rows), and memory cells 11302, 11312, 11322, and 11332 (eg, arranged in rows).

[0135] Stack 11053 may include memory cells 11103, 11113, 11123, and 11133 (eg, arranged in rows), memory cells 11203, 11213, 11223, and 11233 (eg, arranged in rows), and memory cells 11303, 11313, 11323, and 11333 (eg, arranged in rows).

[0136] like Fig.11A As shown, stacks 11050, 11051, 11052, and 11053 may be located on levels (e.g., portions) 1150, 1151, 1152, and 1153, respectively, of the memory device 1100 (e.g., formed vertically in the Z direction). Stacks 11050, 11051, 11052, and 11053 form a three-dimensional (3D) structure of memory cells of the memory device 1100, wherein memory cells of different levels of the memory device 1100 may be located (e.g., formed in) different levels (e.g., different vertical portions) 1150, 1151, 1152, and 1153 of the memory device 1100.

[0137] The stacks 11050, 11051, 11052, and 11053 may be formed one stack at a time. For example, the stacks 11050, 11051, 11052, and 11053 may be formed sequentially in the order of the stacks 11050, 11051, 11052, and 11053 (e.g., stack 11050 is formed first and stack 11053 is formed last). In this example, the memory cells of one stack (e.g., stack 11051) may be formed after forming the memory cells of another stack (e.g., stack 11050) or before forming the memory cells of another stack (e.g., stack 11052). Alternatively, stacks 11050, 11051, 11052, and 11053 may be formed in parallel (e.g., simultaneously) so that the memory cells of stacks 11050, 11051, 11052, and 11053 may be formed in parallel. For example, memory cells in levels 1150, 1151, 1152, and 1153 of memory device 1100 may be formed in parallel.

[0138] The structure of the memory cells in each of the stacks 11050, 11051, 11052, and 11053 may include the above reference Figures 1 to 10E For example, the structure of the memory cells of stacks 11050 , 11051 , 11052 , and 11053 may include the structure of the memory cells of memory devices 200 , 900 , and 1000 .

[0139] The memory device 1100 may include data lines (eg, bit lines) and access lines (eg, word lines) to access the memory cells of the stacks 11050, 11051, 11052, and 11053. For simplicity, Fig.11A The data lines and access lines of the memory cells are omitted. However, the data lines and access lines of the memory device 1100 may be similar to those described above with reference to Figures 1 to 10E Data lines and access lines of a memory device are described.

[0140] As an example, Fig.11A Memory device 1100 is shown to include four stacks (e.g., 11050, 11051, 11052, and 11053). However, the number of stacks may be different than four. As an example, Fig.11A Each of the stacks 11050, 11051, 11052, and 11053 is shown to include one level (e.g., layer) of memory cells. However, at least one of the stacks (e.g., one or more of the stacks 11050, 11051, 11052, and 11053) may have two (or more) levels of memory cells. Fig.11A An example is shown where each of the stacks 11050, 11051, 11052, and 11053 includes four memory cells in the X direction (e.g., in rows) and three memory cells in the Y direction (e.g., in columns). However, the number of memory cells in rows, columns, or both can vary.

[0141] The illustrations of apparatus (e.g., memory devices 100, 200, 900, 1000, and 1100) and methods (e.g., the operation of memory devices 100 and 200, and methods of forming memory devices 900 and 1000) are intended to provide a general understanding of the structure of various embodiments, but are not intended to provide a complete description of all elements and features of apparatus that may utilize the structures described herein. An apparatus herein refers to, for example, any device (e.g., any one of memory devices 100, 200, 900, 1000, and 1100) or a system (e.g., an electronic product that may include any one of memory devices 100, 200, 900, 1000, and 1100).

[0142] References Figures 1 to 10E Any of the components described may be implemented in a variety of ways, including simulation via software. Thus, an apparatus (e.g., memory devices 100, 200, 900, 1000, and 1100) or a portion of each of these memory devices described above may be characterized herein as a "module" (modules or module). Such modules may include hardware circuitry, single-processor and / or multi-processor circuits, memory circuits, software program modules and objects, and / or firmware, and combinations thereof, as required and / or appropriate for a particular implementation of the various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware to operate or simulate the operation of various potential embodiments.

[0143] The memory devices described herein (e.g., memory devices 100, 200, 900, 1000, and 1100) may be included in an apparatus (e.g., electronic circuit system), such as a high-speed computer, a communication and signal processing circuit system, a single processor or a multi-processor module, a single or multiple embedded processors, a multi-core processor, a message information switch, and a dedicated module including a multi-layer, multi-chip module. Such an apparatus may further be included as a subcomponent in a variety of other apparatuses (e.g., electronic systems) (e.g., televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.).

[0144] References Figures 1 to 10E Embodiments described include devices and methods of forming the devices. One of the devices includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. A portion of the conductive line spans a portion of the first region of the first transistor and a portion of the second region of the second transistor. Other embodiments including additional devices and methods are described.

[0145] In the detailed description and claims, the terms "on," one "on" another, used with respect to two or more elements (e.g., materials), mean at least some contact between the elements (e.g., between the materials). The term "over" means that the elements (e.g., materials) are in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "over" implies any directionality as used herein unless so stated.

[0146] In the detailed description and claims, a list of items joined by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0147] In the detailed description and claims, a list of items joined by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means either only A (not including B) or only B (not including A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0148] The above description and drawings illustrate some embodiments of the subject matter of the present invention to enable those skilled in the art to practice the embodiments of the subject matter of the present invention. Other embodiments may have structural, logical, electrical, process and other changes. Examples represent possible variations only. Portions and features of some embodiments may be included in those portions and features of other embodiments, or replace those portions and features. After reading and understanding the above description, those skilled in the art will understand many other embodiments.

Claims

1. A memory device, comprising: A first data line; A second data line; a memory cell coupled to the first and second data lines, the memory cell comprising: a first transistor including a first region electrically coupled to the first and second data lines, a charge storage structure located on a first level of the memory device and electrically separated from the first region; and a second transistor including a second region located on a second level of the memory device and electrically separated from the first region, the second region being electrically coupled to the charge storage structure and the second data line, wherein the first region extends from the first level to the second level such that a portion of the first region is located on the second level and adjacent to the second region; as well as A conductive line is electrically separated from the first and second regions, a portion of the conductive line spanning a portion of the first region of the first transistor and a portion of the second region of the second transistor. 2 . The memory device of claim 1 , wherein the first region includes a channel region of the first transistor, and the second region includes a channel region of the second transistor.

3. The memory device of claim 1, wherein the conductive line is part of an access line for accessing the memory cell. 4 . The memory device of claim 1 , wherein the first region comprises a p-type semiconductor material and the second region comprises an n-type semiconductor material. The memory device of claim 1 , wherein the first region comprises a block of semiconductor material.

6. The memory device of claim 2, wherein the second region comprises a block of oxide material, and the charge storage structure comprises one of a block of metal and a block of semiconductor material directly coupled to the block of oxide material.

7. The memory device of claim 2, wherein the second region comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium oxide Indium zinc (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP). 8 . The memory device of claim 1 , wherein the first region and the conductive line are located above a substrate, and the first region is closer to the substrate than the conductive line.

9. The memory device of claim 1, wherein the first and second transistors have different threshold voltages.

10. The memory device of claim 1, wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor.

11. The memory device of claim 1 , wherein the first transistor has a first threshold voltage less than zero when the charge storage structure is in a first state, and the first transistor has a second threshold voltage less than zero when the charge storage structure is in a second state, and the first and second states represent different values ​​of information stored in the memory cell.

12. A memory device comprising: a first conductive region located in a first level of the memory device; a second conductive region located in a second level of the memory device; a memory cell located between the first and second levels and coupled to the first and second conductive regions, the memory cell comprising: a first material located between the first and second levels in a third level of the memory device, the first material forming a memory element of the memory cell; a second material located between the second and third levels in a fourth level of the memory device, the second material contacting the first material and directly contacting the second conductive region; as well as; A semiconductor material is electrically separated from the first and second materials, the semiconductor material directly contacting the first and second conductive regions.

13. The memory device of claim 12, wherein the second material comprises a block of semiconductor material.

14. The memory device of claim 13, wherein the first material comprises a block of metal directly coupled to the block of semiconductor material.

15. The memory device of claim 13, wherein the first material comprises a block of semiconductor material directly coupled to the block of semiconductor material.

16. The memory device of claim 12, wherein the second material and the semiconductor material have different conductivity types.

17. The memory device of claim 12, wherein the second material comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

18. The memory device of claim 12, wherein the semiconductor material comprises: a first portion separated from a first side of the first material and a first side of the second material by a first dielectric; a second portion separated from a second side of the first material and a second side of the second material by a second dielectric; as well as A third portion is separated from the first material by a third dielectric.

19. The memory device of claim 12, further comprising a conductive material including a portion adjacent to one side of the first material and adjacent to one side of the second material, wherein a direction passing through the first and second materials from the first conductive region to the first and second materials is a first direction, and the conductive material has a length extending in a second direction.

20. The memory device of claim 19, further comprising additional conductive material including portions adjacent to an additional side of the first material and adjacent to an additional side of the second material, and having a length extending in the second direction.

21. The memory device of claim 20, wherein the conductive material and the additional conductive material are part of an access line of the memory device.

22. The memory device of claim 12, wherein the first conductive region is part of a first data line of the memory device and the second conductive region is part of a second data line of the memory device.

23. A method for forming a memory device, comprising: forming a first material over a substrate; forming a second material directly on the first material; removing a portion of the first material to form first portions from remaining portions of the first material, the first portions being electrically separated from each other; removing a portion of the second material to form second portions from remaining portions of the second material, the second portions being electrically separated from each other; forming memory cells such that each of the memory cells includes a first transistor and a second transistor, the first transistor including a charge storage structure formed by a portion of the first portion, and the second transistor including a region formed by a portion of the second portion; Before forming the first material and the second material, forming a first data line on the substrate; forming a channel region directly contacting the first data line; A second data line is formed over the second material and the channel region such that the second data line directly contacts the second material and the channel region.

24. The method of claim 23, wherein forming the first material comprises depositing a metallic material over the substrate.

25. The method of claim 23, wherein forming the second material comprises depositing a semiconductor material on the first material.

26. The method of claim 23, wherein forming the second material comprises depositing an oxide material on the first material.

27. The method of claim 23, wherein forming the second material comprises depositing at least one of the following directly over the first material: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZn zOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

28. The method of claim 23, further comprising: forming a first conductive material over the substrate before forming the first and second materials, the first conductive material being formed such that the first conductive material is electrically separated from the first material; removing a portion of the first conductive material to form the first data line; forming a second conductive material in contact with the channel region and the second material; as well as A portion of the second conductive material is removed to form the second data line.

29. The method of claim 23, further comprising: forming a first conductive line adjacent to a first side of a semiconductor region of the first transistor and adjacent to a first side of the region of the second transistor; as well as A second conductive line is formed adjacent to a second side of the semiconductor region of the first transistor and adjacent to a second side of the region of the second transistor.

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