Isolation enables test coverage for multiple power domains

Abstract

Embodiments of the present disclosure relate to isolation-enabled test coverage for multiple power domains. A method for testing a multiple power domain device includes sending a control signal from a test controller powered by a switchable power domain to a non-scan test data register powered by a normally-on power domain. The method also includes using the control signal to set a test data register value of the register to enable a scan mode by bypassing an isolation unit between an output of the switchable domain and an input of the normally-on domain, and while the register value continuously enables the scan mode: moving a test pattern into a scan chain including a trigger coupled to the isolation unit, capturing a test result from the scan chain, and moving the test pattern out of the scan chain to observe the test result. The isolation unit is configured to allow or prohibit the propagation of a signal from the output to the input.

Description

Technical Field

[0001] The present invention generally relates to isolation enabling test coverage for multiple power domains and, in particular embodiments, to methods for testing isolation enabling faults in devices and systems including multiple power domains and devices and systems utilized therein. Background Art

[0002] As electronic devices become more complex, hardware verification during manufacturing becomes increasingly important. Design for Test (DFT) techniques are often used to incorporate testability features into hardware designs to improve testability. For example, test controllers, test registers, logic, and other components can be included in the circuit design so that the circuit can be tested efficiently. DFT is often used in conjunction with Automatic Test Pattern Generation (ATPG) to test defective digital circuits in an automated manner.

[0003] A test controller can be used to provide an interface between a general purpose computing device and the device under test (DUT) controls. The test controller can be external to the DUT or integrated into the DUT. Industry standards such as the Joint Test Action Group (JTAG) standardize on-chip instrumentation for testing by specifying a serial communication interface that can access test registers.

[0004] A multi-power domain device such as a system on chip (SoC) includes two or more power domains with different characteristics. For example, the power domains may operate at different voltage levels or may be individually capable of being turned on and off. To avoid unknown states, some or all signal transfers between different power domains pass through isolation units, which may be enabled to prohibit signal propagation (e.g., when a power domain is turned off) or may be disabled to allow signals to be transferred between power domains.

[0005] Conventional DFT configurations for multi-power domain devices may not provide test coverage for all isolation enable faults. For example, the isolation enable signal may not be included in the scan process or may be forced to remain static for testing purposes. Therefore, DFT techniques that allow testing of isolation enable faults in multi-power domain devices may be needed. Summary of the invention

[0006] According to an embodiment of the present invention, a method for testing a multi-power domain device includes sending a test control signal from a test controller powered by a first switchable power domain to a non-scan test data register powered by a normally-on power domain. The normally-on power domain includes a normally-on input and is configured to always receive power while the multi-power domain device is powered. The first switchable power domain includes a first switchable output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered. The method also includes using the test control signal to set a test data register value of the test data register to enable a scan mode by bypassing a first isolation unit between the first switchable output and the normally-on input, and while the test data register value continuously enables the scan mode: moving a test pattern into a scan chain including a functional isolation enable trigger coupled to the first isolation unit, capturing a test result from the scan chain, and moving the test pattern out of the scan chain to observe the test result. The first isolation unit is configured to allow or prohibit a first signal originating from the first switchable output from propagating to the normally-on input through the first isolation unit.

[0007] According to another embodiment of the present invention, a method for testing a multi-power domain device includes sending a test control signal from a test controller powered by a first switchable power domain to a non-scan test data register powered by an always-on power domain. The always-on power domain includes an always-on input and core wrapper logic, and the always-on power domain is configured to always receive power while the multi-power domain device is powered. The first switchable power domain includes a first switchable output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered. The always-on power domain also includes an always-on multiplexer, which includes an always-on multiplexer output coupled to a first isolation unit, and the first isolation unit is configured to allow or prohibit a first signal from propagating from the first switchable output to the always-on input. The method also includes setting a test data register value of a test data register to a first value using a test control signal, the test data register value being coupled to an always-on selector input of an always-on multiplexer, inputting a forced isolation signal at an always-on domain connection, selecting the forced isolation signal at the always-on selector input using the first value, and testing the always-on power domain of the multi-power domain device while the forced isolation signal is continuously selected by the first value.

[0008] According to another embodiment of the present invention, a multi-power domain device includes: an always-on power domain, the always-on power domain including an always-on input and configured to always receive power while the multi-power domain device is powered; a first switchable power domain, the first switchable power domain including a first switchable output and configured to switch between a powered state and an unpowered state while the multi-power domain device is powered; an isolation unit coupled between the first switchable output and the always-on input; an isolation enable circuit, the isolation enable circuit being powered by the always-on power domain and configured to output an isolation enable signal to allow or prohibit a first signal originating from the first switchable output from propagating to the always-on input; a non-scan test data register powered by the always-on power domain; and a test controller powered by the first switchable power domain and coupled to the test data register. The test controller is configured to send a test control signal to the test data register to set a test data register value, and to test an isolation enable fault by maintaining a scan mode of the always-on power domain using the test data register value while the isolation enable signal is switched. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 illustrates a schematic diagram of a multi-power domain device having a normally-on power domain including an isolation enable circuit and a switchable power domain including a test controller;

[0011] Figure 2 illustrates a schematic diagram of a multi-power domain device having a normally-on power domain including a first isolation enable circuit, a power-on reset circuit, and an external connection, and a first switchable power domain including a test controller coupled to the external connection;

[0012] Figure 3 A schematic diagram of a multi-power domain device having a non-scan test data register included in an always-on power domain according to an embodiment of the present invention is illustrated;

[0013] Figure 4 illustrates a schematic diagram of another multi-power domain device having a non-scan test data register included in an always-on power domain according to an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of another multi-power domain device having a non-scan test data register included in an always-on power domain according to an embodiment of the present invention is illustrated;

[0015] Figure 6 An example method of testing a multi-power domain device without a core wrapped AO domain according to an embodiment of the present invention is illustrated;

[0016] Figure 7 Another example method of testing a multi-power domain device having a core wrapped AO domain according to an embodiment of the present invention is illustrated;

[0017] Figure 8 illustrates an example method of entering and exiting a low power state by a multi-power domain device according to an embodiment of the present invention;

[0018] Fig. 9 illustrates an example method of entering and exiting a standby state by a multi-power domain device according to an embodiment of the present invention;

[0019] Fig.10 illustrates an example method of testing a multi-power domain device without a core wrapped AO domain according to an embodiment of the present invention; and

[0020] Fig.11 An example method of testing a multi-power domain device having a core wrapped AO domain according to an embodiment of the present invention is illustrated.

[0021] Unless otherwise indicated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the scope of the features. DETAILED DESCRIPTION

[0022] The manufacture and use of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein are applicable to a variety of specific situations. The specific embodiments discussed are only illustrations of specific ways to manufacture and use the various embodiments and should not be interpreted in a limited scope.

[0023] In modern circuit design, multiple power domains can be utilized for a variety of reasons. For example, different functional circuit blocks in a single device can operate at different voltage levels or at different times. These different functional blocks can be logically organized into power domains, which can include a single intellectual property (IP) core or multiple IP cores. When the power domain of a multi-power domain device is configured to remain in a powered state at all times when the device receives power, the power domain can be referred to as a normally-on domain. In contrast, a power domain of a multi-power domain device that is configured to switch between a powered state and an unpowered state while the device continuously receives power can be referred to as a switchable domain.

[0024] Power domains can consist of any number or combination of different circuits integrated in the same chip, different IP cores in an SoC, different chips in a system-in-package (SiP), etc. For example, an SoC implementing multiple power domains can include features such as always-on / standby modes and can find applications in automotive-grade devices, safety application devices, and other devices that combine analog, digital, and hybrid circuits into a single system.

[0025] Improper functionality of isolation enable signals between power domains may negatively impact device functionality. For example, if signals from an unpowered domain are allowed to pass through the isolation, the power consumption of the device may be increased and device failure may occur. Alternatively, if signals such as reset signals are not properly allowed to pass through the isolation, the switchable power domains may not be reset (e.g., after a low power exit, standby exit, etc.), resulting in an unknown device state. Although possible, it is impractical to detect isolation enable failures that degrade device performance.

[0026] The functional pattern may not cover all possible faults involving signals passing through the isolation between switchable power domains (e.g., isolation cell enable faults). For example, a test controller located in one power domain may send a signal into a second power domain during testing. To test the second power domain, the isolation enable value may be fixed to allow the signal to pass through. Therefore, the ability to turn off the isolation enable (i.e., prohibit the signal from passing through) will not be tested.

[0027] Relying solely on functional patterns can also result in coverage loss due to not all device power-up configurations supported by a given tester setup. This can occur when the part is placed externally relative to the multiple power domains being tested. However, even though functional patterns can enable coverage of isolated enable faults, functional patterns disadvantageously increase test time.

[0028] Conventional test methods present other disadvantages for chips with multiple power domains when core wrapping is employed (e.g., for SoCs). Wrapped cores can be checked in two modes: INTEST (where the core logic is tested) and EXTEST (where the core integration within the SoC is tested). Input and output signals that pass through the isolated wrapped core can be tested in EXTEST mode. However, the isolation enable function itself remains untested because it is generated by logic in the core that is not in the EXTEST scan and is in a static state (e.g., the reset state of a flip-flop). However, since the interfaces between the core domain and other domains are not checked during INTEST, the INTEST mode also does not provide isolation enable fault test coverage.

[0029] In various embodiments, a multi-power domain device includes a normally-on power domain and a switchable power domain. At least some inputs of the normally-on power domain configured to receive output signals of the switchable power domain are passed through an isolation unit, which can be enabled to prevent the propagation of the output signal (e.g., when the switchable domain is not powered), or can be disabled to allow the output signal to propagate into the normally-on power domain (e.g., when both domains are powered). A test controller is included in the switchable power domain. The test controller is coupled to a non-scan test data register included in the normally-on power domain.

[0030] Embodiments disclosed herein may have various advantages over conventional methods, devices, and systems for testing devices with multiple power domains. For example, both stuck-at-0 faults and stuck-at-1 faults are advantageous for all isolation cells enabled. Isolation enable faults are detected by ATPG techniques, which may also advantageously reduce the required test time compared to pure functional pattern testing. In addition, embodiments herein may also have the advantage of providing desired isolation enable test coverage at all test temperatures (i.e., cold and hot test scenarios).

[0031] The embodiments provided below describe various methods, devices, and systems for isolating enable faults in methods, devices, and systems for testing devices and systems that include multiple power domains, and in particular, include a test controller in a switchable power domain coupled to a non-scanned test data register in a normally-on power domain. The following description describes the embodiments. Figure 1 An example multi-power domain device including an always-on power domain and a switchable power domain is described. Figure 2 An example multi-power domain device is described that includes an always-on power domain having a first isolation enable circuit, a power-on reset circuit, and an external connection, and a switchable power domain having a test controller coupled to the external connection. Figure 3 , 4 5 and 5 describe three embodiments of a multi-power domain device including a non-scan test data register in an always-on power domain, and Figure 6 and 7 Two example methods for testing multi-power domain devices are described. Figure 8 Methods for entering and exiting low power states by a multi-power domain device of an embodiment are described. Fig. 9 Methods for entering and exiting a standby state of a multi-power domain device through an embodiment are described. Fig.10 and 11 Two additional example methods of testing multiple power domain devices are described.

[0032] Figure 1 A schematic diagram of a multi-power domain device having a normally-on power domain including an isolation enable circuit and a switchable power domain including a test controller is illustrated. Figure 1 The multi-power domain device is intended as an example suitable configuration for the embodiments described herein. However, other suitable configurations including more or fewer power domains will be apparent to those skilled in the art in view of the examples described herein.

[0033] refer to Figure 1 , the multi-power domain device 100 includes a normally-on power domain (AO domain 102), a first switchable power domain (SW1 domain 110), and an optional second switchable power domain (SW2 domain 120). The multi-power domain device 100 can be a monolithic integrated circuit (IC), a SoC, a SiP, a printed circuit board, or any other suitable electronic device. Some or all of the power domains of the multi-power domain device 100 can be core wrapped to simplify the testing process (for example, for large SoCs). In one embodiment, the AO domain 102 is core wrapped.

[0034] The AO domain 102 is configured to be in a powered state at all times when the multi-power domain device 100 is powered. The AO domain 102 can have any functions, but in various embodiments, the functions of the AO domain 102 make its continuous powered state desirable. For example, the AO domain 102 can perform a large number of support tasks for the multi-power domain device 100 that are always required. In some embodiments, the AO domain 102 includes analog IP in one embodiment and includes a power management unit (PMU). The PMU may include embedded regulators, power management control logic, etc. Of course, the AO domain 102 may also include digital IP, mixed signal IP (including multiple IPs or varying types), etc.

[0035] The SW1 domain 110 and the SW2 domain 120 are both configured to switch between a powered state and an unpowered state while the multi-power domain device 100 continuously receives power. In one embodiment, the SW1 domain 110 is configured as a master domain of the multi-power domain device 100. For example, the SW1 domain 110 may be a digital IP such as a processing unit. In one embodiment, the SW1 domain 110 is a microprocessor. Compared to the AO domain 102, performance may be of higher importance to the SW1 domain 110. For example, compared to the AO domain 102, the SW1 domain 110 may run at a higher clock frequency and draw a larger current.

[0036] In one embodiment, the SW2 domain 120 is configured as a low power (LP) domain of the multi-power domain device 100. Similar to the SW1 domain 110, the SW2 domain 120 is configured as a switchable domain. Compared to the SW1 domain 110, when the SW2 domain 120 is configured as a LP domain, the SW2 domain 120 can be configured to play a supporting role for the multi-power domain device 100. Specifically, the performance of the SW2 domain 120 may be less important for the SW2 domain 120 than for the SW1 domain 110. Therefore, the SW2 domain 120 can run at a lower clock frequency and draw less current than the SW1 domain 110.

[0037] In particular, the multi-power domain device 100 can have a standby feature. When the multi-power domain device 100 is in standby mode, the AO domain 102 remains turned on because the AO domain 102 is always on. However, both the SW1 domain 110 and the SW2 domain 120 can be turned off to save power. When the multi-power domain device 100 is not in standby mode, intensive main processing tasks can be handled by the SW1 domain 110 in the operating mode. When not in the operating mode, the SW1 domain 110 can be turned off. Support tasks can be handled by the SW2 domain 120 and can occur in or outside the operating mode. Therefore, regardless of the state of the operating mode, the SW2 domain 120 can be turned on or off. In some cases, when the SW1 domain 110 is turned on (i.e., during the operating mode), the SW2 domain 120 can be turned on all the time, but this is not necessary.

[0038] The multi-power domain device 100 includes various signals passed between the AO domain 102, the SW1 domain 110, and the SW2 domain 120. For example, the AO domain 102 includes an output signal (AO-SW1 signal 104) passed from the AO domain 102 to the SW1 domain 110 and an output signal (AO-SW2 signal 106) passed from the AO domain 102 to the SW2 domain 120. The AO domain 102 also receives an input signal (SW1-AO signal 112) from the SW1 domain 110 and an input signal (SW2-AO signal 122) from the SW2 domain 120. Similarly, input and output signals can be passed between the SW1 domain 110 and the SW2 domain 120 (SW1-SW2 signal 116 and SW2-SW1 signal 124). It should be noted that although illustrated as a group of multiple signals, in some applications, any of these signals can be a single signal.

[0039] Some or all input and output signals between power domains may pass through isolation cells, which may be enabled / disabled to prevent / allow signals to pass between different power domains. For example, isolation cells between power domains may be desirable when one or both of the power domains are switchable, since the output signals of the unpowered domain are not deterministic. That is, if signals are allowed to propagate across the boundary, the inputs of the powered domain may be infected by the "X" value from the unpowered domain.

[0040] Since the AO domain 102 is prohibited from being in an unpowered state, it is not always necessary to include an isolation unit for output signals from the AO domain 102. However, it may still be desirable to pass some output signals (e.g., a reset signal) from the AO domain 102 through the isolation unit. The isolation unit can be enabled when the power domain providing the signal is not powered. When both domains are powered, the isolation unit can be disabled, allowing the signal to cross between the two domains.

[0041] The isolation enable circuit 108 is included in the AO domain 102 and is configured to output an isolation enable signal 138 to an isolation unit of one or more of the AO-SW1 signal 104 and the SW1-AO signal 112. When the isolation enable signal 138 is enabled, the AO-SW1 signal 104 and the SW1-AO signal 112 can be prevented from propagating between the AO domain 102 and the SW1 domain 110. The isolation enable circuit 108 can also be connected to the AO-SW2 signal 106 and the SW2-AO signal 122. Alternatively, different isolation enable circuits can be used to achieve isolation for the AO-SW2 signal 106 and the SW2-AO signal 122.

[0042] The isolation unit can be implemented in various ways. In one embodiment, each signal is passed through an isolation unit that includes a tri-state buffer. In some cases (for example, when the power domains operate at different voltage levels), the isolation unit can be combined with a level shifter. The isolation unit can be as simple as a single logic gate, where one input receives a signal and the other input is connected to an isolation enable circuit (control value). The choice of logic type can affect the output of the isolation enable circuit. For example, the isolation enable signal that enables isolation can be "1" when using an OR gate and can be "0" when using an AND gate.

[0043] For conceptual clarity, inputs and outputs are illustrated as being located in respective power domains. However, in reality, the isolation circuitry may exist in a specific power domain (as opposed to between power domains or bridging power domains). For example, the isolation unit may be powered by (and therefore within) a power domain that includes the isolation enabling circuit. For example, an isolation unit for signal isolation between the AO domain 102 and the SW1 domain 110 may be within the AO domain 102.

[0044] A test controller 118 is included in the SW1 domain 110. Access to test functions and hardware (e.g., registers) may be provided by the test controller 118. In one embodiment, the test controller 118 is a JTAG test controller. The test controller 118 is configured to enable testing of the AO domain 102. The test controller 118 may be included in the SW1 domain 110 instead of the AO domain 102 to maintain lower power consumption of the AO domain 102 (e.g., the AO domain 102 may only draw 2 mA, while the SW1 domain 110 may draw 5 A). Additionally, providing a single test controller in one power domain may be more economical than including a test controller for each power domain.

[0045] The test controller 118 is configured to provide an interface between the multi-power domain device 100 and an external test device. The external test device may not provide power to the multi-power domain device 100 during testing. For example, the external test device may not include any switching power supply (SMPS) components.

[0046] However, the signal from the test controller 118 is part of the SW1-AO signal 112 and passes through the isolation unit between the AO domain 102 and the SW1 domain 110. Therefore, during the test, the isolation enable signal 138 continuously allows the SW1-AO signal 112 to pass into the AO domain 102. Therefore, the ability of the isolation enable circuit 108 to enable the isolation unit using the isolation enable signal 138 remains untested.

[0047] Isolation cell enable faults may only be covered in certain functional patterns (e.g., LP domain entry / exit and AO domain entry / exit patterns). For example, if the isolation enable signal 138 is always "1" (enabling signals from unpowered switchable domains), the output of the isolation enable circuit 108 is unknown. Since the tester setup does not support all device power-up configurations, relying only on functional patterns may result in loss of coverage.

[0048] As a specific example, multiple power domains may exist only in internal regulator mode, but components may be located externally (e.g., external metal oxide semiconductor (MOS) transistors, inductors, capacitors, etc. for SMPS and external bipolar junction transistors in a linear regulator). However, the external components may not be available to the test equipment (e.g., during cold test phases such as electronic wafer sort), resulting in loss of coverage.

[0049] Figure 2 A schematic diagram of a multi-power domain device is illustrated, the multi-power domain device having a normally-on power domain including a first isolation enable circuit, a power-on reset circuit and an external connection, and a first switchable power domain including a test controller coupled to the external connection. For example, Figure 2It may be other multi-power domain devices described herein (such as Figure 1 The specific implementation of multi-power domain devices).

[0050] refer to Figure 2 , the multi-power domain device 200 includes an AO domain 202, a SW1 domain 210, and a SW2 domain 220. It should be noted that for the sake of brevity and clarity, a convention is adopted herein and hereinafter, wherein in various embodiments, an element attached to pattern x02 may be a related implementation of an AO domain. For example, unless otherwise noted, the AO domain 202 may be similar to the AO domain 102. Similar conventions are adopted for other elements, which may be made clear by using similar terminology in conjunction with the three-digit numbering system described above.

[0051] While receiving SW1-AO signal 212 and SW2-AO signal 222 as inputs, AO domain 202 outputs AO-SW1 signal 204 and AO-SW2 signal 206. AO-SW1 isolation enable circuit 208, AO-SW2 isolation enable circuit 209, power-on reset (PoR) circuit 240, and AO domain connection 246 (e.g., pads, contacts, pins, etc.) are included in AO domain 202, which can receive power from an AO power supply connection (vddlv_ao).

[0052] The AO-SW1 isolation enable circuit 208 outputs an AO-SW1 isolation enable signal 238 to the isolation unit 233, and the AO-SW1 signal 204 and the SW1-AO signal 212 pass through the isolation unit 233, while the AO-SW2 isolation enable circuit 209 outputs an AO-SW2 isolation enable signal 237 to the isolation unit 233, and the AO-SW2 signal 206 and the SW2-AO signal 222 pass through the isolation unit 233. When the AO-SW1 isolation enable signal 238 or the AO-SW2 isolation enable signal 237 triggers the corresponding isolation unit 233 to be enabled, the signal will not pass through them to enter or leave the AO domain 202. In the same way, when the AO-SW1 isolation enable signal 238 or the AO-SW2 isolation enable signal 237 triggers the corresponding isolation unit 233 to be disabled, the signal freely passes through the isolation.

[0053] Since both SW1 domain 210 and SW2 domain 220 are switchable domains, as shown, SW1-SW2 signal 216 and SW2-SW1 signal 224 are also passed through isolation unit 233. SW2-SW1 isolation enable circuit 228 sends SW2-SW1 isolation enable signal 239 to isolation unit 233 to enable / disable signal propagation between SW1 domain 210 and SW2 domain 220.

[0054] The SW1 domain 210 may receive power from the SW1 power supply connection (vddlv_main). A test controller 218 and a SW1 domain connection 248 are included in the SW1 domain 210. The test controller 218 is configured to enable testing of the AO domain 202. The test controller 218 may also be configured to facilitate testing of other domains and circuits of the multi-power domain device 200. Some tester setups may not have external SMPS components, which may result in a loss of coverage if only functional patterns are used.

[0055] The test controller 218 outputs a power switch close signal (power_switch_close_MD as SW1 output after traveling through isolation and power_switch_close_AO as AO input) and a scan mode signal (scan_mode_MD as SW1 output after traveling through isolation and scan_mode_AO as AO input), which are shown included in the SW1-AO signal 212. The test controller 218 receives a test controller input 236 from an AO domain connection 246 in the AO domain 202 that does not pass through isolation.

[0056] The scan mode signal and / or the power switch closure signal may be critical to the scan. For example, the scan mode signal may be configured to place the multi-power domain device 200 in a scan mode (i.e., for testing). In some cases, such as if more than one test controller is present in the multi-power domain device 200, the scan mode signal may place only a portion of the multi-power domain device in a scan mode (e.g., the AO domain 202).

[0057] When the AO domain 202 receives power after being unpowered (e.g., turned on, restarted, etc.), the PoR circuit 240 outputs a reset signal. The reset signal is sent to the various domains and circuits in the multi-power domain device 200 so that they will start in a known state. For example, as shown in the figure, the reset signal of the PoR circuit 240 resets the AO domain 202 (reset_AO) and is output to the SW1 domain 210 (reset_MD) and the SW2 domain 220 (reset_LP). Within the AO domain 202, the reset signal is used to reset the AO-SW1 isolation enable circuit 208 and the AO-SW2 isolation enable circuit 209. Similarly, the reset signal is used to reset the test controller 218 (reset_tcu) within the SW1 domain 210 and the SW2-SW1 isolation enable circuit 228 within the SW2 domain 220.

[0058] Although not all output signals from the AO domain 202 are passed through isolation (e.g., because the AO domain 202 is not switchable), the reset signal is passed through the isolation unit 233. For example, the reset signal from the powered domain to the unpowered domain can remain enabled until the unpowered domain gets a new reset when it is powered up again. If isolation is enabled for the signals from the AO domain 202 to the PoR circuit 240 of the SW1 domain 210 during ATPG, the test controller 218 will reset and exit ATPG mode.

[0059] In various embodiments, a core wrapper is implemented for the AO domain 202. For example, the AO domain 202 may be an IP core of a multi-power domain device 200 (e.g., in a SoC) that has registers accessible during testing at some or all of its inputs / outputs. Each register may be implemented as a flip-flop (FF) as part of a scan chain.

[0060] The core wrapping method is a common strategy for ATPG in SoC (e.g., large SoC), which can be used to reduce the number of test patterns and simply reduce integration testing. When the CORE is wrapped, it will be checked in EXTEST and INTEST modes. When the core is in INTEST mode, the core logic can be tested. When the rest of the SoC is tested (e.g., integration of the core with the SoC), the core can be in EXTEST mode.

[0061] During INTEST, the core logic can be driven by the wrapper FF at the core inputs, and the results are captured at the wrapper FF outputs of the core logic. During EXTEST, both the inputs and outputs of the core and the rest of the SoC can be tested together. This operation can be facilitated by capturing the inputs of the core from the rest of the SoC in the wrapper FF. The wrapper FF can then drive the outputs from the core to the rest of the SoC instead of testing the core logic.

[0062] The isolation cell may be placed between the core input and the input of the wrapper FF. For core outputs that pass through isolation, the isolation cell may be placed between the output of the wrapper FF and the core output. The isolation enable signal for the isolation cell may be driven by a FF within the core logic. For example, when core wrapping is employed, the AO-SW1 isolation enable circuit 208 may be implemented as a functional FF within the core logic of the AO domain 202.

[0063] It should be noted that not all inputs and outputs of a wrapped core may be wrapped. For example, it may be desirable for unwrapped inputs and outputs to be static during ATPG, or static during transfer and / or capture. These may include scan mode bits, scan mode controls, connections (e.g., pads) controlled by the ATPG pattern generation script, and non-scanned test data registers (TDRs). For example, when core wrapping is used for the AO domain 202, outputs from the test controller 218 received by the AO domain 202 may not be wrapped.

[0064] Figure 3 A schematic diagram of a multi-power domain device having non-scan test data registers included in a normally-on power domain according to an embodiment of the present invention is illustrated. For example, Figure 3 It may be other multi-power domain devices described herein (such as Figure 1 and 2 A specific implementation of a multi-power domain device). Similar labeled elements may be as previously described.

[0065] refer to Figure 3 , the multi-power domain device 300 includes an AO domain 302, a SW1 domain 310, and a SW2 domain 320. The AO domain 302 outputs an AO-SW1 signal 304 and an AO-SW2 signal 306 while receiving a SW1-AO signal 312 and a SW2-AO signal 322 as inputs. The SW1-SW2 signal 316 and the SW2-SW1 signal 324 are transmitted between the SW1 domain 310 and the SW2 domain 320.

[0066] As previously described, AO-SW1 isolation enable circuit 308 , AO-SW2 isolation enable circuit 309 , power-on reset (PoR) circuit 340 , and AO domain connection 346 are included in AO domain 302 , while test controller 318 and SW1 domain connection 348 are included in SW1 domain 310 .

[0067] The AO-SW1 isolation enable circuit 308 outputs an AO-SW1 isolation enable signal 338 to the isolation unit 333, and the AO-SW1 signal 304 and the SW1-AO signal 312 are transmitted through the isolation unit 333, while the AO-SW2 isolation enable circuit 309 outputs an AO-SW2 isolation enable signal 337 to the isolation unit 333, and the AO-SW2 signal 306 and the SW2-AO signal 322 are transmitted through the isolation unit 333. The SW2-SW1 isolation enable circuit 328 in the SW2 domain 320 sends a SW2-SW1 isolation enable signal 339 to the isolation unit 333 of the SW1-SW2 signal 316 and the SW2-SW1 signal 324.

[0068] As described above, it may be desirable to achieve full isolation cell enable pin coverage during testing for all signals passing between all power domains (i.e., through isolation) (e.g., detecting both stuck-on-"0" and stuck-on-"1" faults) to achieve convenient test setup and minimize test time increase. Such test coverage is also desirable for both cold and hot test scenarios.

[0069] To this end, as shown, an external non-scan test data register (TDR 350) is included in the AO domain 302. The TDR 350 can advantageously provide isolation enable pin coverage for all isolation cells 333 to ATPG. For example, the TDR 350 can be a single bit that can be accessed using the test controller 318 to set (e.g., load) a bit value using a test control signal 352, thereby allowing the TDR value 354 to be delivered to various circuits of the multi-power domain device 300.

[0070] The TDR 350 may be accessed from an external connection such as an AO domain connection 346 (e.g., a JTAG pad) using the test controller input 336. Specifically, in an ATPG test setup covering a channel with an isolated enabled fault, the TDR 350 may be loaded from the AO domain connection 346 via JTAG to set a TDR value 354 within the TDR 350. In this manner, the AO domain connection 346 may be advantageously used for dual purpose (re-used for ATPG). In addition to the test controller input 336, other signals may also be provided using the AO domain connection 346 (e.g., scan_reset and scan_clock as shown).

[0071] In one embodiment, the AO domain 302 is a core wrap IP core. For a core wrap implementation of the AO domain 302, the AO-SW1 isolation enable circuit 308 and the AO-SW2 isolation enable circuit 309 may be included in the scan chain. The AO-SW1 multiplexer 371 (MUX) is included in the AO domain 302 to receive the output of the AO-SW1 isolation enable circuit 308 as input. The AO-SW2 multiplexer 373 is also included in the AO domain 302 to receive the output of the AO-SW2 isolation enable circuit 309 as input.

[0072] The AO-SW1 multiplexer 371 also receives an external signal (force isolation signal 375) from the force isolation input 370, thereby allowing the value of the AO-SW1 isolation enable signal 338 to remain constant during transfer and capture (e.g., isolation is disabled during transfer and enabled during capture). The AO-SW2 isolation enable signal 337 output by the AO-SW2 multiplexer 373 is also similarly controlled by the force isolation input 370. In one embodiment, the force isolation input 370 is included in the AO domain connection 346 in the AO domain 302.

[0073] During functional mode, when the AO-SW1 isolation enable signal 338 is on, the TDR value 354 can remain static at "0", allowing the test controller 318 to reset. This enables the desired behavior of the PoR circuit 340 to reset the SW1 domain 310 and the SW2 domain 320 when the multi-power domain device 300 boots and when it is powered again after isolation is enabled (e.g., during a low power exit or standby exit).

[0074] During ATPG transfer and capture in both EXTPG and INTEST modes, the TDR value 354 can remain static at "1", which selects the forced isolation signal 375 in the AO-SW1 multiplexer 371 and the AO-SW2 multiplexer 373. During ATPG capture in both EXTEST and INTEST, the AO-SW1 isolation enable signal 338 and the AO-SW2 isolation enable signal 337 can also remain constant. For example, isolation can be enabled by selecting the forced isolation signal 375.

[0075] Therefore, to prevent the AO domain 302 from exiting the scan mode during INTEST, an OR gate is included in the AO domain 302, which accepts the test controller 318 signal as an input and accepts the TDR value 354 as another input (scan mode OR gate 361 and power switch OR gate 362). Therefore, the TDR value 354 is ORed with the isolation cell outputs of all scan critical test signals entering the AO domain 302 so that they can be kept at "1" during ATPG, while its isolation cells can be disabled or enabled and checked for both stuck-at-0 faults and stuck-at-1 faults.

[0076] This solution can be extended to other power domains. For example, in an embodiment where the test controller 318 entering the SW2 domain 320 is used to test the SW2 domain 320 , a similar OR gate can be included in the SW2 domain 320 .

[0077] The TDR value 354 is also ORed with the isolated output of the reset source (e.g., from the PoR circuit 340 into the SW1 domain 310 and the SW2 domain 320) using the SW1 reset OR gate 363 and the SW2 reset OR gate 364. This may provide an advantage in that, when entering the ATPG mode, since the TDR value 354 is not passed through the isolation, the test controller 318 will not undesirably exit the ATPG mode when the isolation is enabled.

[0078] This can advantageously enable checking for isolation enable faults when the core (AO domain 302) is in EXTEST mode and INTEST mode. For example, the observation FF can be part of the INTEST scan chain, or can be stitched together in a scan chain with other core wrap FFs and checked in EXTEST mode. If the AO-SW1 multiplexer 371 is excluded, then when the isolation enable value is transferred through the AO-SW1 isolation enable circuit 308 (e.g., a functional FF), during the ATPG transfer, the AO-SW1 isolation enable circuit 308 may disadvantageously remove the AO domain 302 from scan mode.

[0079] Similar advantages can be obtained by including a SW2 multiplexer 372 in the SW2 domain 320 with the output of the SW2-SW1 isolation enable circuit 328 and the forced isolation signal 375 as inputs. By using the TDR value 354, the output (SW2-SW1 isolation enable signal 339) can be selected in the same manner as the AO-SW1 isolation enable signal 338 (because it originates from the normally-on domain and is not passed through the isolation).

[0080] During ATPG, the output of the isolation unit 333 for scan critical signals (e.g., scan_mode, power_switch_close, etc.) can be observed at the AO observation FF 381. In one embodiment, an observation OR gate 365 is included between the scan critical signal and the AO observation FF 381, so only one observation FF is required. Similarly, the output of the isolation unit for the SW1 reset signal can be observed at the SW1 observation FF 383, and the output of the isolation unit for the SW2 reset signal can be observed at the SW2 observation FF 384.

[0081] Stuck-in-0 faults and stuck-in-1 faults can be checked by ATPG by observing the isolation output at the AO observation FF 381 (test signal) and the functional FF (rather than the AO-SW1 isolation enable circuit 308 and the AO-SW2 isolation enable circuit 309) (e.g., during ATPG capture), thereby advantageously providing complete isolation enable fault coverage.

[0082] In this way, the isolated enable functionality of all signals can be advantageously checked for stuck-at-0 and stuck-at-1 with reduced test time compared to functional patterns. Another benefit is that ATPG can be performed in engineering mode (i.e., not device configurations, such as voltage regulator bypass mode (no external SMPS components are required at the tester), where the voltage regulators are located within a multi-power domain device, such as a SoC (SMPS regulator provides vddlv_main to SW1, low power regulator provides vddlv_lp to SW2, and ultra-low power / standby regulator provides vddlv_ao to the AO domain) are forced powered down, and vddlv_main, vddlv_lp, and vddlv_ao are provided directly from the tester power supply to SW1, SW2, and AO). In this way, coverage can advantageously be available at all temperatures at which testing is performed (e.g., cold test and hot test scenarios).

[0083] Figure 4 A schematic diagram of another multi-power domain device having a non-scan test data register included in a normally-on power domain according to an embodiment of the present invention is illustrated. Figure 4 It may be other multi-power domain devices described herein (such as Figure 1 and 2 A specific implementation of a multi-power domain device). Similar labeled elements may be as previously described.

[0084] refer to Figure 4 , the multi-power domain device 400 includes an AO domain 402, a SW1 domain 410, and a SW2 domain 420. The AO domain 402 outputs an AO-SW1 signal 404 and an AO-SW2 signal 406 while receiving a SW1-AO signal 412 and a SW2-AO signal 422 as inputs. The SW1-SW2 signal 416 and the SW2-SW1 signal 424 are transmitted between the SW1 domain 410 and the SW2 domain 420.

[0085] Similar to the multi-power domain device 300, the multi-power domain device 400 further includes an AO-SW1 isolation enable circuit 408, an AO-SW2 isolation enable circuit 409, a PoR circuit 440, and an AO domain connection 446 in the AO domain 402, while a test controller 418 and a SW1 domain connection 448 are included in the SW1 domain 410. An AO-SW1 isolation enable signal 438 from the AO-SW1 isolation enable circuit 408, an AO-SW2 isolation enable signal 437 from the AO-SW2 isolation enable circuit 409, and a SW2-SW1 isolation enable signal 439 from the SW2-SW1 isolation enable circuit 428 are output to corresponding isolation units 433 of the AO domain 402 and the SW2 domain 420.

[0086] Also similar to the multi-power domain device 300 , the multi-power domain device 400 includes a TDR 450 in the AO domain 402 , which can be accessed using a test controller 418 to set a bit value using a test control signal 452 from a test controller input 436 to allow a TDR value 454 to be delivered to various circuits of the multi-power domain device 400 .

[0087] In one embodiment, the AO domain 402 is unpacked (i.e., core wrapping is not implemented). In this case, transparent ATPG can be used (e.g., for small SoCs, EXTEST / INTEST is not used). However, the scan signal still cannot be isolated with the AO-SW1 isolation enable circuit 408 because it will be driven by the scannable FF that is switched during transfer and capture.

[0088] Therefore, the scan mode OR gate 461, the power switch OR gate 462, the SW1 reset OR gate 463, and the SW2 reset OR gate 464 are still included so that the scan key signal can be kept at "1" during ATPG. The observation OR gate 465 and the observation FF (AO observation FF 481, SW1 observation FF 483, and SW2 observation FF 484) are also included. However, in contrast to the multi-power domain device 300, in the absence of a core package, the multiplexer receiving the forced isolation input is not included in the multi-power domain device 400.

[0089] Figure 5 A schematic diagram of another multi-power domain device having a non-scan test data register included in a normally-on power domain according to an embodiment of the present invention is illustrated. Figure 5 It may be other multi-power domain devices described herein (such as Figure 1 , 2 and 4) of the multi-power domain device). Similar labeled elements may be as previously described.

[0090] refer to Figure 5 , the multi-power domain device 500 includes an AO domain 502, a SW1 domain 510, and a SW2 domain 520. The AO domain 502 outputs an AO-SW1 signal 504 and an AO-SW2 signal 506 while receiving a SW1-AO signal 512 and a SW2-AO signal 522 as inputs. The SW1-SW2 signal 516 and the SW2-SW1 signal 524 are transmitted between the SW1 domain 510 and the SW2 domain 520.

[0091] Similar to the multi-power domain device 400, the multi-power domain device 500 further includes an AO-SW1 isolation enable circuit 508, an AO-SW2 isolation enable circuit 509, a PoR circuit 540, and an AO domain connection 546 in the AO domain 502, while the test controller 518 and the SW1 domain connection 548 are included in the SW1 domain 510. An AO-SW1 isolation enable signal 538 from the AO-SW1 isolation enable circuit 508, an AO-SW2 isolation enable signal 537 from the AO-SW2 isolation enable circuit 509, and a SW2-SW1 isolation enable signal 539 from the SW2-SW1 isolation enable circuit 528 are output to corresponding isolation units 533 of the AO domain 502 and the SW2 domain 520.

[0092] Also similar to the multi-power domain device 400 , the multi-power domain device 500 includes a TDR 550 in the AO domain 502 , which can be accessed using a test controller 518 to set a bit value using a test control signal 552 from a test controller input 536 to allow a TDR value 554 to be delivered to various circuits of the multi-power domain device 500 .

[0093] It still includes the scan mode OR gate 561, the power switch OR gate 562, the SW1 reset OR gate 563, the SW2 reset OR gate 564, the observation OR gate 565 and the observation FF (AO observation FF 581, SW1 observation FF 583 and SW2 observation FF 584).

[0094] However, compared to the multi-power domain device 400, various additional logic gates are also included in the AO domain 502 and the SW2 domain 520. Specifically, the multi-power domain device 500 includes a hybrid scan chain for the AO domain 502, the SW1 domain 510, and the SW2 domain 520. As shown in the figure, the multi-power domain device 500 may also not have a core package (e.g., similar to Figure 4 Multi-power domain device 400).

[0095] In this configuration, while in scan mode during transfer, the isolation unit 533 in all domains may need to be disabled. For example, when in scan mode and during transfer (scan_enable is "1"), the isolation unit 533 may receive a scan_enable signal of "1" and be disabled, thereby allowing all signals to pass between domains. However, during capture in scan mode, the isolation unit 533 may need to respond to signals from the isolation enable circuit (AO-SW1 isolation enable signal 538, AO-SW2 isolation enable signal 537, and SW2-SW1 isolation enable signal 539).

[0096] To facilitate this behavior, an OR logic gate may be included that receives the scan_enable_int signal (the AND gate output of scan_mode and scan_enable) as a first input and receives the isolation enable signal as a second input. In particular, the AO-SW1 isolation OR gate 592, the AO-SW2 isolation OR gate 593, and the SW2-SW1 isolation OR gate 594 are located between the AO-SW1 isolation enable circuit 508, the AO-SW2 isolation enable circuit 509, and the SW2-SW1 isolation enable circuit 528 and the corresponding isolation unit 533.

[0097] from Figure 5 As can be seen in , the desired behavior is then achieved because when the scan_enable signal is "1", the isolation unit 533 is always disabled (receives a logic "1"), while when the scan_enable signal is "0", the isolation unit 533 is switched by the isolation enable signal.

[0098] Importantly, when the scan_mode signal is also high, it is ensured that the scan_enable signal is only allowed to control all isolation cells 533 (between the AO domain 502 and the SW1 domain 510, between the AO domain 502 and the SW2 domain 520, and between the SW2 domain 520 and the SW1 domain 510). To this end, an AND gate 591 may also be included to accept the scan_mode and scan_enable signals as inputs and have outputs coupled to inputs of an AO-SW1 isolation OR gate 592, an input of an AO-SW2 isolation OR gate 593, and an input of an SW2-SW1 isolation OR gate 594. This may allow, for example, the connection of the AO domain connection 546 for inputting the scan_enable signal to be used for purposes other than scan mode.

[0099] Figure 6 An example method of testing a multi-power domain device without a core wrapping AO domain according to an embodiment of the present invention is illustrated. Figure 6 The method can be performed using the embodiment devices and systems described herein. For example, Figure 6 The method can be used with Figure 4 and 5 Combination of embodiments. Figure 6 The arrows in the figure are intended to indicate the order of the steps and are not intended to be limiting. The following method steps may be performed in any suitable order that is clear to those skilled in the art.

[0100] refer to Figure 6, step 601 of method 600 is to send a test control signal from a test controller powered by a first switchable (SW1) power domain to a non-scanned test data register (TDR) powered by an always-on (AO) power domain. The AO power domain includes an AO input and is configured to always receive power while the multi-power domain device is powered. The SW1 power domain includes a SW1 output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered.

[0101] Step 602 is to set the TDR value of the TDR using the test control signal to enable the scan mode by bypassing the first isolation unit between the SW1 output and the AO input. The first isolation unit is configured to allow or prohibit the first signal originating from the SW1 output from propagating to the AO input through the first isolation unit. Step 603 includes shifting the test pattern into a scan chain including a functional isolation enable flip-flop coupled to the first isolation unit. The shifting is performed while the TDR value continuously enables the scan mode.

[0102] Step 604 is to capture the test results from the scan chain. The capture is performed while the TDR value continuously enables the scan mode. Step 605 is to move the test pattern out of the scan chain to observe the test results, which is also performed while the TDR value continuously enables the scan mode.

[0103] Figure 7 Another example method of testing a multi-power domain device having a core wrapped AO domain according to an embodiment of the present invention is illustrated. Figure 7 The method can be performed using the embodiment devices and systems described herein. For example, Figure 7 The method can be used with Figure 1-3 Combination of embodiments. Figure 7 The arrows in the figure are intended to indicate the order of the steps and are not intended to be limiting. The following method steps may be performed in any suitable order that is clear to those skilled in the art.

[0104] refer to Figure 7 , step 701 of method 700 is to send a test control signal from a test controller powered by a first switchable (SW1) power domain to a non-scanned test data register (TDR) powered by an always-on (AO) power domain. The AO power domain includes an AO input and core wrapped logic, and the AO power domain is configured to always receive power while the multi-power domain device is powered. The SW1 power domain includes a SW1 output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered. The AO power domain also includes an AO multiplexer, the AO multiplexer including an AO multiplexer output coupled to a first isolation unit, the first isolation unit configured to allow or prohibit a first signal from propagating from the SW1 output to the AO input.

[0105] Step 702 is setting a TDR value of the TDR to a first value using a test control signal, the TDR value being coupled to an AO selector input of the AO multiplexer. In step 703, a force isolation signal is input at the AO domain connection. Step 704 includes selecting the force isolation signal at the AO selector input using the first value. Step 705 is testing the AO power domains of the multi-power domain device (e.g., in EXTEST and INTEST modes) while the force isolation signal is continuously selected by the first value.

[0106] Figure 8 An example method of entering and exiting a low power state by a multi-power domain device according to an embodiment of the present invention is illustrated. Figure 8 The method can be performed using the embodiment devices and systems described herein. For example, Figure 8 The method can be used with Figure 1-5 In addition, Figure 8 The method can be combined with other methods, such as Figure 6 and 7 For example, the device can enter and exit a low-power state before or after testing. Figure 8 The arrows in the figure are intended to indicate the order of the steps and are not intended to be limiting. The following method steps may be performed in any suitable order that is clear to those skilled in the art.

[0107] refer to Figure 8 , a multi-power domain device including the AO domain, the SW1 domain, and the SW2 domain may be in a powered-off state (e.g., none of the power domains of the device receives power). If the device is started in a powered-on state (e.g., power is provided to all domains for the first time), step 801 of method 800 asserts a reset signal (e.g., from a PoR circuit) to reset all circuits (e.g., flip-flops) of the entire device (i.e., AO, SW1, SW2, etc.). Alternatively, step 801 may be omitted if the device is already fully powered.

[0108] This stage may be a boot stage of the device. During step 801, all isolation units between all domains may be disabled (ie, all signals are allowed to pass through isolation). That is, all isolation enable circuits may be forced to "1" to allow signals to propagate.

[0109] At some time after all circuits are reset and while all domain multi-power domain devices are receiving power, the reset signal is de-asserted. The AO domain, SW1 domain, and SW2 domain are then de-reset (e.g., the boot phase is complete). All isolation cells remain disabled.

[0110] Then, the multi-power domain device initiates an entry sequence to enter a low power state of the device. The entry sequence includes step 802, i.e., enabling the isolation unit between the AO domain and the SW1 domain and between the SW2 domain and the SW1 domain (disabling signal passing through). That is, the AO-SW1 isolation enable circuit powered by the AO domain and the SW2-SW1 isolation enable circuit powered by the SW2 domain can both be forced to "0" to prevent the signal from leaving the SW1 domain.

[0111] After the isolation unit is enabled in step 802, the SW1 domain is reset. At some time after resetting the SW1 domain, power is removed from the SW1 domain and enters an unpowered state. At all times when the SW1 domain is unpowered, the isolation unit that controls the passing of signals from the SW1 domain to both the AO domain and the SW2 domain is enabled.

[0112] Once the SW1 domain is unpowered, the multi-power domain device will be in a low power state. Specifically, the AO domain and SW2 domain remain powered, and signals can be passed between these powered domains, but SW1 is in an unpowered state, and no signals can be passed from the SW1 domain to the AO domain or the SW2 domain.

[0113] When the multi-power domain device attempts to exit the low power state, an exit sequence is initiated to transition the SW1 domain from the unpowered state to the powered state. The exit sequence includes step 803, resetting the SW1 domain while the isolation unit between the SW1 domain and both the AO domain and the SW2 domain remains enabled. The SW1 domain receives power, and the isolation unit remains enabled while the SW1 domain is reset.

[0114] Once the SW1 domain is reset and receives power, the device will exit the low power state and disable the isolation units between the AO domain and the SW1 domain and between the SW2 domain and the SW1 domain (allowing signals to pass through) in step 804. The SW1 domain is not reset because the PoR circuit in the AO domain remains deasserted.

[0115] Fig. 9 An example method of entering and exiting a standby state by a multi-power domain device according to an embodiment of the present invention is illustrated. Fig. 9 The method can be performed using the embodiment devices and systems described herein. For example, Fig. 9 The method can be used with Figure 1-5 In addition, Fig. 9 The method can be combined with other methods, such as Figure 6 and 7 For example, the device can enter and exit standby before or after testing. Fig. 9The arrows in the figure are intended to indicate the order of the steps and are not intended to be limiting. The following method steps may be performed in any suitable order that is clear to those skilled in the art.

[0116] refer to Fig. 9 , method 900 begins with a multi-power domain device including an AO domain, a SW1 domain, and a SW2 domain in a low power state 901. In particular, as shown, the device may have just executed step 802 (as in method 800) such that the SW1 domain is not powered, and both the AO-SW1 isolation enable circuit and the SW2-SW1 isolation enable circuit remain forced to "0" to prevent leaving the SW1 domain (isolation unit is enabled).

[0117] From the low power state, the multi-power domain device initiates an entry sequence to enter a standby state (e.g., a functional standby state). The entry sequence includes step 902, i.e., enabling the isolation unit between the AO domain and the SW2 domain (disabling signal passing through). That is, the AO-SW2 isolation enable circuit powered by the AO domain can be forced to "0" to prevent the signal from leaving the SW2 domain.

[0118] After the isolation unit is enabled in step 902, the SW2 domain is reset. At some time after resetting the SW2 domain, power is removed from the SW2 domain and enters an unpowered state. At all times when the SW2 domain is unpowered, the isolation unit that controls the transfer of signals from the SW2 domain to the AO domain is enabled.

[0119] Once the SW2 domain is not powered, the multi-power domain device will be in standby state. Specifically, the AO domain remains powered, but the SW1 domain and the SW2 domain are not powered, and no signal can be passed from the SW1 domain or the SW2 domain to the AO domain.

[0120] When the multi-power domain device attempts to exit the standby state, an exit sequence is initiated to transition both the SW1 domain and the SW2 domain from the unpowered state to the powered state. The exit sequence includes step 903, i.e., resetting both the SW1 domain and the SW2 domain while all isolation units between the SW1 domain and the SW2 domain and the AO domain remain enabled. That is, the SW1 domain and the SW2 domain receive power, and the isolation units remain enabled while the SW1 domain and the SW2 domain are in reset.

[0121] Once the SW1 domain and the SW2 domain are reset and receive power, in step 904, the device will exit the standby state and disable the isolation units between the AO domain and the SW1 domain, the AO domain and the SW2 domain, and the SW2 domain and the SW1 domain (allowing signals to pass through). For example, all AO-SW1 isolation enable circuits, AO-SW2 isolation enable circuits, and SW2-SW1 isolation enable circuits can be forced to "1". The SW1 domain and the SW2 domain are not reset because the PoR circuit in the AO domain remains de-asserted.

[0122] Fig.10 An example method of testing a multi-power domain device without a core wrapping AO domain according to an embodiment of the present invention is illustrated. Fig.10 The method can be performed using the embodiment devices and systems described herein. For example, Fig.10 The method can be used with Figure 4 and 5 In addition, Fig.10 The method can be combined with other methods, such as Figure 8 and 9 method. Fig.10 The arrows in the figure are intended to indicate the order of the steps and are not intended to be limiting. The following method steps may be performed in any suitable order that is clear to those skilled in the art.

[0123] refer to Fig.10 , step 1001 of method 1000 is to send a test control signal from a test controller powered by the SW1 domain to a non-scanning TDR powered by the AO domain. Step 1001 is performed when all domains are powered and all isolation units are in a disabled state to allow signal transmission through all domains. For example, step 1001 can be performed after the boot phase (e.g., step 801) is completed.

[0124] Step 1002 is to use the test control signal to set the TDR value of the TDR to an appropriate value for the scan mode. For example, the TDR value causes the AO domain and the SW2 domain to remain in the scan mode while the isolation is switched. In addition, the SW1 domain will not reset when the isolation is switched during ATPG.

[0125] Step 1003 is to set the scan_mode signal to enter scan mode (e.g., to enter ATPG). Then, in step 1004, the scan_enable signal is used (e.g., by forcing the scan_enable signal to "1") to enter transfer mode (e.g., ATPG transfer mode). In a hybrid chain architecture (e.g., such as Figure 5 ), the isolation cell will remain disabled by the scan_enable signal to allow the signal to pass to all domains.

[0126] Step 1005 is to move the test pattern into one or more scan chains including isolation enabling circuits (eg, function FFs). For example, the scan chain includes an AO-SW1 isolation enabling circuit, an AO-SW2 isolation enabling circuit, and a SW2-SW1 isolation enabling circuit.

[0127] After the test pattern is shifted into the scan chain, in step 1006, the capture mode is entered using the scan_enable signal (e.g., by forcing the scan_enable signal to "0"). In the capture mode, the isolation unit can be switched according to the control of the AO-SW1 isolation enable circuit, the AO-SW2 isolation enable circuit, and the SW2-SW1 isolation enable circuit. For example, while the isolation is switched, the TDR value combined with the logic gate (e.g., the scan mode OR gate, the SW1 reset OR gate, etc.) can maintain the scan mode.

[0128] The result of the test pattern (i.e., the captured value) is in the scan chain after the capture mode. In step 1007, the transfer mode is entered again using the scan_enable signal. Step 1008 is to shift out the test pattern to observe the captured value. For example, the captured value can be observed on the observation FF and other functional FFs (e.g., except the isolation enable FF) in the multi-power domain device.

[0129] Fig.11 An example method of testing a multi-power domain device having a core wrapped AO domain according to an embodiment of the present invention is illustrated. Fig.11 The method can be performed using the embodiment devices and systems described herein. For example, Fig.11 The method can be used with Figure 1-3 In addition, Fig.11 The method can be combined with other methods, such as Figure 1-9 method. Fig.11 The arrows in the figure are intended to indicate the order of the steps and are not intended to be limiting. The following method steps may be performed in any suitable order that is clear to those skilled in the art.

[0130] refer to Fig.11 , step 1101 of method 1100 is to send a test control signal from a test controller powered by the SW1 domain to a non-scanning TDR powered by the AO domain. Step 1101 is performed when all domains are powered and all isolation units are in a disabled state to allow signal transmission through all domains. For example, step 1101 can be performed after the boot phase (e.g., step 801) is completed.

[0131] Step 1102 is to set the TDR value of the TDR to an appropriate value to select the forced isolation signal input at the multiplexer, each multiplexer receiving a signal from a corresponding isolation enable circuit at another input. The TDR value is coupled to the selector input of each multiplexer. For example, the TDR value can be coupled to the AO-SW1 multiplexer receiving an input from the AO-SW1 isolation enable circuit, the AO-SW2 multiplexer receiving an input from the AO-SW2 isolation enable circuit, and the SW2 multiplexer receiving an input from the SW2-SW1 isolation enable circuit.

[0132] Step 1103 is to set the scan_mode signal to enter scan mode (e.g., to enter ATPG). Then, in step 1104, the scan_enable signal is used (e.g., by forcing the scan_enable signal to "1") to enter transfer mode (e.g., ATPG transfer mode), and all isolations are disabled using the force isolation signal. That is, the force isolation signal can be forced to "1" to disable all isolation cells coupled to the multiplexer output that receive the force isolation signal selected by the TDR value.

[0133] Step 1105 includes moving the test pattern into one or more scan chains. After moving the test pattern into the scan chain, in step 1106, the capture mode is entered using the scan_enable signal (e.g., by forcing the scan_enable signal to "0"), and all isolations are enabled using the force isolation signal (e.g., forcing it to "0"). The result of the test pattern (i.e., the captured value) is in the scan chain after the capture mode. In step 1107, the transfer mode is entered again using the scan_enable signal (e.g., forced to "1"), and all isolations are disabled again using the force isolation signal (e.g., forced to "1"). Step 1108 is to move out the test pattern to observe the captured value. For example, the captured value can be observed on the core package FF, observation FF, and other functional FFs (e.g., except the isolation enable FF) in a multi-power domain device.

[0134] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the entire specification and claims presented herein.

[0135] Example 1. A method for testing a multi-power domain device, the method comprising: sending a test control signal from a test controller powered by a first switchable (SW1) power domain to a non-scan test data register (TDR) powered by an always-on (AO) power domain, wherein the AO power domain includes an AO input and is configured to always receive power while the multi-power domain device is powered, and wherein the SW1 power domain includes a SW1 output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered; using the test control signal to set a TDR value of the TDR to enable a scan mode by bypassing a first isolation unit between the SW1 output and the AO input, the first isolation unit being configured to allow or prohibit a first signal originating from the SW1 output from propagating to the AO input through the first isolation unit; and while the TDR value continuously enables the scan mode, shifting a test pattern into a scan chain including a functional isolation enable flip-flop coupled to the first isolation unit, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result.

[0136] Example 2. The method of Example 1, wherein bypassing the first isolation unit comprises: performing a logical OR operation on the first signal and the TDR value using an OR gate powered by the AO power domain.

[0137] Example 3. The method of one of Examples 1 and 2, wherein the first signal is a scan mode signal configured to place the multi-power domain device in the scan mode.

[0138] Example 4. A method according to one of Examples 1 to 3, wherein while bypassing the first isolation unit, the TDR value also bypasses a second isolation unit between the AO output and the SW1 input, the second isolation unit being configured to allow or prohibit a second signal originating from the AO output from propagating to the SW1 input.

[0139] Example 5. The method of Example 4, wherein bypassing the second isolation unit comprises: performing a logical OR operation on the second signal and the TDR value using an OR gate powered by the SW1 power domain.

[0140] Example 6. The method of Example 4, wherein the second signal is a reset signal, the reset signal originating from a power-on reset (PoR) circuit powered by the AO power domain and configured to reset circuits of the SW1 power domain.

[0141] Example 7. The method according to one of Examples 1 to 6 further includes: while the TDR value continuously enables the scan mode: before moving the test pattern into the scan chain, entering the transfer mode using a scan enable signal; before capturing the test result, entering the capture mode using the scan enable signal, wherein while capturing the test result, the first isolation unit is controlled by an isolation enable circuit, and the isolation enable circuit is powered by the AO power domain; and before moving the test pattern out of the scan chain, re-entering the transfer mode using the scan enable signal.

[0142] Example 8. A method of testing a multi-power domain device, the method comprising: sending a test control signal from a test controller powered by a first switchable (SW1) power domain to a non-scanned test data register (TDR) powered by an always-on (AO) power domain, wherein the AO power domain includes an AO input and core wrapper logic, the AO power domain is configured to always receive power while the multi-power domain device is powered, wherein the SW1 power domain includes a SW1 output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered, and wherein the AO power domain also includes an AO multiplexer, The AO multiplexer includes an AO multiplexer output coupled to a first isolation unit, the first isolation unit being configured to allow or prohibit a first signal from propagating from the SW1 output to the AO input; setting a TDR value of the TDR to a first value using the test control signal, the TDR value being coupled to an AO selector input of the AO multiplexer; inputting a forced isolation signal at an AO domain connection; selecting the forced isolation signal at the AO selector input using the first value; and testing the AO power domain of the multi-power domain device while the forced isolation signal is continuously selected by the first value.

[0143] Example 9. A method according to Example 8, wherein providing the forced isolation signal includes: providing a first forced isolation signal to the first isolation unit to disable isolation, thereby allowing the first signal to propagate to the first AO input while moving a test pattern into the scan chain of the core wrapper logic; and providing a second forced isolation signal to the first isolation unit to enable isolation, thereby prohibiting the first signal from propagating to the first AO input while capturing test results from the scan chain.

[0144] Example 10. The method of one of Examples 8 and 9, further comprising: testing the AO power domain of the multi-power domain device while the output of the forced isolation signal is continuously selected by the first value.

[0145] Example 11. A method according to one of Examples 8 to 10, wherein the multi-power domain device includes a second switchable (SW2) power domain, and the second switchable (SW2) power domain is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered, and the method further includes: selecting the forced isolation signal using the first value at the SW2 selector input of a SW2 multiplexer powered by the SW2 power domain; and testing the SW2 power domain of the multi-power domain device while the forced isolation signal is continuously selected by the first value.

[0146] Example 12. The method of one of Examples 8 to 11, wherein the first signal is a scan mode signal configured to place the multi-power domain device in a scan mode.

[0147] Example 13. A method according to one of Examples 8 to 12, wherein the TDR value is also coupled to a second isolation unit, and the second isolation unit is configured to allow or prohibit a second signal originating from the AO output from propagating to the SW1 input through the second isolation unit while allowing or prohibiting the first signal from propagating through the first isolation unit.

[0148] Example 14. The method of Example 13, wherein the second signal is a reset signal, the reset signal originating from a power-on reset (PoR) circuit powered by the AO power domain and configured to reset circuits of the SW1 power domain.

[0149] Example 15. A multi-power domain device, comprising: an always-on (AO) power domain, including an AO input, and configured to always receive power while the multi-power domain device is powered; a first switchable (SW1) power domain, including a SW1 output, and configured to switch between a powered state and an unpowered state while the multi-power domain device is powered; an isolation unit, coupled between the SW1 output and the AO input; an isolation enable circuit, powered by the AO power domain, and configured to output an isolation enable signal to allow or prohibit a first signal originating from the SW1 output from propagating to the AO input; a non-scan test data register (TDR), powered by the AO power domain; and a test controller, powered by the SW1 power domain and coupled to the TDR, the test controller being configured to send a test control signal to the TDR to set a TDR value, and to test an isolation enable fault by maintaining a scan mode of the AO power domain using the TDR value while the isolation enable signal is switched.

[0150] Example 16. The multi-power domain device of Example 15, wherein the isolation enabling circuit is a functional trigger.

[0151] Example 17. The multi-power domain device of one of Examples 15 and 16, further comprising: an observation trigger powered by the AO power domain and configured to capture the first signal while testing an isolation enable fault.

[0152] Example 18. The multi-power domain device according to one of Examples 15 to 17 further includes: a power-on reset (PoR) circuit, which is powered by the AO power domain and is configured to reset the circuit of the AO power domain and the circuit of the SW2 power domain, and the circuit of the SW1 power domain includes the test controller.

[0153] Example 19. The multi-power domain device of one of Examples 15 to 18, further comprising: a multiplexer including a multiplexer output coupled to the isolation unit and a first multiplexer input coupled to the isolation enable circuit.

[0154] Example 20. The multi-power domain device of Example 19, further comprising: an AO domain pad coupled to a second multiplexer input of the multiplexer.

[0155] Although the present invention has been described with reference to illustrative embodiments, this specification is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art by reference to the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for testing a multi-power domain device, the method comprising: sending a test control signal from a test controller powered by the first switchable SW1 power domain to a non-scanned test data register TDR powered by the normally-on AO power domain, wherein the AO power domain includes an AO input and core wrapper logic, the AO power domain being configured to always receive power while the multi-power domain device is powered, wherein the SW1 power domain includes a SW1 output and is configured to switch between a powered state and an unpowered state while the multi-power domain device is powered, and wherein the AO power domain further comprises an AO multiplexer, the AO multiplexer comprising an AO multiplexer output coupled to a first isolation unit, the first isolation unit being configured to allow or prohibit a first signal from propagating from the SW1 output to the AO input; setting a TDR value of the TDR to a first value using the test control signal, the TDR value being coupled to an AO selector input of the AO multiplexer; Input the forced isolation signal at the AO power domain connection; selecting the forced isolation signal using the first value at the AO selector input; as well as The AO power domain of the multi-power domain device is tested while the forced isolation signal is continuously selected by the first value.

2. The method of claim 1, wherein providing the forced isolation signal comprises: providing a first force isolation signal to the first isolation unit to disable isolation, thereby allowing the first signal to propagate to the AO input while shifting a test pattern into a scan chain of the core wrap logic; as well as A second forced isolation signal is provided to the first isolation unit to enable isolation, thereby inhibiting the first signal from propagating to the AO input while capturing test results from the scan chain.

3. The method according to claim 1, further comprising: The AO power domain of the multi-power domain device is tested while the output of the forced isolation signal is continuously selected by the first value.

4. The method of claim 1 , wherein the multi-power domain device comprises a second switchable SW2 power domain configured to switch between a powered state and an unpowered state while the multi-power domain device is powered, the method further comprising: selecting the forced isolation signal using the first value at a SW2 selector input of a SW2 multiplexer powered by the SW2 power domain; as well as The SW2 power domain of the multi-power domain device is tested while the forced isolation signal is continuously selected by the first value. The method of claim 1 , wherein the first signal is a scan mode signal configured to place the multi-power domain device into a scan mode.

6. The method of claim 1 , wherein the TDR value is further coupled to a second isolation unit, the second isolation unit being configured to allow or prohibit a second signal originating from the AO output from propagating to the SW1 input through the second isolation unit while allowing or prohibiting the first signal from propagating through the first isolation unit. 7 . The method according to claim 6 , wherein the second signal is a reset signal, the reset signal originates from a power-on reset (PoR) circuit powered by the AO power domain and configured to reset the circuit of the SW1 power domain.

8. A multi-power domain device, comprising: an always-on AO power domain, including an AO input, and configured to always receive power while the multi-power domain device is powered; a first switchable SW1 power domain including a SW1 output and configured to switch between a powered state and an unpowered state while the multi-power domain device is powered; an isolation unit coupled between the SW1 output and the AO input; an isolation enable circuit powered by the AO power domain and configured to output an isolation enable signal to allow or prohibit a first signal originating from the SW1 output from propagating to the AO input; A non-scan test data register TDR, powered by the AO power domain; as well as A test controller, powered by the SW1 power domain and coupled to the TDR, is configured to sending a test control signal to the TDR to set a TDR value, and testing an isolation enable fault by maintaining a scan mode of the AO power domain using the TDR value while the isolation enable signal is toggled, wherein the AO power domain further comprises an AO multiplexer, the AO multiplexer comprising an AO multiplexer output coupled to a first isolation unit, the first isolation unit being configured to allow or prohibit a first signal from propagating from the SW1 output to the AO input, and the multi-power domain device being configured to: setting a TDR value of the TDR to a first value using the test control signal, the TDR value being coupled to an AO selector input of the AO multiplexer; Input the forced isolation signal at the AO power domain connection; selecting the forced isolation signal using the first value at the AO selector input; as well as The AO power domain of the multi-power domain device is tested while the forced isolation signal is continuously selected by the first value. 9 . The multi-power domain device of claim 8 , wherein the isolation enabling circuit is a functional trigger.

10. The multi-power domain device according to claim 8, further comprising: An observation trigger is powered by the AO power domain and is configured to capture the first signal while testing an isolation enable fault.

11. The multi-power domain device according to claim 8, further comprising: A power-on reset PoR circuit is powered by the AO power domain and is configured to reset the circuits of the AO power domain and the circuits of the SW1 power domain, wherein the circuits of the SW1 power domain include the test controller.

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