Secondary side controller for flyback converter and method for detecting fault condition

Abstract

The present invention is entitled "Flyback Converter with Synchronous Rectifier Switch Fault Detection". The present invention provides a flyback converter that compares the drain-to-source voltage of a synchronous rectifier switching transistor with a negative threshold voltage to detect whether the synchronous rectifier switching transistor has a partial open circuit fault condition or an open circuit fault condition. The flyback converter also compares the gate terminal voltage of a gate driver to the synchronous rectifier switching transistor with a positive threshold voltage to detect whether the synchronous rectifier switching transistor has a gate open circuit fault condition or a gate short circuit fault condition.

Description

Technical Field

[0001] The present application relates to switching power converters and, more particularly, to a flyback converter with synchronous rectifier switch fault detection. Background Art

[0002] As is known in the flyback art, the secondary winding current in the transformer of a flyback converter is rectified to not conduct when the primary winding current conducts. This rectification can be performed by an output diode or a synchronous rectifier switching transistor. Although the output diode is passive and therefore does not require synchronous rectifier control, the use of an output diode reduces efficiency compared to a flyback converter with synchronous rectification. Therefore, synchronous rectification is widely used to improve efficiency.

[0003] The synchronous rectifier switching transistor is typically a metal oxide semiconductor field effect transistor (MOSFET). To control the switching of the synchronous rectifier (SR) switching MOSFET, the SR controller monitors the drain-to-source voltage on the SR MOSFET. Based on the drain-to-source voltage, the SR controller detects whether the power switch transistor has been turned off so that the SR MOSFET can be turned on. For example, if the SR MOSFET is an n-type metal oxide semiconductor (NMOS) transistor, the SR controller turns on the SR MOSFET by increasing the gate-to-source voltage of the SR MOSFET above its threshold voltage.

[0004] However, like any semiconductor device, the SR switch transistor is subject to manufacturing defects. For example, although its threshold voltage is met, the SR switch transistor may only be slightly turned on (partial open circuit fault condition) or turned off (open circuit fault condition). In addition, for such partial open circuit fault conditions or full open circuit fault conditions, the gate of the SR switch transistor may be shorted to ground (gate-to-ground short circuit fault condition) or shorted to the source of the SR switch transistor (gate-to-source short circuit fault condition).

[0005] Due to these fault conditions, the drain current that would normally be conducted through the channel of the SR switch transistor is instead conducted through its body diode. Conduction through the body diode rather than the channel results in a relatively high drain-to-source voltage on the SR switch transistor, which results in thermal stress on the power supply. Therefore, detection of open circuit fault conditions, partial open circuit fault conditions, gate-to-ground short circuit fault conditions, and gate-to-source short circuit fault conditions are critical to power supply reliability. Despite this criticality, existing fault condition techniques are typically unable to detect partial open circuit fault conditions.

[0006] In conventional SR switch transistor fault detection, a current source is applied to the gate of the SR switch transistor while detecting the rate of change (dV / dt) of the drain-to-source voltage (Vds) across the SR switch transistor to determine the gate-to-source capacitance of the SR switch transistor. If the gate-to-source capacitance is less than a first threshold amount, a gate open fault is considered detected. Conversely, if the gate-to-source capacitance is above a second threshold amount, a gate-to-source short fault condition is considered detected. The resulting conventional fault detection is applicable only during the startup phase and cannot detect a partial open fault condition, which is problematic for ensuring the reliability of the flyback converter.

[0007] Therefore, there is a need in the art for a flyback converter with improved fault detection for the operation of the synchronous rectifier switching transistor. Summary of the invention

[0008] According to a first aspect of the present disclosure, a secondary side controller for a flyback converter is provided, the secondary side controller comprising: a gate driver for controlling a cycle of a synchronous rectifier switching transistor; a drain terminal for connecting to the drain of the synchronous rectifier switching transistor; a timer for timing a detection cycle, the detection cycle starting when the gate driver turns on the synchronous rectifier switching transistor and ending when the voltage at the drain terminal exceeds a negative voltage threshold; and a logic circuit configured to compare the detection cycle with a threshold cycle to detect whether the synchronous rectifier switching transistor has a partial open circuit fault condition or an open circuit fault condition.

[0009] According to a second aspect of the present disclosure, a secondary side controller for a flyback converter is provided, the secondary side controller comprising: a gate driver for controlling a cycle of a synchronous rectifier switching transistor through a gate terminal; a timer for timing a detection period, the detection period starting when the gate driver turns on the synchronous rectifier switching transistor and ending when the voltage at the gate terminal exceeds a positive threshold voltage; and a logic circuit configured to detect whether the synchronous rectifier switching transistor has an open gate fault condition in response to the detection period being shorter than a first threshold period.

[0010] According to a third aspect of the present disclosure, a method for detecting a fault condition of a synchronous rectifier switching transistor in a flyback converter is provided, the method comprising: turning on the synchronous rectifier switching transistor; when the synchronous rectifier switching transistor is turned on, starting timing of a first detection cycle in response to a drain-to-source voltage of the synchronous rectifier switching transistor being greater than a negative threshold voltage; ending the timing of the first detection cycle in response to the turning off of the synchronous rectifier switching transistor; and detecting a partial open circuit fault condition of the synchronous rectifier switching transistor in response to the first detection cycle being shorter than a first threshold cycle.

[0011] By reading the following specific embodiments, these and other aspects of the present invention will be more fully understood. When reading the following description of specific exemplary embodiments in conjunction with the accompanying drawings, other aspects, features and embodiments will become apparent to those of ordinary skill in the art. Although features can be discussed relative to certain embodiments and the following drawings, all embodiments may include one or more of the advantageous features discussed herein. In other words, although one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used according to the various embodiments discussed herein. In a similar manner, although exemplary embodiments may be discussed as equipment, system or method embodiments below, it should be understood that such exemplary embodiments may be implemented in various devices, systems and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A flyback converter including a secondary side controller according to one aspect of the present disclosure is shown, which is configured to detect synchronous rectifier switching transistor fault conditions, including partial open circuit fault conditions, open circuit fault conditions, gate open circuit fault conditions and gate short circuit fault conditions.

[0013] Figure 2 A method for detecting a partial open circuit fault condition and an open circuit fault condition according to one aspect of the present disclosure is shown. Figure 1 The drain-to-source voltage monitoring feature of the secondary-side controller.

[0014] Figure 3A Shows Figure 2 Some operating waveforms of the secondary side controller during normal (fault-free) operation.

[0015] Figure 3B Shows Figure 2 Some operating waveforms of the secondary side controller during operation with a fault condition.

[0016] Figure 4A method for detecting a gate open fault condition and a gate short fault condition according to one aspect of the present disclosure is shown. Figure 1 The gate terminal voltage monitoring feature of the secondary side controller.

[0017] Figure 5A Shows Figure 4 Some operating waveforms of the secondary side controller during normal (fault-free) operation.

[0018] Figure 5B Shows Figure 4 Some operating waveforms of the secondary side controller during operation with a gate open fault condition.

[0019] Figure 5C Shows Figure 4 Some operating waveforms of the secondary side controller during operation with a gate short circuit fault condition.

[0020] A complete understanding of the embodiments of the present disclosure and its advantages may be obtained by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements shown in one or more of the figures in the accompanying drawings. DETAILED DESCRIPTION

[0021] The present invention provides a flyback converter in which a secondary side controller monitors the drain-to-source voltage (Vds) of an SR switch transistor as the SR switch transistor cycles to detect both an open circuit fault condition and a partial open circuit fault condition. The following discussion will relate to an embodiment in which the secondary side controller is also an SR switch controller, but it should be understood that SR switch transistor fault monitoring and SR switch control can be implemented in separate integrated circuits. An open circuit fault condition occurs when the drain current of the SR switch transistor is completely conducted through the body diode so that the channel is closed (non-conducting). In contrast, the channel conducts some current in a partial open circuit fault condition, so that the drain current is shunted between the partially closed channel and the body diode. In addition, a flyback converter is provided in which a secondary side controller monitors the gate driver voltage that controls the SR switch transistor to detect a gate open circuit fault condition or a gate short circuit fault condition. The gate short circuit fault condition can be caused by a gate to ground short or a gate to source short.

[0022] Turning now to the accompanying drawings, Figure 11 shows a flyback converter 100 with a fault monitoring secondary side SR controller 120. The flyback converter 100 is powered by a rectified input voltage Vin, such as generated by a diode bridge 112 that rectifies an AC voltage VAC from an AC mains. The input voltage Vin is carried on an input rail 114 and supported by an input capacitor Cin coupled between the input rail 114 and a primary side ground. A primary side controller 118 controls the cycle of a power switch transistor SW to regulate an output voltage Vout supplied to a load 130. When the primary side controller 118 turns on the power switch transistor SW, a primary winding current is conducted through the primary winding 108 of the transformer T1. A sense resistor Rs is connected between the drain of the power switch transistor SW and the primary side ground. Therefore, the primary winding current flows through the sense resistor Rs and generates a sense resistor voltage across the sense resistor Rs, which is sensed by the primary side controller 118. When the sense resistor voltage reaches the desired peak value (Vipk), the primary side controller 118 turns off the power switch transistor SW.

[0023] The SR controller 120 detects whether the power switch transistor SW is turned on or off by monitoring the drain-to-source voltage Vds on the SR switch transistor. To perform this monitoring, the SR controller 120 has a drain monitoring terminal SR_D and a source monitoring terminal SR_S. In addition, the SR controller 120 includes a gate terminal SR_G, which is connected to the gate of the SR switch transistor to control whether the SR switch transistor is turned on or off. In response to detecting that the power switch transistor SW is turned on, the SR controller 120 maintains the SR switch transistor off to prevent the secondary winding current from flowing in the secondary winding 110 of the transformer T1. In response to detecting that the power switch transistor SW is turned off, the SR controller 120 turns on the SR switch transistor to allow the secondary winding current to flow and charges the output capacitor Cout with the output voltage. In an alternative embodiment, instead of monitoring the drain-to-source voltage of the SR switch transistor to determine the switching state of the power switch transistor, the SR controller 120 can instead receive the on or off state of the power switch transistor SW through an isolation channel (such as an optocoupler).

[0024] Fault monitoring of the SR switch transistor by the SR controller 120 for a fault condition will now be discussed in more detail. First, drain-to-source voltage monitoring for detecting an open circuit fault condition or a partially open circuit fault condition will be discussed, followed by gate driver voltage monitoring for detecting a gate open circuit fault condition or a gate short circuit fault condition. Figure 21 shows the drain-to-source voltage monitoring feature of the SR controller 120 in more detail. Since the source voltage of the SR switch transistor is secondary-side grounded, the SR controller 120 can monitor the drain-to-source voltage of the SR switch transistor by monitoring the drain voltage received through its drain monitoring terminal SR_D. It should be noted that due to the conduction through the body diode of the SR switch transistor, the partial open circuit fault condition or the open circuit fault condition of the SR switch transistor causes the negative value of the drain-to-source voltage to be significantly lower than the negative value of the normal case when the SR switch transistor is turned on. The SR controller 120 advantageously utilizes this negative nature of the drain-to-source voltage by including a comparator 205 that compares the drain voltage with a negative threshold voltage. In some embodiments, the negative threshold voltage should be lower than the body diode voltage drop at higher operating temperatures, but higher than the voltage drop caused by the drain-to-source resistance in the drain-to-source voltage at these higher operating temperatures. Since both voltage drops have positive coefficients corresponding to temperature increases, the threshold adaptive circuit 235 can adaptively reduce the negative threshold voltage at higher operating temperatures. In the following discussion, a default value of -280 mV will be assumed for the negative threshold voltage, but it will be understood that the default value and any adaptation to the default value will depend on the particular semiconductor process node used to fabricate the SR switch transistor. In some embodiments, the SR switch transistor is a discrete device that is not integrated with an integrated circuit including the SR controller 120.

[0025] The comparator 205 receives the drain voltage at its non-inverting input such that the comparator 205 will charge its output signal (designated Comp_SRGO) to the power supply voltage in response to the drain-to-source voltage being greater than the negative threshold voltage. However, it should be understood that in alternative embodiments, the comparator 205 may be in an active low configuration such that the drain voltage is received at its inverting input. As used herein, a binary signal (such as a comparator output signal) is considered asserted if it is true, regardless of whether the comparator is in an active high configuration or an active low configuration.

[0026] The timer 210 begins counting the cycles of the clock signal from the clock 220 in response to the assertion of the comparator output signal Comp_SRGO, thereby starting to time the detection period T. When the gate driver 215 turns off the SR switch transistor, the timer 210 stops counting for the detection period T. In an NMOS embodiment, the gate driver 215 discharges the gate terminal SR_G to the ground to turn off the SR switch transistor. The timer 210 responds to the discharge of the gate terminal SR_G by stopping the count. Then, the logic circuit 230 checks the resulting count from the counter 210 to detect a partial open circuit fault condition and an open circuit fault condition. Specifically, when the logic circuit 230 determines that the count (detection period T) is less than the threshold count, it is considered that a partial open circuit fault condition or an open circuit fault condition of the SW switch transistor is detected. Therefore, a partial open circuit fault condition or an open circuit fault condition is detected in response to the detection period T being less than the threshold period. In an alternative embodiment, the timing of the detection period T can be performed using an analog circuit instead of the timer 210. For example, the current source can be configured to charge the capacitor according to the RC time constant in response to the assertion of the comparator output signal Comp_SRGO. The current source will then stop charging the capacitor in response to the gate driver 215 turning off the SR switch transistor. Therefore, the resulting voltage on the capacitor is proportional to the detection period T during which the capacitor is charged. Therefore, the analog timing of the detection period T is similar to the timing performed by the counter 210, except that the former is performed in the analog domain.

[0027] Regardless of whether the detection period T between the crossing of the negative threshold voltage and the turning off of the SR switch transistor is measured in the digital domain (as discussed with respect to the timer 210 and the logic circuit 230) or in the analog domain, a fault condition is detected in response to the detection period T being less than the threshold period. Figure 3A and Figure 3B This can be better understood by the exemplary operating waveforms shown. Figure 3A The drain voltage waveform related to the comparator output signal Comp_SRGO and the SR_G terminal voltage waveform is shown in the absence of a fault condition of the SR switch transistor (i.e., normal operation). Since the channel is operating normally, the body diode of the SR switch transistor conducts a negligible current, so that when the SR switch transistor is conducting (and therefore the SR_G terminal voltage is charged to a high level), the negative value of the drain-to-source voltage of the SR switch transistor is not very low. The SR switch transistor starts to conduct at time T0. Since the source-to-drain voltage is not strongly pulled negatively due to the conduction of the body diode, the drain voltage crosses the negative threshold voltage of -280mV at time T1, which is long before the time T2 when the SW switch transistor stops conducting (e.g., about 1μs before). Therefore, Figure 3AThe detection period T in is about 1 μs. The detection period T is the delay between the negative threshold voltage crossing at time T1 and the SR switch transistor turning off at time T2.

[0028] In contrast, Figure 3B In the waveform of , the SR switch transistor has a partial open circuit fault (or open circuit fault) condition. Figure 3B In the example, the SR switch transistor is turned on again at time T0 and turned off at time T2. However, due to the stronger negative pull on the drain-to-source voltage caused by the body diode conduction caused by the fault condition, the drain voltage rises above the negative threshold voltage only at time T1, which is just before time T2. Therefore, Figure 3B The detection period T in is relatively short (eg, about 400ns).

[0029] Reference again Figure 1 , the SR controller 120 may respond to the fault detection by stopping cycling of the power switch transistor SW. For example, the SR controller 120 may communicate the detection of the partial open circuit / open circuit fault condition by transmitting an alarm signal through a ground isolation channel 125 (such as an optoisolator or a digital isolator). Additionally (or alternatively), the SR controller 120 may notify a user of the fault detection, such as by communicating the detection of the fault through a USB cable used to charge a cellular phone.

[0030] exist Figure 4 1 shows a gate drive voltage monitoring feature of the SR controller 120 for detecting a gate open fault condition and / or a gate short fault condition. The SR gate driver 215 includes a pull-up PMOS transistor P1 having a source connected to a power node for a power supply voltage Vdrive and a drain connected to a gate terminal SR_G. The SR gate driver 215 also includes a pull-down NMOS transistor M1 having a source connected to a ground portion and a drain connected to the gate terminal SR_G. During normal operation, a low-level active pull-up signal Spu drives the gates of transistors P1 and M1 to control whether the SR switch transistor is turned on or off. When the SR switch transistor is to be turned on, the pull-up signal Spu discharges to turn on the pull-up transistor P1, thereby charging the gate terminal SR_G to the power supply voltage Vdrive. The discharge of the pull-up signal Spu turns off the pull-down transistor M. When the SR switch transistor is to be turned off, the pull-up signal Spu is charged to the controller power supply voltage to turn on the pull-down transistor M1 and turn off the pull-up transistor P1. Turning on the pull-down transistor M1 discharges the gate terminal SR_G, turning off the SR switch transistor.

[0031] In order to be able to detect a gate open fault condition or a gate short fault condition during normal operation, the SR gate driver 215 is also connected to a fault detection circuit 405 that measures a detection period T2, which corresponds to a delay from when the SR gate driver 215 starts the pull-up of the SR_G terminal voltage to when the SR_G terminal voltage crosses a positive threshold voltage Vdet_ref (such as half of the supply voltage Vdriver). If the detection period T2 is too long compared to a fault-free delay, a gate short fault condition is considered to be detected. Conversely, if the detection period T2 is too short, a gate open fault condition is considered to be detected.

[0032] The rise time of the SR_G terminal voltage associated with these fault conditions can be better understood through the following discussion. Figure 4 As shown, the gate terminal SR_G of the SR controller 120 is connected to the gate (G) of the SR switch transistor through a gate resistor Rg. The SR switch transistor also has a gate-to-source capacitance Cgs between its gate G and its source S. During the pull-up period of the SR_G terminal, the SR gate driver 215 has a pull-up resistor Rpu that includes the on-resistance of the pull-up transistor P1. In view of these factors, it can be shown that the gate voltage (Vg(t)) as a function of time during the pull-up period of the SR_G terminal can be expressed as:

[0033] Vg(t)=Vdrive(1-e -t / τ )

[0034] Where the time constant τ is equal to (Rpu+Rg)*Cgs. Similarly, the SR_G terminal voltage (VSR_G(t)) as a function of time during the pull-up period can be expressed as:

[0035]

[0036] If the gate resistance Rg is considerable or even larger than the pull-up resistance Rpu, the measurement of the detection period T2 becomes problematic due to the rapid increase of the SR_G terminal voltage. In order to facilitate the measurement of the detection period T2, the SR gate driver 215 may include a second pull-up PMOS transistor P2 arranged in parallel with the pull-up transistor P1. The fault detection low-level active pull-up signal Sdet controls the gate of the PMOS transistor P2 and the pull-down transistor M1 during the fault detection mode. The size of the pull-up transistor P2 is set to be a fraction of the pull-up transistor P1, so that the detection pull-up resistance Rdet of the SR gate driver 215 during the fault detection operating mode is several times the pull-up resistance Rpu. During the fault measurement, the pull-up transistor P1 is not used, but the gate terminal SR_G voltage is charged by the pull-up transistor P2. Therefore, the SR_G terminal voltage (VSR_G(t)) as a function of time during the pull-up in the fault detection mode can be expressed as:

[0037]

[0038] Wherein the time constant τ1 is equal to (Rdet+Rg)*Cgs. The time constant τ1 is greater than the time constant τ to slow down the increase of the SR_G terminal voltage. In some applications, Rdet can be 20 ohms or 30 ohms. Due to the relatively large resistance Rdet, the turn-on time of the SR switch transistor increases, but this increase is negligible because the default detection mode may be run relatively infrequently during operation. For example, the fault detection mode can be used to cycle on the SR switch transistor once every 1000 cycles.

[0039] The fault detection circuit 405 includes a counter or timer 415 that, when the fault detection active low pull-up signal Sdet is asserted, begins counting the detection period T2 in response to cycles of the clock signal from the clock 420. The comparator 410 compares the SR_G terminal voltage with a positive threshold voltage Vdet_ref (e.g., half of the supply voltage Vdrive). When the SR_G terminal voltage rises to equal the positive threshold voltage Vdet_ref, the comparator 410 asserts its output signal Vdet_out to stop the counting of the counter 415. The logic circuit 425 then compares the resulting period T2 with a range of fault-free periods extending from a minimum value (denoted as Tgood) to a maximum value (denoted as Tshort). It should be understood that the timer 415 can also be implemented in the analog domain similar to that discussed for timer 210. If the period T2 is within the fault-free period range such that Tgood ≤ T2 ≥ Tshort, the logic circuit 425 does not detect any faults. But if T2 < Tgood or T2 > Tshort, the logic circuit 425 asserts the fault detection signal. The minimum value can also be denoted herein as the second threshold period. Similarly, the maximum period Tshort can be denoted herein as the third threshold period. As discussed regarding the detection of partial open circuit fault conditions and open circuit fault conditions, since the gate open circuit fault condition or the gate short circuit fault condition is detected by the corresponding alarm signal, the SR controller 120 can stop the cycling of the power switch transistor SW, which is transmitted through the isolation channel 125 (e.g., a command transmitted through an opto-isolator). Similarly, the SR controller 120 can notify the user of the detected fault, such as through a message transmitted via a USB cable to the user's smartphone.

[0040] In Figure 5A , Figure 5B and Figure 5C some exemplary waveforms of the detection of gate open circuit fault conditions and gate short circuit fault conditions by the fault detection circuit 405 are shown. Although Sdet can be an active low signal, for illustrative purposes, it is shown as an active high signal in FIG. 5A to FIG. 5C . The SR_G terminal voltage waveform is designated as VSR_G. In Figure 5A , the assertion of the Vdet_out output signal from the comparator 410 occurs after the assertion of the Sdet signal, such that the detection period T2 is greater than the minimum period Tgood and less than the maximum period Tshort. Thus, Figure 5A corresponds to normal operation in which no gate open condition or gate short condition is detected. In Figure 5B, the assertion of the Vdet_out output signal occurs relatively quickly after the assertion of the Sdet signal, so that the detection period T2 is less than the minimum period Tgood. Figure 5B corresponds to a detected gate open fault condition. Figure 5C In the example, the assertion of the Vdet_out output signal occurs relatively slowly after the assertion of the Sdet signal, so that the detection period T2 is greater than the maximum period Tshort. Figure 5C Corresponding to the detection of a gate short circuit fault condition. Therefore, it should be understood that the fault detection circuit 405 distinguishes between a gate open circuit fault condition and a gate short circuit fault condition. Therefore, separate alarm signals can be used to transmit these fault conditions so that the user can be alerted to the fault identification.

[0041] Those skilled in the art will now appreciate that various modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the apparatus of the present invention without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are only some examples thereof, but should be fully commensurate with the scope of the claims appended hereto and their functional equivalents.

Claims

1. A secondary side controller for a flyback converter, the secondary side controller comprising: a gate driver for controlling the cycling of a synchronous rectifier switching transistor; a drain terminal for connecting to a drain of the synchronous rectifier switching transistor; a timer for timing a detection period that begins when the gate driver has turned on the synchronous rectifier switching transistor and ends when the voltage at the drain terminal exceeds a negative threshold voltage; as well as A logic circuit is configured to compare the detection period with a threshold period to detect whether the synchronous rectifier switching transistor has a partial open-circuit fault condition or an open-circuit fault condition.

2. The secondary side controller according to claim 1, further comprising: A comparator is configured to compare the voltage at the drain terminal with the negative threshold voltage to provide an output signal to the timer to stop timing the detection cycle in response to the voltage at the drain terminal being greater than the negative threshold voltage. 3 . The secondary-side controller of claim 2 , wherein the timer is a counter that counts in response to cycles of a clock signal.

4. The secondary side controller of claim 2, wherein the timer is an analog circuit timer.

5. The secondary-side controller of claim 1 , wherein the negative threshold voltage is an adaptive negative threshold voltage, the secondary-side controller further comprising: A threshold adaptation circuit is used to adapt the adaptive negative threshold voltage. 6 . The secondary side controller of claim 5 , wherein the threshold adaptation circuit is configured to adapt the adaptive negative threshold voltage in response to an operating temperature of the flyback converter. 7 . The secondary side controller of claim 1 , wherein the secondary side controller is configured to transmit an alarm signal to the primary side controller in response to detecting the partial open circuit fault condition or detecting the open circuit fault condition. 8 . The secondary side controller of claim 7 , wherein the primary side controller is configured to stop cycling a power switch transistor in response to receiving the alarm signal.

9. The secondary side controller of claim 1, wherein the negative threshold voltage is -280 millivolts. 10 . The secondary side controller of claim 1 , wherein the logic circuit is configured to detect whether the synchronous rectifier switching transistor has the partial open circuit fault condition or the open circuit fault condition in response to the detection period being less than the threshold period.

11. The secondary-side controller of claim 10, wherein the threshold period is 1 μs.

12. A secondary side controller for a flyback converter, the secondary side controller comprising: a gate driver for controlling the cycling of a synchronous rectifier switching transistor via a gate terminal; a timer for timing a detection period that begins when the gate driver has turned on the synchronous rectifier switching transistor and ends when the voltage at the gate terminal exceeds a positive threshold voltage; as well as A logic circuit is configured to detect whether the synchronous rectifier switching transistor has an open gate fault condition in response to the detection period being shorter than a first threshold period.

13. The secondary side controller of claim 12, wherein the logic circuit is configured to detect whether the synchronous rectifier switching transistor has a gate short fault condition in response to the detection period being longer than a second threshold period, wherein the second threshold period is longer than the first threshold period.

14. The secondary side controller of claim 12, wherein the gate driver comprises: a first pull-up transistor for charging the gate terminal during normal operation when the timer and the logic circuit are inactive; as well as A second pull-up transistor for charging the gate terminal during a fault detection mode of operation in which the timer and the logic circuit are both active, wherein the second pull-up transistor has a smaller size than the first pull-up transistor.

15. The secondary-side controller of claim 13, wherein the timer comprises a counter configured to count in response to cycles of a clock signal. 16 . The secondary side controller of claim 13 , wherein the logic circuit is configured to assert a first alarm signal in response to detecting the gate open fault condition and to assert a second alarm signal in response to detecting the gate short fault condition. 17 . The secondary-side controller of claim 14 , wherein the first pull-up transistor and the second pull-up transistor are both PMOS transistors.

18. A method of detecting a fault condition of a synchronous rectifier switching transistor in a flyback converter, the method comprising: turning on the synchronous rectifier switching transistor; when the synchronous rectifier switching transistor is turned on, in response to a drain-to-source voltage of the synchronous rectifier switching transistor being greater than a negative threshold voltage, starting timing of a first detection period; ending the timing of the first detection period in response to turning off the synchronous rectifier switching transistor; as well as A partial open-circuit fault condition of the synchronous rectifier switching transistor is detected in response to the first detection period being shorter than a first threshold period.

19. The method of claim 18, wherein the turning on of the synchronous rectifier switching transistor comprises charging a gate terminal coupled to a gate of the synchronous rectifier switching transistor, the method further comprising: initiating timing of a second detection period in response to said turning on of said synchronous rectifier switching transistor; ending timing of the second detection period in response to the voltage of the gate terminal exceeding a positive threshold voltage; detecting an open gate fault condition of the synchronous rectifier switching transistor in response to the second detection period being less than a second threshold period; as well as A gate shorted fault condition of the synchronous rectifier switching transistor is detected in response to the second detection period being greater than a third threshold period, wherein the third threshold period is longer than the second threshold period.

20. The method of claim 19, wherein the positive threshold voltage is half of a power supply voltage of a gate driver.

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