Command-triggered power gating for memory devices

Abstract

The present application relates to command-triggered power gating for a memory device. Row logic circuitry for a memory array may be powered on (turned on) or powered off (turned off) independently of at least some other components of the memory device. For example, the row logic circuitry may be turned on when a bank of the memory array is in an active state, but may be turned off when the bank is in a standby or powered off state. Additionally or alternatively, error correction circuitry for a memory array may be powered on (turned on) or powered off (turned off) independently of at least some other components of the memory device. For example, the error correction circuitry may be turned on during an access portion of an access sequence and may be turned off otherwise.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 16 / 885,912 filed by Akamatsu et al. on May 28, 2020, entitled “COMMAND TRIGGERED POWER GATING FOR AMEMORY DEVICE,” which is assigned to its assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to command triggered power gating for memory devices. Background Art

[0004] The following relates generally to one or more memory systems, and more specifically, to command triggered power gating for memory devices.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state into the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (such as FeRAM) can retain its stored logic state for a long time even in the absence of external power. Volatile memory devices (such as DRAM) lose their stored state when disconnected from the external power supply. FeRAM is able to achieve densities similar to volatile memory, but can be non-volatile due to the use of ferroelectric capacitors as storage devices. Summary of the invention

[0007] In some examples, a memory device may receive an activate command at the memory device including a memory array. The memory device may activate row logic circuitry coupled to the memory array in response to receiving the activate command. The memory device may activate a memory bank of the memory array after activating the row logic circuitry in response to receiving the activate command. The memory device may perform an access operation on one or more memory cells within the memory bank after activating the memory bank and the row logic circuitry.

[0008] In some examples, a memory device may receive an activate command at the memory device including a memory array. The memory device may receive an access command at the memory device after receiving the activate command. The memory device may activate error correction code circuitry coupled to the memory array in response to receiving the access command. The memory device may access one or more memory cells within a memory bank of the memory array based on activating the error correction code circuitry.

[0009] In some examples, an apparatus may include a die including: row logic circuitry; a memory bank of a memory array, the memory bank coupled to the row logic circuitry; and a controller coupled to the row logic circuitry and the memory bank. The controller may be configured to: receive an activate command at the die; activate the row logic circuitry in response to receiving the activate command; activate the memory bank after activating the row logic circuitry in response to receiving the activate command; and perform an access operation on one or more memory cells within the memory bank after activating the memory bank and using the row logic circuitry.

[0010] In some examples, an apparatus may include a die including: error correction code circuitry; a memory bank of a memory array, the memory bank coupled to the error correction code circuitry; and a controller coupled to the error correction code circuitry and the memory bank. The controller may be configured to: receive an activate command at the die; receive an access command at the die after receiving the activate command; activate the error correction code circuitry in response to receiving the access command; and access one or more memory cells within the memory bank based at least in part on activating the error correction code circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting command triggered power gating for a memory device according to examples disclosed herein is described.

[0012] Figure 2An example of a memory die supporting command triggered power gating for a memory device according to examples disclosed herein is described.

[0013] Figure 3 An example of a low power domain circuit that supports command triggered power gating for a memory device according to examples disclosed herein is described.

[0014] Figure 4 An example of a memory device architecture that supports command triggered power gating for a memory device according to examples disclosed herein is described.

[0015] Figure 5A and 5B An example of a signaling diagram supporting command triggered power gating for a memory device according to examples disclosed herein is illustrated.

[0016] Figure 6 A block diagram of a memory device supporting command triggered power gating for the memory device according to examples disclosed herein is shown.

[0017] Figure 7 A block diagram of a memory device supporting command triggered power gating for the memory device according to examples disclosed herein is shown.

[0018] Figure 8 and 9

[0013] A flow chart illustrating one or several methods of supporting command-triggered power gating for a memory device according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0019] Reducing the amount of power consumption of a memory device may have one or more advantages. For example, reducing the amount of power consumption may extend the battery life of a battery-powered device. One way in which a memory device may reduce power may be for the memory device to enable different components within the memory device to be activated or deactivated independently of each other. Deactivating components when they are not in use may enable the memory device to save power and therefore reduce power consumption. To enable independent activation and deactivation, the memory device may include multiple local power domains (LPDs), where each LPD provides power to one or more components, and the LPDs may be activated and deactivated independently of each other.

[0020] To save power, the row logic circuit system for a memory bank of a memory array may be active when the memory bank is in an active state, and inactive otherwise (e.g., when the memory device is in a power-off state or the memory bank is in a standby state). For example, the LPD for the row logic circuit system may be turned on (e.g., powered on, activated) in response to an activation command for the memory bank or its memory cells (e.g., as opposed to being turned on (active) when the memory device or memory array is in a standby state, or additionally or alternatively whenever the memory device or memory array is not in a power-off (e.g., low-power) state). Subsequently, the LPD for the row logic circuit system may be turned off (e.g., powered off, deactivated) in response to a corresponding precharge command for the memory bank.

[0021] Additionally or alternatively, to save power, error correction code (ECC) circuitry for a bank of a memory array may be active during a write or read cycle of the bank and may otherwise be inactive. For example, an LPD for the ECC circuitry may be turned on (e.g., powered on, activated) in response to an access command (e.g., a write command or a read command) for the bank or its memory cells (e.g., as opposed to being turned on (active) whenever the bank is active, or additionally or alternatively, in response to an activate command for the bank or its memory cells and thus prior to the access command). Subsequently, the LPD for the ECC circuitry may be turned off (e.g., powered off, deactivated) in response to a corresponding precharge command for the bank.

[0022] The features of the present disclosure are first described in reference Figures 1 to 2 The features of the present disclosure are described in the context of the memory system and die described in the present disclosure. Figures 3 to 5B These and other features of the present disclosure are described in the context of low power domain circuits, memory device architectures, and signaling diagrams described herein. Figures 6 to 9 The apparatus diagrams and flow diagrams described herein that relate to command-triggered power gating for a memory device are further illustrated and described with reference to the apparatus diagrams and flow diagrams described herein.

[0023] Figure 1 An example of a system 100 that supports command-triggered power gating for a memory device according to examples disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device, such as the memory device 110.

[0024] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of the system that is operable to store data for one or more other components of system 100.

[0025] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0026] Memory device 110 may be a stand-alone device or component that is operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme for modulating signals, various pin configurations for transmitting signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0027] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0028] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0029] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a single chip system (SoC), among other examples. In some examples, the external memory controller 120 may be implemented by or be part of the processor 125.

[0030] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0031] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support the desired capacity or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sectors), each of which is operable to store at least one data bit. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package. In some cases, the memory device 110 may include LPDs that each provide power to a subset of the memory device (e.g., one or more components) and the memory device 110 may independently activate or deactivate. For example, memory device 110 may include a first LPD for ECC circuitry coupled to memory array 170, a second LPD for row logic circuitry coupled to memory array 170, a third LPD for column logic circuitry and / or a column select buffer coupled to memory array 170, and so on.

[0032] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0033] In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store data for host device 105 or a read command indicating that memory device 110 is to provide data stored in memory die 160 to host device 105.

[0034] The local memory controller 165 (e.g., local to the memory die 160) is operable to control the operation of the memory die 160. In some examples, the local memory controller 165 is operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 may not include the device memory controller 155 and the local memory controller 165, or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0035] The external memory controller 120 is operable to enable one or more of information, data, or commands to be transferred between a component of the system 100 or host device 105, such as the processor 125, and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or functions thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or functions thereof described herein may be implemented by one or more components of the memory device 110, such as the device memory controller 155, the local memory controller 165, or vice versa.

[0036] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of the system 100, and the pin may be operable to serve as part of a channel.

[0037] The channels 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling may be transmitted over the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either the rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both the rising and falling edges of a clock signal).

[0038] In some examples, CA channel 186 is operable to communicate commands between host device 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, the commands carried by CA channel 186 may include a read command with an address of desired data. In some examples, CA channel 186 may include any number of signal paths to decode one or more of the address or command data (e.g., eight or nine signal paths).

[0039] In some cases, an activate command may be received by the memory device 110 via the CA channel 186. In response to the activate command, the memory device 110 may activate a memory bank of the memory array 170 and open a row within the memory bank (e.g., activate a word line). When activated, the memory bank may be considered to be in an active mode. In some cases, a precharge command may be received by the memory device 110 via the CA channel 186. In response to the precharge command, the memory device 110 may close an open row (e.g., deactivate a previously activated word line) and deactivate a memory bank including a closed row. When deactivated, the memory bank may be considered to be in a standby (e.g., idle) mode. Between receiving an activate command for a row and a precharge command, an access (e.g., read or write) command may be received by the memory device 110 via the CA channel 186. The memory device may perform a corresponding access operation in response to the access command (e.g., may read data from one or more cells of an open row in response to a read command, may write data to one or more cells of an open row in response to a write command). In some cases, the memory device may receive power-down and power-up (e.g., power-down exit) commands via CA channel 186, and may transition memory array 170 or its memory banks into or out of one or more power-down (e.g., low power) modes in response to such power-down and power-up commands. When a memory bank or an entity including a memory bank (e.g., memory 170 or memory device 110) is in a power-down mode, the memory bank may be considered to be in a power-down mode.

[0040] In some examples, the clock signal channel 188 is operable to transmit one or more clock signals between the host device 105 and the memory device 110. Each clock signal is operable to oscillate between a high state and a low state, and can support coordination (e.g., in time) between the actions of the host device 105 and the memory device 110. In some examples, the clock signal may be single-ended. In some examples, the clock signal may provide a timing reference for command and address operations for the memory device 110 or other full system operations for the memory device 110. Therefore, the clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0041] In some examples, data channel 190 is operable to transfer one or more of data or control information between host device 105 and memory device 110. For example, data channel 190 may transfer information written to memory device 110 (e.g., bidirectional) or information read from memory device 110.

[0042] In some examples, memory device 110 may activate and deactivate LPDs independently of one another (e.g., at different or independently configurable times) to save power. For example, memory device 110 may activate row logic circuitry for a bank of memory array 170 when the bank is in an active state, and may otherwise keep the row logic circuitry deactivated (e.g., the row logic circuitry may be deactivated when memory device 110 is in a power-off state and the bank is in a standby state). For example, memory device 110 may turn on the LPD for the row logic circuitry in response to receiving an activate command for the bank. Subsequently, memory device 110 may turn off the LPD for the row logic circuitry in response to receiving a corresponding precharge command for the bank.

[0043] Additionally or alternatively, to save power, the memory device 110 may activate the ECC circuitry for a bank of the memory array 170 during a write or read cycle of an access sequence, and may otherwise keep the ECC circuitry deactivated. For example, the memory device 110 may turn on the LPD for the ECC circuitry in response to receiving an access command (e.g., a write command or a read command) for the bank (e.g., the ECC circuitry may be deactivated when the memory device 110 is in a power-off state and the bank is in a standby state, and may only last for a portion of the time that the bank is in an active state). Subsequently, the memory device 110 may turn off the LPD for the ECC circuitry in response to receiving a corresponding precharge command for the bank.

[0044] Figure 2 An example of a memory die 200 that supports command-triggered power gating for a memory device according to examples disclosed herein is illustrated. The memory die 200 may be a reference Figure 11 . An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store a different logical state (e.g., programmed to one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, such as with reference to FIG. Figure 1 Described memory array 170. Although aspects of the techniques disclosed herein may be described with reference to examples in the context of FeRAM memory dies, it should be noted that some or each of the techniques may also be applied to other types of memory or memory dies (eg, DRAM memory dies).

[0045] The memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) representing a programmable state in a capacitor. In a FeRAM architecture, the memory cell 205 may include a capacitor 240 that includes a ferroelectric material for storing a charge and / or polarization representing a programmable state. The memory cell 205 may include a logic storage component (e.g., capacitor 240) and a switching component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled to the switching component 245, and a second node of the capacitor 240 may be coupled to the plate line 220. The switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0046] Memory die 200 may include access lines such as word lines 210, digit lines 215, and plate lines 220 arranged in a pattern such as a grid-like pattern. Access lines may be conductive lines coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or the like, may be interchanged without loss of understanding or operation. Memory cells 205 may be positioned at the intersections of word lines 210, digit lines 215, and / or plate lines 220.

[0047] Operations such as reading and writing can be performed on the memory cells 205 by activating or selecting access lines such as word lines 210, digit lines 215, and / or plate lines 220. By biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying voltages to the word lines 210, digit lines 215, or plate lines 220), a single memory cell 205 can be accessed at their intersections. Activating or selecting a word line 210, digit line 215, or plate line 220 can include applying voltages to the respective lines.

[0048] Access to the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from the local memory controller 265 and activate the word lines 210 based on the received row address. The column decoder 230 may receive a column address from the local memory controller 265 and activate the digit lines 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265 and activate the plate lines 220 based on the received plate address.

[0049] Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switching component 245. Capacitor 240 may be in electronic communication with digit line 215 using switching component 245. For example, capacitor 240 may be isolated from digit line 215 when switching component 245 is deactivated, and capacitor 240 may be coupled to digit line 215 when switching component 245 is activated.

[0050] The word line 210 can be a conductive line in electronic communication with the memory cell 205, which can be used to perform access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with the gate of the switching element 245 of the memory cell 205, and can be operated to control the switching element 245 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching element.

[0051] The digit line 215 can be a conductive line that connects the memory cell 205 with the sensing element 250. In some architectures, the memory cell 205 can be selectively coupled with the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 245 of the memory cell 205 can operate to selectively couple and / or isolate the capacitor 240 of the memory cell 205 from the digit line 215. In some architectures, the memory cell 205 can be in electronic communication with the digit line 215 (e.g., continuously).

[0052] Plate line 220 may be a conductive line in electronic communication with memory cell 205, which may be used to perform access operations on memory cell 205. Plate line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of capacitor 240. During access operations of memory cell 205, plate line 220 may cooperate with digit line 215 to bias capacitor 240.

[0053] The sensing component 250 can determine the state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205, and determine the logic state of the memory cell 205 based on the detected state. The sensing component 250 can include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sensing component 250 can compare the signal received from the memory cell 205 across the digital line 215 with a reference 255 (e.g., a reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., to the input / output 260), and the detected logic state can be indicated to another component of the memory device 110 including the memory die 200.

[0054] The local memory controller 265 may control the operation of the memory cell 205 through various components such as the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250. The local memory controller 265 may be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 225, column decoder 230, and plate driver 235 and sensing component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 265 may generate row signals and column address signals to activate the target word line 210, the target digit line 215, and the target plate line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary or be different as the various operations discussed in operating the memory die 200 are performed.

[0055] The local memory controller 265 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 is operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0056] The local memory controller 265 is operable to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. The local memory controller 265 may identify a target memory cell 205 on which a write operation is performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled to the target memory cell 205. The local memory controller 265 may activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The local memory controller 265 may apply a specific signal (e.g., a write pulse) to the digit line 215 during a write operation to store a specific state (e.g., a charge) in the capacitor 240 of the memory cell 205. The pulse used as part of the write operation may include one or more voltage levels for a duration.

[0057] The local memory controller 265 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in a memory cell 205 of the memory die 200 may be determined. The local memory controller 265 may identify a target memory cell 205 on which a read operation is performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled to the target memory cell 205. The local memory controller 265 may activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transfer a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 can activate the sense component 250 (eg, latch the sense component) and thereby compare the signal received from the memory cell 205 to the reference 255. Based on the comparison, the sense component 250 can determine the logic state stored on the memory cell 205.

[0058] In some examples, memory die 200 may include row logic circuitry 270. Row logic circuitry 270 may, for example, include control circuitry and generate control signals for aspects of memory die 200 related to operating one or more rows of memory cells 205. In some examples, row logic circuitry 270 may be coupled with or included in local memory controller 265. In some examples, row logic circuitry 270 may be coupled with row decoder 225. In such cases, row logic circuitry 270 may include one or more word line drivers that may be coupled with one or more word lines 210 of memory die 200 via row decoder 225. Row logic circuitry 270 may be configured to control the word line drivers to cause the drivers to activate or deactivate one or more word lines 210. Additionally or alternatively, row logic circuitry may be coupled with sensing component 250. In such cases, row logic circuitry 270 may include control logic coupled with one or more sense amplifiers of sensing component 250. Row logic circuitry 270 may be configured to activate or deactivate one or more sense amplifiers or generate timing signals that control the operation of one or more sense amplifiers. In some examples, row logic circuitry 270 may be active when a bank of a memory array is in an active state and inactive otherwise (e.g., when the memory device is in a power-off state or the bank is in a standby state). For example, the LPD for row logic circuitry 270 may be turned on in response to an activate command for a bank. Subsequently, the LPD for row logic circuitry 270 may be turned off in response to a corresponding precharge command for the bank.

[0059] In some examples, the memory die 200 may include an ECC circuit system 275. In some examples, the ECC circuit system 275 may be coupled to or included in the local memory controller 265. The ECC circuit system 275 may be coupled to the memory array of the memory die 200 (e.g., via the local memory controller 265). If the local memory controller 265 receives a write command, the ECC circuit system 275 may be configured to generate an ECC for a set of data stored in the memory array indicated by the write command. In such a case, the generated ECC may be stored in the memory array. Alternatively, if the local memory controller 265 receives a read command, the ECC circuit system 275 may be configured to perform an error correction procedure using an ECC retrieved from the memory array and associated with a set of data retrieved from the memory array indicated by the read command. As used herein, error correction may broadly refer to error detection or error correction. The ECC circuit system 275 may generate a second set of data based on the retrieved data set and the retrieved ECC. In such a case, the memory die 200 may transmit the second set of data. In some examples, ECC circuitry 275 may be active during a write or read cycle of a bank of the memory array and may be inactive otherwise. For example, the LPD for ECC circuitry 275 may be turned on in response to an access command (e.g., a write command or a read command) for the bank. Subsequently, the LPD for the ECC circuitry may be turned off in response to a corresponding precharge command for the bank.

[0060] Figure 3 An example of an LPD circuit 300 that supports command-triggered power gating for a memory device according to examples disclosed herein is described. It should be noted that the examples and techniques described herein may be applied to one or more types of memory arrays (e.g., FeRAM memory arrays, DRAM memory arrays). The LPD circuit 300 may be a circuit configured to support powering one or more components within a memory device and selectively activating or deactivating one or more components within the memory device independently of other components of the memory device via a technique known as power gating. Components that are powered by the same LPD circuit 300 and selectively activated or deactivated using the same LPD circuit 300 may be referred to as an LPD or within an LPD. Power gating may involve the LPD circuit 300 selectively cutting off current to one or more components. In one example, a first LPD circuit 300 may be used to activate or deactivate a row logic circuit system (e.g., reference 1 to FIG. 1 ). Figure 2 The second LPD circuit 300 may be used to activate or deactivate the ECC circuit system (eg, referring to the row logic circuit system 270 described above). Figure 2 1 and / or the ECC circuitry 275 described above), and the third LPD circuit 300 may be used to activate or deactivate the column logic circuitry and / or the column select buffer.

[0061] The LPD circuit 300 may include a first node 305 and a second node 310. The first node 305 may be coupled to a first power gate switch 315 and circuitry 325. The first power gate switch 315 may include one or more transistors, such as one or more positive channel metal oxide semiconductor (PMOS) transistors, and may be coupled to a voltage supply. The second node 310 may be coupled to a second power gate switch 320 and circuitry 325. The second power gate switch 320 may include one or more transistors, such as one or more negative channel metal oxide semiconductor (NMOS) transistors, and may be coupled to ground. The circuitry 325 may include any circuitry configured to be coupled to and powered by the first node 305 and the second node 310. The circuitry 325 may represent one or more components within the LPD corresponding to the memory device 110 of the LPD circuit 300.

[0062] In some examples, the LPD circuit 300 may be operated to switch from activating the circuit system 325 (e.g., in an active or on state, which may be referred to as LPD on) to deactivating the circuit system 325 (e.g., in an inactive or off state, which may be referred to as LPD off), or vice versa. When the circuit system 325 is in the active state (activated), the first power gate switch 315 may be activated (e.g., turned on, conducting), which may supply a voltage to the first node 305 based on a voltage supply (e.g., a positive supply) coupled to the first power gate switch 315. Additionally, the second power gate switch 320 may be activated, which may supply a voltage to the second node 310 based on a voltage supply (e.g., a ground or negative supply) coupled to the second power gate switch 320. Providing these voltages to the first node 305 and the second node 310 may configure the circuit system 325 to be powered on and in an active state. When the circuit system 325 is in an inactive state (deactivated), one or more of the first power gate switch 315 or the second power gate switch 320 may be deactivated (e.g., turned off, non-conductive), thereby isolating the circuit system 325 from one or more of the voltage supplies coupled to the first power gate switch 315 or the voltage supplies coupled to the second power gate switch 320.

[0063] The timing of operating LPD circuit 300 to switch from circuit system 325 active to circuit system 325 inactive or vice versa may depend on the function of circuit system 325. For example, if circuit system 325 is row logic circuit system (e.g., reference Figure 2If the row logic circuit system 270 described in the embodiment of the present invention is used, the LPD circuit 300 can be operated to activate the circuit system 325 when the memory bank of the memory array switches from the standby state to the active state, and otherwise maintain the circuit system 325 in the inactive (deactivated) state. However, if the circuit system 325 is an ECC circuit system (e.g., referring to Figure 2 If the ECC circuitry 275 described above is present, then the LPD circuit 300 may be operated to activate the circuitry 325 during a read or write cycle of an access sequence, and otherwise maintain the circuitry 325 in an inactive (deactivated) state.

[0064] Turning off power-gated switches 315 and 320 to place circuit system 325 in an inactive mode may have one or more advantages. For example, power-gated switches 315 and 320 may have lower leakage when in an off state than transistors or other components of circuit system 325. In some cases, power-gated switches 315 and 320 may be physically larger (e.g., thicker gate oxide) or have a higher threshold voltage than transistors or other components of circuit system 325. Thus, by isolating first node 305 and second node 310 from the corresponding power supply, power-gated switches 315 and 320 may mitigate the amount of current that circuit system 325 may otherwise leak.

[0065] Figure 4 An example of a memory device architecture 400 that supports command-triggered power gating for a memory device according to examples disclosed herein is illustrated. It should be noted that the examples and techniques described herein can be applied to one or more types of memory arrays (e.g., FeRAM memory arrays, DRAM memory arrays). Memory device architecture 400 can represent one or more components of a memory die 402 (which can be an example of memory die 160 or memory die 200). Memory array 405 can be a reference Figure 1 The memory array 170 described or referenced Figure 2 The row logic element 415 may be referenced to an example memory array. Figure 2 The examples of row logic circuitry 270 described herein and the ECC components 410 may be referenced. Figure 2 An example of ECC circuitry 275 is described.

[0066] Memory device architecture 400 may include a memory array 405. Memory array 405 may include memory cells (e.g., memory cell 205) coupled to respective row lines (e.g., word lines 210) and respective column lines (e.g., digit lines 215). Memory array 405 may be operable to store data (e.g., if a memory device including memory array 405 receives a write command) or retrieve data (e.g., if a memory device including memory array 405 receives a read command).

[0067] The memory device architecture 400 may include an ECC component 410, which may be a reference Figure 2 4. An example of an aspect of the ECC circuit system 275 described herein. An ECC component 410 may be coupled to a memory array 405. When a memory device including the memory array 405 receives a write command, the ECC component 410 may be configured to generate an ECC that the write command indicates a set of data stored in the memory array 405. In such a case, the generated ECC may be stored in the memory array 405. Alternatively, if the memory device including the memory array 405 receives a read command, the ECC component 410 may be configured to perform an error correction procedure using an ECC retrieved from the memory array 405. The retrieved ECC may be associated with a first set of data retrieved from the memory array 405 indicated by the read command. The ECC component 410 may generate a second set of data based on the retrieved set of data and the retrieved ECC. In such a case, the memory device may transmit the second set of data (e.g., to the host device 105).

[0068] The memory device architecture 400 may include a row logic component 415, which may be a reference Figure 2 4. The row logic component 415 may be coupled to the memory array 405. The row logic component 415 may include or be configured to control the operation of one or more row line drivers (e.g., word line drivers) that may be coupled to one or more row lines of the memory array 405. The row line drivers may be configured to activate or deactivate the one or more row lines via the row line drivers. Additionally or alternatively, the row logic component 415 may include control logic coupled to one or more sense amplifiers for the memory array 405. In such cases, the row logic component 415 may be configured to activate or deactivate or otherwise control the one or more sense amplifiers.

[0069] The memory device architecture 400 can include a column logic component 420 and a column select buffer 425. The column logic component 420 and the column select buffer 425 can be coupled with the memory array 405.

[0070] In some examples, a memory device including memory array 405 may support one or more power-down modes (modes may alternatively be referred to as states). When operating in a power-down mode, some or all LPDs within the memory device may be deactivated. When not in a power-down mode, memory array 405 or a memory bank of memory array 405 may operate in an active state or a standby state (which may alternatively be referred to as an idle state). Different LPDs associated with a memory bank may be active or inactive in various combinations, depending on whether the memory bank is in an active state or a standby state. In some cases, a memory bank may switch to an active state in response to an activate command for the memory bank or a memory cell therein, and a memory bank may switch to a standby state in response to a precharge command for the memory bank or its memory cells, as long as the memory bank or memory array 405 is not in a power-down mode.

[0071] In some examples, one or more components of the memory device architecture may be independently activated or deactivated using LPD (e.g., as described in reference Figure 3 4. For example, column logic component 420 and column select buffer 425 may be within first LPD 430; row logic component 415 may be within second LPD 435; and ECC component 410 may be within third LPD 440. Thus, ECC component 410 and row logic component 415 may each be activated or deactivated independently of each other and also independently of column logic component 420 and column select buffer 425.

[0072] In some examples, the column logic component 420 and the column select buffer may be active when a memory bank of the memory array 405 is in an active state, and may be inactive otherwise (e.g., may be inactive when a memory device including the memory array 405 is in a powered-off state or a memory bank is in a standby state). Thus, the first LPD 430 may be turned on in response to an activate command for a memory bank, and may then be turned off in response to a corresponding precharge command for the memory bank.

[0073] In some examples, the row logic component 415 can be active when a bank of the memory array is in an active state, and can be inactive otherwise (e.g., can be inactive when a memory device including the memory array 405 is in a powered-off state or a bank is in a standby state). Thus, the second LPD 435 can be turned on in response to an activate command for a bank, and can then be turned off in response to a corresponding precharge command for the bank.

[0074] In some examples, the ECC component 410 may be active during a write or read of an access sequence of a bank of the memory array 405 (e.g., a subset of a time period during which a bank of the memory array 405 is active), and may be inactive otherwise. For example, the third LPD 440 for the ECC circuitry 275 may be turned on in response to an access command for the bank (e.g., a write command or a read command). Subsequently, the third LPD 440 for the ECC circuitry may be turned off in response to a corresponding precharge command for the bank.

[0075] Figure 5A and 5B Examples of signaling diagrams 500-a and 500-b that support command-triggered power gating for a memory device according to examples disclosed herein are illustrated. It should be noted that the examples and techniques described herein can be applied to one or more types of memory arrays (e.g., FeRAM memory arrays, DRAM memory arrays). Signaling diagram 500-a can depict signaling associated with when row logic component 415 is activated and subsequently deactivated. Similarly, signaling diagram 500-b can depict signaling associated with when ECC component 410 is activated and subsequently deactivated.

[0076] Figure 5A Depict clock signaling 505-a, bank signaling 510, and LPD signaling 515-a. Clock signaling 505-a may be referenced Figure 1 4. The bank signaling 510 may represent signaling indicating a state of a bank of the memory array 405. For example, before time 520-f, the bank signaling 510 may have a low value indicating that the bank is in a standby state. After time 520-f, the bank signaling 510 may have a high value indicating that the bank is in an active state. The LPD signaling 515-a may represent signaling indicating a state of the second LPD 435. For example, before time 520-d, the LPD signaling 515-a may have a low value indicating that the LPD circuit (e.g., LPD circuit 300) of the second LPD 435 cuts off current from the row logic component 415 (e.g., and thus the row logic component 415 is to be activated). At time 520 - f , LPD signaling 515 - a may have a high value indicating that the LPD circuit of the second LPD 435 is to provide current to the row logic component 415 (eg, and thus the row logic component 415 is to be deactivated).

[0077] Between times 520-a and 520-b (e.g., one clock cycle), a memory device including memory array 405 may receive a first activate command. Between times 520-b and 520-e (e.g., one clock cycle), the memory device may receive a second activate command. In some cases, the first activate command may include a first portion of an address for one or more memory cells (e.g., for a row of memory cells), and the second activate command may include a second portion of the address. The interval between times 520-c and 520-d may represent a delay from the falling edge of clock signaling 505-a to the time when LPD signaling 515-a switches from a low value to a high value.

[0078] After receiving the second activation command, the bank may switch from the standby state to the active state. This may occur during the bank active delay interval 525, which may span from time 520-c to time 520-f. Thus, for row logic components 415 activated before 520-f, the row logic components 415 may be activated within the LPD wake-up margin 530, and thus activated at any time after time 520-d and before time 520-f. At time 520-f, the bank signaling 510 may switch from a low value to a high value.

[0079] Between time 520-g and time 520-h (e.g., one clock cycle), the memory device may receive a precharge command. After receiving the precharge command (e.g., with some delay relative thereto), LPD signaling 515-a may switch from a high value to a low value. Thus, after LPD signaling 515-a switches from a high value to a low value, row logic component 415 may be deactivated.

[0080] By activating and deactivating row logic component 415 in this manner, a memory device can save power. For example, as disclosed herein, the total duration of activation of row logic component 415 can be less than in some devices, such as some devices where row logic component 415 is only deactivated during a power-off mode. Row logic component 415 can consume less power in a deactivated state. Therefore, row logic component 415 can consume less power according to the methods described herein.

[0081] Figure 5B Depicted are clock signaling 505-b, LPD signaling 515-b, and internal signaling 517 (eg, column redundancy signaling). Clock signaling 505-b may be reference Figure 1405. The LPD signaling 515-b may represent signaling indicating a state of the third LPD 440. For example, before time 535-e, the LPD signaling 515-b may have a low value indicating that the LPD circuit of the third LPD 440 (e.g., the LPD circuit 300) cuts off current from the ECC component 410 (e.g., and thus the ECC component 410 will be activated). At time 535-g, the LPD signaling 515-b may have a high value indicating that the LPD circuit of the third LPD 440 provides current to the ECC component 410 (e.g., and thus the ECC component 410 will be deactivated). The internal signaling 517 may represent signaling indicating whether a bank of the memory array 405 is in a read or write cycle. For example, before time 535-g, the internal signaling 517 may have a low value indicating that the bank is not in a read or write cycle. After time 535 - g , internal signaling 517 may have a high value indicating that the memory bank is in a read or write cycle.

[0082] Between time 535-a and 535-b (e.g., one clock cycle), a memory device including the memory array 405 may receive an activate command. At a later time, between time 535-c and 535-f (e.g., one clock cycle), the memory device may receive an access command (e.g., a read command or a write command). Between time 535-b and time 535-c, the column logic component 420 and the column select buffer 425 may be activated. Additionally, in response to the activate command (e.g., between time 535-b and time 535-c), the memory banks of the memory array 405 may switch from a standby state to an active state. The interval between time 535-d and 535-e may represent a delay from the falling edge of the clock signaling 505-b to the time when the LPD signaling 515-b switches from a low value to a high value.

[0083] After receiving the access command, the memory bank may prepare for an access (e.g., read or write) cycle in the interval spanning from time 535-f to time 535-g. Thus, for the ECC component 410 activated before 535-g, the ECC component 410 may be activated within the LPD wake-up margin 540, and thus activated at any time after 535-e and before time 535-g. At time 535-g, the internal signaling 517 may switch from a low value to a high value.

[0084] Between time 535-h and time 535-i (e.g., one clock cycle), the memory device may receive a precharge command. After receiving the precharge command (e.g., with some delay relative thereto), LPD signaling 515-b may switch from a high value to a low value. Thus, after LPD signaling 515-b switches from a high value to a low value, ECC component 410 may be deactivated.

[0085] By activating and deactivating ECC component 410 in this manner, a memory device can save power. For example, as disclosed herein, the total duration of activating ECC component 410 can be less than in some devices, such as some devices where ECC component 410 can be activated in response to an activate command (e.g., between time 535-a and time 535-b), and therefore at a time earlier than when activated in response to an access command. ECC component 410 can consume less power in a deactivated state. Therefore, ECC component 410 can consume less power according to the methods described herein.

[0086] Figure 6 A block diagram 600 is shown of a memory device 605 that supports command-triggered power gating for a memory device according to examples disclosed herein. The memory device 605 may be a reference Figures 1 to 5B Memory device 605 may include a command receiver 610, a row logic activation component 615, a bank activation component 620, an access component 625, and a memory array operation component 630. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0087] The command receiver 610 may receive an activate command at a memory device including a memory array. In some examples, the command receiver 610 may receive a second activate command prior to the activate command. In some examples, the command receiver 610 may receive a precharge command at the memory device.

[0088] The row logic activation component 615 may activate the row logic circuitry coupled to the memory array in response to receiving the activate command. In some instances, the row logic activation component 615 may deactivate the row logic circuitry in response to receiving the precharge command. In some instances, the row logic circuitry activates in response to receiving the activate command and the second activate command. In some cases, the row logic circuitry activates based on a delay relative to an edge of a clock signal, where the edge occurs simultaneously with receiving the activate command. In some cases, the edge is a falling edge of the clock signal.

[0089] The bank activation component 620 may activate a bank of the memory array after activating the row logic circuitry in response to receiving an activate command.

[0090] The access component 625 may perform access operations on one or more memory cells within a memory bank after activating the memory bank and row logic circuitry.

[0091] In some examples, the memory array operation component 630 may operate the memory array in a standby mode prior to receiving an activate command, wherein the row logic circuitry is deactivated while the memory array is in the standby mode, and wherein the row logic circuitry is deactivated when the memory device receives the activate command.

[0092] In some examples, the memory array operation component 630 may operate the memory array in a power down mode prior to receiving an activate command, wherein the row logic circuitry is deactivated while the memory array is in the power down mode, and wherein the row logic circuitry is deactivated when the memory device receives the activate command.

[0093] Figure 7 A block diagram 700 is shown of a memory device 705 that supports command-triggered power gating for a memory device according to examples disclosed herein. The memory device 705 may be a reference Figures 1 to 5B Memory device 705 may include a command receiver 710, an ECC activation component 715, an access component 720, a bank activation component 725, a data communication component 730, an ECC component 735, and an internal signaling receiver 740. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0094] The command receiver 710 may receive an activate command at a memory device including a memory array. In some examples, the command receiver 710 may receive an access command at the memory device after receiving the activate command. The access command may be a write command or a read command. In some examples, the command receiver 710 may receive a precharge command at the memory device.

[0095] The ECC activation component 715 may activate an error correction code circuitry coupled to the memory array in response to receiving an access command. In some examples, the ECC activation component 715 may deactivate the error correction code circuitry in response to receiving a precharge command. In some cases, the error correction code circuitry is activated based on a delay relative to an edge of a clock signal, and wherein the edge occurs simultaneously with receiving the access command. In some cases, the edge is a falling edge of the clock signal.

[0096] The access component 720 may access one or more memory cells within a memory bank of the memory array based on activating the error correction code circuitry. In some examples, the access component 720 may store a set of data at one or more additional memory cells of the memory array. In some examples, the access component 720 may retrieve a first set of data associated with a read command from the one or more additional memory cells of the memory array. In some examples, the access component 720 may retrieve an error correction code for the first set of data from the memory array, wherein accessing the one or more memory cells involves retrieving the error correction code from the one or more memory cells.

[0097] The bank activation component 725 can activate a bank of the memory array in response to receiving an activate command and prior to receiving an access command.

[0098] The data communication component 730 can receive a set of data associated with the write command. In some examples, the data communication component 730 can transmit a second set of data (eg, generated by the ECC component 735).

[0099] The ECC component 735 may generate an error correction code for the set of data by an error correction code circuit system, wherein accessing the one or more memory cells includes storing the error correction code at the one or more memory cells. In some examples, the ECC component 735 may use the error correction code to perform an error correction procedure on the first set of data based on the retrieved error correction code to generate a second set of data.

[0100] Internal signaling receiver 740 may receive internal signaling corresponding to an access command at the error correction code circuitry after activating the error correction code circuitry and before accessing one or more memory cells within a memory bank of the memory array. In some cases, the internal signaling includes column redundancy signaling.

[0101] In some examples, the memory devices described herein may include any combination of one or more components of memory device 605 and one or more components of memory device 705 .

[0102] Figure 8 A flowchart illustrating one or more methods 800 for supporting command-triggered power gating for a memory device according to examples disclosed herein is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 800 may be implemented by reference to Figure 6 The memory device described herein performs. In some examples, a memory controller may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory controller may use dedicated hardware to cause the memory device to perform aspects of the described functions.

[0103] At 805, the memory device may receive an activation command. The memory device may include a memory array. The operations of 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be described with reference to Figure 6 Describes the commands the receiver executes.

[0104] At 810, the memory device may activate row logic circuitry coupled to the memory array in response to receiving an activate command. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be described with reference to Figure 6 The line that describes the logic that activates the component execution.

[0105] At 815, the memory device may activate the memory bank of the memory array after activating the row logic circuitry in response to receiving the activation command. The operations of 815 may be performed according to the methods described herein. In some examples, aspects of the operations of 815 may be described with reference to Figure 6 The described storage bank activation component performs.

[0106] At 820, the memory device may perform access operations on one or more memory cells within the memory bank after activating the memory bank and row logic circuitry. The operations of 820 may be performed according to the methods described herein. In some examples, aspects of the operations of 820 may be described with reference to Figure 6 Describes the access component implementation.

[0107] In some examples, an apparatus described herein may perform one or several methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an activate command at a memory device including a memory array; activating row logic circuitry coupled to the memory array in response to receiving the activate command; activating a memory bank of the memory array after activating the row logic circuitry in response to receiving the activate command; and performing an access operation on one or more memory cells within the memory bank after activating the memory bank and the row logic circuitry.

[0108] In some examples of the method 800 and apparatus described herein, the row logic circuitry may be activated based on a delay relative to an edge of a clock signal, where the edge may occur simultaneously with receiving an activate command.

[0109] In some examples of the method 800 and apparatus described herein, the edge can be a falling edge of a clock signal.

[0110] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for receiving a second activation command prior to the activation command, wherein the row logic circuitry may activate in response to receiving the activation command and the second activation command.

[0111] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for receiving a precharge command at a memory device and deactivating the row logic circuitry in response to receiving the precharge command.

[0112] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for operating a memory array in a standby mode prior to receiving an activate command, wherein the row logic circuitry may be deactivated while the memory array is in the standby mode, and wherein the row logic circuitry may be deactivated when the memory device receives the activate command.

[0113] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for operating a memory array in a power-off mode prior to receiving an activate command, wherein the row logic circuitry may be deactivated while the memory array is in the power-off mode, and wherein the row logic circuitry may be deactivated when the memory device receives the activate command.

[0114] Fig. 9 A flowchart illustrating one or more methods 900 for supporting command-triggered power gating for a memory device according to examples disclosed herein is shown. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by reference to Figure 7 The memory device described herein performs. In some examples, a memory controller may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory controller may use dedicated hardware to cause the memory device to perform aspects of the described functions.

[0115] At 905, the memory device may receive an activation command. The memory device may include a memory array. The operations of 905 may be performed according to the methods described herein. In some examples, aspects of the operations of 905 may be described with reference to Figure 7 Describes the commands the receiver executes.

[0116] At 910, the memory device may receive an access command after receiving the activate command. The operations of 910 may be performed according to the methods described herein. In some examples, aspects of the operations of 910 may be described with reference to Figure 7 Describes the commands the receiver executes.

[0117] At 915, the memory device may activate an error correction code circuit system coupled to the memory array in response to receiving the access command. The operations of 915 may be performed according to the methods described herein. In some examples, aspects of the operations of 915 may be described with reference to Figure 7 Describes the ECC activation component implementation.

[0118] At 920, the memory device may access one or more memory cells within a memory bank of the memory array based on activating the error correction code circuitry. The operations of 920 may be performed according to the methods described herein. In some examples, aspects of the operations of 920 may be described with reference to Figure 7 Describes the access component implementation.

[0119] In some examples, an apparatus described herein may perform one or several methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an activate command at a memory device including a memory array; receiving an access command at the memory device after receiving the activate command; activating error correction code circuitry coupled to the memory array in response to receiving the access command; and accessing one or more memory cells within a memory bank of the memory array based on activating the error correction code circuitry.

[0120] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for activating a bank of a memory array in response to receiving an activate command and prior to receiving an access command.

[0121] In some examples of the method 900 and apparatus described herein, the access command may be a write command, and the apparatus may include operations, features, components, or instructions for: receiving a set of data associated with a write command; generating, by an error correction code circuit system, an error correction code for the set of data, wherein accessing one or more memory cells includes storing the error correction code at the one or more memory cells; and storing the set of data at one or more additional memory cells of a memory array.

[0122] In some examples of the method 900 and apparatus described herein, the access command may be a read command, and the apparatus may include operations, features, components, or instructions for: retrieving a first set of data associated with the read command from one or more additional memory cells of a memory array; retrieving an error correction code for the first set of data from the memory array, wherein accessing the one or more memory cells may include operations, features, components, or instructions for retrieving the error correction code from the one or more memory cells; performing an error correction procedure on the first set of data based on the retrieved error correction code using the error correction code to generate a second set of data; and transmitting the second set of data.

[0123] In some examples of methods 900 and apparatus described herein, the error correction code circuitry may be activated based on a delay relative to an edge of a clock signal, and the edge may occur simultaneously with receiving an access command. In some examples of methods 900 and apparatus described herein, the edge may be a falling edge of the clock signal.

[0124] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for receiving internal signaling corresponding to an access command at the error correction code circuitry after activating the error correction code circuitry and before accessing one or more memory cells within a memory bank of the memory array.

[0125] In some examples of the method 900 and apparatus described herein, the internal signaling may be or include column redundancy signaling.

[0126] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for receiving a precharge command at a memory device and deactivating the error correction code circuitry in response to receiving the precharge command.

[0127] It should be noted that the methods described herein are possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0128] An apparatus is described. The apparatus may include a die. The die may include: row logic circuitry; a memory bank of a memory array, wherein the memory bank may be coupled to the row logic circuitry; and a controller coupled to the row logic circuitry and the memory bank. The controller may be configured to: receive an activate command at the die; activate the row logic circuitry in response to receiving the activate command; activate the memory bank after activating the row logic circuitry in response to receiving the activate command; and perform an access operation on one or more memory cells within the memory bank after activating the memory bank and using the row logic circuitry.

[0129] In some examples, the die may further include a first set of power supply nodes configured to have a first voltage differential and a second set of power supply nodes configured to have a second voltage differential and coupled with the row logic circuitry. The second voltage differential may be less than the first voltage differential. The controller may further be configured to activate the row logic circuitry based at least in part on coupling one or more of the first set of power supply nodes with one or more of the second set of power supply nodes.

[0130] In some examples, the row logic circuitry may include control logic coupled to one or more sense amplifiers of the memory bank and may be configured to activate the one or more sense amplifiers. In some examples, the row logic circuitry may include one or more word line drivers coupled to one or more word lines of the memory bank and may be configured to activate the one or more word lines.

[0131] In some examples, the controller may be further configured to receive a precharge command at the die and deactivate the row logic circuitry in response to receiving the precharge command.

[0132] An apparatus is described. The apparatus may include a die, and the die may include: error correction code circuitry; a memory bank of a memory array, wherein the memory bank may be coupled to the error correction code circuitry; and a controller coupled to the error correction code circuitry and the memory bank. The controller may be configured to: receive an activate command at the die; receive an access command at the die after receiving the activate command; activate the error correction code circuitry in response to receiving the access command; and access one or more memory cells within the memory bank based on activating the error correction code circuitry.

[0133] In some examples, the die further may include column logic circuitry coupled to the memory bank and a buffer coupled to the memory bank. The controller may be further configured to activate the column logic circuitry, the buffer, or both after receiving the activate command and before activating the error correction code circuitry.

[0134] In some examples, the die may include a first set of power supply nodes configured to have a first voltage differential and a second set of power supply nodes configured to have a second voltage differential and coupled with the error correction code circuitry. The second voltage differential may be less than the first voltage differential. The controller may be further configured to activate the error correction code circuitry based on coupling one or more of the first set of power supply nodes with one or more of the second set of power supply nodes.

[0135] In some examples, the controller may be further configured to receive a precharge command at the die and deactivate the error correction code circuitry in response to receiving the precharge command.

[0136] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0137] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components may be considered to be in electronic communication (or conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication (or conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0138] The term "coupling" refers to a condition that transitions from an open-circuit relationship between components (where signals cannot currently be transmitted between components through conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components through conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through conductive paths that previously did not allow signals to flow.

[0139] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components from one another, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0140] As used herein, the term "substantially" means that the modified property (such as a verb or adjective modified by the term "substantially") may not be absolute, but is close enough to achieve the advantage of the property.

[0141] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or any other doping method.

[0142] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0143] The [Detailed Description] described herein in conjunction with the accompanying drawings describes example configurations and does not represent every example that may be implemented or within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration" rather than "preferred" or "better than other examples". The [Detailed Description] includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0144] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, without regard to the second reference label.

[0145] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0146] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0147] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function may be stored on a computer-readable medium as one or more instructions or codes or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. In addition, as used herein (included in the claims), the "or" used in a list of items (e.g., a list of items starting with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on..." should not be understood as referring to a set of closed conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same manner as the phrase "based at least in part on..."

[0148] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. A person skilled in the art will appreciate the various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operation, comprising: receiving an activate command at a memory device including a memory array; activating row logic circuitry coupled to the memory array in response to receiving the activate command; activating a bank of the memory array after activating the row logic circuitry in response to receiving the activate command, the row logic circuitry activating based at least in part on a delay relative to an edge of a clock signal; and An access operation is performed on one or more memory cells within the memory bank after activating the memory bank and the row logic circuitry. The method of claim 1 , wherein the edge occurs simultaneously with receiving the activation command. The method of claim 2 , wherein the edge is a falling edge of the clock signal.

4. The method according to claim 3, further comprising: A second activate command is received prior to the activate command, wherein the row logic circuitry activates in response to receiving the activate command and the second activate command.

5. A method for memory operation, comprising: receiving an activate command at a memory device including a memory array; activating row logic circuitry coupled to the memory array in response to receiving the activate command; activating a memory bank of the memory array after activating the row logic circuitry in response to receiving the activate command; performing an access operation on one or more memory cells within the memory bank after activating the memory bank and the row logic circuitry; receiving a precharge command at the memory device; and The row logic circuitry is deactivated in response to receiving the precharge command.

6. A method for memory operation, comprising: operating the memory array in a standby mode prior to receiving an activate command, wherein the row logic circuitry is deactivated while the memory array is in said standby mode; receiving the activate command at a memory device including the memory array, wherein the row logic circuitry is deactivated when the memory device receives the activate command; activating the row logic circuitry coupled to the memory array in response to receiving the activate command; activating a memory bank of the memory array after activating the row logic circuitry in response to receiving the activate command; and An access operation is performed on one or more memory cells within the memory bank after activating the memory bank and the row logic circuitry.

7. A method for memory operation, comprising: operating a memory array in a power-down mode prior to receiving an activate command, wherein row logic circuitry is deactivated while the memory array is in the power-down mode; receiving the activate command at a memory device including the memory array, wherein the row logic circuitry is deactivated when the memory device receives the activate command; activating the row logic circuitry coupled to the memory array in response to receiving the activate command; activating a memory bank of the memory array after activating the row logic circuitry in response to receiving the activate command; and An access operation is performed on one or more memory cells within the memory bank after activating the memory bank and the row logic circuitry.

8. A method for memory operation, comprising: receiving an activate command at a memory device including a memory array; receiving an access command at the memory device after receiving the activate command; activating error correction code circuitry coupled to the memory array in response to receiving the access command; and One or more memory cells within a memory bank of the memory array are accessed based at least in part on activating the error correction code circuitry.

9. The method according to claim 8, further comprising: The memory bank of the memory array is activated in response to receiving the activate command and before receiving the access command.

10. The method according to claim 8, wherein the access command comprises a write command, the method further comprising: receiving a set of data associated with the write command; generating, by the error correction code circuitry, an error correction code for the set of data, wherein accessing the one or more memory cells comprises storing the error correction code at the one or more memory cells; and The set of data is stored at one or more additional memory cells of the memory array.

11. The method of claim 8, wherein the access command comprises a read command, the method further comprising: retrieving a first set of data associated with the read command from one or more additional memory cells of the memory array; retrieving an error correction code for the first set of data from the memory array, wherein accessing the one or more memory cells comprises retrieving the error correction code from the one or more memory cells; using the error correction code to perform an error correction process on the first set of data to generate a second set of data; and The second set of data is transmitted.

12. The method of claim 8, wherein the error correction code circuitry is activated based at least in part on a delay relative to an edge of a clock signal, and wherein the edge occurs simultaneously with receiving the access command. The method of claim 12 , wherein the edge is a falling edge of the clock signal.

14. The method according to claim 8, further comprising: After activating the error correction code circuitry and before accessing the one or more memory cells within the memory bank of the memory array, internal signaling corresponding to the access command is received at the error correction code circuitry. The method of claim 14 , wherein the internal signaling comprises column redundancy signaling.

16. The method according to claim 8, further comprising: receiving a precharge command at the memory device; and The error correction code circuitry is deactivated in response to receiving the precharge command.

17. A memory device comprising: A bare die comprising: Line logic circuit system; a memory bank of a memory array, the memory bank coupled to the row logic circuitry; a first set of power supply nodes configured to have a first voltage differential; a second set of power supply nodes configured to have a second voltage differential and coupled to the row logic circuitry, wherein the second voltage differential is less than the first voltage differential; and a controller coupled to the row logic circuitry and the memory bank, wherein the controller is configured to: receiving an activate command at the die; activating the row logic circuitry in response to receiving the activate command; in response to receiving the activate command, activating the memory bank after activating the row logic circuitry based at least in part on coupling one or more of the first set of power supply nodes with one or more of the second set of power supply nodes; and After the memory bank is activated and access operations are performed on one or more memory cells within the memory bank using the row logic circuitry.

18. The memory device of claim 17, wherein the row logic circuitry comprises control logic coupled to one or more sense amplifiers of the memory bank and configured to activate the one or more sense amplifiers.

19. The memory device of claim 17, wherein the row logic circuitry comprises one or more word line drivers coupled to one or more word lines of the memory bank and configured to activate the one or more word lines.

20. A memory device comprising: A bare die comprising: Line logic circuit system; a memory bank of a memory array, the memory bank coupled to the row logic circuitry; and a controller coupled to the row logic circuitry and the memory bank, wherein the controller is configured to: receiving an activate command at the die; activating the row logic circuitry in response to receiving the activate command; activating the memory bank after activating the row logic circuitry in response to receiving the activate command; performing an access operation on one or more memory cells within the memory bank using the row logic circuitry after activating the memory bank; receiving a precharge command at the die; and The row logic circuitry is deactivated in response to receiving the precharge command.

21. A memory device comprising: A bare die comprising: Error correction code circuit system; a memory bank of a memory array, the memory bank coupled to the error correction code circuitry; and a controller coupled to the ECC circuitry and the memory bank, wherein the controller is configured to: receiving an activate command at the die; receiving an access command at the die after receiving the activate command; activating the error correction code circuitry in response to receiving the access command; and One or more memory cells within the memory bank are accessed based at least in part on activating the error correction code circuitry.

22. The memory device of claim 21 , wherein the die further comprises: column logic circuitry coupled to the memory bank; and a buffer coupled to the memory bank, wherein the controller is further configured to: The column logic circuitry, the buffer, or both are activated after receiving the activate command and before activating the error correction code circuitry.

23. The memory device of claim 21 , wherein the die further comprises: a first set of power supply nodes configured to have a first voltage differential; and a second set of power supply nodes configured to have a second voltage differential and coupled to the error correction code circuitry, wherein the second voltage differential is less than the first voltage differential, and wherein the controller is further configured to: The error correction code circuitry is activated based at least in part on coupling one or more of the first set of power supply nodes with one or more of the second set of power supply nodes.

24. The memory device of claim 21, wherein the controller is further configured to: receiving a precharge command at the die; and The error correction code circuitry is deactivated in response to receiving the precharge command.

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