Memory device

Abstract

The present invention discloses a memory device, including a memory array and a purification unit. The memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells. The purification unit applies a first read voltage and a second read voltage to find at least one first target memory cell and at least one second target memory cell to be purified from the target memory page, applies a first programming voltage to the at least one first target memory cell to change the logic state of the at least one first target memory cell to a logic state of a higher threshold voltage, and applies a second programming voltage to the at least one second target memory cell to change the logic state of the at least one second target memory cell to a logic state of a higher threshold voltage.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a memory data management method and a memory device using the same. Background Art

[0002] In recent years, flash memory has gradually replaced traditional hard disks as storage units in consumer electronic products. Compared with hard disks, flash memory has the advantages of good performance, low power consumption, shock resistance and small size.

[0003] However, flash memory is different from traditional hard disks. Flash memory has the feature of out-of-place update. Before the erase operation, the data page with written data cannot be rewritten. When the user wants to update the data on the data page with written data in the flash memory, a new blank data page must be found in the flash memory, the updated data must be written to the new blank data page, and the logical address of the original data page with written data must be remapped to the new blank data page to complete the data update.

[0004] That is to say, in the flash memory, when the stored data needs to be updated, the file system will write the new copy to a new data page of the flash memory block and re-point the file pointer. Due to the above characteristics of the flash memory, one or more data copies will be left in the flash memory after each update of the stored data of the flash memory.

[0005] The erase command of the flash memory cannot erase a single memory data page that stores these data copies. Therefore, hackers can reconstruct data through these data copies left in the memory, causing data security risks. Furthermore, if the memory block of the memory data page that stores these data copies is erased after garbage collection, the life cycle of the memory may be shortened and the processing performance of the memory may be affected. Therefore, how to effectively clean up data after data update is one of the current directions of the industry. Summary of the invention

[0006] The present invention relates to a memory data management method and a memory device using the same. By applying voltage to change the logical state of a memory cell in a memory block, the data content stored in the memory cell is changed, so that the original written data cannot be correctly read, thereby achieving the purpose of "deleting" the data. In addition, the present invention can improve the data security of the memory, prevent hackers from obtaining the original written data and rebuilding the data, and can also reduce the number of times the memory block is erased, thereby improving the life cycle of the memory and increasing the efficiency of the memory. In addition, the present invention can reduce the applied read voltage when reading a data page, thereby improving the memory performance.

[0007] According to one aspect of the present invention, a memory data management method is proposed. The memory includes a plurality of memory pages, each memory page includes a plurality of storage cells, each of the storage cells includes a first storage located at a high storage page, a second storage located at a middle storage page, and a third storage located at a low storage page, and these storage cells include a first logic state, a second logic state, a third logic state, a fourth logic state, a fifth logic state, a sixth logic state, a seventh logic state, and an eighth logic state with threshold voltages from low to high. The data management method includes the following steps. A data update instruction corresponding to a logical address is received, and before receiving the data update instruction, the logical address is mapped to a physical address of one of the target memory pages. A first read voltage and a second read voltage are applied to find at least one first target memory cell and at least one second target memory cell to be purified from the target memory page; a first programming voltage is applied to the at least one first target memory cell to change the logic state of the at least one first target memory cell to one of the fifth, the sixth, the seventh and the eighth logic states, and a second programming voltage is applied to the at least one second target memory cell to change the logic state of the at least one second target memory cell to one of the fifth, the sixth, the seventh and the eighth logic states, wherein the first programming voltage is different from the second programming voltage.

[0008] According to another aspect of the present invention, a memory device is provided. The memory device includes a memory array and a purification unit. The memory array includes a plurality of memory pages, each of which includes a plurality of memory cells, each of which includes a first memory cell located at a high-order memory page, a second memory cell located at a middle-order memory page, and a third memory cell located at a low-order memory page, and these memory cells include a first logic state, a second logic state, a third logic state, a fourth logic state, a fifth logic state, a sixth logic state, a seventh logic state, and an eighth logic state with threshold voltages from low to high. The purification unit receives a data update instruction corresponding to a logical address, and before receiving the data update instruction, the logical address corresponds to a physical address of one of the target memory pages. The purification unit applies a first read voltage and a second read voltage to find at least one first target memory cell and at least one second target memory cell to be purified from the target memory page, applies a first programming voltage to the at least one first target memory cell to change the logic state of the at least one first target memory cell to one of the fifth, sixth, seventh and eighth logic states, and applies a second programming voltage to the at least one second target memory cell to change the logic state of the at least one second target memory cell to one of the fifth, sixth, seventh and eighth logic states, wherein the first programming voltage is different from the second programming voltage.

[0009] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a memory system according to an embodiment of the present invention is shown;

[0011] Figure 2 A flow chart of a memory data management method according to an embodiment of the present invention is shown;

[0012] Figures 3 to 9 Schematic diagrams of applying a cleanup voltage to a triple-level cell (TLC) according to an embodiment of the present invention are respectively shown;

[0013] Figure 10A-10C to Figures 11A-11C Schematic diagrams of applying a cleanup voltage to a triple-level cell (TLC) according to an embodiment of the present invention are respectively shown.

[0014]

Explanation of symbols

[0015] 10: Memory system

[0016] 102: Main controller

[0017] 104: Purification unit

[0018] 106: Control unit

[0019] 108: Memory Array

[0020] 110, 110′, 120, 120′, 130, 130′, 140, 140′, 150, 150′, 160, 160′, 170, 170′: storage block

[0021] 111, 111′, 121, 121′, 131, 131′, 141, 141′, 151, 151′, 161, 161′, 171, 171′ 181, 181′, 191, 191′: memory voltage distribution

[0022] S202~S214:Process steps

[0023] P1~P15:Data page

[0024] X: Purified data page

[0025] V R1 , V R2 , V R3 , V R4 , V R5 , V R6 , V R7 : Read voltage

[0026] V t :Voltage DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0028] Various embodiments are provided below for detailed description. However, the embodiments are only used as examples and do not limit the scope of the invention. In addition, some components are omitted in the drawings in the embodiments to clearly show the technical features of the invention. The same reference numerals will be used to represent the same or similar components in all drawings.

[0029] Please also refer to Figure 1 and Figure 2 . Figure 1 FIG. 1 is a schematic diagram of a memory system 10 according to an embodiment of the present invention. Figure 2A flow chart of a memory data management method according to an embodiment of the present invention is shown. The memory system 10 includes a host machine 102, a sanitizer unit 104, a control unit 106, and a memory array 108. The host machine 102 can be used to send read, write (program), erase or data update instructions to the control unit 106. The sanitizer unit 104 is responsible for managing the data management method of the present invention. The memory array 108 is, for example, a NAND flash memory or any form of flash memory or storage device. The memory array 108 can include a plurality of storage blocks, each storage block includes a plurality of memory pages (data pages), and each memory page includes a plurality of storage cells. The host machine 102, the sanitizer unit 104, and the control unit 106 can be implemented, for example, by using a chip, a circuit block in a chip, a firmware circuit, a circuit board containing a plurality of electronic components and wires, or a storage medium storing a plurality of array program codes, or can be implemented by executing corresponding software, firmware, or programs in electronic devices such as computer systems, embedded systems, handheld devices, and servers.

[0030] In step S202, the control unit 106 determines whether the command sent by the main controller 102 is to read data, write new data, or update written data. When the command sent by the main controller 102 is to read data, in step S204, the control unit 106 receives the data read command, and in step S206, the control unit 106 reads the data stored in the memory array 108.

[0031] When the instruction sent by the main controller 102 is to write new data, in step S208, the control unit 106 receives the data write instruction, and in step S210, the control unit 106 programs the memory array 108 to write (program) the new data to be written into the memory array 108. The above-mentioned new data refers to the data that is not stored in the memory array 108, and the flash translation layer (FTL) cannot find the storage block corresponding to the data in the memory array 108. That is, there is no copy of the data stored in the memory array 108.

[0032] When the instruction sent by the main controller 102 is to update the written data, in step S212, the control unit 106 receives a data update instruction corresponding to a logical address, and the cleaning unit 104 also receives a data update instruction corresponding to the logical address to perform data update. Since the flash translation layer records the correspondence between a physical address and a logical address of the memory page where the written data is located, before receiving the data update instruction, the logical address is mapped to a physical address. In step S214, the memory page where the written data is located is regarded as the target memory page, and the cleaning unit 104 applies a cleaning voltage to the target memory page to the memory array 108 to change the logical state of a target memory cell in the target memory page. By applying the cleaning voltage to change the logical state of the memory cell in the target memory page, the memory cell is reprogrammed, and the data of the memory cell is changed to achieve an effect similar to deleting data. In this way, hackers cannot reconstruct data through data replication. In the present invention, the term "cleaning" means changing the logical state of the memory cell in the target memory page and reprogramming the target memory cell to change the data in the target memory cell, thereby achieving an effect similar to "deleting" data.

[0033] Please refer to Figures 3 to 9 . Figures 3 to 9 Schematic diagrams of applying a cleanup voltage to a triple-level cell (MLC) according to an embodiment of the present invention are respectively shown. Figures 3 to 9 The application of the purge voltage is further described to change the logic state of at least one memory cell in a target memory page.

[0034] Figures 3 to 9The storage blocks 110, 120, 130, 140, 150, 160, and 170 in the embodiment have the same configuration. Each of the above storage blocks includes a plurality of word lines, and a word line may include a first data page, a second data page, and a third data page. A data page may include more than one storage unit. The storage unit in each storage block is a three-level storage unit, including a first storage bit, a second storage bit, and a third storage bit, and can store three bits of data. Storing three data pages of data in a word line is equivalent to storing 3 bits of data in a storage unit on the same word line. The above three-level storage unit includes a first logic state, a second logic state, a third logic state, a fourth logic state, a fifth logic state, a sixth logic state, a seventh logic state, and an eighth logic state, whose threshold voltages are from low to high, that is, the threshold voltage of the first logic state is less than the threshold voltage of the second logic state, the threshold voltage of the second logic state is less than the threshold voltage of the third logic state, and so on. For example, the first logic state is "111", the second logic state is "110", the third logic state is "100", the fourth logic state is "000", the fifth logic state is "010", the sixth logic state is "011", the seventh logic state is "001", and the eighth logic state is "101". For example, the first data page is a high-order data page, the second data page is a middle-order data page, and the third data page is a low-order data page. The first word line of the memory block includes a high data page P1, a middle data page P3 and a low data page P6, the second word line includes a high data page P2, a middle data page P5 and a low data page P9, the third word line includes a high data page P4, a middle data page P8 and a low data page P12, the fourth word line includes a high data page P7, a middle data page P11 and a low data page P14, and the fifth word line includes a high data page P10, a middle data page P13 and a low data page P15. It should be understood that, in order to simplify the drawings, the memory blocks 110, 120, 130, 140, 150, 160, 170 only illustrate part of the data pages.

[0035] Please refer to Figure 3 In the present embodiment, the storage block 110 is a storage block before "purification", and the storage block 110' is a storage block after the storage block 110 is "purified". The upper data page P1, the middle data page P3, the lower data page P6, the upper data page P2, the middle data page P5, the lower data page P9, the upper data page P4, the middle data page P8 and the lower data page P12 of the storage block 110 have been written with data, while the upper data page P7, the middle data page P11, the lower data page P14, the upper data page P10, the middle data page P13 and the lower data page P15 have not been written with data.

[0036] Figure 3The memory cell voltage distribution 111 indicates that the high data page P2, the middle data page P5 and the low data page P9 of the second word line have been written with data. At this time, if you want to "clean" the low data page P9 but keep the data of the high data page P2 and the middle data P5, the cleaning unit 104 will apply the second read voltage V R2 , the third reading voltage V R3 and the fourth read voltage V R4 , find out the first target memory cell at the third logic state ("100") and the second target memory cell at the fourth logic state ("000"). Subsequently, a programming trigger is applied, and a first programming voltage is applied in an incremental step pulse programming manner to change the logic state of the first target memory cell from the third logic state ("100") to the eighth logic state ("10X") of a higher threshold voltage, and a second programming voltage is applied in an incremental step pulse programming manner to change the logic state of the second target memory cell from the fourth logic state ("000") to the seventh logic state ("00X") of a higher threshold voltage. Because the first target memory cell is applied with a programming trigger, the logic state of the first target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fifth read voltage V R5 , the data of the storage cell of the lower data page P9 has been changed from 0 to 1, and the fifth read voltage V R5 The data of the memory cell of the lower data page is correctly read. In addition, because the second target memory cell is subjected to programming trigger, the logic state of the second target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fifth read voltage V R5 , the data of the storage cell of the lower data page P9 has been changed from 0 to 1, and the fifth read voltage V R5 The data of the storage unit of the lower data page is correctly read. R5 Greater than the second read voltage V R2 and the fourth read voltage V R4 .

[0037] However, for the upper data page P2 and the middle data page P5, the data of the memory cells of the upper data page P2 and the middle data page P5 are still 1, and the data of the memory cells of the upper data page P2 and the middle data page P5 are not changed, and the voltage V can still be read. R3 And read the voltage V R7 Correctly read the data of the memory cell of the high data page P2, and use the read voltage V R6 The data of the storage unit of the middle data page P5 is correctly read. In this way, the written data of the lower data page P9 can be "deleted" while the written data of the upper data page P2 and the middle data page P5 are retained.

[0038] Figure 3 The memory cell voltage distribution 111′ represents the voltage distribution of the memory cells of the high-order data page P2 and the middle-order data page P5 of the second word line after the low-order data page P9 of the second word line is “cleaned” and the written data of the high-order data page P2 and the middle-order data page P5 are retained. The memory block 110′ represents the memory block where the low-order data page P9 is “cleaned” and the written data of the high-order data page P2 and the middle-order data page P5 are retained. The low-order data page P9 is marked with an X, indicating that its data can no longer be correctly read, which is equivalent to the data originally written in the low-order data page P9 being deleted.

[0039] In this embodiment, after “cleaning” the lower data page P9, only the read voltage V R6 , the data of the middle data page P5 can be read, and the second read voltage V R2 , the fourth reading voltage V R4 and the sixth read voltage V R6 Compared with the conventional method of reading the data of the middle data page P5, the present invention can improve the reading performance of the memory. R6 Greater than the read voltage V R4 .

[0040] Please refer to Figure 4 In the present embodiment, the storage block 120 is a storage block before "purification", and the storage block 120' is a storage block after the storage block 120 is "purified". The high data page P1, the middle data page P3, the low data page P6, the high data page P2, the middle data page P5, the low data page P9, the high data page P4, the middle data page P8, and the low data page P12 of the storage block 120 have been written with data, while the high data page P7, the middle data page P11, the low data page P14, the high data page P10, the middle data page P13, and the low data page P15 have not been written with data.

[0041] Figure 4 The memory cell voltage distribution 121 indicates that the high data page P2, the middle data page P5 and the low data page P9 of the second word line have been written with data. At this time, if you want to "clean" the middle data page P5 but keep the data of the high data page P2 and the low data page P9, the cleaning unit 104 applies the first read voltage V R1 , the third reading voltage V R3 , the fourth reading voltage V R4, find the first target memory cell at the first logic state ("111") and the second target memory cell at the fourth logic state ("000"). Subsequently, a programming trigger is applied, and a first programming voltage is applied in an incremental step pulse programming manner to change the logic state of the first target memory cell from the first logic state ("111") to the eighth logic state ("1X1") with a higher threshold voltage, and a second programming voltage is applied to change the logic state of the second target memory cell from the fourth logic state ("000") to the fifth logic state ("0X0") with a higher threshold voltage. Because the first target memory cell is applied with a programming trigger, the logic state of the first target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the second read voltage V R2 , the data of the storage cell of the middle data page P5 has been changed from 1 to 0, and the second read voltage V R2 The data of the memory cell of the middle data page is correctly read out. In addition, because the second target memory cell is subjected to programming trigger, the logic state of the second target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fourth read voltage V R4 , the data of the storage cell of the middle data page P5 has been changed from 0 to 1, and the fourth read voltage V R4 The data of the storage unit of the middle data page is correctly read. R4 Greater than the second read voltage V R2 .

[0042] However, for the upper data page P2 and the lower data page P9, the data of the storage cells of the upper data page P2 and the lower data page P9 are still 1, and the data of the storage cells of the upper data page P2 and the lower data page P9 are not changed, and the voltage V can still be read. R3 And read the voltage V R7 Correctly read the data of the memory cell of the high data page P2, and use the read voltage V R5 The data of the storage unit of the lower data page P9 is correctly read. In this way, the written data of the middle data page P5 can be "deleted" while the written data of the upper data page P2 is retained.

[0043] Figure 4The memory cell voltage distribution 121′ represents the voltage distribution of the memory cells of the upper data page P2 and the lower data page P9 of the second word line after the middle data page P5 of the second word line is “cleaned” and the written data of the upper data page P2 and the lower data page P9 are retained. The memory block 120′ represents the memory block where the middle data page P5 is “cleaned” and the written data of the upper data page P2 and the lower data page P9 are retained. The middle data page P5 is marked with an X, indicating that its data can no longer be correctly read, which is equivalent to the data originally written in the middle data page P5 being deleted.

[0044] In this embodiment, after “cleaning” the middle data page P5, only the read voltage V R5 , the data of the lower data page P9 can be read, and the first read voltage V R1 and the fifth read voltage V R5 Compared with the conventional method of reading the data of the lower data page P9, the present invention can improve the reading performance of the memory. R5 Greater than the first read voltage V R1 .

[0045] Please refer to Figure 5 In the present embodiment, the storage block 130 is a storage block before "purification", and the storage block 130' is a storage block after the storage block 130 is "purified". The high data page P1, the middle data page P3, the low data page P6, the high data page P2, the middle data page P5, the low data page P9, the high data page P4, the middle data page P8 and the low data page P12 of the storage block 130 have been written with data, while the high data page P7, the middle data page P11, the low data page P14, the high data page P10, the middle data page P13 and the low data page P15 have not been written with data.

[0046] Figure 5 The memory cell voltage distribution 131 indicates that the high data page P2, the middle data page P5 and the low data page P9 of the second word line have been written with data. At this time, if you want to "clean" the high data page P2 but keep the data of the middle data page P5 and the low data page P9, the cleaning unit 104 will apply the first read voltage V R1 and the second read voltage V R2, find out the first target memory cell at the first logic state ("111") and the second target memory cell at the second logic state ("110"). Then, apply a programming trigger, apply a first programming voltage in the form of incremental step pulse programming, so that the logic state of the first target memory cell changes from the first logic state ("111") to the sixth logic state ("X11") of the higher threshold voltage, and apply a second programming voltage, so that the logic state of the second target memory cell changes from the second logic state ("110") to the fifth logic state ("X10") of the higher threshold voltage. Because the first target memory cell is applied with a programming trigger, the logic state of the first target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the third read voltage V R3 , the data of the memory cell of the upper data page P2 has been changed from 1 to 0, and the third read voltage V R3 The data of the memory cell of the high data page is correctly read. In addition, because the second target memory cell is subjected to programming trigger, the logic state of the second target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the third read voltage V R3 , the data of the memory cell of the upper data page P2 has been changed from 1 to 0, and the third read voltage V R3 The data of the storage unit of the high-order data page is correctly read out.

[0047] However, for the middle data page P5 and the lower data page P9, the data of the storage cells of the middle data page P5 and the lower data page P9 are still 1, and the data of the storage cells of the middle data page P5 and the lower data page P9 are not changed, and the voltage V can still be read. R4 And read the voltage V R6 Correctly read the data of the memory cell of the middle data page P5, and use the read voltage V R5 The data of the storage unit of the lower data page P9 is correctly read. In this way, the written data of the upper data page P2 can be "deleted" while the written data of the middle data page P5 and the lower data page P9 are retained.

[0048] Figure 5 The memory cell voltage distribution 131′ represents the voltage distribution of the memory cells of the middle data page P5 and the low data page P9 of the second word line after the high data page P2 of the second word line is “purified” and the written data of the middle data page P5 and the low data page P9 are retained. The memory block 130′ represents the memory block where the high data page P2 is “purified” and the written data of the middle data page P5 and the low data page P9 are retained. The high data page P2 is marked with an X, indicating that its data can no longer be correctly read, which is equivalent to the data originally written in the high data page P2 being deleted.

[0049] In this embodiment, after “cleaning” the upper data page P2, only the read voltage V R4 And read the voltage V R6 , the data of the middle data page P5 can be read, and the second read voltage V R2 , the fourth reading voltage V R4 and the sixth read voltage V R6 Compared with the conventional method of reading the data of the middle data page P5, the present invention can improve the reading performance of the memory. At the same time, after "cleaning" the high data page P2, only the reading voltage V R5 , the data of the lower data page P9 can be read, and the first read voltage V R1 and the fifth read voltage V R5 Compared with the conventional method of reading the data of the lower data page P9, the present invention can improve the reading performance of the memory. R6 Greater than the fifth read voltage V R5 , the fifth reading voltage V R5 is greater than the fourth read voltage V R4 .

[0050] Please refer to Figure 6 In the present embodiment, the storage block 140 is a storage block before "purification", and the storage block 140' is a storage block after the storage block 140 is "purified". The high data page P1, the middle data page P3, the low data page P6, the high data page P2, the middle data page P5, the low data page P9, the high data page P4, the middle data page P8 and the low data page P12 of the storage block 140 have been written with data, while the high data page P7, the middle data page P11, the low data page P14, the high data page P10, the middle data page P13 and the low data page P15 have not been written with data.

[0051] Figure 6 The memory cell voltage distribution 141 indicates that the high data page P2, the middle data page P5 and the low data page P9 of the second word line have been written with data. At this time, if you want to "clean" the middle data page P5 and the low data page P9, but keep the data of the high data page P2, the cleaning unit 104 will apply the third read voltage V R3 and the fourth read voltage V R4, find out three first target memory cells at the first logic state ("111"), the second logic state ("110") and the third logic state ("100") and the second target memory cell at the fourth logic state ("000"). Subsequently, a programming trigger is applied, and a first programming voltage is applied in an incremental step pulse programming manner to change the logic states of the three first target memory cells from the first logic state ("111"), the second logic state ("110") and the third logic state ("100") to the eighth logic state ("1XX") of a higher threshold voltage, and a second programming voltage is applied to change the logic state of the second target memory cell from the fourth logic state ("000") to the fifth logic state ("0XX"), the sixth logic state ("0XX") or the seventh logic state ("0XX") of a higher threshold voltage. Because the three first target memory cells are applied with a programming trigger, the logic states of the three first target memory cells are programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the third read voltage V R5 , the data of the storage cell of the lower data page P9 has been changed from 0 to 1, and the first read voltage V R1 and the fifth read voltage V R5 The data of the memory cell of the lower data page is correctly read. In addition, because the second target memory cell is subjected to programming trigger, the logic state of the second target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fourth read voltage V R4 , the data of the storage cell of the middle data page P5 has been changed from 0 to 1, and the fourth read voltage V R4 The data of the storage unit of the middle data page is correctly read. R4 Greater than the first read voltage V R1 .

[0052] However, for the upper data page P2, the data of the memory cell of the upper data page P2 is still 1, the data of the memory cell of the upper data page P2 has not been changed, and the voltage V can still be read. R7 The data of the storage unit of the upper data page P2 is correctly read. In this way, the written data of the middle data page P5 and the lower data page P9 can be "deleted" while the written data of the upper data page P2 is retained.

[0053] Figure 6The memory cell voltage distribution 141′ represents the voltage distribution of the memory cells of the high-order data page P2 of the second word line after the middle data page P5 and the low-order data page P9 of the second word line are “cleaned” and the written data of the high-order data page P2 is retained. The memory block 140′ represents the memory block where the middle data page P5 and the low-order data page P9 are “cleaned” and the written data of the high-order data page P2 is retained. The middle data page P5 and the low-order data page P9 are marked with X, indicating that their data can no longer be correctly read, which is equivalent to the data originally written in the middle data page P5 and the low-order data page P9 has been deleted.

[0054] In this embodiment, after “cleaning” the middle data page P5 and the lower data page P9, only the read voltage V R7 , the data of the upper data page P2 can be read, and the third read voltage V R3 and the seventh read voltage V R7 Compared with the conventional method of reading the data of the high-order data page P2, the present invention can improve the reading performance of the memory. R7 is greater than the third read voltage V R3 .

[0055] Please refer to Figure 7 In the present embodiment, the storage block 150 is a storage block before "purification", and the storage block 150' is a storage block after the storage block 150 is "purified". The high data page P1, the middle data page P3, the low data page P6, the high data page P2, the middle data page P5, the low data page P9, the high data page P4, the middle data page P8 and the low data page P12 of the storage block 150 have been written with data, while the high data page P7, the middle data page P11, the low data page P14, the high data page P10, the middle data page P13 and the low data page P15 have not been written with data.

[0056] Figure 7 The memory cell voltage distribution 151 indicates that the high data page P2, the middle data page P5 and the low data page P9 of the second word line have been written with data. At this time, if you want to "clean" the high data page P2 and the low data page P9, but keep the data of the middle data page P5, the cleaning unit 104 will apply the second read voltage V R2 and the fourth read voltage V R4, find out two first target memory cells at the first logic state ("111") and the second logic state ("110") and two second target memory cells at the third logic state ("100") and the fourth logic state ("000"). Subsequently, a programming trigger is applied, and a first programming voltage is applied in an incremental step pulse programming manner to change the logic states of the two first target memory cells from the first logic state ("111") and the second logic state ("110") to the fifth logic state ("X1X") of a higher threshold voltage, and a programming voltage is applied to change the logic states of the two second target memory cells from the third logic state ("100") and the fourth logic state ("000") to the seventh logic state ("X0X") of a higher threshold voltage. Because the two first target memory cells are applied with programming triggers, the logic states of the two first target memory cells are programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the third read voltage V R3 , the data of the memory cell of the upper data page P2 has been changed from 1 to 0, and the third read voltage V R3 The data of the memory cell of the high data page is correctly read. In addition, because the second target memory cell is subjected to programming trigger, the logic state of the second target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fifth read voltage V R5 , the data of the memory cell of the lower data page P9 has been changed from 0 to 1, and the fifth read voltage V R5 The data of the storage unit of the lower data page is correctly read. R5 is greater than the third read voltage V R3 .

[0057] However, for the middle data page P5, the data of the memory cell of the middle data page P5 is still 1, the data of the memory cell of the middle data page P5 has not been changed, and the voltage V can still be read. R6 The data of the storage unit of the middle data page P5 is correctly read. In this way, the written data of the upper data page P2 and the lower data page P9 can be "deleted" while the written data of the middle data page P5 is retained.

[0058] Figure 7The memory cell voltage distribution 151′ represents the voltage distribution of the memory cell of the middle data page P5 of the second word line after the upper data page P2 and the lower data page P9 of the second word line are “cleaned” and the written data of the middle data page P5 is retained. The memory block 150′ represents the memory block where the upper data page P2 and the lower data page P9 are “cleaned” and the written data of the middle data page P5 is retained. The upper data page P2 and the lower data page P9 are marked with X, indicating that their data can no longer be correctly read, which is equivalent to the data originally written in the upper data page P2 and the lower data page P9 having been deleted.

[0059] In this embodiment, after “cleaning” the upper data page P2 and the lower data page P9, only the read voltage V R6 , the data of the middle data page P5 can be read, and the second read voltage V R2 , the fourth reading voltage V R4 and the sixth read voltage V R6 Compared with the conventional method of reading the data of the middle data page P5, the present invention can improve the reading performance of the memory. R6 Greater than the second read voltage V R2 and the fourth read voltage V R4 .

[0060] Please refer to Figure 8 In the present embodiment, the storage block 160 is a storage block before "purification", and the storage block 160' is a storage block after the storage block 160 is "purified". The high data page P1, the middle data page P3, the low data page P6, the high data page P2, the middle data page P5, the low data page P9, the high data page P4, the middle data page P8 and the low data page P12 of the storage block 160 have been written with data, while the high data page P7, the middle data page P11, the low data page P14, the high data page P10, the middle data page P13 and the low data page P15 have not been written with data.

[0061] Figure 8 The memory cell voltage distribution 161 indicates that the high data page P2, the middle data page P5 and the low data page P9 of the second word line have been written with data. At this time, if you want to "clean" the high data page P2 and the middle data page P5, but keep the data of the low data page P9, the cleaning unit 104 will apply the first read voltage V R1 and the fourth read voltage V R4, find out the first target memory cell at the first logic state ("111") and the three second target memory cells at the second logic state ("110"), the third logic state ("100") and the fourth logic state ("000"). Subsequently, a programming trigger is applied, and a first programming voltage is applied in an incremental step pulse programming manner to change the logic state of the first target memory cell from the first logic state ("111") to the sixth logic state ("XX1") of a higher threshold voltage, and a second programming voltage is applied to change the logic state of the second target memory cell from the second logic state ("110"), the third logic state ("100") and the fourth logic state ("000") to the fifth logic state ("XX0") of a higher threshold voltage. Because the programming trigger is applied to the first target memory cell, the logic state of the first target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the third read voltage V R3 , the data of the memory cell of the upper data page P2 has been changed from 1 to 0, and the third read voltage V R3 The data of the memory cell of the high data page is correctly read. In addition, because the second target memory cell is subjected to programming trigger, the logic state of the second target memory cell is programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fourth read voltage V R4 , the data of the storage cell of the middle data page P5 has been changed from 0 to 1, and the fourth read voltage V R4 The data of the storage unit of the middle data page is correctly read. R4 is greater than the third read voltage V R3 .

[0062] However, for the lower data page P9, the data of the memory cell of the lower data page P9 is still 1, the data of the memory cell of the lower data page P9 has not been changed, and the voltage V can still be read. R5 The data of the storage unit of the lower data page P9 is correctly read. In this way, the written data of the upper data page P2 and the middle data page P5 can be "deleted" while the written data of the lower data page P9 is retained.

[0063] Figure 8The memory cell voltage distribution 161′ represents the voltage distribution of the memory cell of the low-order data page P9 of the second word line after the high-order data page P2 and the middle-order data page P5 of the second word line are “cleaned” and the written data of the low-order data page P9 is retained. The memory block 160′ represents the memory block where the high-order data page P2 and the middle-order data page P5 are “cleaned” and the written data of the low-order data page P9 is retained. The high-order data page P2 and the middle-order data page P5 are marked with X, indicating that their data can no longer be correctly read, which is equivalent to the data originally written in the high-order data page P2 and the middle-order data page P5 has been deleted.

[0064] In this embodiment, after “cleaning” the upper data page P2 and the middle data page P5, only the read voltage V R5 , the data of the lower data page P9 can be read, and the first read voltage V R1 and the fifth read voltage V R5 Compared with the conventional method of reading the data of the lower data page P9, the present invention can improve the reading performance of the memory. R5 Greater than the first read voltage V R1 .

[0065] Please refer to Fig. 9 In the present embodiment, the storage block 170 is a storage block before "purification", and the storage block 170′ is a storage block after the storage block 170 is "purified". The high data page P1, the middle data page P3, the low data page P6, the high data page P2, the middle data page P5, the low data page P9, the high data page P4, the middle data page P8 and the low data page P12 of the storage block 170 have been written with data, while the high data page P7, the middle data page P11, the low data page P14, the high data page P10, the middle data page P13 and the low data page P15 have not been written with data.

[0066] Fig. 9 The memory cell voltage distribution 171 indicates that the upper data page P2, the middle data page P5 and the lower data page P9 of the second word line have been written with data. At this time, if the upper data page P2, the middle data page P5 and the lower data page P9 are to be "cleaned", the cleaning unit 104 will apply the fourth read voltage V R4, find out four target memory cells at a first logic state ("111"), a second logic state ("110"), a third logic state ("100"), and a fourth logic state ("000"). Then, apply a programming trigger, apply a programming voltage in an incremental step pulse programming manner, so that the logic state of the target memory cell at the first logic state ("111") changes from the first logic state ("111") to a logic state of a higher threshold voltage ("0"), the logic state of the first target memory cell at the second logic state ("110") changes from the second logic state ("110") to a logic state of a higher threshold voltage ("0"), the logic state of the target memory cell at the third logic state ("100") changes from the third logic state ("100") to a logic state of a higher threshold voltage ("0"), and the logic state of the target memory cell at the fourth logic state ("000") changes from the fourth logic state ("000") to a logic state of a higher threshold voltage ("0"). Because the four target memory cells are subjected to programming triggers, the logic states of the target memory cells are programmed to a higher threshold voltage (the logic state moves to the right), which is higher than the fourth read voltage V R4 , the data of the storage cells of the upper data page P2, the middle data page P5 and the lower data page P9 have been changed from 1 to 0, and the fourth read voltage V R4 The data of the storage cells of the upper data page, the middle data page and the lower data page are correctly read out, so that the written data of the upper data page P2, the middle data page P5 and the lower data page P9 can be "deleted".

[0067] Fig. 9 The memory cell voltage distribution 171′ shows the voltage distribution of the memory cells of the second word line after the upper data page P2, the middle data page P5 and the lower data page P9 of the second word line are “purified”. The memory block 170′ shows the memory block where the upper data page P2, the middle data page P5 and the lower data page P9 are “purified”. The upper data page P2, the middle data page P5 and the lower data page P9 are marked with X, indicating that their data can no longer be correctly read, which is equivalent to the data originally written in the upper data page P2, the middle data page P5 and the lower data page P9 have been deleted.

[0068] Please refer to Figure 10A-10C In this embodiment, Fig. 10A The memory cell voltage distribution 181 indicates that data has been written into the upper data page P2 , the middle data page P5 , and the lower data page P9 of the second word line. Fig. 10BThe memory cell voltage distribution 181′ represents the voltage distribution of the upper data page P2 and the middle data page P5 of the memory cells of the second word line after the lower data page P9 of the second word line is “cleaned” and the written data of the upper data page P2 and the middle data page P5 are retained. Fig. 10C The storage cell voltage distribution 181" indicates the voltage distribution of the high data page P2 of the storage cell of the second word line after the low data page P9 of the second word line is "purified", the middle data page P5 is "purified" and the write data of the high data page P2 is retained. Fig. 10B If the lower data page P9 is to be “cleaned” but the data of the upper data page P2 and the middle data page P5 are to be retained, the cleaning unit 104 will apply the second read voltage V R2 , the third reading voltage V R3 and the fourth read voltage V R4 , find out two first target memory cells located at the third logic state ("100") and the fourth logic state ("000") and two second target memory cells located at the first logic state ("111") and the second logic state ("110"). Subsequently, a first programming voltage is applied in an incremental step pulse programming manner to change the logic state of the memory cell in the third logic state ("100") from the third logic state ("100") to the eighth logic state ("10X") of a higher threshold voltage, and also to change the logic state of the memory cell in the fourth logic state ("000") from the fourth logic state ("000") to the seventh logic state ("00X") of a higher threshold voltage. In this way, the written data of the lower data page P9 can be "deleted" while retaining the written data of the upper data page P2 and the middle data page P5.

[0069] exist Fig. 10C If the middle data page P5 is to be "purified" but the data of the upper data page P2 is to be retained, the purification unit 104 applies a second programming voltage in an incremental step pulse programming manner to change the logic state of the memory cell in the first logic state ("11X") from the first logic state ("11X") to the eighth logic state ("1XX") of a higher threshold voltage, and also changes the logic state of the memory cell in the second logic state ("11X") from the second logic state ("11X") to the eighth logic state ("1XX") of a higher threshold voltage. In this way, the written data of the middle data page P5 can be "deleted" while retaining the written data of the upper data page P2. In addition, when reading the upper data page P2, the reading performance of the data page can be increased.

[0070] Please refer to Figures 11A-11C In this embodiment, Fig.11A The memory cell voltage distribution 191 indicates that data has been written into the upper data page P2 , the middle data page P5 , and the lower data page P9 of the second word line. Fig. 11B The memory cell voltage distribution 191′ represents the voltage distribution of the upper data page P2 and the middle data page P5 of the memory cells of the second word line after the lower data page P9 of the second word line is “cleaned” and the written data of the upper data page P2 and the middle data page P5 are retained. Fig. 11C The storage cell voltage distribution 191" indicates the voltage distribution of the middle data page P5 of the storage cell of the second word line after the low data page P9 of the second word line is "purified", the high data page P2 is "purified" and the write data of the middle data page P5 is retained. Fig. 11B If the lower data page P9 is to be “cleaned” but the data of the upper data page P2 and the middle data page P5 are to be retained, the cleaning unit 104 will apply the second read voltage V R2 and the fourth read voltage V R4 , find out two first target memory cells located at the third logic state ("100") and the fourth logic state ("000") and two second target memory cells located at the first logic state ("111") and the second logic state ("110"). Subsequently, a first programming voltage is applied in an incremental step pulse programming manner to change the logic state of the memory cell in the third logic state ("100") from the third logic state ("100") to the seventh logic state ("00X") of a higher threshold voltage, and also to change the logic state of the memory cell in the fourth logic state ("000") from the fourth logic state ("000") to the seventh logic state ("00X") of a higher threshold voltage. In this way, the written data of the lower data page P9 can be "deleted" while retaining the written data of the upper data page P2 and the middle data page P5.

[0071] exist Fig. 11C If it is desired to "clean" the upper data page P2 but retain the data of the middle data page P5, the cleaning unit 104 will apply a second programming voltage in an incremental step pulse programming manner to change the memory cells of the first logic state ("11X") and the second logic state ("11X") from the logic state ("11X") to the fifth logic state ("X1X") of a higher threshold voltage. In this way, the written data of the upper data page P2 can be "deleted" while retaining the written data of the middle data page P5. In addition, when reading the middle data page P5, the reading performance of the data page can be increased.

[0072] The present invention is not limited to the above embodiments in which the purge voltage is applied to the three-level memory cell (TLC). After referring to the above embodiments, those skilled in the art should understand various situations in which the purge voltage is applied to the three-level memory cell. It is also understood that the present invention can be applied to memories in which each memory cell stores 4 bits or more, in addition to the three-level memory cell.

[0073] According to the present invention, a programming trigger is applied and a programming voltage is applied in an incremental step pulse programming manner to change the logical state of the storage cell of the memory page in the storage block, the logical state of the storage cell is programmed, and the data content stored in the storage cell is changed, so that the original written data cannot be correctly read, thereby achieving the purpose of "deleting" the data. In addition, the present invention can improve the data security of the memory and prevent hackers from obtaining the original written data and rebuilding the data. The present invention can also perform the operation of "deleting" data for a specific data page, without performing garbage collection and erasing operations on the storage block of the specific data page, which can reduce the number of times the storage block of the memory is erased and increase the life cycle of the memory. In addition, when reading the data page, the applied read voltage can be reduced, which can improve the memory performance. In addition, purifying the logic state of the memory cell to the fifth, sixth, seventh or eighth logic state with a higher threshold voltage can avoid the problem of deterioration of data retention characteristics or data retention time caused by the lateral charge migration phenomenon that is prone to occur in the known three-level memory cell flash memory (3D TLC-type NAND Flash) structure, thereby improving the reliability of the memory.

[0074] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, wherein: include: A memory array includes a plurality of memory pages, each of the memory pages includes a plurality of memory cells, each of the memory cells includes a first memory cell located at a high data page, a second memory cell located at a middle data page, and a third memory cell located at a low data page, and the memory cells include a first logic state, a second logic state, a third logic state, a fourth logic state, a fifth logic state, a sixth logic state, a seventh logic state, and an eighth logic state with threshold voltages from low to high; and a purification unit, receiving a data update instruction corresponding to a logical address, before receiving the data update instruction, the logical address corresponds to a physical address of one of the target memory pages, the purification unit applies a first read voltage and a second read voltage, finds at least one first target memory cell and at least one second target memory cell to be purified from the target memory page, applies a first programming voltage to the at least one first target memory cell to change the logic state of the at least one first target memory cell to one of the fifth, sixth, seventh and eighth logic states, and applies a second programming voltage to the at least one second target memory cell to change the logic state of the at least one second target memory cell to one of the fifth, sixth, seventh and eighth logic states, wherein the first programming voltage is different from the second programming voltage; The purification unit applies a programming trigger and a programming voltage in an incremental step pulse programming manner to change the logic state of the memory cell of the memory page in the memory block, and purifies the logic state of the memory cell to a fifth, sixth, seventh or eighth logic state with a higher threshold voltage, including: Clean the low-order data page and the middle-order data page, but retain the data of the high-order data page; Clean the high-order data page and the low-order data page, but retain the data of the middle-order data page; Clean the high-order data page and the middle-order data page, but retain the data of the low-order data page; Cleaning the high data page, the middle data page and the low data page; Purify the low data page, but retain the data of the high data page and the middle data page, continue to purify the middle data page, but retain the data of the high data page; or Purify the low data page, but keep the data of the high data page and the middle data page, continue to purify the high data page, but keep the data of the middle data page; Wherein, if the lower data page and the middle data page are to be cleaned but the data of the upper data page is to be retained, applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell comprises: applying a programming trigger, applying the first programming voltage in an incremental step pulse programming manner, so that the logic states of the three first target memory cells are changed from the first logic state, the second logic state and the third logic state to the eighth logic state; applying the second programming voltage in an incremental step pulse programming manner, so that the logic state of the second target memory cell is changed from the fourth logic state to the fifth logic state, the sixth logic state and the seventh logic state; If the upper data page and the lower data page are to be cleaned but the data of the middle data page is to be retained, applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell comprises: applying a programming trigger, applying the first programming voltage in an incremental step pulse programming manner, so that the logic state of the two first target memory cells is changed from the first logic state and the second logic state to the fifth logic state; applying the second programming voltage in an incremental step pulse programming manner, so that the logic state of the two second target memory cells is changed from the third logic state and the fourth logic state to the seventh logic state; If the upper data page and the middle data page are to be cleaned but the data of the lower data page is to be retained, applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell comprises: applying a programming trigger to apply the first programming voltage in an incremental step pulse programming manner so that the logic state of the first target memory cell is changed from the first logic state to the sixth logic state; applying the second programming voltage in an incremental step pulse programming manner so that the logic states of the three second target memory cells are changed from the second logic state, the third logic state and the fourth logic state to the fifth logic state; If the upper data page, the middle data page and the lower data page are to be cleaned, applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell comprises: applying a programming trigger to apply the first programming voltage in an incremental step pulse programming manner, so that the logic states of the four target memory cells are changed from the first logic state, the second logic state, the third logic state and the fourth logic state to a logic state "0" with a higher threshold voltage; If it is desired to clean the lower data page but keep the data of the upper data page and the middle data page, and continue to clean the middle data page but keep the data of the upper data page, then applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell include: applying a programming trigger, applying the first programming voltage in an incremental step pulse programming manner, so that the logic state of the two first target memory cells is changed from the third logic state and the fourth logic state to the eighth logic state and the seventh logic state; applying a programming trigger, applying the second programming voltage in an incremental step pulse programming manner, so that the logic state of the two second target memory cells is changed from the first logic state and the second logic state to the eighth logic state; If it is desired to purify the low data page but retain the data of the high data page and the middle data page, and continue to purify the high data page but retain the data of the middle data page, then applying the first programming voltage to change the logic state of the at least one first target storage unit and applying the second programming voltage to change the logic state of the at least one second target storage unit include: applying a programming trigger, applying the first programming voltage in an incremental step pulse programming manner, so that the logic state of the two first target storage units is changed from the third logic state and the fourth logic state to the seventh logic state with a higher threshold voltage; applying a programming trigger, applying the second programming voltage in an incremental step pulse programming manner, so that the logic state of the two second target storage units is changed from the first logic state and the second logic state to the fifth logic state with a higher threshold voltage.

2. The memory device according to claim 1, wherein: Applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell include: If you want to clean the low data page but keep the data of the high data page and the middle data page, applying the first programming voltage in an incremental step pulse programming manner to change the logic state of the first target memory cell from the third logic state to the eighth logic state, and The second programming voltage is applied in an incremental step pulse programming manner to change the logic state of the second target memory cell from the fourth logic state to the seventh logic state.

3. The memory device according to claim 1, wherein: Applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell include: If you want to clean the middle data page but keep the data of the high data page and the low data page, Applying a programming trigger to apply the first programming voltage in an incremental step pulse programming manner to change the logic state of the first target memory cell from the first logic state to the eighth logic state, and The second programming voltage is applied in an incremental step pulse programming manner to change the logic state of the second target memory cell from the fourth logic state to the fifth logic state.

4. The memory device according to claim 1, wherein: Applying the first programming voltage to change the logic state of the at least one first target memory cell and applying the second programming voltage to change the logic state of the at least one second target memory cell include: If you want to clean the high data page but keep the data of the middle data page and the low data page, Applying a programming trigger to apply the first programming voltage in an incremental step pulse programming manner to change the logic state of the first target memory cell from the first logic state to the sixth logic state, and The second programming voltage is applied in an incremental step pulse programming manner to change the logic state of the second target memory cell from the second logic state to the fifth logic state.

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