Fault prediction method, device and electronic equipment

Abstract

The present application provides a fault prediction method, including: monitoring the target memory chip, recording the time and number of erasures; based on the time and number of erasures meeting the preset fault conditions, generating an alarm message to warn that the target memory chip is in a dangerous state. In this solution, by real-time detection of the time and number of erasures of the target memory chip each time, the situation of the target memory chip is mastered, and when the time and number of erasures meet the preset fault conditions, an alarm message is generated to warn the user that the target memory chip is in a dangerous state, so that the user can perform operations based on the warning, such as turning off the power to stop the target memory chip from being further erased, so as to achieve the purpose of protecting the target memory chip.

Description

Technical Field

[0001] The present application relates to the field of information processing, and more specifically, to a fault prediction method, device and electronic equipment. Background Art

[0002] Flash (coded flash memory) chips are widely used storage materials that can quickly store and erase data. Flash is generally designed with an upper limit for erase. When the number of erases reaches the upper limit, the flash chip reaches the end of its service life and will be damaged.

[0003] However, when certain programs or other functions in the device are running, the frequency of erasing and writing part of the storage on the flash chip will increase, which can easily cause the flash chip to reach its design upper limit and be damaged at the end of its service life, resulting in the system possibly being unable to boot. Summary of the invention

[0004] In view of this, the present application provides a fault prediction method as follows:

[0005] A fault prediction method, comprising:

[0006] Monitoring the target storage chip and recording the time and number of times the erasure occurs;

[0007] Based on the time and number of erasures that meet preset fault conditions, an alarm message is generated to warn that the target storage chip is in a dangerous state.

[0008] Optionally, the above method, determining whether the time and number of erasures meet a preset fault condition, includes:

[0009] Based on the time and number of times the target memory chip is erased, analyzing and obtaining an average period of erasing the target memory chip within a preset time period, wherein the preset time period includes at least two average periods;

[0010] Determine whether the number of times and the average period meet the preset fault condition;

[0011] Based on the number of times and the average period satisfying the preset fault condition, it is determined that the erased information satisfies the preset fault condition.

[0012] Optionally, the above method, determining whether the number and the average period meet a preset fault condition, includes:

[0013] Determine whether the number is greater than a preset first number threshold, and obtain a first determination result;

[0014] Based on the first judgment result indicating that the number of times is greater than a preset first number threshold, judging whether the average period is less than a preset first period threshold, and obtaining a second judgment result;

[0015] Based on the fact that the second judgment result indicates that the average period is less than a preset first period threshold, it is determined that the erasure information meets a preset fault condition.

[0016] Optionally, in the above method, the preset number threshold includes at least two number thresholds, and the preset period threshold includes at least two period thresholds;

[0017] Wherein, after the second judgment result indicates that the average period is less than a preset first period threshold, the method further includes:

[0018] Based on the time when the target storage chip is erased, analyzing and obtaining the erase interval time of the target storage chip within a preset time period;

[0019] Determine whether the erasing interval of the target storage chip within the preset time period meets a preset fixed period condition, and obtain a third determination result;

[0020] Based on the third judgment result indicating that the erasure interval of the target storage chip within the preset time period meets the preset fixed period condition, it is determined that the erasure information meets the preset fault condition;

[0021] Based on the third judgment result indicating that the erasing interval of the target storage chip within the preset time period does not meet the preset fixed period condition, judging whether the number of times is greater than a preset second number threshold, and obtaining a fourth judgment result, the second number threshold is greater than the first number threshold;

[0022] Based on the fourth judgment result indicating that the number is greater than a preset second number threshold, judging whether the average period is less than a preset second period threshold, and obtaining a fifth judgment result that the second period threshold is greater than the first period threshold;

[0023] Based on the fifth judgment result indicating that the average period is less than a preset second period threshold, it is determined that the erasure information meets a preset fault condition.

[0024] Optionally, in the above method, the generating of warning information to warn that the target storage chip is in a dangerous state includes:

[0025] Alarm information is generated and sent to a baseboard management controller, so that the baseboard management controller adds the alarm information to the web page configuration information, so that an alarm is issued on the web page.

[0026] Optionally, in the above method, the generating of warning information to warn that the target storage chip is in a dangerous state includes:

[0027] Generate warning information, and send the warning information to the operating system, so that the operating system can output display content on the display screen by configuring the extensible firmware interface parameters, and the display content is used to warn that the target storage chip is in a dangerous state.

[0028] A fault prediction device, comprising:

[0029] A monitoring module, used to monitor the target storage chip and record the time and number of times the erasure occurs;

[0030] The early warning module is used to generate an alarm message based on the time and number of erasures that meet the preset fault conditions, so as to warn that the target storage chip is in a dangerous state.

[0031] Optionally, the above-mentioned device further includes:

[0032] The analysis module is used to analyze and obtain the average cycle of the target storage chip within a preset time period based on the time and number of times the target storage chip is erased, and the preset time period includes at least two average cycles; determine whether the number and the average cycle meet the preset fault condition; based on the number and the average cycle meeting the preset fault condition, determine that the erasure information meets the preset fault condition.

[0033] An electronic device, comprising: a memory and a processor;

[0034] Wherein, the memory stores a processing program;

[0035] The processor is used to load and execute the processing program stored in the memory to implement each step of the fault prediction method as described in any one of the above items.

[0036] A readable storage medium stores a computer program, wherein the computer program is called and executed by a processor to implement each step of the fault prediction method as described in any one of the above claims.

[0037] Through the above technical solution, it can be known that the present application provides a fault prediction method, including: monitoring the target storage chip, recording the time and number of erasures; based on the time and number of erasures meeting the preset fault conditions, generating an alarm message to warn that the target storage chip is in a dangerous state. In this solution, by real-time detection of the time and number of erasures of the target storage chip each time, the situation of the target storage chip is mastered, and when the time and number of erasures meet the preset fault conditions, an alarm message is generated to warn the user that the target storage chip is in a dangerous state, so that the user can operate based on the warning, such as turning off the power to stop the target storage chip from being erased and written, so as to achieve the purpose of protecting the target storage chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0039] Figure 1 This is a flowchart of a fault prediction method embodiment 1 provided by the present application;

[0040] Figure 2 This is a flow chart of a fault prediction method embodiment 2 provided by the present application;

[0041] Figure 3 is a flowchart of a fault prediction method embodiment 3 provided by the present application;

[0042] Figure 4 is a flowchart of a fault prediction method embodiment 4 provided by the present application;

[0043] Figure 5 is a flowchart of a fault prediction method embodiment 5 provided by the present application;

[0044] Figure 6 is a flowchart of a fault prediction method embodiment 6 provided by the present application;

[0045] Figure 7 It is a structural schematic diagram of a fault prediction device embodiment 1 provided by the present application;

[0046] Figure 8 It is a structural diagram of a fault prediction device embodiment 2 provided in the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] like Figure 1 The figure is a flowchart of a fault prediction method embodiment 1 provided by the present application. The method is applied to an electronic device and includes the following steps:

[0049] Step S101: monitoring the target storage chip and recording the time and number of times the erasure occurs;

[0050] The time and number of times the target storage chip is erased are recorded by monitoring software.

[0051] Specifically, the erasure time may be a specific moment.

[0052] Each time erasure occurs, the erasure time is recorded and the number of times is accumulated.

[0053] Step S102: based on the erasure time and number of times satisfying a preset fault condition, generating an alarm message to warn that the target storage chip is in a dangerous state.

[0054] If the time and number of erasures meet the preset fault conditions, an alarm message is generated to remind the user that the target storage chip is in a dangerous state.

[0055] It should be noted that in the present application, the time and number of times the target memory chip is erased are detected in real time to understand the situation of the target memory chip, and an alarm is issued when the target memory chip is in a dangerous state so that the user can quickly understand the situation of the target memory chip.

[0056] In summary, the present embodiment provides a fault prediction method, including: monitoring the target storage chip, recording the time and number of erasures; based on the time and number of erasures meeting the preset fault conditions, generating an alarm message to warn that the target storage chip is in a dangerous state. In this solution, by real-time detection of the time and number of erasures of the target storage chip each time, the situation of the target storage chip is mastered, and when the time and number of erasures meet the preset fault conditions, an alarm message is generated to warn the user that the target storage chip is in a dangerous state, so that the user can perform operations based on the warning, such as turning off the power to stop the target storage chip from being further erased, so as to achieve the purpose of protecting the target storage chip.

[0057] like Figure 2 The figure is a flowchart of a fault prediction method embodiment 2 provided by the present application, and the method comprises the following steps:

[0058] Step S201: monitoring the target storage chip and recording the time and number of times the erasure occurs;

[0059] Among them, step S201 is consistent with step S101 in embodiment 1, and is not described in detail in this embodiment.

[0060] Step S202: Based on the time and number of times the target memory chip is erased, an average period of erasing the target memory chip within a preset time period is analyzed and obtained;

[0061] Wherein, the preset time period includes at least two averaging periods.

[0062] The number of times the target storage chip is erased is obtained according to a preset time period. The preset time period can be obtained by selecting a certain erasure as the first analysis erasure and selecting a subsequent erasure as the last analysis erasure, and calculating the time difference between the first analysis erasure and the last analysis erasure.

[0063] For example, the time of the first analysis and erasure is 01:20:25, and the time of the last analysis and erasure is 01:25:25, then the calculated preset time period is 5 minutes.

[0064] Specifically, the number of erasures of the target storage chip in the preset time period is determined. For example, if the last erase analysis is 10 times and the first erase analysis is 2 times, the number of erases calculated to be 8 times is.

[0065] Then, the average period can be obtained by calculating based on the length of the preset time period and the number of erasures that occur within the time period.

[0066] Specifically, the preset time period is 5 minutes, and the number of erasures is 8 times, then the average period is calculated as follows: 5 minutes / 8 times=37.5 seconds / time, that is, the average period is 37.5 seconds.

[0067] It should be noted that, in a specific implementation, the preset time period may be randomly selected or may be selected according to a set time threshold, and the preset time period may be calculated within the preset time threshold.

[0068] For example, the set time threshold may be 5-10 minutes, 2-3 minutes, 30-35 minutes or other thresholds, which are not limited in this application.

[0069] Step S203: determining whether the number and the average period meet a preset fault condition;

[0070] If the number of times and the average period meet the preset fault condition, it is determined that the erasure information meets the preset fault condition, and step S204 is executed.

[0071] Among them, the electronic device also has preset fault conditions, which are respectively related to the number of times and the average period.

[0072] Specifically, if the number of erasures is large and the frequency of erasures is high, it can be considered that frequent erasures may cause a target storage chip to fail.

[0073] For example, if the number of times is greater than the number threshold and the average period is less than the period threshold, the preset fault condition is met.

[0074] Step S204: Generate warning information to warn that the target storage chip is in a dangerous state.

[0075] Among them, step S204 is consistent with step S102 in embodiment 1, and is not described in detail in this embodiment.

[0076] In summary, in a fault prediction method provided by this embodiment, judging whether the time and number of erasures meet the preset fault condition includes: based on the time and number of erasures of the target storage chip, analyzing and obtaining the average cycle of the target storage chip in a preset time period, wherein the preset time period includes at least two average cycles; judging whether the number and average cycle meet the preset fault condition; judging whether the erasure information meets the preset fault condition based on the number and average cycle meeting the preset fault condition. In this solution, judging whether a fault occurs based on the number of erasures in a period of time and the average cycle of erasures in the period of time only requires simple calculations to judge, and the amount of data processing is small.

[0077] like Figure 3 The figure is a flowchart of a fault prediction method embodiment 3 provided by the present application, and the method comprises the following steps:

[0078] Step S301: monitoring the target storage chip and recording the time and number of times the erasure occurs;

[0079] Step S302: Based on the time and number of times the target memory chip is erased, an average period of erasing the target memory chip within a preset time period is analyzed and obtained, wherein the preset time period includes at least two average periods;

[0080] Among them, steps S301-302 are consistent with steps S201-202 in Example 2, and are not repeated in this embodiment.

[0081] Step S303: Determine whether the number of times is greater than a preset first number threshold;

[0082] If the number of erasures of the target memory chip in the preset time period is greater than the first number threshold, it indicates that the target memory chip has been erased a large number of times in the time period.

[0083] The first number threshold value may be a smaller value, such as 100 times or 50 times, so as to quickly discover the fault when a large number of erases occur.

[0084] For example, if only 10 erasures occur in the preset time period, which is less than the first count threshold of 100 times, it can be determined that the target storage chip is normal in this time period and no alarm is needed; but if 110 erasures occur in the preset time period, which is greater than the first count threshold of 100 times, the target storage chip may fail, triggering step S304.

[0085] In order to improve the accuracy of the judgment, when the number of times the target storage chip is erased in the preset time period is greater than the first number threshold, step S304 is triggered.

[0086] Step S304: determining whether the average period is less than a preset first period threshold;

[0087] Wherein, based on the fact that the second judgment result indicates that the average period is less than a preset first period threshold, it is determined that the erasure information meets a preset fault condition.

[0088] The first cycle threshold is the average cycle critical value of the memory chip being erased under normal circumstances, such as 1000 seconds, 500 seconds, etc. This value can be set by a technician based on historical experience.

[0089] For example, in the preset time period, 110 erasures occurred, which is greater than the first number threshold of 100 times, and the average cycle is 5 seconds, which is less than the first cycle threshold of 1000 seconds. It is determined that the target storage chip is frequently erased, triggering step S305 and issuing an alarm.

[0090] If the average cycle is less than the first cycle threshold, it indicates that the target storage chip is frequently erased during the preset time period, which is a fault condition.

[0091] Therefore, if the average period is less than the preset first period threshold, step S305 is triggered.

[0092] It should be noted that the present application does not limit the specific values ​​of the first number threshold and the first cycle threshold.

[0093] Step S305: Generate warning information to warn that the target storage chip is in a dangerous state.

[0094] Among them, step S305 is consistent with step S205 in embodiment 2, and is not described in detail in this embodiment.

[0095] In summary, in a fault prediction method provided by this embodiment, judging whether the number and the average period meet the preset fault condition includes: judging whether the number is greater than a preset first number threshold, and obtaining a first judgment result; based on the first judgment result indicating that the number is greater than the preset first number threshold, judging whether the average period is less than the preset first period threshold, and obtaining a second judgment result; based on the second judgment result indicating that the average period is less than the preset first period threshold, judging that the erasure information meets the preset fault condition. In this scheme, based on the number of times the target storage chip is erased in a preset time period and the average period of erasure, judgments are made respectively to determine that the target storage chip is frequently erased in the time period, which is a fault condition and requires an early warning. Only simple data calculations are required, and the amount of data processing is small.

[0096] like Figure 4 The figure is a flowchart of a fault prediction method embodiment 4 provided by the present application, and the method comprises the following steps:

[0097] Step S401: monitoring the target storage chip and recording the time and number of times the erasure occurs;

[0098] Step S402: Based on the time and number of times the target memory chip is erased, an average cycle of the target memory chip within a preset time period is analyzed and obtained, wherein the preset time period includes at least two average cycles;

[0099] Step S403: Determine whether the number of times is greater than a preset first number threshold;

[0100] When the number of times the target storage chip is erased in the preset time period is greater than the first number threshold, step S404 is triggered.

[0101] Step S404: determining whether the average period is less than a preset first period threshold;

[0102] If the average period is less than the preset first period threshold, step S405 is triggered.

[0103] Among them, steps S401-404 are consistent with steps S401-404 in Example 3, and are not repeated in this embodiment.

[0104] Step S405: based on the time when the target memory chip is erased, analyzing and obtaining the erase interval time of the target memory chip within a preset time period;

[0105] Wherein, based on each time when the target storage chip is erased within the preset time period, the interval time of the erasure is analyzed and determined.

[0106] Specifically, the erasure interval time is obtained by subtracting the time between any two erasures, and the erasure interval time of the target storage chip in the preset time period is obtained by subtracting the time between two adjacent erasures in the preset time period.

[0107] As an example, N is an integer greater than 1, the N-1th erasure occurs at 01:20:21, the Nth erasure occurs at 01:21:00, and the N+1th erasure occurs at 01:21:05, then two erasure interval times are calculated: 49 seconds and 5 seconds.

[0108] Step S406: determining whether the erasing interval of the target memory chip satisfies a preset fixed period condition;

[0109] The preset fixed cycle condition means that each interval time is the same, and the storage chip is erased at a fixed cycle.

[0110] It should be noted that when the software is set up incorrectly, due to incompatibility or other problems between the software and the target memory chip, the software will frequently erase the memory chip at a fixed frequency / cycle, and the system may quickly enter a dangerous state according to this trend.

[0111] The erasure operation of the memory chip caused by software setting error is characterized by a very high erasure frequency and occurs within a fixed period (the interval between two times is the same). Its growth rate is very fast, and the security risk is high, but it is relatively easy to be confirmed, so this application adopts a smaller number of erasures and an average cycle to judge.

[0112] Therefore, in this embodiment, whether the erase information meets the fault condition is determined by judging whether the memory chip is frequently erased at a fixed period within a preset time period.

[0113] If the frequent erasures within the preset time period are not performed at a fixed cycle, it may be that the flash writing test within a period of time causes the increase to be too fast, so continue monitoring and execute step S407.

[0114] If it is further determined that the erasure interval of the target storage chip within the preset time period meets the preset fixed period condition, it is determined that the erasure information meets the preset fault condition and step S409 is executed;

[0115] If it is further determined that the erasing interval of the target storage chip within the preset time period does not meet the preset fixed period condition, step S407 is executed.

[0116] Step S407: Determine whether the number of times is greater than a preset second number threshold;

[0117] Wherein, the second number threshold is greater than the first number threshold;

[0118] If the number is greater than a preset second number threshold, step S408 is executed.

[0119] It should be noted that if the erasure of the target memory chip is not performed according to a fixed cycle, the erasure operation may increase too quickly due to a targeted flash test, and the flash test may only be performed for a period of time. However, if the flash test erases the memory chip too much, it may also cause the memory chip to fail.

[0120] The characteristic of targeted flash test is that the frequency of flash is fast, but the duration is not too long. The total number of flash tests is still safe. You can set a slightly larger number threshold and cycle threshold to determine it.

[0121] Therefore, based on a larger number threshold, another judgment is made. If the number of erasures for the target memory chip is greater than the second number threshold, it indicates that a large number of erasures have occurred, and there is a potential fault hazard for the target memory chip. Step S408 is executed to further determine whether an alarm is required.

[0122] If the number of erasures of the target memory chip is not greater than the second number threshold, it indicates that the erasures are still within the permissible range, and the erasures of the target memory chip can continue to be counted and judged.

[0123] The second number threshold value may be a relatively large value, such as 1000 times or 2000 times, so as to timely discover the situation when a large amount of erasure occurs due to the flash writing test.

[0124] Step S408: determining whether the average period is less than a preset second period threshold;

[0125] The second cycle threshold is greater than the first cycle threshold.

[0126] If the average period is less than a preset second period threshold, it is determined that the erasure information meets a preset fault condition and step S409 is executed.

[0127] Among them, when a large number of target storage chips are erased due to the flash writing test, the erasure occurring in this time period is judged to determine whether the average erasure cycle is less than the second cycle threshold to determine whether the target storage chip is erased too quickly, at which point the system may be in a dangerous state.

[0128] The second cycle threshold is greater than the first cycle threshold, and may be a larger value, such as 100,000 seconds, 10,000 seconds, etc.

[0129] It should be noted that, in the present application, by setting different number thresholds and cycle thresholds, it is possible to judge a large number of erasures caused by different reasons and handle them in different ways, thereby improving the accuracy of fault prediction.

[0130] In a specific implementation, other number thresholds and cycle thresholds may be set according to actual conditions to determine more reasons for large-scale erasures and perform corresponding processing.

[0131] Step S409: Generate warning information to warn that the target storage chip is in a dangerous state.

[0132] Among them, step S409 is consistent with step S305 in embodiment 3, and is not described in detail in this embodiment.

[0133] In summary, a fault prediction method provided by this embodiment also includes: based on the time when the target storage chip is erased, analyzing to obtain the erasure interval time of the target storage chip within the preset time period; judging whether the erasure interval time of the target storage chip within the preset time period satisfies the preset fixed period condition, and obtaining a third judgment result; based on the third judgment result, indicating that the erasure interval time of the target storage chip within the preset time period satisfies the preset fixed period condition, judging that the erasure information satisfies the preset fault condition; based on the third judgment result, indicating that the erasure interval time of the target storage chip within the preset time period does not satisfy the preset fixed period condition, judging whether the number is greater than a preset second number threshold, and obtaining a fourth judgment result, wherein the second number threshold is greater than the first number threshold; based on the fourth judgment result, indicating that the number is greater than the preset second number threshold, judging whether the average period is less than the preset second period threshold, and obtaining a fifth judgment result, wherein the second period threshold is greater than the first period threshold; based on the fifth judgment result, indicating that the average period is less than the preset second period threshold, judging that the erasure information satisfies the preset fault condition. In this scheme, whether the erasure of the target storage chip is caused by a fixed-cycle erasure within a preset time period is determined to be caused by a software design vulnerability or a flash test, and an alarm is issued when a large amount of erasure is caused by a software vulnerability design; and when a large amount of erasure is caused by a flash test, an alarm is issued when the number of erasures is greater than the second number threshold and the average cycle is less than the second cycle threshold. Judgments are made for large-scale erasures caused by different reasons, and different methods are used to handle them, thereby improving the accuracy of fault prediction.

[0134] like Figure 5The figure is a flowchart of a fault prediction method embodiment 5 provided by the present application, and the method comprises the following steps:

[0135] Step S501: monitoring the target storage chip and recording the time and number of times the erasure occurs;

[0136] Among them, step S501 is consistent with step S101 in embodiment 1, and is not described in detail in this embodiment.

[0137] Step S502: generating alarm information based on the erasure time and number of times satisfying a preset fault condition;

[0138] When the time and number of erasures meet preset fault conditions, an alarm message is generated to issue an alarm prompt.

[0139] The alarm information may include only an alarm instruction, or a corresponding relationship between the alarm information and the judgment condition may be preset.

[0140] For example, within a preset time period, the storage chip is frequently erased at a fixed cycle to determine that the erasure information meets the fault condition, and the first alarm information is generated to provide a subsequent prompt that the fault is caused by a software setting error.

[0141] For example, frequent erasure of the storage chip at irregular intervals occurs within a preset time period to determine that the erasure information meets the fault condition, and a second alarm message is generated to provide a subsequent prompt that the fault is caused by the flash writing test.

[0142] In this application, the substrate control manager is used for prompting.

[0143] Step S503: sending the alarm information to a baseboard management controller, so that the baseboard management controller adds the alarm information to the web page configuration information, so that an alarm is issued on the web page.

[0144] It should be noted that the baseboard management controller is provided with a web page (web) interface, and the relevant information on the baseboard can be displayed on the web page.

[0145] After the alarm information is sent to the baseboard management controller, the baseboard management controller responds to the alarm information and adds the alarm information to the configuration information of the web page, so that the alarm content is displayed on the web page.

[0146] When the alarm information is an alarm instruction, an alarm is prompted on a web page based on the alarm instruction.

[0147] For example, the web page displays "The storage chip is frequently erased, and there is a potential malfunction in the system. It is recommended to shut down and cut off the power."

[0148] When the alarm information is the first alarm information or the second alarm information, the alarm prompted on the web page based on the alarm information may carry the alarm generation reason.

[0149] For example, when it is determined that the alarm information is generated by a large amount of erasure caused by a flash test, the generated alarm information includes corresponding information, and the web page of the baseboard management controller displays "The flash test causes frequent erasure of storage chips, and there is a hidden danger of system failure. It is recommended to shut down and power off."

[0150] The user of the electronic device can see the content displayed on the web page, and can shut down the device according to the content prompt to stop the target memory chip from being erased and written, thereby protecting the target memory chip. The user can also contact a technical engineer to further determine and eliminate the potential fault.

[0151] However, it should be noted that the web page in the present application can prompt that there is a system failure, and the specific prompt content can be selected according to the actual situation and is not limited to the examples in this embodiment.

[0152] In summary, in a fault prediction method provided by this embodiment, the generation of alarm information to warn that the target storage chip is in a dangerous state includes: generating alarm information, and sending the alarm information to a baseboard management controller, so that the baseboard management controller adds the alarm information to the web page configuration information, so that the alarm is issued on the web page. In this solution, by displaying the alarm information on the web page of the baseboard management controller, the user can understand that the current target storage chip is in a dangerous state based on the content displayed on the web page, and take corresponding measures to protect it.

[0153] like Figure 6 The figure is a flowchart of a fault prediction method embodiment 6 provided by the present application, and the method comprises the following steps:

[0154] Step S601: monitor the target storage chip and record the time and number of times the erasure occurs;

[0155] Among them, step S601 is consistent with step S101 in embodiment 1, and is not described in detail in this embodiment.

[0156] Step S602: Generate alarm information based on the erasure time and number of times meeting the preset fault condition;

[0157] When the time and number of erasures meet preset fault conditions, an alarm message is generated to issue an alarm prompt.

[0158] In this application, the prompting method is adopted by the operating system.

[0159] The alarm information may include only an alarm instruction, or a corresponding relationship between the alarm information and the judgment condition may be preset.

[0160] For example, within a preset time period, the storage chip is frequently erased at a fixed cycle to determine that the erasure information meets the fault condition, and the first alarm information is generated to provide a subsequent prompt that the fault is caused by a software setting error.

[0161] For example, frequent erasure of the storage chip at irregular intervals occurs within a preset time period to determine that the erasure information meets the fault condition, and a second alarm message is generated to provide a subsequent prompt that the fault is caused by the flash writing test.

[0162] Step S603: Send the warning information to the operating system, so that the operating system can output display content on the display screen by configuring the extensible firmware interface parameters, and the display content is used to warn that the target storage chip is in a dangerous state.

[0163] The operating system sends the warning information of the target storage chip to the display screen by configuring the extensible firmware interface parameters, so that the display screen outputs display content based on the warning information.

[0164] When the warning information is a warning instruction, a warning is prompted on the display screen based on the warning instruction.

[0165] For example, the display screen shows "The memory chip is frequently erased, there is a hidden danger of system failure, it is recommended to shut down and cut off the power."

[0166] When the alarm information is the first alarm information or the second alarm information, the alarm prompted on the display screen based on the alarm information may carry the cause of alarm generation.

[0167] For another example, when it is determined that the alarm information is generated by a large amount of erasure caused by a flash test, the generated alarm information includes corresponding information, and the display screen shows "The flash test causes frequent erasure of storage chips, and there is a hidden danger of system failure. It is recommended to shut down and power off."

[0168] The user of the electronic device can see the content displayed on the display screen and shut down the device according to the content prompt to stop the target memory chip from being erased and written, thereby protecting the target memory chip. The user can also contact a technical engineer to further determine and eliminate the potential fault.

[0169] However, it should be noted that the display screen in the present application is used to prompt that there is a system fault, and the specific prompt content can be selected according to actual conditions and is not limited to the examples in this embodiment.

[0170] In summary, in a fault prediction method provided by this embodiment, the generation of alarm information to warn that the target storage chip is in a dangerous state includes: generating alarm information and sending the alarm information to the operating system, so that the operating system outputs display content on the display screen by configuring the extensible firmware interface parameters, and the display content is used to warn that the target storage chip is in a dangerous state. In this solution, the alarm information is displayed on the web page of the baseboard management controller, so that the user can understand that the current target storage chip is in a dangerous state based on the content displayed on the web page, and take corresponding measures to protect it.

[0171] Corresponding to the above-mentioned fault prediction method embodiment provided by the present application, the present application also provides an apparatus embodiment applying the fault prediction method.

[0172] like Figure 7 The structure diagram of a fault prediction device embodiment 1 provided by the present application is shown, and the device includes the following structures: a monitoring module 701 and an early warning module 702;

[0173] The monitoring module 701 is used to monitor the target storage chip and record the time and number of times the erasure occurs;

[0174] The early warning module 702 is used to generate an alarm message based on the time and number of erasures that meet a preset fault condition, so as to warn that the target storage chip is in a dangerous state.

[0175] Optionally, the early warning module is specifically used for:

[0176] Alarm information is generated and sent to a baseboard management controller, so that the baseboard management controller adds the alarm information to the web page configuration information, so that the alarm information is displayed on the web page.

[0177] Optionally, the early warning module is specifically used for:

[0178] Generate warning information, and send the warning information to the operating system, so that the operating system can output display content on the display screen by configuring the extensible firmware interface parameters, and the display content is used to warn that the target storage chip is in a dangerous state.

[0179] Among them, the functions of various components of the fault prediction device are explained in the method embodiment and will not be repeated in this embodiment.

[0180] In summary, the present embodiment provides a fault prediction device, which detects in real time the time and number of times the target storage chip is erased each time, grasps the situation of the target storage chip, and generates an alarm message when the time and number of times the erasure occurs meet the preset fault conditions, warning the user that the target storage chip is in a dangerous state, so that the user can take action based on the warning, such as turning off the power to stop the target storage chip from being erased further, thereby achieving the purpose of protecting the target storage chip.

[0181] like Figure 8 The figure is a schematic diagram of the structure of an electronic device embodiment 2 provided by the present application, and the electronic device includes the following structures: a monitoring module 801, an analysis module 802 and an early warning module 803;

[0182] Among them, the structural functions of the monitoring module 801 and the early warning module 803 are consistent with the corresponding structural functions in Example 1, and are not described in detail in this embodiment.

[0183] Among them, the analysis module 802 is used to analyze the average cycle of the target storage chip within a preset time period based on the time and number of times the target storage chip is erased, and the preset time period includes at least two average cycles; determine whether the number of times and the average cycle meet the preset fault condition; based on the number of times and the average cycle meeting the preset fault condition, determine that the erasure information meets the preset fault condition.

[0184] Optionally, the analysis module is used to:

[0185] Determine whether the number is greater than a preset first number threshold, and obtain a first determination result;

[0186] Based on the first judgment result indicating that the number of times is greater than a preset first number threshold, judging whether the average period is less than a preset first period threshold, and obtaining a second judgment result;

[0187] Based on the fact that the second judgment result indicates that the average period is less than a preset first period threshold, it is determined that the erasure information meets a preset fault condition.

[0188] Optionally, the preset number threshold includes at least two number thresholds, and the preset period threshold includes at least two period thresholds;

[0189] Optionally, the analysis module is also used for:

[0190] Based on the time when the target storage chip is erased, analyzing and obtaining the erase interval time of the target storage chip within a preset time period;

[0191] Determine whether the erasing interval of the target storage chip within the preset time period meets a preset fixed period condition, and obtain a third determination result;

[0192] Based on the third judgment result indicating that the erasure interval of the target storage chip within the preset time period meets the preset fixed period condition, it is determined that the erasure information meets the preset fault condition;

[0193] Based on the third judgment result indicating that the erasing interval of the target storage chip within the preset time period does not meet the preset fixed period condition, judging whether the number of times is greater than a preset second number threshold, and obtaining a fourth judgment result, the second number threshold is greater than the first number threshold;

[0194] Based on the fourth judgment result indicating that the number is greater than a preset second number threshold, judging whether the average period is less than a preset second period threshold, and obtaining a fifth judgment result that the second period threshold is greater than the first period threshold;

[0195] Based on the fifth judgment result indicating that the average period is less than a preset second period threshold, it is determined that the erasure information meets a preset fault condition.

[0196] It should be noted that in a specific implementation, the function of the analysis module can be implemented through registers and logic gates, wherein the registers count the number of times, cycles and other information, and the logic gates determine whether the information exceeds a preset threshold to determine whether the judgment conditions are met.

[0197] Among them, the functions of various components of the fault prediction device are explained in the method embodiment and will not be repeated in this embodiment.

[0198] In summary, the fault prediction device provided in this embodiment determines whether a fault occurs based on the number of erasures that occur in a period of time and the average period of erasures in the period of time. The determination can be made by performing only simple calculations, and the amount of data processing is small.

[0199] Corresponding to the above-mentioned embodiment of a fault prediction method provided by the present application, the present application also provides an electronic device and a readable storage medium corresponding to the fault prediction method.

[0200] The electronic device includes: a memory and a processor;

[0201] Wherein, the memory stores a processing program;

[0202] The processor is used to load and execute the processing program stored in the memory to implement each step of the fault prediction method as described in any one of the above items.

[0203] Wherein, the memory stores a processing program;

[0204] The processor is used to load and execute the processing program stored in the memory to implement each step of the fault prediction method as described in any one of the above items.

[0205] For details on the method for implementing the fault prediction of the electronic device, please refer to the aforementioned fault prediction method embodiment.

[0206] The readable storage medium stores a computer program thereon, and the computer program is called and executed by a processor to implement each step of the fault prediction method as described in any one of the above claims.

[0207] Specifically, the computer program stored in the readable storage medium is executed to implement the fault prediction method, and reference may be made to the aforementioned fault prediction method embodiment.

[0208] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device provided in the embodiment, since it corresponds to the method provided in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0209] The above description of the embodiments provided enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features provided herein.

Claims

1. A fault prediction method, comprising: Monitor the target storage chip and record the time and number of times the erasure occurs; Generate warning information based on the erasure time and number of times meeting the preset fault condition to warn that the target storage chip is in a dangerous state; The process of determining whether the erasure time and the number of erasures meet a preset fault condition includes: Based on the time and number of times the target memory chip is erased, analyzing and obtaining an average period of erasing the target memory chip within a preset time period, wherein the preset time period includes at least two average periods; Determine whether the number of times and the average period meet the preset fault condition; Based on the number of times and the average period satisfying the preset fault condition, determining that the erased information satisfies the preset fault condition; Wherein, judging whether the number and the average period meet the preset fault condition includes: Determine whether the number is greater than a preset first number threshold, and obtain a first determination result; Based on the first judgment result indicating that the number of times is greater than a preset first number threshold, judging whether the average period is less than a preset first period threshold, and obtaining a second judgment result; Based on the fact that the second judgment result indicates that the average period is less than a preset first period threshold, it is determined that the erasure information meets a preset fault condition.

2. According to the method of claim 1, the preset number threshold includes at least two number thresholds, and the preset period threshold includes at least two period thresholds; in, After the second judgment result indicates that the average period is less than a preset first period threshold, the method further includes: Based on the time when the target storage chip is erased, analyzing and obtaining the erase interval time of the target storage chip within a preset time period; Determine whether the erasing interval of the target storage chip within the preset time period meets a preset fixed period condition, and obtain a third determination result; Based on the third judgment result indicating that the erasure interval of the target storage chip within the preset time period meets the preset fixed period condition, it is determined that the erasure information meets the preset fault condition; Based on the third judgment result indicating that the erasing interval of the target storage chip within the preset time period does not meet the preset fixed period condition, judging whether the number of times is greater than a preset second number threshold, and obtaining a fourth judgment result, the second number threshold is greater than the first number threshold; Based on the fourth judgment result indicating that the number is greater than a preset second number threshold, judging whether the average period is less than a preset second period threshold, and obtaining a fifth judgment result that the second period threshold is greater than the first period threshold; Based on the fifth judgment result indicating that the average period is less than a preset second period threshold, it is determined that the erasure information meets a preset fault condition.

3. The method according to claim 1, wherein generating warning information to warn that the target storage chip is in a dangerous state comprises: Alarm information is generated and sent to a baseboard management controller, so that the baseboard management controller adds the alarm information to the web page configuration information, so that an alarm is issued on the web page.

4. The method according to claim 1, wherein generating warning information to warn that the target storage chip is in a dangerous state comprises: Generate warning information, and send the warning information to the operating system, so that the operating system can output display content on the display screen by configuring the extensible firmware interface parameters, and the display content is used to warn that the target storage chip is in a dangerous state.

5. A fault prediction device, comprising: A monitoring module is used to monitor the target storage chip and record the time and number of times the erasure occurs; An early warning module, used to generate an alarm message based on the time and number of erasures that meet a preset fault condition, so as to warn that the target storage chip is in a dangerous state; An analysis module, configured to analyze and obtain an average cycle of the target storage chip within a preset time period based on the time and number of times the target storage chip is erased, wherein the preset time period includes at least two average cycles; determine whether the number and the average cycle meet a preset fault condition; and determine that the erasure information meets the preset fault condition based on the number and the average cycle meeting the preset fault condition; The analysis module determines whether the number and the average period meet the preset fault condition, including: Determine whether the number is greater than a preset first number threshold, and obtain a first determination result; Based on the first judgment result indicating that the number of times is greater than a preset first number threshold, judging whether the average period is less than a preset first period threshold, and obtaining a second judgment result; Based on the fact that the second judgment result indicates that the average period is less than a preset first period threshold, it is determined that the erasure information meets a preset fault condition.

6. An electronic device comprising: Memory, processor; Wherein, the memory stores a processing program; The processor is used to load and execute the processing program stored in the memory to implement each step of the fault prediction method described in any one of 1-4 above.

7. A readable storage medium having a computer program stored thereon, wherein the computer program is called and executed by a processor to implement the steps of the fault prediction method according to any one of claims 1 to 4 above.

Images