Memory device and memory module including the memory device

Abstract

A memory device and a memory module including the memory device are provided. The memory device includes a peripheral circuit that communicates with a plurality of memory storage bodies. Each of the plurality of storage bodies includes: a memory cell array including a plurality of memory cells; a row decoder connected to the plurality of memory cells through a plurality of word lines; a bit line sense amplifier connected to the plurality of memory cells through a plurality of bit lines including a first bit line and a second bit line; and a column decoder configured to connect the bit line sense amplifier to the peripheral circuit. The memory cell array includes: a first segment connected to the first bit line and a second segment connected to the second bit line, and the first segment and the second segment are independent of each other with respect to row-related errors.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2020-0063542 filed on May 27, 2020, in the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the inventive concept generally relate to semiconductor memory devices, and more particularly, to memory systems and memory devices that provide improved error correction functions. Embodiments of the inventive concept relate to memory modules including at least one memory device that provides improved error correction functions. Background Art

[0003] The memory device may be variously configured to store data received from an external host device and thereafter provide the stored data in response to a request received from the external host device. One or more errors may occur when data is programmed (or written) to the memory device (when data is stored in the memory device) and / or when data is retrieved (or read) from the memory device.

[0004] One or more errors occurring in the data may cause system errors or processing failures in an external host device using the data. To prevent such failures, the external host device may include a data integrity function capable of detecting and / or correcting one or more errors.

[0005] As the data integrity functions provided by the external host device improve in their ability to detect and / or correct one or more errors, the probability of system errors or processing failures decreases. However, improved (or emerging) data integrity functions (e.g., data detection and / or correction functions) require considerable memory system resources. Summary of the invention

[0006] Embodiments of the inventive concept provide a memory device having a structure supporting an error correction function and a memory module having an improved error correction function or capable of reducing an amount of resources required for error correction by including the memory device.

[0007] According to one embodiment, a memory device includes: a plurality of memory bodies; and a peripheral circuit configured to receive commands and addresses from an external host device, transmit the commands and addresses to the plurality of memory bodies, and transfer data between the external host device and the plurality of memory bodies. Each of the plurality of memory bodies includes: a memory cell array including a plurality of memory cells; a row decoder connected to the plurality of memory cells through a plurality of word lines; a bit line sense amplifier connected to the plurality of memory cells through a plurality of bit lines including a first bit line and a second bit line; and a column decoder configured to connect the bit line sense amplifier to the peripheral circuit. The memory cell array includes: a first segment connected to the first bit line and a second segment connected to the second bit line, and the first segment and the second segment are independent of each other for row-related errors.

[0008] According to one embodiment, a memory module includes: a plurality of first memory devices; a second memory device; a driver configured to receive a command and an address from an external host device and transmit the command and the address to the plurality of first memory devices and the second memory device; and a power management circuit configured to receive an external power signal from the external host device, generate an internal power signal from the external power signal, and provide the internal power signal to at least one of the plurality of first memory devices, the second memory device, and the driver. Each of the plurality of first memory devices and the second memory device is configured to communicate data with the external host device according to a burst length, and each of the plurality of first memory devices and the second memory device provides two error-independent coverage ranges for the burst length, respectively.

[0009] According to one embodiment, a memory module includes: eight (8) first memory devices; a second memory device; a driver configured to receive commands and addresses from an external host device and transmit the commands and addresses to the first memory device and the second memory device; and a power management circuit configured to receive an external power signal from the external host device, generate an internal power signal from the external power signal, and provide the internal power signal to at least one of the first memory device, the second memory device, and the driver. Each of the first memory device and the second memory device is configured to communicate data with the external host device according to a burst length. Each of the first memory device and the second memory device provides at least two error-independent coverage ranges for the burst length, and the second memory device is configured to store a cyclic redundancy code and a parity check for correcting errors in data stored in at least one of the eight (8) first memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the inventive concepts may be better understood through the following detailed description considered together with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a computing system according to an embodiment of the inventive concept.

[0012] Figure 2 is a block diagram further illustrating a memory device 100 according to an embodiment of the inventive concept in one example.

[0013] Figure 3 is a block diagram further illustrating a bank 200 according to an embodiment of the inventive concept in one example.

[0014] Figure 4 It is further shown in the relevant part Figure 3 Conceptual diagram of a memory cell array.

[0015] Figure 5 is a conceptual diagram illustrating an example of reading data or an error correction code from a memory cell array during a read operation.

[0016] Figure 6 , Figure 7 , Fig. 9 , Fig.10 are respective conceptual diagrams variously illustrating examples of data blocks that can be used to communicate data or error correction codes with an external host device.

[0017] Figure 8 and Fig.11 are respective conceptual diagrams illustrating examples of data blocks including data, cyclic redundancy codes, and parities of a first memory device associated with a first channel of a memory module.

[0018] Fig.12 is a conceptual diagram illustrating one possible structure for supporting error-independent coverage or independent sections for row-dependent errors.

[0019] Fig.13 is a block diagram illustrating one example of a memory bank having an architecture for supporting error-independent coverage or independent sectors for row-related errors.

[0020] Fig.14 It further shows Fig.13 Conceptual diagram of a memory cell array.

[0021] Fig.15 is a block diagram illustrating an example of a memory bank having an architecture for supporting error-independent coverage or independent sectors for row-related errors.

[0022] Fig.16 It further shows Fig.15 Conceptual diagram of a memory cell array.

[0023] Fig.17 The operation of an embodiment according to the inventive concept is summarized in one example. Figure 1 A flowchart of a method of a computing system.

[0024] Fig.18 is an example that summarizes the embodiments according to the inventive concept. Figure 1 Flowchart of a read operation performed by a memory module.

[0025] Fig.19 is a block diagram illustrating a computing system according to an embodiment of the inventive concept.

[0026] Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 and Fig.25 is shown in various examples that can be used in Fig.19 Respective conceptual diagrams of communicating one or more blocks of data and / or error correction codes in a computing system. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the inventive concept may be described in detail and clearly to such an extent that a person having ordinary skill in the art can easily implement the inventive concept.

[0028] Figure 1 1 is a block diagram showing a computing system 1000 according to an embodiment of the inventive concept. Figure 1 , the computing system 1000 may include a memory module 1100 and an external host device 1200 .

[0029] The memory module 1100 may include a driver 1110 , first memory devices 1121 to 1125 , second memory devices 1126 to 1130 , a driver connector 1150 , first memory connectors 1161 to 1165 , second memory connectors 1166 to 1170 , a power management circuit 1180 , and a power connector 1190 .

[0030] The driver 1110 may communicate various signals with the external host device 1200 through the driver connector 1150. For example, the driver 1110 may transmit and / or receive (hereinafter, "communicate") one or more data signals (DQ), one or more commands (CMD), one or more addresses (ADDR), one or more clock signals (CK), one or more control signals (e.g., CTRL, DQS), etc. to the external host device 1200 (see, for example, Figure 2 ).

[0031] For example, the driver 1110 may receive various unidirectional signals from the external host device 1200 , exchange various bidirectional signals with the external host device 1200 , and / or transmit various unidirectional signals to the external host device 1200 .

[0032] In addition, the driver 1110 can send one or more command signals CMD and / or one or more addresses ADDR to the first memory devices 1121 to 1125 through the first channel CH1, and / or send one or more control signals CTRL received from the external host device 1200 to the first memory devices 1121 to 1125 through the first channel CH1.

[0033] The driver 1110 may also transmit control signals received from the first memory devices 1121 to 1125 to the external host device 1200 through the first channel CH1. Here, the control signal CTRL transmitted between the driver 1110 and the external host device 1200 may be the same, partially the same, or different from the control signal transmitted between the driver 1110 and the first memory devices 1121 to 1125.

[0034] The foregoing descriptions regarding the driver 1110 , the first memory devices 1121 to 1125 , and the first channel CH1 may be similarly applied to the driver 1110 , the second memory devices 1126 to 1130 , and the second channel CH2 .

[0035] In some embodiments, driver 1110 can be a register clock driver (RCD) defined according to one or more technical standards associated with one or more dual in-line memory modules (DIMMs) (such as, fifth generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) DIMMs).

[0036] The first memory devices 1121 to 1125 may communicate with the external host device 1200 through the first memory connectors 1161 to 1165. For example, the first memory devices 1121 to 1125 may transmit data signals DQ and data strobe signals DQS (eg, see Figure 2 ).

[0037] The second memory devices 1126 to 1130 may communicate with the external host device 1200 through the second memory connectors 1166 to 1170. For example, the second memory devices 1126 to 1130 may transfer a data signal DQ and a data strobe signal DQS with the external host device 1200.

[0038] In some embodiments, the first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may be DDR5 SDRAM. Therefore, the first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may communicate with the external host device 1200 using a protocol defined according to one or more technical standards associated with DIMMs (such as DDR5 SDRAM DIMMs).

[0039] The first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may simultaneously (e.g., at least partially overlap in time) receive the data signal DQ and may write the received data signal DQ according to a request of the external host device 1200. The first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may simultaneously read the data signal DQ and may write the read data signal DQ according to a request of the external host device 1200.

[0040] The first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may sequentially receive data signals DQ or sequentially transmit data signals DQ according to a defined burst length BL. For example, a burst length BL of 16 may be used according to one or more standards associated with a DDR5 SDRAM DIMM.

[0041] In some embodiments, the number of data signals DQ of the DDR5 SDRAM may be reduced compared to one or more existing memory devices (e.g., DDR4 SDRAM and outdated DDR memory devices). In contrast, the external host device 1200 may be configured to communicate 64-byte data signals DQ with one memory device. To support 64-byte compatibility, the first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may be configured to have a burst length BL of 16.

[0042] That is, the first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may continuously receive the data signal DQ for 16 time periods or may continuously send the data signal DQ for 16 time periods in response to one write request or one read request received from the external host device 1200. In some embodiments, each of the first memory devices 1121 to 1125 and each of the second memory devices 1126 to 1130 may be a (x8) memory device capable of communicating eight (8) data signals DQ with the external host device 1200.

[0043] The power management circuit 1180 may receive one or more external power signals from the external host device 1200 through the power connector 1190. Then, the power management circuit 1180 may generate one or more internal power signals from the one or more external power signals and provide the one or more internal power signals to the driver 1110, the first memory devices 1121 to 1125, and / or the second memory devices 1126 to 1130 variously.

[0044] In some embodiments, the power management circuit 1180 may be a power management integrated circuit (PMIC) designed according to one or more technical standards associated with DDR5 SDRAM DIMMs. Figure 1 In the illustrated example, it is assumed that the memory module 1100 is a registered DIMM (RDIMM). However, alternatively, the memory module 1100 may be an unbuffered DIMM (UDIMM), a load-reduced DIMM (LRDIMM), or a fully buffered DIMM (FBDIMM). In this regard, those skilled in the art will recognize that memory modules of different configurations may vary in constituent components and functionality compared to standard DIMMs (e.g., RDIMMs).

[0045] The external host device 1200 may include a processor 1210, a power supply 1220, a host power management circuit 1230, and a device driver 1240. The processor 1210 may include a general-purpose processor such as a central processing unit (CPU) and a dedicated processor such as an application processor (AP), a graphics processing unit (GPU), or a neuromorphic processor (NP).

[0046] The processor 1210 may include a memory controller 1211. The memory controller 1211 may control the memory module 1100 and may communicate with the memory module 1100. The communication with the external host device 1200 described with reference to the memory module 1100 may be performed by the memory controller 1211.

[0047] The memory controller 1211 may include an error correction circuit (ECC) 1212. The ECC 1212 may be configured to generate an error correction code. When the memory controller 1211 writes data DT to the memory module 1100, the memory controller 1211 may generate an error correction code for error correction from the data DT.

[0048] The memory controller 1211 may write data DT to the first memory devices 1121 to 1124 which are part of the first memory devices 1121 to 1125 (hereinafter, “first memory devices for data”), and may write error correction codes to the first memory device 1125 which is the remaining memory device of the first memory devices 1121 to 1125 (hereinafter, “first memory device for ECC”).

[0049] The memory controller 1211 may write data DT to the second memory devices 1127 to 1130 which are part of the second memory devices 1126 to 1130 (hereinafter, “second memory devices for data”), and may write error correction codes to the second memory device 1126 which is the remaining memory device of the second memory devices 1126 to 1130 (hereinafter, “second memory device for ECC”).

[0050] In some embodiments, the error correction code may include a cyclic redundancy code "C" for detecting errors and parity information "P" (hereinafter, "parity") for correcting detected errors (see, for example, Figure 7 ). The memory controller 1211 may read the data DT and the error correction code from the memory module 1100 and perform an error detection and correction function.

[0051] The power supply 1220 of the external host device 1200 may generate power required to variously drive the computing system 1000. The power may be provided to the host power management circuit 1230. The host power management circuit 1230 may generate internal power required to drive the external host device 1200. The host power management circuit 1230 may be a PMIC designed and manufactured according to the system requirements of the external host device 1200. The host power management circuit 1230 may supply internal power to the processor 1210 and components of the external host device 1200.

[0052] The device driver 1240 may control various additional devices under the control of the processor 1210. For example, the device driver 1240 may be connected with various devices such as a storage device, a modem, and a user interface device, and may arbitrate communications between the various devices and the processor 1210.

[0053] Here, the number of the first memory devices 1121 to 1125 and the number of the second memory devices 1126 to 1130 may be varied by design and are not limited to Figure 1 An example of what is shown.

[0054] Figure 2 1 is a block diagram further illustrating a memory device 100 according to an embodiment of the inventive concept in one example. Here, the exemplary memory device 100 may correspond to Figure 1 One of the first memory devices 1121 to 1125 and / or one of the second memory devices 1126 to 1130. In some embodiments, the first memory devices 1121 to 1125 and the second memory devices 1126 to 1130 may have the same structure and / or configuration, and may perform one or more of the same operations.

[0055] Reference Figure 1 and Figure 2 , the memory device 100 may include a first memory bank group BG1 and a second memory bank group BG2, wherein the first memory bank group BG1 includes first to fourth memory banks BANK1 to BANK4, and the second memory bank group BG2 includes first to fourth memory banks BANK1 to BANK4. Here, in some embodiments, each memory bank group and each memory bank may have the same structure and may perform the same one or more operations.

[0056] Each of the first to fourth memory banks BANK1 to BANK4 may include a plurality of memory cells, wherein the memory cells may be used to store data DT and / or an error correction code communicated with the external host device 1200 .

[0057] Figure 2 The memory device 100 also includes a peripheral circuit 110 capable of transmitting one or more data signals DQ and DQS, one or more control signals CTRL, one or more addresses ADDR, and / or one or more clock signals CK differently from the external host device 1200. In some embodiments, the peripheral circuit 110 may select a memory bank from among the first memory bank BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and / or the second memory bank group BG2 according to the received address ADDR. In an example, the peripheral circuit may transmit a command and an address to the first memory bank BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and / or the second memory bank group BG2.

[0058] Then, the peripheral circuit 110 may control the selected memory bank so that the operation (e.g., a write operation or a read operation) indicated by the received command CMD is performed on the memory cell indicated by the received address ADDR among the memory cells of the selected memory bank. Then, the peripheral circuit 110 may communicate the data signal DQ and / or the data strobe signal DQS with the external host device 1200, wherein the data strobe signal DQS may be used to control the latch timing of the data signal DQ.

[0059] The peripheral circuit 110 may include an input and output circuit 120 configured to exchange a data signal DQ and a data strobe signal DQS with an external host device 1200. The peripheral circuit 110 may also include a control logic 130 configured to control a selected memory bank in response to a command CMD, an address ADDR, a clock signal CK, and a control signal CTRL.

[0060] The number of memory bank groups and the number of memory banks within each memory bank group may vary with the design and is not limited to Figure 2 An example of what is shown.

[0061] Figure 3 2 is a block diagram further illustrating a memory bank 200 according to an embodiment of the inventive concept in one example. Here, the memory bank 200 may correspond to Figure 2 one of the first to fourth memory banks BANK1 to BANK4 of the first memory bank group BG1 and / or the second memory bank group BG2.

[0062] Reference Figure 1 , Figure 2 and Figure 3 , the memory bank 200 may include a memory cell array 210 , a row decoder 220 , a first bit line sense amplifier (BLSA) 240 , a second bit line sense amplifier 250 , and a column decoder 260 .

[0063] The memory cell array 210 may include memory cells arranged in a row direction and a column direction. The memory cell array 210 may include a 0th region R0 to a 15th region R15, wherein the 0th region R0 to the 15th region R15 may collectively correspond to a burst length BL of, for example, 16. However, as an example, assuming that the burst length BL is 8, the number of regions of the memory cell array 210 may be 8, and assuming that the burst length BL is 32, the number of regions of the memory cell array 210 may be 32.

[0064] The row decoder 220 may be connected to the memory cells in the row through word lines WL1 to WLn (where 'n' is a positive integer). The row decoder 220 may receive a row address RA of the address ADDR, and may select one of the first to nth word lines WL1 to WLn in response to the row address RA. For example, the row decoder 220 may apply a voltage (e.g., a positive voltage) for activation to the selected word line.

[0065] The first bit line sense amplifier 240 and the second bit line sense amplifier 250 may be connected to the memory cells in the column through the bit lines. The bit line connected to the first bit line sense amplifier 240 may be different from the bit line connected to the second bit line sense amplifier 250. For example, the first bit line sense amplifier 240 may be connected to the even (or odd) bit lines along the row direction, and the second bit line sense amplifier 250 may be connected to the odd (or even) bit lines along the row direction.

[0066] The first bit line sense amplifier 240 and the second bit line sense amplifier 250 may apply a voltage to the bit line or may sense the voltage of the bit line. By adjusting or sensing the voltage of the bit line, the first bit line sense amplifier 240 and the second bit line sense amplifier 250 may perform a write operation or a read operation on the memory cells of the selected row.

[0067] The column decoder 260 may receive a column address CA of the address ADDR. The column decoder 260 may electrically connect a portion of the bit line to the peripheral circuit 110 in response to the column address CA. In some embodiments, the column decoder 260 may output data DT or an error correction code ECC corresponding to a burst length BL of 16 by sequentially selecting the 0th region R0 to the 15th region R15 and outputting data read from memory cells of the sequentially selected regions.

[0068] For example, suppose Figure 3 The memory cell array 210 includes the 0th region R0 to the 15th region R15. However, the memory cell array 210 may include a plurality of sub-arrays, and each sub-array may include the 0th region R0 to the 15th region R15. During a write operation or a read operation, one of the plurality of sub-arrays may be selected, and the write operation or the read operation may be performed in the 0th region R0 to the 15th region R15 in the selected sub-array in units of a burst length BL.

[0069] exist Figure 3In the illustrated embodiment, it is assumed that the column decoder 260 is included in the memory bank 200. However, the column decoder 260 may be included in the peripheral circuit 110 instead of the memory bank 200. In the case where the column decoder 260 is included in the peripheral circuit 110, the column decoder 260 may control the input or output of the data DT or the error correction code ECC associated with one memory bank selected from the first memory bank BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2. That is, the column decoder 260 may be commonly applied to the first memory bank BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2.

[0070] Figure 4 is shown in the relevant part Figure 3 A conceptual diagram of a memory cell array 210. Figure 1 , Figure 2 , Figure 3 and Figure 4 , the memory cell array 210 may include memory cells MC (marked as small white circles). The memory cells MC may be connected to a sub-word line driver SD through a sub-word line SWL. The sub-word line driver SD may be connected to word lines (eg, third to sixth word lines WL3 to WL6).

[0071] The 0th region R0 to the 15th region R15 may respectively correspond to time periods associated with the burst length 16. That is, the memory cells of the 0th region R0 may correspond to the 0th data transferred in the 0th burst length BL0 of the 16 burst lengths BL, the memory cells of the 1st region R1 may correspond to the 1st data transferred in the 1st burst length BL1 of the 16 burst lengths BL, etc. Therefore, the 0th region R0 to the 15th region R15 may be said to correspond to the 0th burst length BL0 to the 15th burst length BL15, respectively.

[0072] In the 0th region R0, the memory cells MC corresponding to the fourth word line WL4 and the sixth word line WL6 may be connected to the sub word lines placed on the right side of the corresponding sub word line drivers SD. The memory cells MC corresponding to the third word line WL3 and the fifth word line WL5 may be connected to the sub word lines placed on the left side of the corresponding sub word line drivers SD.

[0073] During a write operation or a read operation, at least one of the sub word line drivers SD (or sub word lines SWL) connected to the selected word line may also be selected. A write operation or a read operation may be performed on a memory cell MC connected to a sub word line SWL connected to at least one selected sub word line driver SD, or a write operation or a read operation may be performed on a memory cell MC connected to at least one selected sub word line SWL.

[0074] In some embodiments, a decoding line for selecting at least one of the sub-word line drivers SD or at least one of the sub-word lines SWL connected to the selected word line may be further provided. The decoding line may be controlled by the row decoder 220 in response to the row address RA. Hereinafter, the decoding line will be omitted from the drawings for clarity.

[0075] Therefore, the sub-word line drivers SD connected to the third to sixth word lines WL3 to SW6 may be sequentially disposed on the left and right sides of the 0th region R0 along the column direction. Similarly, in each of the 1st to 15th regions R1 to R15, the sub-word line drivers SD may be sequentially disposed on the left and right sides of the corresponding region along the column direction.

[0076] In each of the 0th to 15th regions R0 to R15, the first bit line sense amplifier 240 may be connected to the even bit lines. In each of the 0th to 15th regions R0 to R15, the second bit line sense amplifier 250 may be connected to the odd bit lines.

[0077] In some embodiments, eight (8) memory cells MC may be connected to one sub-word line SWL. The memory cells MC connected to one sub-word line SWL may be written or read simultaneously. That is, the memory device 100 may receive or send eight (8) data signals DQ (e.g., eight (8) bits) at a time. In one example, the column decoder simultaneously sends data from two or more memory cells connected to a sub-word line selected from a plurality of sub-word lines to a peripheral circuit.

[0078] In some embodiments, multiple memory cell groups may be connected to one sub word line SWL. Each of the multiple memory cell groups may include memory cells MC corresponding to the number of data signals DQ simultaneously received or transmitted by the memory device 100 (eg, eight (8) memory cells MC).

[0079] During a write operation or a read operation, one of a plurality of memory cell groups connected to one sub word line SWL may be selected, and a write operation or a read operation may be performed on memory cells of the selected memory cell group.

[0080] Figure 5 2 is a conceptual diagram showing an example of reading data DT or error correction code ECC from the memory cell array 210 during a read operation. Figure 1 and Figure 5 , assuming that word line WL5 has been selected.

[0081] During the 0th burst length BL0 (during a time period corresponding to the 0th burst length BL0), data DT or error correction code ECC may be read from the memory cells MC in the 0th region R0 using the first bit line sense amplifier 240 and the second bit line sense amplifier 250. The data DT or error correction code ECC thus read may be simultaneously transmitted from the memory device 100 as a data signal DQ.

[0082] Thereafter, during the first to fifteenth burst lengths BL1 to BL15 , data DT or error correction codes ECC may be read from the first to fifteenth regions R1 to R15 , respectively, and the obtained data DT or error correction codes ECC may be simultaneously transmitted from the memory device 100 as data signals DQ.

[0083] Expanding on the above assumptions, for example, the memory device 100 may send eight (8) data signals (eg, data bits) DQ during sixteen (16) consecutive time periods corresponding to the entire burst length 16 .

[0084] The write operation may be performed similarly, except that the memory device 100 receives a sequence of data signals DQ instead of sending a sequence of data signals DQ. In this manner, data DT or error correction codes ECC may be written into the memory cells MC.

[0085] Figure 6 1 is a conceptual diagram showing an example of a data block that can be used to exchange data between each of the first memory devices 1121 to 1124 for data and the second memory devices 1127 to 1130 for data and the external host device 1200. Figures 1 to 6 , it is assumed that the memory device simultaneously receives or sends the first data signal DQ1 to the eighth data signal DQ8.

[0086] Therefore, the memory device may continuously receive or transmit the first to eighth data signals DQ1 to DQ8 during a number of time periods corresponding to the number of the 0th to 15th burst lengths BL0 to BL15, assuming again here that the burst length is 16. Under such an assumption, Figure 6 The data block may be understood as a unit in which the memory device 100 exchanges data DT including, for example, 128 bits with the external host device 1200 .

[0087] Furthermore, continuing the previous assumption that the memory module 1100 includes four (4) first memory devices 1121 to 1124 for data and four (4) second memory devices 1127 to 1130 for data, the memory module 1100 can exchange data DT with the external host device 1200 in units of 1024 bits.

[0088] Figure 7is a conceptual diagram showing another example of a data block that can be used to exchange data between each of the first memory device 1125 for ECC and the second memory device 1126 for ECC and the external host device 1200. Here again, it is assumed that Figure 6 As an example, a data block (e.g., 128 bits) is used. However, in Figure 7 In the example shown in FIG. 1 , half of the 128-bit data block (e.g., the first half corresponding to the 0th burst length BL0 to the 7th burst length BL7) can be used to transfer the cyclic redundancy code "C". In addition, the other half of the 128-bit data block (e.g., the second half corresponding to the 8th burst length BL8 to the 15th burst length BL15) can be used to transfer the parity check "P".

[0089] In this manner, the first memory device 1125 for ECC and the second memory device 1126 for ECC of the memory module 1100 may exchange error correction codes ECC (eg, including 256 bits) with the external host device 1200 .

[0090] Figure 8 1 is a conceptual diagram showing an example of five (5) data blocks transferred from the first memory devices 1121 to 1125 using the first channel CH1 of the memory module 1100, the five (5) data blocks including four (4) data blocks of data DT, a half block (1 / 2) cyclic redundancy code "C", and a half block (1 / 2) parity "P". In addition to the respective positions of the data blocks, the data blocks of the second memory devices 1126 to 1130 of the second channel CH2 may be the same as those of the reference numerals 1140 to 1141. Figure 8 Therefore, refer to Figures 1 to 8 , the first memory devices 1121 to 1125 of the first channel CH1 can communicate with the external host device 1200 in units of four (4) data blocks including data DT plus one (1) data block including (for example) a cyclic redundancy code "C" and a parity check "P".

[0091] Therefore, in the aforementioned example, in the data block of the first memory devices 1121 to 1125, the ratio of the first memory devices for data (e.g., 1121 to 1124) to the first memory device for ECC (e.g., 1125) is 4 to 1. And as a result, Figure 1 The RAS (reliability, availability, serviceability) coverage of the first memory devices 1121 to 1130 (assuming a x8 memory device transmitting eight (8) data signals DQ1 to DQ8) of the memory module 1100 can be understood as a single error correction double error detection (SECDED) type.

[0092] Fig. 9is a conceptual diagram showing an example in which a data block corresponding to data DT provides two or more error-independent coverages. Figure 1 , Figure 2 , Figure 3 and Fig. 9 As used in this context, the term "coverage" may be understood as a subset of data blocks, wherein each data block is a unit of data DT exchanged between the memory device 100 and the external host device 1200. For example, the 0th burst length BL0 to the 7th burst length BL7 (e.g., data blocks transferred during the 0th burst length BL0 to the 7th burst length BL7) may constitute a first coverage range, and the 8th burst length BL8 to the 15th burst length BL15 (e.g., data blocks transferred during the 8th burst length BL8 to the 15th burst length BL15) may constitute a second coverage range, wherein the first coverage range includes the first data DT1, and the second coverage range includes the second data DT2.

[0093] As an example, with this configuration, an error occurring in the first coverage will not affect the second coverage, and an error occurring in the second coverage will not affect the first coverage. Therefore, the first coverage and the second coverage may be referred to as "error-independent coverage". As a result, again extending the above working assumption, the memory device 100 may be referred to as providing two error-independent coverages for a burst length BL of 16. Those skilled in the art will also appreciate that in other embodiments of the inventive concept, more than two error-independent coverages may be provided for burst lengths of arbitrary lengths.

[0094] Refer again Figure 3 , the 0th region R0 to the 15th region R15 corresponding to the 0th burst length BL0 to the 15th burst length BL15, respectively, may be arranged along the row direction. Therefore, for row-dependent errors, two or more error-independent coverages may correspond to two or more "sections" independent of each other. Here, the term "section" refers to a subset within the memory cell array 210, wherein each section may include two or more regions of the 0th region R0 to the 15th region R15. Here, a row-dependent error may indicate an error occurring in a memory cell arranged along the row direction.

[0095] Fig.102 is a conceptual diagram showing an example in which an exemplary (e.g., 128-bit) data block including a cyclic redundancy code "C" and a parity check "P" can provide two or more error-independent coverage ranges. Here, the 0th burst length BL0 to the 7th burst length BL7 can constitute a first coverage range, and the 8th burst length BL8 to the 15th burst length BL15 can constitute a second coverage range.

[0096] Reference Figure 1 , Figure 2 , Figure 3 , Fig. 9 and Fig.10 , the data blocks of the first memory devices 1121 to 1124 for data may be data blocks for data, and the data blocks of the first memory device 1125 for ECC may be data blocks for ECC. When the data blocks for data provide error-independent coverage, the external host device 1200 may independently perform error correction encoding / error correction decoding on the error-independent coverage.

[0097] In this regard, error correction encoding may generate a cyclic redundancy code "C" and a parity check "P" from the data DT during a write operation. And during a read operation, error correction decoding may use the cyclic redundancy code "C" to detect one or more errors in the read data DT, and use the parity check "P" to correct the detected one or more errors.

[0098] like Fig.10 As shown in , a data block for ECC may include first and second cyclic redundancy codes C1 and C2 for a first coverage range of the data block for ECC, and first and second parities P1 and P2 for a second coverage range of the data block for ECC.

[0099] For example, the data block for ECC of the first channel CH1 may include a first cyclic redundancy code C1, a second cyclic redundancy code C2, a first parity check P1, and a second parity check P2 corresponding to the data block for data of the first channel CH1. The data block for ECC of the second channel CH2 may include a first cyclic redundancy code C1, a second cyclic redundancy code C2, a first parity check P1, and a second parity check P2 corresponding to the data block for data of the second channel CH2.

[0100] Fig.11 is shown with Figure 1 1 is a conceptual diagram of another example of data blocks of first memory devices 1121 to 1125 corresponding to one channel (e.g., first channel CH1) of the memory module 1100. In addition to the respective positions of the data blocks, data blocks of second memory devices 1126 to 1130 corresponding to another channel (e.g., second channel CH2) may be similar to the reference Fig.11The data blocks described are identical.

[0101] Reference Figure 1 , Figure 2 , Figure 3 , Fig. 9 , Fig.10 and Fig.11 , the data block for data belonging to the first memory device 1121 to 1124 for data may include the first data DT1 of the first coverage range 1121a to 1124a and the second data DT2 of the second coverage range 1121b to 1124b. For example, the data block for data belonging to the first memory device 1121 for data may include the first data DT1 of the first coverage range 1121a and the second data DT2 of the second coverage range 1121b.

[0102] The first coverage range 1125a of the data block for ECC belonging to the first memory device 1125 for ECC may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2, wherein the first cyclic redundancy code C1 corresponds to the first data DT1 of the first coverage range 1121a to 1124a of the data block for data, and the second cyclic redundancy code C2 corresponds to the second data DT2 of the second coverage range 1121b to 1124b of the data block for data.

[0103] The second coverage range 1125b of the data block for ECC belonging to the first memory device 1125 for ECC may include a first parity P1 and a second parity P2, wherein the first parity P1 corresponds to the first data DT1 of the first coverage range 1121a to 1124a of the data block for data, and the second parity P2 corresponds to the second data DT2 of the second coverage range 1121b to 1124b of the data block for data.

[0104] The first coverage range 1121a to 1124a and the second coverage range 1121b to 1124b are error-independent and, as a functional result, can be considered as independent, separate and different memories. Therefore, the data range on which the memory controller 1211 needs to perform error correction encoding / decoding can be effectively reduced.

[0105] Therefore, when the memory controller 1211 maintains the desired performance level for error detection and / or correction, the amount of cyclic redundancy code and parity check required can be reduced accordingly. For example, when the amount of data of the coverage range related to the error is equal to the total amount of data of two coverage ranges that are not related to the error, the amount of error correction code required to maintain the same level of error detection and / or correction performance can be halved because the two coverage ranges are not related to the error.

[0106] like Fig.11As shown in , the amount of cyclic redundancy code and the amount of parity check can be the same (with Figure 8 ). Therefore, the error correction performance of the memory controller 1211 can be improved. For example, the RAS coverage of the error-independent coverage of the memory module 1100 can be extended to single device data correction (SDDC). In an example, the first part of the first coverage 1125a of the data block for ECC (e.g., the first cyclic redundancy code C1) and the first part of the second coverage 1125b (e.g., the first parity P1) can provide the SDDC of the first coverage for each of the first memory devices 1121 to 1124, and the second part of the first coverage 1125a of the data block for ECC (e.g., the second cyclic redundancy code C2) and the second part of the second coverage 1125b (e.g., the second parity P2) can provide the SDDC of the second coverage for each of the first memory devices 1121 to 1124.

[0107] Since a data block can be implemented using two or more error-independent coverages, and since a memory cell can be divided into two independent segments for one or more row-related errors, the error correction capability of the memory module 1100 can be improved. Examples of two (2) error-independent coverages and two (2) independent segments have been described above, but those skilled in the art will recognize from the foregoing that embodiments of the inventive concept may include examples having more than two coverages and / or more than two segments. In this regard, as the number of error-independent coverages and / or the number of independent segments increases, the error correction capability of the memory module 1100 can be further improved.

[0108] Fig.12 is a conceptual diagram showing, in relevant parts, a memory cell array supporting error-independent coverage and / or independent banks for one or more row-related errors.

[0109] Reference Figure 1 , Figure 2 , Figure 3 and Fig.12 In the seventh region R7 and the eighth region R8 corresponding to the seventh burst length BL7 and the eighth burst length BL8, respectively, the sub-word line drivers SD may be set independently of each other. That is, the sub-word line SWL of the seventh region R7 may be driven independently of the sub-word line SWL of the eighth region R8.

[0110] Reference Figure 4In a comparative example, a memory cell array structure in which a sub-word line driver is shared between two regions may cause an error associated with the sub-word line driver SD shared by the 7th region R7 and the 8th region R8 to cause one or more errors in both the 7th region R7 and the 8th region R8. Fig.12 In the memory cell array structure of FIG. 1 , even if an error occurs at one of the sub-word line drivers SD associated with the 0th region R0 to the 7th region R7, the error will not affect the 8th region R8 to the 15th region R15. Likewise, an error occurring in one of the sub-word line drivers SD associated with the 8th region R8 to the 15th region R15 will not cause an error affecting the 0th region R0 to the 7th region R7.

[0111] Therefore, the 0th region R0 to the 7th region R7 and the 8th region R8 to the 15th region R15 are independent sections for row-related errors. In other words, the 0th burst length BL0 to the 7th burst length BL7 and the 8th burst length BL8 to the 15th burst length BL15 of the memory block provide two (2) error-independent coverage areas.

[0112] Fig.13 is a conceptual diagram showing an example of a memory bank 300 having a structure that supports multiple error-independent coverage or independent sectors for row-related errors. Figure 1 , Figure 2 and Fig.13 , the memory bank 300 may include a memory cell array 310 , a first row decoder 320 , a second row decoder 330 , a first bit line sense amplifier 340 , a second bit line sense amplifier 350 , and a column decoder 360 .

[0113] Here, the structure and operation of the memory bank 300 may be generally similar to that of the memory bank 300 except that both the first row decoder 320 and the second row decoder 330 are provided. Figure 3 The structure and operation of the memory bank 200 are the same.

[0114] Due to this structure, the first row decoder 320 can be connected to the 11th word line WL11 to the 1nth word line WL1n, wherein the 11th word line WL11 to the 1nth word line WL1n can be connected to the memory cells of the 0th region R0 to the 7th region R7. In a similar manner, the second row decoder 330 can be connected to the 21st word line WL21 to the 2nth word line WL2n, wherein the 21st word line WL21 to the 2nth word line WL2n can be connected to the memory cells of the 8th region R8 to the 15th region R15.

[0115] Fig.14 It is further shown in the relevant part Fig.13 A conceptual diagram of a memory cell array 310. Figure 1 , Figure 2 , Fig.13 and Fig.14 , (and as shown by the thick dotted lines), the 13th to 16th word lines WL13 to WL16 and the 23rd to 26th word lines WL23 to WL26 may be electrically and physically isolated between the 7th region R7 and the 8th region R8. Therefore, the sub-word line drivers SD in the 7th region R7 and the 8th region R8 are not shared.

[0116] In this regard, the 11th to 1nth word lines WL11 to WL1n (e.g., the first word line set) may pass through the first segment including the 0th region R0 to the 7th region R7, but may not pass through the second segment including the 8th region R8 to the 15th region R15. In addition, the 21st to 2nth word lines WL21 to WL2n (e.g., the second word line set) may pass through the second segment including the 8th region R8 to the 15th region R15, but may not pass through the first segment including the 0th region R0 to the 7th region R7. In one example, the memory cells of the first segment are electrically isolated from the second word line set, and the memory cells of the second segment are electrically isolated from the first word line set.

[0117] Reference Figure 3 , Fig.12 , Fig.13 and Fig.14 , due to the structure of the illustrated embodiment of the inventive concept, an error associated with a sub-word line driver SD belonging to the first segment including the 0th region R0 to the 7th region R7 will not affect the 8th region R8 to the 15th region R15 of the second segment. In a similar manner, an error associated with a sub-word line driver SD in the 8th region R8 to the 15th region R15 will not affect the 0th region R0 to the 7th region R7. In addition, an error caused by a fault occurring in the 11th word line WL11 to the 1nth word line WL1n will not affect the 8th region R8 to the 15th region R15, and an error caused by a fault occurring in the 21st word line WL21 to the 2nth word line WL2n will not affect the 0th region R0 to the 7th region R7. Therefore, error-independent coverage can also be provided for faults occurring at the word line level and faults occurring at the sub-word line driver level. Furthermore, a failure associated with the first row decoder 320 will not cause a failure associated with the second row decoder 330, and a failure associated with the second row decoder 330 will not cause a failure associated with the first row decoder 320. Thus, error-independent coverage may be provided for failures at the row decoder level.

[0118] Fig.15 is a conceptual diagram showing an example of a memory bank 400 having a structure that supports error-independent coverage or independent sectors for row-related errors. Figure 1 , Figure 2 and Fig.15, the memory bank 400 may include a memory cell array 410 , a row decoder 420 , a first bit line sense amplifier 440 , a second bit line sense amplifier 450 , and a column decoder 460 .

[0119] Here, the structure and operation of the memory bank 400 may be the same as that of the memory bank 400, except that the number of word lines WL1 to WL2n connected to the row decoder 420 has been doubled. Figure 3 The structure and operation of the memory bank 200 are the same.

[0120] Fig.16 It is further shown in the relevant part Fig.15 A conceptual diagram of a memory cell array 410. Figure 1 , Figure 2 , Fig.15 and Fig.16 , the first to 2n word lines WL1 to WL2n may be sequentially connected to memory cells of a first section including a 0th to 7th region R0 to R7 and memory cells of a second section including an 8th to 15th region R8 to R15.

[0121] In some embodiments, odd word lines including the fifth word line WL5, the seventh word line WL7, and the ninth word line WL9 may be connected to memory cells of the first segment including the 0th region R0 to the 7th region R7. Therefore, the odd word lines may pass through the second segment to reach the first segment. Similarly, even word lines including the sixth word line WL6, the eighth word line WL8, and the cross line WL10 may be connected to memory cells of the second segment including the 8th region R8 to the 15th region R15. In one example, the memory cells of the first segment are electrically isolated from the even word lines, and the memory cells of the second segment are electrically isolated from the odd word lines.

[0122] As reference Fig.12 As mentioned above, Fig.15 and Fig.16 With the described structure, an error occurring in a sub-word line driver SD belonging to the first segment including the 0th region R0 to the 7th region R7 will not affect the 8th region R8 to the 15th region R15 of the second segment. Furthermore, an error occurring in a sub-word line driver SD belonging to the second segment including the 8th region R8 to the 15th region R15 will not affect the 0th region R0 to the 7th region R7 of the first segment. Furthermore, an error associated with a failure occurring in an odd word line will not affect the 8th region R8 to the 15th region R15, and an error associated with a failure occurring in an even word line will not affect the 0th region R0 to the 7th region R7. Therefore, error-independent coverage can be provided for failures at the word line level and failures at the sub-word line driver level.

[0123] Fig.17 is outlined in an example for Figure 1 Flow chart of the operating method of the computing system 1000. Figure 1 and Fig.17 , the memory controller 1211 may detect power-on (S110). Then, the memory controller 1211 may identify the isolated x8 memory module operating according to the defined burst length BL (S120). For example, the memory controller 1211 may receive information indicating the attributes of the isolated x8 memory module and its burst length BL from a serial presence detect (SPD) of the memory module 1100.

[0124] An isolated x8 memory module may be a memory module such as: Figures 9 to 16 The example illustrated in the manner described supports two or more error-independent coverages for burst length BL (for example, two or more error-independent coverages for row-related errors), and an isolated x8 memory module may be based on a memory device that receives or sends data DT or error correction code ECC via eight (8) data signals (x8).

[0125] The memory controller 1211 may perform error correction coding on the first data DT1 corresponding to the first part (e.g., the first half) of the entire burst length BL to generate a first cyclic redundancy code C1 and a first parity check P1 (S130). In addition, the memory controller 1211 may perform error correction coding on the second data DT2 corresponding to the second part (e.g., the second half) of the entire burst length BL to generate a second cyclic redundancy code C2 and a second parity check P2 (S140).

[0126] The memory controller 1211 may write the first data DT1 and the second data DT2 to the first memory device (eg, the first memory devices 1121 to 1124 for data) during the first partial burst length and the second partial burst length (S150).

[0127] The memory controller 1211 may write the first cyclic redundancy code C1, the second cyclic redundancy code C2, the first parity P1 and the second parity P2 to the second memory device (eg, the first memory device 1125 for ECC) during the first partial burst length and the second partial burst length (S160).

[0128] In addition to the first channel CH1 , two or more of the aforementioned operation method steps (eg, S110 to S160 ) may be performed in full or in part in parallel for the second memory devices 1126 to 1130 using the second channel CH2 .

[0129] Fig.18 is outlined in an example that can be Figure 1Another flow chart of a read operation performed by the computing system 1000. Figure 1 and Fig.18 , the memory controller 1211 may receive third data from the first memory device (eg, the first memory devices 1121 to 1124 for data) and receive fourth data from the second memory device (eg, the first memory device 1125 for ECC) (S210).

[0130] The memory controller 1211 may then perform error correction decoding (S220) on a first partial burst length of the third data (e.g., data received during the first partial burst length) using a portion of the fourth data (e.g., the first cyclic redundancy code C1 and the first parity check P1), and the memory controller 1211 may perform error correction decoding (S230) on a second partial burst length of the third data (e.g., data received during the second partial burst length) using a remaining portion of the fourth data (e.g., the second cyclic redundancy code C2 and the second parity check P2).

[0131] Here, two or more of the read operation steps (eg, S210 to S230 ) may be fully or partially performed in parallel on the second memory devices 1126 to 1130 using the second channel CH2 in addition to the first channel CH1 .

[0132] Fig.19 2 is a block diagram showing a computing system 2000 according to an embodiment of the inventive concept. Fig.19 , the computing system 2000 may include a memory module 2100 and an external host device 2200 of the memory module 2100 .

[0133] The memory module 2100 may include a driver 2110, first memory devices 2121 to 2125 and 2131 to 2135, second memory devices 2126 to 2130 and 2136 to 2140, a driver connector 2150, first memory connectors 2161 to 2165, second memory connectors 2166 to 2170, a power management circuit 2180 and a power connector 2190.

[0134] The configuration and operation of the memory module 2100 may be similar to those of the first channel CH1 except that the number of the first memory devices 2121 to 2125 and 2131 to 2135 is 10 and the number of the second memory devices 2126 to 2130 and 2136 to 2140 of the second channel CH2 is increased from 5 to 10. Figure 1 The memory module 1100 is the same.

[0135] exist Fig.19In the illustrated embodiment, each of the first memory devices 2121 to 2125 and 2131 to 2135 and the second memory devices 2126 to 2130 and 2136 to 2140 may be implemented such that the number of memory cells MC connected to one sub-word line SWL is four (4).

[0136] Therefore, each of the first memory devices 2121 to 2125 and 2131 to 2135 and the second memory devices 2126 to 2130 and 2136 to 2140 may be a x4 memory device that communicates four (4) data signals DQ (eg, 4 bits) with the memory controller 2211. Figure 1 The eight (8) data signal DQ connectors used by an x8 memory device may be divided so that two vertically stacked memory devices may be used.

[0137] The external host device 2200 may include a processor 2210, a power supply 2220, a host power management circuit 2230, and a device driver 2240. The processor 2210 may include a memory controller 2211. The memory controller 2211 may include an error correction circuit 2212. The configuration and operation of the external host device 2200 may be similar to those described with reference to FIG. Figure 1 The configuration and operation of the external host device 1200 are described.

[0138] Fig. 20 It shows that Fig.19 21. A conceptual diagram of an example of a data block used by the first memory devices 2121 to 2125 and 2131 to 2135 and the second memory devices 2126 to 2130 and 2136 to 2140 of the memory module 2100. Fig.19 and Fig. 20 , the data block may include 512 bits corresponding to the first to fourth data signals DQ1 to DQ4 and the 0th to 15th burst lengths BL0 to BL15.

[0139] The first memory devices 2121 to 2124 and 2131 to 2134 for data and the second memory devices 2127 to 2130 and 2137 to 2140 for data may store data DT and may transfer the data DT with the memory controller 2211. The first memory devices 2125 and 2135 for ECC and the second memory devices 2126 and 2136 for ECC may store an error correction code ECC including a cyclic redundancy code “C” and a parity check “P” and may transfer the error correction code ECC with the memory controller 2211.

[0140] Fig.212 is a conceptual diagram showing an example of data blocks including data DT, cyclic redundancy code "C", and parity "P" of first memory devices 2121 to 2125 and 2131 to 2135 of one channel (e.g., first channel CH1) of memory module 2100. In addition to the respective positions of the data blocks, data blocks of second memory devices 2126 to 2130 and 2136 to 2140 of the second channel CH2 may be referred to as Fig.21 The data blocks described are identical.

[0141] Reference Fig.19 , Fig. 20 and Fig.21 , the first memory devices 2121 to 2125 and 2131 to 2135 of the first channel CH1 may communicate with the external host device 2200 in units of eight data blocks including data DT and two data blocks including a cyclic redundancy code “C” and a parity “P”.

[0142] As reference Fig.11 As described, two (2) error-independent memory devices for ECC may be provided for eight (8) error-independent memory devices for data. Thus, the RAS coverage of the memory module 2100 may be SDDC.

[0143] Fig. 22 is a conceptual diagram showing a data block for data for providing two or more error-independent coverage areas in one example. Fig.19 , Fig. 20 , Fig.21 and Fig. 22 , and as referenced Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 As described, two or more error-independent coverage areas may be provided based on two or more independent zones for row-related errors.

[0144] The first coverage corresponding to the 0th burst length BL0 to the 7th burst length BL7 may include the first data DT1. The second coverage corresponding to the 8th burst length BL8 to the 15th burst length BL15 may include the second data DT2.

[0145] Fig.23 is a conceptual diagram showing a data block for ECC that provides two or more error-independent coverages in one example. Fig.19 , Fig. 20 , Fig.21 , Fig. 22 and Fig.23 , and as referenced Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 As described, two or more error-independent coverage areas may be provided based on two or more independent zones for row-related errors.

[0146] The first coverage corresponding to the 0th burst length BL0 to the 7th burst length BL7 may include the first cyclic redundancy code C1 and / or the first parity check P1 corresponding to the first data DT1. The second coverage corresponding to the 8th burst length BL8 to the 15th burst length BL15 may include the second cyclic redundancy code C2 and / or the second parity check P2 corresponding to the second data DT2.

[0147] Fig.24 2 is a conceptual diagram showing data blocks of first memory devices 2121 to 2125 and 2131 to 2135 associated with one channel (e.g., first channel CH1) of memory module 2100 in one example. In addition to the respective positions of the data blocks, data blocks of second memory devices 2126 to 2130 and 2136 to 2140 of second channel CH2 may be similar to those of reference 1. Fig.24 The data blocks described are the same.

[0148] Reference Fig. 22 , Fig.23 and Fig.24 , the data block for data belonging to the first memory devices 2121 to 2124 and 2131 to 2134 for data may include the first data DT1 of the first coverage range 2121a to 2124a and 2131a to 2134a and the second data DT2 of the second coverage range 2121b to 2124b and 2131b to 2134b. For example, the data block for data belonging to the first memory device 2121 for data may include the first data DT1 of the first coverage range 2121a and the second data DT2 of the second coverage range 2121b.

[0149] and Fig.21 Compared with the data block of the memory device, the range of the space irrelevant to the error is reduced from the memory device level to the coverage level. Therefore, the range in which the memory controller 2211 can perform error correction encoding and error correction decoding can be reduced. Fig.11 As described, the amount of cyclic redundancy code and parity checks required by the memory controller 2211 to maintain a desired level of error correction performance can be reduced by half.

[0150] like Fig.24 As shown in Fig.21Compared to the example shown in FIG. 1 , the amount of the first cyclic redundancy code C1 and the second cyclic redundancy code C2 and the amount of the first parity check and the second parity check can be halved. Therefore, even if one of the first memory devices 2125 and 2135 for ECC is removed from the memory module 2100, the RAS of the memory module 2100 can maintain the SDDC.

[0151] In a state where the RAS of the SDDC is maintained, the memory module 2100 may remove one of the first memory devices 2121 to 2125 and 2131 to 2135, and may remove one of the second memory devices 2126 to 2130 and 2136 to 2140. Therefore, in a state where the performance of the memory module 2100 is maintained, the cost of the memory module 2100 may be reduced. In addition, the power consumption of the memory module 2100 may be reduced.

[0152] The connector for the removed first memory device and the data signal and the data strobe signal assigned to the removed first memory device may be used for the driver 2110 to send a signal for notifying the external host device 2200 of information about the state of the memory module 2100 or to send any other necessary signal. Therefore, the flexibility of the memory module 2100 can be improved.

[0153] The memory module 1100 according to an embodiment of the inventive concept may include a x8 memory device and may extend the RAS from SECDED to SDDC without reducing bandwidth or degrading performance. In addition, the memory module 2100 according to an embodiment of the inventive concept may include a x4 memory device and may maintain the RAS at SDDC in a state where one memory device is used to store an error correction code ECC without reducing bandwidth or degrading performance.

[0154] Fig.25 2 is a conceptual diagram showing data blocks of first memory devices 2121 to 2125 and 2131 to 2135 associated with one channel (e.g., first channel CH1) of the memory module 2100 in another example. In addition to the respective positions of the data blocks, data blocks of second memory devices 2126 to 2130 and 2136 to 2140 of the second channel CH2 may be similar to those of the reference numeral 2140. Fig.25 The data blocks described are the same.

[0155] Reference Fig.19 , Fig. 22 , Fig.23 and Fig.25, the data block for data belonging to the first memory devices 2121 to 2124 and 2131 to 2134 for data may include the first data DT1 of the first coverage range 2121a to 2124a and 2131a to 2134a and the second data DT2 of the second coverage range 2121b to 2124b and 2131b to 2134b. For example, the data block for data belonging to the first memory device 2121 for data may include the first data DT1 of the first coverage range 2121a and the second data DT2 of the second coverage range 2121b.

[0156] and Fig.21 Compared with the data block of the memory device, the range of the space irrelevant to the error is reduced from the memory device level to the coverage level. Therefore, the range in which the memory controller 2211 can perform error correction encoding and decoding can be reduced. Fig.11 As described, the amount of cyclic redundancy code and parity check required by the memory controller 2211 to maintain error correction performance can be reduced by half.

[0157] like Fig.25 As shown in FIG. , the amount of the first cyclic redundancy code C1 and the second cyclic redundancy code C2 and the amount of the first parity check and the second parity check can be maintained as Fig.21 The same as the example shown in FIG. Fig.21 Compared with the example of , the error correction performance and RAS of the memory module 2100 can be improved.

[0158] The foregoing embodiments describe specific locations within a data block where cyclic redundancy codes "C" and parity checks "P" may be stored. However, such locations may vary with design, and the inventive concept is not limited to the examples shown. In some embodiments, the arrangement and location of the cyclic redundancy codes "C" and parity checks "P" stored in a data block may be randomly determined by an external host device.

[0159] In the aforementioned embodiments, components according to the inventive concept have been described according to "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other without limiting the inventive concept. For example, the terms "first", "second", "third", etc. do not refer to any form of order or numerical meaning.

[0160] In the above embodiments, the components according to the embodiments of the inventive concept are described by using blocks. The blocks can be implemented with various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven by hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits registered as intellectual property (IP) blocks.

[0161] According to an embodiment of the inventive concept, a memory device has been described as including segments whose row-related errors are independent of each other. Therefore, a memory device having a structure supporting an error correction function is provided. In addition, a memory device including segments whose row-related errors are independent of each other can provide two or more error-independent coverages for data corresponding to a burst length. Therefore, a memory module having an improved error correction function or capable of reducing the amount of resources required for error correction is provided.

[0162] While the inventive concept has been described with reference to exemplary embodiments of the inventive concept, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A memory device, comprising: Multiple storage banks; and a peripheral circuit configured to receive commands and addresses from an external host device, transmit the commands and addresses to the plurality of memory banks, and transfer data between the external host device and the plurality of memory banks, Wherein, each of the plurality of storage banks comprises: a memory cell array comprising a plurality of memory cells; a row decoder connected to the plurality of memory cells via a plurality of word lines; A bit line sense amplifier connected to the plurality of memory cells through a plurality of bit lines including a first bit line and a second bit line; and a column decoder configured to connect the bit line sense amplifier to a peripheral circuit, The memory cell array includes a first section connected to a first bit line and a second section connected to a second bit line, and The first section and the second section are independent of each other with respect to row-related errors.

2. The memory device according to claim 1, wherein: The memory cell array includes a plurality of regions corresponding to burst lengths, and The plurality of regions are divided into a first section and a second section.

3. The memory device according to claim 2, wherein: The burst length is 16.

4. The memory device according to claim 3, wherein: The first section includes the 0th to 7th regions, and the second section includes the 8th to 15th regions.

5. The memory device according to any one of claims 1 to 4, wherein: The plurality of memory cells are connected to a plurality of sub word lines connected to the plurality of word lines through a plurality of sub word line drivers, and the first segment and the second segment are connected to different sub word lines and different sub word line drivers.

6. The memory device according to claim 5, wherein: Each of the plurality of word lines is commonly connected to a sub word line driver of the first segment and a sub word line driver of the second segment.

7. The memory device according to claim 5, wherein: The column decoder simultaneously transmits data from two or more memory cells connected to a sub-word line selected from the plurality of sub-word lines to a peripheral circuit.

8. The memory device according to any one of claims 1 to 4, wherein: The row decoder connected to the plurality of memory cells through the plurality of word lines comprises: A first row decoder connected to a first memory cell belonging to a first section through a first word line; and The second row decoder is connected to the second memory cell belonging to the second section through the second word line.

9. The memory device according to claim 8, wherein: The first memory cell is electrically isolated from the second word line, and the second memory cell is electrically isolated from the first word line.

10. The memory device according to claim 8, wherein: The first word line does not pass through the second segment, and the second word line does not pass through the first segment.

11. The memory device according to any one of claims 1 to 4, wherein: The plurality of word lines include a first word line and a second word line different from the first word line, The plurality of memory cells include: a first memory cell included in a first section and connected to a first word line; and a second memory cell included in a second section and connected to a second word line, the second memory cell being different from the first memory cell.

12. The memory device according to claim 11, wherein: The first memory cell is electrically isolated from the second word line, and the second memory cell is electrically isolated from the first word line.

13. The memory device according to claim 11, wherein: The second word line passes through the first section.

14. A memory module, comprising: a plurality of first memory devices; a second memory device; a driver configured to receive a command and an address from an external host device and transmit the command and the address to the plurality of first memory devices and second memory devices; and a power management circuit configured to receive an external power signal from an external host device, generate an internal power signal from the external power signal, and provide the internal power signal to at least one of the plurality of first memory devices, the second memory device, and the driver, wherein each of the plurality of first memory devices and second memory devices is configured to communicate data with an external host device according to a burst length, and Each of the plurality of first memory devices and second memory devices provides two error-independent coverage ranges for burst lengths, respectively.

15. The memory module according to claim 14, wherein: The plurality of first memory devices include four memory devices configured to store data received from an external host device, and The second memory device is configured to store a cyclic redundancy code and a parity check for correcting errors in the data stored in the four memory devices.

16. The memory module according to claim 15, wherein: Each of the plurality of first memory devices and second memory devices is configured to transmit eight bits of data simultaneously.

17. The memory module according to claim 15, wherein: The two error-independent coverage areas of the second memory device include a first coverage area and a second coverage area, the two error-independent coverage ranges of each of the plurality of first memory devices include a third coverage range and a fourth coverage range, The first portion of the first coverage and the first portion of the second coverage among the cyclic redundancy code and the parity check provide single device data correction of a third coverage for each of the plurality of first memory devices, and The second portion of the first coverage and the second portion of the second coverage among the cyclic redundancy code and the parity provide single device data correction of a fourth coverage for each of the plurality of first memory devices.

18. The memory module according to claim 17, wherein: The first coverage range and the third coverage range correspond to a first portion of the burst length, and The second coverage range and the fourth coverage range correspond to a second portion of the burst length.

19. A memory module comprising: eight first memory devices; a second memory device; a driver configured to receive commands and addresses from an external host device and transmit the commands and addresses to the eight first memory devices and second memory devices; and a power management circuit configured to receive an external power signal from an external host device, generate an internal power signal from the external power signal, and provide the internal power signal to at least one of the eight first memory devices, the second memory devices, and the driver, wherein each of the eight first memory devices and the second memory devices is configured to communicate data with an external host device according to a burst length, wherein each of the eight first memory devices and the second memory devices provides at least two error-independent coverage ranges for burst lengths, and The second memory device is configured to store a cyclic redundancy code and a parity check for correcting errors in data stored in at least one of the eight first memory devices.

20. The memory module according to claim 19, wherein: The burst length is 16, and each of the eight first memory devices and second memory devices is configured to send four bits of data simultaneously.

Images