Semiconductor Structure and Method of Forming the Same

Abstract

The method includes: providing a substrate having a first semiconductor material; creating a mask covering the nFET region of the substrate; etching the pFET region of the substrate to form trenches; epitaxially growing a second semiconductor material in the trenches, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to create a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material, and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material and the bottom portion includes the first semiconductor material. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The electronics industry has an increasing demand for smaller and faster electronic devices that can simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to fabricate low-cost, high-performance, and low-power ICs. So far, these goals have been largely achieved by reducing the IC size (e.g., the minimum IC component size), thereby improving production efficiency and reducing related costs. However, such scaling also increases the complexity of the IC manufacturing process. Therefore, achieving continuous progress in IC devices and their performance requires similar progress in IC manufacturing processes and technologies.

[0003] FinFET devices have been introduced to increase gate-channel coupling, reduce off-state current, and reduce short-channel effects (SCEs) above planar transistors. As device scaling continues, such as at the 5 nm and 3 nm process nodes, traditional silicon-based FinFETs are also approaching their performance limits. For example, extremely compact gate sizes and extremely small device volumes make doping and strain engineering for performance very challenging for FinFET devices. There is an urgent need to improve FinFET fabrication. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor structure, including: providing a substrate having a first semiconductor material; creating a mask covering an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material, and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; a first fin extending from the substrate; and a second fin extending from the substrate, wherein the second fin includes a top portion above a bottom portion, the bottom portions of the first fin and the second fin include crystalline silicon, the top portion of the second fin includes a semiconductor material having a higher charge carrier mobility than silicon, the top surfaces of the second fin and the first fin are substantially coplanar, and the bottom portion of the second fin extends deeper into the substrate than the first fin.

[0006] Some further embodiments of the present application provide a semiconductor structure, including: a substrate; two first fins adjacent to each other and extending from a first region of the substrate; two second fins adjacent to each other and extending from a second region of the substrate; and an isolation structure located above the substrate and adjacent to the first fins and the second fins, wherein each of the second fins includes a top portion above a bottom portion, the bottom portions of the first fins and the second fins include crystalline silicon, the top portions of the second fins include silicon germanium, the top surfaces of the second fins and the first fins are substantially coplanar, and each of the second fins is higher than the first fins. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A and Figure 1B show a flowchart of a method for forming a semiconductor device according to various aspects of the present invention.

[0009] Figure 2A 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6 、 Figure 7 、 Figure 9B 、 Figure 10 and Figure 11 show a cross-sectional view of a portion of a semiconductor device in an intermediate step of manufacturing according to an embodiment of the method according to Figures 1A to 1B and in accordance with some embodiments.

[0010] Figure 2B show a top view of a portion of a semiconductor device according to some embodiments.

[0011] Figure 8 and Figure 9AA perspective view of a portion of a semiconductor device in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components may be formed between the first and second components such that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented otherwise (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, when a numerical value or numerical range is described using "about", "substantially", etc., such term includes values within certain variations (such as + / - 10% or other variations) of the described numerical value, according to the knowledge of those skilled in the art considering the specific technology disclosed herein, unless otherwise specified. For example, the term "about 5 nm" may include a size range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0014] This application generally relates to semiconductor structures and manufacturing processes, and more particularly to CMOS (complementary metal oxide semiconductor) devices having p-channel FinFET transistors and n-channel FinFET transistors. The object of the present invention is to provide a method for forming p-channel fins and n-channel fins on the same substrate, wherein the n-channel fins comprise a first semiconductor material, and the p-channel fins comprise a second semiconductor material having a higher charge carrier (e.g., hole) mobility than the first semiconductor material. In an embodiment of the present invention, the first semiconductor material is single-crystalline silicon, and the second semiconductor material is a silicon-germanium alloy. In an embodiment, the p-channel fins are used to form p-type FinFETs, and the n-channel fins are used to form n-type FinFETs. Using p-channel fins further enhances the performance of the p-type FinFETs compared to methods where n-type FinFETs and p-type FinFETs use the same material in their channels. Embodiments of the present invention also optimize the etching of the p-channel fins and the n-channel fins by the same etching process, thereby forming p-channel fins and n-channel fins having closely matched critical dimensions and closely matched fin heights. This further improves the flatness of the isolation structure between the p-channel fins and the n-channel fins. The flatness of the isolation structure in turn improves subsequent manufacturing processes, such as gate formation. Those of ordinary skill in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein.

[0015] Figure 1A is a flowchart of a method 10 for manufacturing a semiconductor device according to various aspects of the present invention. The present invention contemplates additional processing. Additional operations may be provided before, during, and after method 10, and for additional embodiments of method 10, some of the described operations may be moved, replaced, or eliminated.

[0016] The following is combined with Figures 2A to 11 describe method 10, Figures 2A to 11Shows various views of a semiconductor device (or semiconductor structure) 100 at various steps of manufacturing according to Method 10 in accordance with some embodiments. In some embodiments, device 100 is part of an IC chip, a system-on-chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs or pFETs), n-type field-effect transistors (NFETs or nFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. For clarity, Figures 2A to 11 , to better understand the inventive concept of the present invention. Additional components may be added to device 100, and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 100.

[0017] In operation 12, Method 10 ( Figure 1A ) provides or is provided with a substrate 102, such as Figure 2A shown. In the depicted embodiment, substrate 102 is a silicon substrate, such as a silicon wafer having crystalline silicon. Optionally, substrate 102 may include: another elemental semiconductor such as germanium; compound semiconductors including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors including silicon-germanium, gallium phosphide arsenide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium phosphide arsenide; or combinations thereof.

[0018] In operation 14, Method 10 ( Figure 1A ) forms a patterned mask 103 over substrate 102, such as Figure 2A and Figure 2B shown. According to an embodiment, Figure 2A shows the patterned mask 103 and the substrate 102 in a cross-sectional view in the "X-Z" plane, while Figure 2BThe patterned mask 103 and the substrate 102 are shown in a top view in the “X - Y” plane. The patterned mask 103 covers the substrate 102 in the nFET region and exposes the substrate 102 in the pFET region. In the present invention, an n - type transistor such as an n - type FinFET will be formed in the nFET region, and a p - type transistor such as a p - type FinFET will be formed in the pFET region. The n - type transistor and the p - type transistor can be coupled to form a CMOS device. In the present embodiment, the patterned mask 103 is shown as having parallel rectangular stripes. In alternative embodiments, the patterned mask 103 can have other shapes and configurations. The patterned mask 103 can be formed using one or more lithography processes including double - patterning or multi - patterning processes. In various embodiments, the patterned mask 103 can include silicon oxide, silicon nitride, photoresist, or other suitable materials.

[0019] In operation 16, method 10( Figure 1A ) etches the substrate 102 through the patterned mask 103, thereby forming trenches 102’ in the substrate 102, such as according to the embodiment Figure 3 shown. Trenches 102’ are formed in the pFET region ( Figure 3 one of those shown), while the substrate 102 remains intact or substantially intact in the nFET region under the patterned mask 103. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process can implement oxygen - containing gases, fluorine - containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine - containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine - containing gases (e.g., HBr and / or CHBR3), iodine - containing gases, other suitable gases, and / or plasmas and / or combinations thereof. For example, the wet etching process can include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. In an embodiment, the etching process is anisotropic, such that the boundary between the nFET region and the pFET region can be well maintained during operation 16. In some embodiments, the depth of the trenches 102’ is controlled to be in the range of about 40 nm to about 70 nm along the “Z” direction from the top surface of the substrate 102. This range is intended to provide an appropriate semiconductor thickness for forming fins, which will be discussed later. In the present embodiment, the depth of the trenches 102’ can be controlled using a timer and depends on the etching rate of the material in the substrate 102 in the etching process.

[0020] In operation 18, according to an embodiment, method 10( Figure 1A)Epitaxially grow semiconductor material in the trench 102' to form a semiconductor layer 104 over the substrate 102 in the pFET region, such as Figure 4 shown. In this embodiment, the semiconductor material in the semiconductor layer 104 has a higher charge carrier mobility (or simply mobility) than the material in the substrate 102. In this embodiment, the substrate 102 includes crystalline silicon, and the semiconductor layer 104 includes silicon germanium (SiGe) having a higher hole mobility than crystalline silicon. This is applicable to creating high-performance pFETs in the pFET region and high-performance nFETs in the nFET region. In a further embodiment, the silicon germanium in the semiconductor layer 104 has a constant or nearly constant percentage of germanium atoms (at. %). In a further embodiment, the silicon germanium in the semiconductor layer 104 has a constant or nearly constant percentage of germanium atoms in the range of about 15 at. % to about 30 at. %. In other words, the semiconductor layer 104 includes Si 1-x Ge x , where x is in the range of 15 at. % to 30 at. %. When a portion of the semiconductor layer 104 is used as the FinFET transistor channel, the range of Ge at. % is intended to provide an appropriate performance enhancement. In another embodiment, the semiconductor layer 104 includes silicon germanium (SiGe) having a graded Ge at. %. For example, the Ge at. % in the semiconductor layer 104 can gradually increase as the semiconductor layer 104 is grown to adjust the crystal quality. In such an instance, when the growth of the semiconductor layer 104 is completed, the lower portion (close to the substrate 102) of the semiconductor layer 104 has a lower Ge at. % than the upper portion of the semiconductor layer 104. In various embodiments, depending on the material in the substrate 102, the material in the semiconductor layer 104 can include silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium phosphoarsenide, indium aluminum phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium phosphoarsenide, or a combination thereof. In an embodiment, the epitaxial growth of the semiconductor layer 104 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metalorganic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

[0021] After the growth of the semiconductor layer 104 is completed, operation 18 removes the patterned hard mask 103 and planarizes the top surface of the device 100, for example, using chemical mechanical planarization (CMP). As Figure 4As shown, the top surface of the semiconductor layer 104 (in the pFET region) and the top surface of the substrate 102 in the nFET region are coplanar or substantially coplanar. In an embodiment, the height (or thickness) h1 of the semiconductor layer 104 in the Z direction is in the range of about 40 nm to about 70 nm. This height range is intended to provide sufficient sidewall surface area for the pFET fin channel, which is approximately twice the product of the height h1 and the fin channel length (or gate length Lg). It is also intended to provide a good aspect ratio for the pFET fin (which is the ratio of the height h1 of the pFET fin to the width) to achieve stable manufacturability. If the height h1 is too small (such as less than 40 nm), the pFET fin generated by the semiconductor layer 104 may not have sufficient surface area for current conduction, which will result in a decrease in pFET performance. If the height h1 is too large (such as greater than 70 nm), the aspect ratio of the pFET fin generated by the semiconductor layer 104 may be undesirably high, and the pFET fin may be prone to collapse during manufacturing.

[0022] In operation 20, method 10 ( Figure 1A ) forms a hard mask 105 for etching the substrate 102 and the semiconductor layer 104 to form fins. The hard mask 105 is also referred to as the fin hard mask 105. Operation 20 involves Figure 5A 、 Figure 5B and Figure 5C the respective steps shown. Referring to Figure 5A , operation 20 forms hard mask layers 105A, 105B, and 105C above the top surfaces of the substrate 102 and the semiconductor layer 104. In an embodiment, the hard mask layer 105A includes an oxide that can be formed by oxidizing the top surfaces of the substrate 102 and the semiconductor layer 104 or by deposition (such as chemical vapor deposition (CVD)); the hard mask layer 105B includes a nitride such as silicon nitride (Si3N4) that can be formed by CVD; and the hard mask layer 105C includes an oxide such as silicon dioxide (SiO2) that can be formed by CVD. Still referring to Figure 5A , operation 20 further forms a patterned mask 105D above the hard mask layer 105C. The patterned mask 105D can be formed using one or more lithography processes including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thus allowing the creation of patterns with, for example, pitches smaller than those achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above the hard mask layer 105C and patterned using a lithography process. A spacer is formed beside the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacer or mandrel becomes the patterned mask 105D. In various embodiments, the patterned mask 105D can include silicon oxide, silicon nitride, or other suitable materials.

[0023] Reference Figure 5B , in some embodiments, operation 20 forms a capping layer 105E over the patterned mask 105D and the hard mask layer 105C. In an embodiment, the capping layer 105E includes silicon nitride or other suitable material and is deposited using atomic layer deposition (ALD). The thickness of the capping layer 105E is controlled to adjust the size of the combined hard mask 105 (e.g., the combined size of the hard masks 105D and 105E in the "X" direction) to meet the target fin width. In some embodiments, the capping layer 105E is omitted in operation 20. Reference Figure 5C , the combined hard masks 105D and 105E are used as an etch mask to etch the hard mask layers 105C, 105B, and 105A, and the combined hard masks 105D and 105E are consumed by the etching process or removed after the etching process is completed. At this stage, the fin hard mask 105 includes the patterned hard masks 105A, 105B, and 105C.

[0024] In operation 22, method 10( Figure 1A ) etches the substrate 102 and the semiconductor layer 104 to form an nFET fin 108n in the nFET region and a pFET fin 108p in the pFET region. According to an embodiment, the resulting structure is in Figure 6Shown in. When etching the substrate 102 and the semiconductor layer 104, the fin hard mask 105 is used as an etching mask. An etching process that provides the same etching rate for the semiconductor layer 104 and the substrate 102 is desirable for operation 22 to produce fins 108n and 108p with the same dimensions. However, since the semiconductor layer 104 and the substrate 102 comprise different materials, they typically etch at different rates in the same etching process in practice. For example, when the semiconductor layer 104 comprises SiGe and the substrate 102 comprises crystalline Si, in a typical dry etching process, the semiconductor layer 104 can be etched faster than the substrate 102. Thus, when a common etching process is used to etch the nFET and pFET regions, the pFET fin 108p can be narrower and taller than the nFET fin 108n. When the difference between the dimensions (such as height and width) of the pFET fin 108p and the nFET fin 108n is large (such as greater than 30%), this poses challenges to subsequent manufacturing processes and may reduce the production yield. In this embodiment, operation 22 implements an iterative etching process comprising multiple steps of dry etching and chemical treatment such that nFET fins 108n and pFET fins 108p with closely matched dimensions (such as fin widths w1 and w2 that are closely matched in the "X" direction and fin heights h3 and h4 that are closely matched in the "Z" direction) can be formed simultaneously. This generally improves the production yield while producing fins 108n and 108p with acceptable matched dimensions (e.g., the mismatch is less than 25%). Additionally, compared to a method of etching the pFET fin 108p and the nFET fin 108n in different etching processes (e.g., forming a mask covering the pFET region while etching the nFET region and vice versa, which requires separately forming fin hard masks 105 for the nFET region and the pFET region), this embodiment saves manufacturing costs and produces a fin hard mask 105 with better pattern uniformity by using one lithography process to form the fin hard mask 105.

[0025] Figure 1B FIG. shows a flowchart of operation 22 using an iterative etching process according to an embodiment. Refer to Figure 1B, Operation 22 includes step 30, where anisotropic etching is simultaneously performed on both the pFET region and the nFET region. In an embodiment, the anisotropic etching uses HBr gas, Cl2 gas, Ar gas, other suitable gases, or a mixture thereof to perform a dry etching process. The gas flow rate, etching time, and other etching parameters (such as temperature and pressure) of the anisotropic etching are controlled to produce the initial structures of the pFET fin 108p and the nFET fin 108n. For example, step 30 can etch the pFET region and the nFET region a few nanometers deep. Then, operation 22 proceeds to step 32, where isotropic etching is simultaneously performed on both the pFET region and the nFET region. In an embodiment, the isotropic etching uses NF3 gas, CHF3 gas, CF4 gas, other suitable gases, or a mixture thereof to perform a dry etching process. The gas flow rate, etching time, and other etching parameters (such as temperature and pressure) of the isotropic etching are controlled to maintain a good profile in fins 108n and 108p and to compensate (to some extent) for the different etching depths in the anisotropic etching (step 30) between the nFET region and the pFET region. Then, operation 22 proceeds to step 34, where the heights of fins 108n and 108p are inspected (or monitored). If fins 108n and 108p have not yet reached the target fin height, operation 22 proceeds to step 36, where the sidewalls of fins 108n and 108p are treated with certain chemicals. For example, step 36 can apply a processing gas including O2, CO2, SF6, CH3F, other suitable gases, or a mixture thereof. This treatment produces some polymers on the sidewalls of fins 108n and 108p to help control the profiles of fins 108n and 108p during subsequent etching processes. After the treatment is completed, operation 22 proceeds to step 30 to start another iteration of the anisotropic and isotropic etching processes. Operation 22 can repeat steps 30, 32, 34, and 36 until fins 108n and 108p reach the target fin height.

[0026] In an embodiment, even with the iterative etching process implemented in operation 22, fins 108n and 108p can still end up at slightly different heights (e.g., the fin heights are within 25% of each other). The region that etches slower than other regions in operation 22 controls when to stop operation 22. For example, when the substrate 102 includes crystalline Si and the semiconductor layer 104 includes SiGe, the nFET region etches slower than the pFET region. Therefore, operation 22 in step 34 uses the height of the nFET fin 108n as the control. In other words, when step 34 determines that the height of the nFET fin 108n has reached the target fin height, operation 22 proceeds to step 38 to complete the etching. Step 38 can also perform a cleaning process on fins 108n and 108p. In Figure 6In the depicted embodiment, the pFET fins 108p end up being slightly taller than the nFET fins because the pFET regions are etched faster.

[0027] Reference Figure 6 , from the top surface of the remaining substrate 102 to the bottom surface of the fin hard mask 105, each nFET fin 108n has a width w2 in the "X" direction and a height h4 in the "Z" direction. The nFET fins 108n are created by etching the substrate 102 in operation 22 and thus have the same material as the substrate 102. From the top surface of the remaining substrate 102 to the bottom surface of the fin hard mask 105, each pFET fin 108p has a width w1 in the "X" direction and a height h3 in the "Z" direction. Each pFET fin 108p includes a top created by etching the semiconductor layer 104 in operation 22 and a bottom created by etching the substrate 102 in operation 22. For ease of discussion, the top of the pFET fin 108p is referred to as top 104, and the bottom of the pFET fin 108p is referred to as bottom 106. The top 104 has the same material as the semiconductor layer 104, and the bottom 106 has the same material as the substrate 102. The top 104 has a height h1, the bottom 106 has a height h2, and the height h3 is the sum of the height h1 and the height h2. Because the pFET regions are etched faster in this embodiment, the top surface of the remaining portion of the substrate 102 in the pFET region is lower by a step height h5 than the top surface of the remaining portion of the substrate 102 in the nFET region. Even Figure 6 depicts two nFET fins 108n adjacent to two pFET fins 108p, but the present invention is not limited thereto. In various embodiments, there may be one or more nFET fins 108n in the nFET region and one or more pFET fins 108p in the pFET region.

[0028] In this embodiment, the bottoms 106 of the nFET fins 108n and pFET fins 108p include crystalline Si, and the tops 104 of the pFET fins 108p include SiGe. The width w2 may be slightly larger than the width w1, e.g., about 5% to about 10%, because SiGe etches faster than Si in operation 22. For example, the width w1 may be in the range of about 6.1 nm to about 7.1 nm, and the width w2 may be in the range of about 6.5 nm to about 7.5 nm. When these fins are used as FinFET channels, these fin width ranges are designed considering proper gate channel control. Additionally, the height h1 is in the range of about 40 nm to about 70 nm, as in reference Figure 4As will be discussed, in an embodiment, the height h4 is in the range of about 100 nm to about 115 nm. As will be discussed, the height h4 can vary between the nFET fins 108n, depending on the pitch (or center-to-center distance) between adjacent nFET fins 108n. This range is intended to provide sufficient fin sidewall surface area for current conduction and to provide a stable aspect ratio (h4:w2) for the manufacturability of the nFET fins 108n. The height h3 is greater than the height h4 because SiGe etches faster than Si in operation 22. In the present embodiment, due to the iterative etching and processing techniques implemented in operation 22, the height h3 is slightly greater than the height h4. For example, the height h3 is 25% or less greater than the height h4, such as 20% or less. For example, in an embodiment, the height h3 can be in the range of about 115 nm to about 125 nm. Additionally, in various embodiments, the step height h5 can be in the range of about 10 nm to about 30 nm. Operation 22 can be adjusted to minimize the step height h5.

[0029] In operation 24, method 10 ( Figure 1A ) forms an isolation structure 110 that laterally isolates each of the fins 108n and 108p over the remaining portion of the substrate 102. According to an embodiment, the resulting structure is in Figure 7is shown. For example, the isolation structure 110 surrounds the bottoms of the fins 108n and 108p to separate and isolate the fins 108n and 108p from each other. The isolation structure 110 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. The isolation structure 110 may include different structures, such as a shallow trench isolation (STI) structure and / or a deep trench isolation (DTI) structure. In some embodiments, the isolation structure 110 includes a multi-layer structure. For example, the isolation structure 110 may include the substrate 102 and a thermally formed oxide liner layer on the surfaces of the fins 108n and 108p and a silicon nitride layer disposed above the oxide liner layer. In an embodiment, the isolation structure 110 is formed by filling the trench between the fins 108n and 108p with one or more insulating materials (e.g., by using a CVD process or a spin-on glass process); performing a chemical mechanical polishing (CMP) process to remove excess insulating material, remove the fin hard mask 105, and / or planarize the top surface of the insulating material; and etching back the insulating material to form the isolation structure 110. In this embodiment, the etching back of the isolation structure 110 is controlled such that the top surface of the isolation structure 110 in the pFET region is flush with or slightly higher than the bottom surface of the top 104 of the pFET fin 108p. Due to the stepped profile in the substrate 102, the top surface of the isolation structure 110 may also have steps. In other words, the top surface of the isolation structure 110 in the nFET region may be slightly higher in step height h6 than the top surface of the isolation structure 110 in the pFET region. In some embodiments where the height h5 is in the range of about 10 nm to about 30 nm, the height h6 is in the range of about 1 nm to about 6 nm. This range of the height h6 is generally within the desired range for facilitating good production yield. The operation 22 may be adjusted to minimize the step height h5, which results in minimizing the step height h6.

[0030] In operation 26, the method 10 ( Figure 1A ) proceeds to further manufacturing steps to form FinFET devices over the nFET fins 108n and the pFET fins 108p. For example, operation 26 may: form a dummy gate over the fins 108n and 108p; form source / drain regions by etching the fins 108n and 108p in the source / drain regions and epitaxially growing source / drain components over the remaining portions of the fins 108n and 108p in the source / drain regions; replace the dummy gate with a high-k metal gate; form an interlayer dielectric layer; form contacts to the source / drain components and the high-k metal gate; form a multi-layer interconnect structure; and perform other manufacturing. In that regard, Figure 8 a perspective view of the device 100 after operation 24 is completed is shown, Figure 8Shown are two nFET fins 108n and two pFET fins 108p extending from a substrate 102 and passing through an isolation structure 110. Each of the pFET fins 108p includes a top 104 and a bottom 106. Figure 9A Shown is a perspective view of the device 100 after further fabrication of the device 100 in operation 26 according to an embodiment. Figure 9B Shown is along Figure 9A a cross-sectional view of the device 100 along line “B-B” in. As Figure 9A and Figure 9B shown, operation 26 forms an n-type FinFET over the nFET fins 108n and a p-type FinFET over the pFET fins 108p, where portions of the fins 108n and 108p serve as channels for the respective FinFETs. In Figure 9A and Figure 9B the embodiment shown, a common high-k metal gate 112 engages the fins 108n and 108p to form a CMOS device. In an alternative embodiment, the n-type FinFET and the p-type FinFET may have different high-k metal gates.

[0031] Referring Figure 9A and Figure 9B , in this embodiment, the device 100 includes a high-k metal gate 112, gate spacers 114 on the sidewalls of the high-k metal gate 112, fin sidewall spacers 116, an n-type source / drain component 118n (after a source / drain trench etching process) over the remaining portion of the fin 108n, and a p-type source / drain component 118p (after a source / drain trench etching process) over the remaining portion of the fin 108p. The device 100 may include various other elements not shown in Figure 9A and Figure 9B . Referring Figure 9B , in the p-type FinFET, the high-k metal gate 112 is disposed over the top 104 of the pFET fin 108p that provides high carrier mobility. The top 104 of the pFET fin 108p connects the two p-type source / drain components 118p and serves as a transistor channel. Since the top 104 uses a high-mobility semiconductor material, the performance of the p-type FinFET is improved. In this embodiment, the top 104 of the pFET fin 108p is partially etched in the source / drain region, and the source / drain component 118p is directly disposed on the remaining portion of the top 104 in the source / drain region. In an alternative embodiment, the top 104 of the pFET fin 108p is completely etched in the source / drain region, and the source / drain component 118p is directly disposed on the bottom 106 in the source / drain region.

[0032] The source / drain components 118n and 118p can be formed by any suitable epitaxial process, such as vapor phase epitaxy, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain component 118n comprises silicon and can be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, the source / drain component 118p comprises silicon germanium or germanium and can be doped with boron, other p-type dopants, or combinations thereof (e.g., to form a Si:Ge:B epitaxial source / drain component). In some embodiments, the epitaxial source / drain components 118n and 118p are doped during deposition by adding impurities to the source material of the epitaxial process (i.e., in-situ). In some embodiments, the epitaxial source / drain components 118n and 118p are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is implemented to activate the dopants in the epitaxial source / drain components 118n and 118p. In some embodiments, the epitaxial source / drain components 118n and 118p are formed in different processing sequences, including: for example, masking the pFET region when forming the epitaxial source / drain component 118n in the nFET region; and masking the nFET region when forming the epitaxial source / drain component 118p in the pFET region).

[0033] In an embodiment, the high-k metal gate 112 includes a high-k gate dielectric layer 112A and a gate electrode layer 112B. The gate electrode layer 112B may include a work function layer and a bulk metal layer. The high-k metal gate 112 may include additional layers, such as a dielectric interface layer between the top 104 and the high-k gate dielectric layer 112A. In various embodiments, the dielectric interface layer may include a dielectric material, such as silicon oxide, silicon oxynitride, or silicon germanium oxide, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The dielectric interface layer may include different dielectric materials for n-type FinFETs and for p-type FinFETs. For example, the dielectric interface layer may include silicon oxide for n-type FinFETs and silicon germanium oxide for p-type FinFETs. The high-k gate dielectric layer 112A may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal-oxides, or combinations thereof; and may be formed by ALD and / or other suitable methods. The work function layer (a part of the gate electrode layer 112B) may include a metal selected from the group consisting of, but not limited to, titanium aluminum nitride (TiAlN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), aluminum (Al), or combinations thereof; and may be deposited by CVD, PVD, and / or other suitable processes. The bulk metal layer (a part of the gate electrode layer 112B) may include metals such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials; and may be deposited using plating, CVD, PVD, or other suitable processes.

[0034] Each of the fin sidewall spacers 116 and the gate spacers 114 may be a single-layer or multi-layer structure. In some embodiments, each of the spacers 116 and 114 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), other dielectric materials, or combinations thereof. In an example, the spacers 116 and 114 are formed by depositing a first dielectric layer (e.g., a SiO2 layer with a substantially uniform thickness) as a liner layer over the device 100; and depositing a second dielectric layer (e.g., a Si3N4 layer) as a main D-shaped spacer over the first dielectric layer; and then anisotropically etching to remove portions of the dielectric layers to form the spacers 116 and 114. Additionally, during an etching process for forming grooves in the fins 108n and 108p before growing the source / drain components 118n and 118p, the fin sidewall spacers 116 may be partially removed. In some embodiments, the fin sidewall spacers 116 may be completely removed by such an etching process.

[0035] Figure 10 A cross-sectional view of a portion of device 100 according to an embodiment is shown. For example, the portion of device 100 within Figure 10 may be part of a ring oscillator circuit, where high-performance p-type FinFETs may be used to improve the performance of the circuit. Referring to Figure 10 , device 100 includes a repeating pattern of dual nFET fins 108n and dual pFET fins 108p. More specifically, device 100 includes a repeating pattern of a pair of nFET fins 108n, another pair of nFET fins 108n, a pair of pFET fins 108p, and another pair of pFET fins 108p. In some embodiments, two nFET fins 108n within the same pair are used to form a single n-type FinFET, and two pFET fins 108p within the same pair are used to form a single p-type FinFET. The pitch (center-to-center distance) between two nFET fins 108n within the same pair is S2, and the pitch between two pFET fins 108p within the same pair is S4. In an embodiment, S4 is substantially equal to S2. The center-to-center distance between two adjacent pairs of nFET fins 108n and another nFET fin 108n is S1. The center-to-center distance between two adjacent pairs of pFET fins 108p and another pFET fin 108p is S5. The center-to-center distance between two adjacent pairs of nFET fins 108n and pFET fins 108p is S3. In an embodiment, distances S1, S3, and S5 are substantially the same. Figure 10 Respective depths D1, D2, D3, D4, D5, D6, and D7 are also shown, each of the depths being measured from the top surface of fins 108n / 108p to the top surface of substrate 102 after operation 22 is completed. Depth D1 is measured between two nFET fins 108n within the same pair. Depth D2 is measured between two adjacent pairs of nFET fins 108n. Depths D3, D4, and D5 are measured at respective points between a pair of nFET fins 108n and a pair of pFET fins 108p. Depth D6 is measured between two adjacent pairs of pFET fins 108p. Depth D7 is measured between two pFET fins 108p within the same pair.

[0036] Figure 10Shows the influence of the spacings S1 to S5 on the depths D1 to D7. Specifically, when two fins in the same device region (two fins in the nFET region or two fins in the pFET region) are closer, the etching depth between the two fins is smaller. For example, each of the spacings S1 and S5 is larger than each of the spacings S2 and S4, and each of the depths D2 and D6 is larger than each of the spacings D1 and D7. Additionally, even though S2 and S4 are substantially the same, the depth D7 is larger than the depth D1 because the semiconductor layer 104 is etched at a rate faster than the substrate 102, as discussed above. In some embodiments, the depth D7 is about 25% or less larger than the depth D1, such as about 5% to about 20%. For the same reason, even though S1 and S5 are substantially the same, the depth D6 is larger than the depth D2. In some embodiments, the depth D6 is about 25% or less larger than the depth D2, such as about 5% to about 20%. For this embodiment, the difference between D6 and D2 represents the step height h5( Figure 6 ). As the measurement point moves from the nFET fin 108n to the pFET fin 108p, the depths D3, D4, and D5 gradually increase in sequence. In other words, D4 is larger than D3, and D5 is larger than D4. Additionally, in this embodiment, the depth D2 is equal to or less than the depth D3, and the depth D5 is equal to or less than the depth D6. The gradual change in the depths from D3 to D5 represents the step between the nFET region and the pFET region as Figure 6 shown.

[0037] In an embodiment, the width of the pFET fin 108p is in the range of about 6.1 nm to about 7.1 nm, and the width of the nFET fin 108n is larger than the width of the pFET fin 108p and can be in the range of about 6.5 nm to about 7.5 nm. These fin width ranges are intended to achieve desired FinFET performance, such as DIBL (Drain-Induced Barrier Lowering) and increased fin density. Additionally, each of S2 and S4 is in the range of about 23 nm to about 28 nm, and each of S1, S3, and S5 is in the range of about 68 nm to about 73 nm. These spacing ranges are intended to increase the density of the fins (or devices) while avoiding fin-to-fin bridging issues. Additionally, the depth D1 is in the range of about 100 nm to about 105 nm; the depth D2 is in the range of about 101 nm to about 106 nm; the depth D3 is in the range of about 105 nm to about 110 nm; the depth D4 is in the range of about 113 nm to about 118 nm; each of the depths D5 and D6 is in the range of about 120 nm to about 125 nm; and the depth D7 is in the range of about 115 nm to about 120 nm. These depth ranges achieve good depth uniformity, which provides good topography when performing CMP on the isolation structure 110.

[0038] Figure 11A cross-sectional view of a portion of device 100 according to another embodiment is shown. For example, the portion of device 100 in Figure 11 can be part of an SRAM circuit, where high-performance p-type FinFETs can be used to improve the performance of the circuit. Referring to Figure 11 , device 100 includes a repeating pattern of dual nFET fins 108n and single pFET fins 108p. More specifically, device 100 includes a repeating pattern of a single pFET fin 108p, another single pFET fin 108p, a pair of nFET fins 108n, another pair of nFET fins 108n, a single pFET fin 108p, and another single pFET fin 108p. In some embodiments, two nFET fins 108n in the same pair are used to form a single n-type FinFET, and each pFET fin 108p is used to form a single p-type FinFET. The pitch (center-to-center distance) between two nFET fins 108n in the same pair is S8, the pitch between two adjacent pFET fins 108p is S6, the pitch between a pFET fin 108p and an adjacent nFET fin 108n is S7, and the pitch between two nFET fins 108n of two adjacent pairs is S9. In an embodiment, S7 is substantially equal to S9, S8 is smaller than S6, and S6 is smaller than S7. Figure 11 Also shown are respective depths D8, D9, D10, and D11, each of the depths being measured from the top surface of fins 108n / 108p to the top surface of substrate 102 after operation 22 is completed. Depth D8 is measured between two adjacent pFET fins 108p. Depth D9 is measured between a pFET fin 108p and an adjacent nFET fin 108n. Depth D10 is measured between two nFET fins 108n in the same pair. Depth D11 is measured between two pairs of adjacent nFET fins 108n.

[0039] Figure 11Illustrates the influence of spacings S6 to S9 on depths D8 to D11. Specifically, when two fins in the same device region (two fins in the nFET region or two fins in the pFET region) are closer, the etch depth between the two fins is smaller. For example, spacing S9 is larger than spacing S8, and depth D11 is larger than depth D10 (both are measured between nFET fins 108n). Additionally, even though S7 and S9 are substantially the same, depth D9 is larger than depth D11 because depth D9 is between pFET fin 108p and nFET fin 108n, and the semiconductor layer 104 is etched at a rate faster than the substrate 102, as discussed above. Further, in various embodiments, depth D8 can be greater than, equal to, or less than depth D9, depending on spacings S6 and S7. When spacing S6 is approximately equal to spacing S7 (e.g., within 10% of each other), depth D8 can be equal to or greater than depth D9 because depth D8 is measured between two pFET fins 108p and depth D9 is measured between pFET fin 108p and nFET fin 108n. In some embodiments, depth D11 is approximately 10% or less greater than depth D10. In some embodiments, depth D8 is approximately 20% or less greater than depth D11, such as about 5% to about 12%. For this embodiment, the difference between D8 and D11 represents the step height h5( Figure 6 ).

[0040] In an embodiment, the width of pFET fin 108p is in the range of about 6.1 nm to about 7.1 nm, and the width of nFET fin 108n is larger than the width of pFET fin 108 and can be in the range of about 6.5 nm to about 7.5 nm. These fin width ranges are intended to achieve desired FinFET performance, such as DIBL (Drain-Induced Barrier Lowering) and increased fin density. Additionally, spacing S6 is in the range of about 33 nm to about 38 nm; spacing S7 is in the range of about 40 nm to about 45 nm; spacing S8 is in the range of about 23 nm to about 28 nm; and spacing S9 is in the range of about 40 nm to about 45 nm. These spacing ranges are intended to increase the density of the fins (or devices) while avoiding fin-to-fin bridging issues. Further, depth D8 is in the range of about 120 nm to about 125 nm; depth D9 is in the range of about 117 nm to about 122 nm; depth D10 is in the range of about 100 nm to about 105 nm; and depth D11 is in the range of about 108 nm to about 113 nm. These depth ranges achieve good depth uniformity, which provides good topography when performing CMP on the isolation structure 110.

[0041] While not intended to be limiting, embodiments of the present invention provide one or more of the following advantages. For example, embodiments of the present invention form pFET fins and nFET fins above the same substrate, where the pFET fins include a material having a higher hole mobility than the material in the nFET fins. This improves the performance of the p-type FinFET formed by the pFET fins. Additionally, embodiments of the present invention use a common process that implements iterative etching and processing to etch the pFET fins and the nFET fins. This process reduces or minimizes the size difference between the pFET fins and the nFET fins and results in good planarity of the subsequently formed isolation structure. Embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes.

[0042] In one exemplary aspect, the present invention is directed to a method that includes: providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, where the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, where the first fin includes the first semiconductor material and the second fin includes a top above a bottom, where the top includes the second semiconductor material and the bottom includes the first semiconductor material.

[0043] In an embodiment of the method, the substrate is a silicon substrate and the second semiconductor material includes silicon germanium. In an embodiment, the method further includes: after epitaxially growing the second semiconductor material, planarizing the top surfaces of the nFET region and the pFET region.

[0044] In an embodiment, patterning the nFET region and the pFET region includes: forming a fin hard mask over the nFET region and the pFET region; and etching the nFET region and the pFET region through the fin hard mask by the same process to create a first fin and a second fin. In a further embodiment, etching the nFET region and the pFET region includes: anisotropically etching the nFET region and the pFET region through the fin hard mask; after the anisotropic etching, isotropically etching the nFET region and the pFET region through the fin hard mask; treating the structure resulting from the anisotropic etching and the isotropic etching with a processing gas mixture; and repeating the anisotropic etching, the isotropic etching, and the treatment to create a first fin in the nFET region and a second fin in the pFET region, wherein different gases are applied for the anisotropic etching, the isotropic etching, and the treatment. In some embodiments, the anisotropic etching includes applying HBr, Cl2, Ar, or a mixture thereof. In some embodiments, the isotropic etching includes applying NF3, CHF3, CF4, or a mixture thereof. In some embodiments, the treatment includes applying O2, CO2, SF6, CH3F, or a mixture thereof.

[0045] In an embodiment, the method further includes: forming an isolation structure between the first fin and the second fin, wherein a first bottom surface of the isolation structure adjacent to the first fin is about 10 nm to about 30 nm higher than a second bottom surface of the isolation structure adjacent to the second fin.

[0046] In another exemplary aspect, the present invention is directed to a structure that includes: a substrate; a first fin extending from the substrate; and a second fin extending from the substrate. The second fin includes a top above a bottom. The bottoms of the first fin and the second fin include crystalline silicon. The top of the second fin includes a semiconductor material having a higher charge carrier mobility than silicon. The top surface of the second fin and the top surface of the first fin are substantially coplanar. The bottom of the second fin extends deeper into the substrate than the first fin.

[0047] In an embodiment of the structure, the first fin extends from a first portion of the substrate and the second fin extends from a second portion of the substrate, wherein the first portion is higher than the second portion. In a further embodiment, the first portion is about 10 nm to about 30 nm higher than the second portion. In another embodiment of the structure, the top of the second fin includes silicon germanium.

[0048] In an embodiment, the structure further includes: an isolation structure adjacent to the first fin and the second fin, wherein a top surface of the isolation structure is substantially flush with a bottom surface of the top of the second fin. In some embodiments, the structure further includes: a first gate structure located above the isolation structure and engaging the first fin; and a second gate structure located above the isolation structure and engaging the top of the second fin.

[0049] In yet another exemplary aspect, the present invention is directed to a structure that includes: a substrate; two first fins adjacent to each other and extending from a first region of the substrate; two second fins adjacent to each other and extending from a second region of the substrate; and an isolation structure located above the substrate and adjacent to the first fins and the second fins. Each of the second fins includes a top portion above a bottom portion. The bottom portions of the first fins and the second fins include crystalline silicon. The top portions of the second fins include silicon germanium. The top surfaces of the second fins and the top surfaces of the first fins are substantially coplanar. Each of the second fins is taller than the first fins.

[0050] In an embodiment of the structure, a first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first spacing between the two first fins is approximately equal to a second spacing between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure. In a further embodiment, a third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and a depth of the third portion of the isolation structure is greater than the depth of the second portion of the isolation structure.

[0051] In an embodiment of the structure, a first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first spacing between the two first fins is smaller than a second spacing between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure. In a further embodiment, a third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and a depth of the third portion of the isolation structure is greater than the depth of the first portion of the isolation structure and less than the depth of the second portion of the isolation structure.

[0052] The features of several embodiments are outlined above so that those of ordinary skill in the art can better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor structure, comprising: Providing a substrate having a first semiconductor material; Creating a mask covering the nFET region of the substrate; Etching the pFET region of the substrate to form trenches; Epitaxially growing a second semiconductor material in the trenches, wherein the second semiconductor material is different from the first semiconductor material; and Patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin comprises the first semiconductor material, and the second fin comprises a top portion above a bottom portion, wherein the top portion comprises the second semiconductor material and the bottom portion comprises the first semiconductor material, wherein patterning the nFET region and the pFET region comprises: Anisotropically etching the nFET region and the pFET region through a fin hard mask; After the anisotropic etching, isotropically etching the nFET region and the pFET region through the fin hard mask; Treating the structure produced by the anisotropic etching and the isotropic etching with a process gas mixture, the treatment producing a polymer on sidewalls of the structure produced by the anisotropic etching and the isotropic etching to assist in controlling the profile of the structure produced by the anisotropic etching and the isotropic etching during a subsequent etching process; and Repeating the anisotropic etching, the isotropic etching, and the treatment until the structure produced by the anisotropic etching and the isotropic etching reaches a target fin height to produce the first fin in the nFET region and the second fin in the pFET region, wherein different gases are applied for the anisotropic etching, the isotropic etching, and the treatment; wherein the first fin is wider than the second fin.

2. The method according to claim 1, wherein, The substrate is a silicon substrate, and the second semiconductor material comprises silicon germanium.

3. The method according to claim 1, further comprising: After epitaxially growing the second semiconductor material, planarizing the top surfaces of the nFET region and the pFET region.

4. The method according to claim 1, wherein Patterning the nFET region and the pFET region comprises: Forming the fin hard mask over the nFET region and the pFET region; and Etching the nFET region and the pFET region through the fin hard mask by the same process to produce the first fin and the second fin.

5. The method according to claim 3, removing the mask covering the nFET region of the substrate after epitaxially growing the second semiconductor material and before planarizing the top surfaces of the nFET region and the pFET region.

6. The method according to claim 1, wherein, The anisotropic etching comprises applying HBr, Cl2, Ar, or a mixture thereof.

7. The method according to claim 1, wherein The isotropic etching comprises applying NF3, CHF3, CF4, or a mixture thereof.

8. The method according to claim 1, wherein The treatment comprises applying O2, CO2, SF6, CH3F, or a mixture thereof.

9. The method according to claim 1, further comprising: An isolation structure is formed between the first fin and the second fin, wherein a first bottom surface of the isolation structure adjacent to the first fin is 10 nm to 30 nm higher than a second bottom surface of the isolation structure adjacent to the second fin.

10. A semiconductor structure, comprising: a substrate; a first fin extending from a first portion of the substrate; and a second fin extending from a second portion of the substrate, wherein the second fin includes a top portion above a bottom, the bottoms of the first fin and the second fin include crystalline silicon, the top portion of the second fin includes a semiconductor material having a higher charge carrier mobility than silicon, a top surface of the second fin and a top surface of the first fin are substantially coplanar, and the bottom of the second fin extends deeper into the substrate than the first fin, wherein the first fin is wider than the second fin; an isolation structure adjacent to the first fin and the second fin; wherein the substrate has a step between the first portion and the second portion, and the first portion of the substrate is higher than the second portion of the substrate; wherein a first portion of the isolation structure extends laterally continuously between the first fin and the second fin, a top surface of the isolation structure has a step in the first portion of the isolation structure, and the step of the isolation structure is formed above the step of the substrate.

11. The semiconductor structure according to claim 10, wherein, A second portion of the isolation structure extends laterally between the two first fins, a third portion of the isolation structure extends laterally between the two second fins, and a first spacing between the two first fins is approximately equal to a second spacing between the two second fins.

12. The semiconductor structure according to claim 11, wherein, The first portion of the substrate is 10 nm to 30 nm higher than the second portion of the substrate.

13. The semiconductor structure according to claim 10, wherein, The top portion of the second fin includes silicon germanium.

14. The semiconductor structure according to claim 10, further comprising: a top surface of a portion of the isolation structure extending between two adjacent second fins is flush with a bottom surface of the top portion of the second fin.

15. The semiconductor structure according to claim 14, further comprising: a first gate structure located above the isolation structure and engaging the first fin; and a second gate structure located above the isolation structure and engaging the top portion of the second fin.

16. A semiconductor structure, comprising: a substrate; two first fins adjacent to each other and extending from a first region of the substrate, the first fins having a uniform first width; two second fins adjacent to each other and extending from a second region of the substrate, the second fins having a uniform second width; and an isolation structure located above the substrate and adjacent to the first fins and the second fins, wherein each of the second fins includes a top portion above a bottom, the bottoms of the first fins and the second fins include crystalline silicon, the top portions of the second fins include silicon germanium, top surfaces of the second fins and top surfaces of the first fins are substantially coplanar, each of the second fins is higher than the first fins, wherein the first width is greater than the second width; Wherein, the substrate has a step, and a third portion of the isolation structure extends laterally and continuously between one of the two first fins and one of the two second fins; Wherein, a top surface of the isolation structure has a step in the third portion of the isolation structure, and the step of the isolation structure is formed above the step of the substrate.

17. The semiconductor structure according to claim 16, wherein, A first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first spacing between the two first fins is approximately equal to a second spacing between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure.

18. The semiconductor structure according to claim 17, wherein, A depth of the third portion of the isolation structure is greater than the depth of the second portion of the isolation structure.

19. The semiconductor structure according to claim 16, wherein, A first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first spacing between the two first fins is smaller than a second spacing between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure.

20. The semiconductor structure according to claim 19, wherein, A third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and a depth of the third portion of the isolation structure is greater than a depth of the first portion of the isolation structure and less than a depth of the second portion of the isolation structure.

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