Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, wherein the method comprises: providing a substrate; forming a first electrode material layer on the surface of the substrate; forming a plurality of mutually discrete magnetic tunnel junctions on the surface of the first electrode material layer, and forming a second electrode layer on the top surface of each magnetic tunnel junction; forming sidewalls on the sidewalls of the magnetic tunnel junction and the second electrode layer; after forming the sidewalls, removing the first electrode material layer exposed on the surface of the substrate to form the first electrode layer. Thus, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] MRAM (Magnetic Random Access Memory) is a non-volatile magnetic random access memory. It has the high-speed read and write capabilities of static random access memory (SRAM), the high integration of dynamic random access memory (DRAM) and much lower power consumption than DRAM. Compared with flash memory (Flash), its performance will not degrade with the increase of usage time. Due to the above characteristics of MRAM, it is called universal memory and is considered to be able to replace SRAM, DRAM, EEPROM and Flash.

[0003] Unlike traditional random access memory chip manufacturing technology, the data in MRAM is not stored in the form of charge or current, but in a magnetic state, and is sensed by measuring resistance without interfering with the magnetic state. MRAM uses a magnetic tunnel junction (MTJ) structure to store data. Generally speaking, an MRAM unit consists of a transistor (1T) and a magnetic tunnel junction (MTJ) to form a storage unit. The magnetic tunnel junction (MTJ) structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. The current flows vertically from one electromagnetic layer through the insulating layer or "through" another electromagnetic layer. One of the electromagnetic layers is a fixed magnetic layer, which fixes the electrode in a specific direction through a strong fixed field. The other electromagnetic layer is a freely rotatable magnetic layer that keeps the electrode on one side.

[0004] However, existing semiconductor structures have poor performance. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a plurality of mutually discrete magnetic tunnel junctions located on the substrate; a second electrode layer located on the top surface of the magnetic tunnel junction; a side wall located on the side wall surface of the magnetic tunnel junction and the second electrode layer; a first electrode layer located between the bottom surface of the magnetic tunnel junction and the surface of the substrate, and between the bottom surface of the side wall and the surface of the substrate.

[0007] Optionally, the magnetic tunnel junction includes: a first electromagnetic layer located on a surface of the first electrode layer, a tunneling layer located on a surface of the first electromagnetic layer, and a second electromagnetic layer located on a surface of the tunneling layer.

[0008] Optionally, it also includes: a first dielectric layer located on the surface of the substrate, the second electrode layer and the sidewall, the first dielectric layer includes a first lower dielectric layer and a first upper dielectric layer located on the surface of the first lower dielectric layer.

[0009] Optionally, the substrate includes a storage area, at least one magnetic tunnel junction, a second electrode layer located on the top surface of the magnetic tunnel junction, a first electrode layer located between the magnetic tunnel junction and the substrate, a side wall located on the side wall of the magnetic tunnel junction, and at least a portion of the first dielectric layer located on the storage area.

[0010] Optionally, it also includes: a first interconnect structure located in a first upper dielectric layer of the storage area, wherein the first interconnect structure is electrically interconnected with a second electrode layer of the storage area.

[0011] Optionally, the substrate also includes a logic area, at least one of the magnetic tunnel junctions, a second electrode layer located on the top surface of the magnetic tunnel junction, a first electrode layer located between the magnetic tunnel junction and the substrate, a side wall located on the side wall of the magnetic tunnel junction, and at least a portion of the first dielectric layer located on the logic area.

[0012] Optionally, the substrate of the logic area has a logic circuit, a first logic interconnection structure for electrically interconnecting the logic circuit, and a substrate dielectric structure surrounding the logic circuit and the first logic interconnection structure.

[0013] Optionally, it also includes: a second interconnection structure located in the first lower dielectric layer of the logic area and the substrate, the second interconnection structure is electrically interconnected with the first logic interconnection structure; and a third interconnection structure located in the first upper dielectric layer, the third interconnection structure is electrically interconnected with the second interconnection structure.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a first electrode material layer on the surface of the substrate; forming a plurality of discrete magnetic tunnel junctions on the surface of the first electrode material layer, and forming a second electrode layer on the top surface of each magnetic tunnel junction; forming side walls on the side walls of the magnetic tunnel junction and the second electrode layer; after forming the side walls, removing the first electrode material layer exposed on the surface of the substrate to form a first electrode layer.

[0015] Optionally, the method for forming the magnetic tunnel junction includes: forming a magnetic tunnel junction material layer on the surface of the first electrode material layer; forming a plurality of mutually discrete first mask structures on the magnetic tunnel junction material layer; and etching the magnetic tunnel junction material layer using the first mask structures as masks until the surface of the first electrode material layer is exposed.

[0016] Optionally, the process of etching the magnetic tunnel junction material layer includes an ion beam etching process.

[0017] Optionally, the process parameters of the ion beam etching process include: the gas used includes at least one of argon, krypton and xenon; the ion energy range is 100eV to 800eV; the ion incident angle range is 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

[0018] Optionally, the method for forming the first electrode layer includes: after forming the sidewalls, etching the first electrode material layer using the second electrode layer and the sidewalls as masks until the substrate surface is exposed.

[0019] Optionally, the process of etching the first electrode material layer includes a reactive ion etching process or an ion beam etching process.

[0020] Optionally, when an ion beam etching process is used to etch the first electrode material layer, the process parameters of the ion beam etching process include: an ion energy range of 100eV to 800eV; an ion incident angle range of 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

[0021] Optionally, the method for forming the side wall includes: forming a side wall material layer on the surface of the magnetic tunnel junction, the second electrode layer and the first electrode material layer; and etching back the side wall material layer until the top surface of the second electrode layer and the surface of the first electrode material layer are exposed.

[0022] Optionally, the process of etching back the spacer material layer includes a reactive ion etching process or an ion beam etching process.

[0023] Optionally, process parameters of a reactive ion etching process or an ion beam etching process for etching the sidewall material layer include: an ion incident angle range of 20 degrees to 45 degrees, and the ion incident angle is an angle between an ion incident direction and a substrate normal direction.

[0024] Optionally, it also includes: after forming the first electrode layer, forming a first dielectric layer on the substrate, the second electrode layer and the side wall surface, the first dielectric layer includes a first lower dielectric layer, and a first upper dielectric layer located on the surface of the first lower dielectric layer, and the surface of the first lower dielectric layer is higher than or flush with the surface of the second electrode layer.

[0025] Optionally, the material of the first lower dielectric layer includes a low dielectric constant material or a combination of a low dielectric constant material and a low temperature oxide.

[0026] Optionally, the material of the first upper dielectric layer includes a low dielectric constant material.

[0027] Optionally, the method for forming the first dielectric layer includes: forming an initial first lower dielectric layer on the surface of the substrate, the second electrode layer and the side wall; flattening the initial first lower dielectric layer until the surface of the second electrode layer is exposed; after forming the first lower dielectric layer, forming a first upper dielectric layer on the surface of the first lower dielectric layer.

[0028] Optionally, the thickness of the initial first lower dielectric layer ranges from 2000 angstroms to 3000 angstroms.

[0029] Optionally, the substrate includes a storage area, at least one magnetic tunnel junction, a second electrode layer located on the top surface of the magnetic tunnel junction, a first electrode layer located between the magnetic tunnel junction and the substrate, a side wall located on the side wall of the magnetic tunnel junction, and at least a portion of the first dielectric layer located on the storage area.

[0030] Optionally, the method further includes: forming a first interconnect structure in a first upper dielectric layer of the storage area, wherein the first interconnect structure is electrically interconnected with a second electrode layer of the storage area.

[0031] Optionally, the method for forming the first interconnect structure includes: after forming the first upper dielectric layer, forming a first interconnect opening in the first upper dielectric layer of the storage area, the first interconnect opening exposing the surface of the second electrode layer of the storage area; and forming the first interconnect structure in the first interconnect opening.

[0032] Optionally, the substrate also includes a logic area, at least one of the magnetic tunnel junctions, a second electrode layer located on the top surface of the magnetic tunnel junction, a first electrode layer located between the magnetic tunnel junction and the substrate, a side wall located on the side wall of the magnetic tunnel junction, and at least a portion of the first dielectric layer located on the logic area.

[0033] Optionally, the substrate of the logic area has a logic circuit, a first logic interconnection structure electrically interconnected with the logic circuit, and a substrate dielectric structure surrounding the logic circuit and the first logic interconnection structure.

[0034] Optionally, it also includes: before forming the first upper dielectric layer, forming a second interconnection structure in the first lower dielectric layer of the logic area and the substrate, and the second interconnection structure is electrically interconnected with the first logic interconnection structure; after forming the first upper dielectric layer, forming a third interconnection structure in the first upper dielectric layer, and the third interconnection structure is electrically interconnected with the second interconnection structure.

[0035] Optionally, the method for forming the second interconnect structure includes: forming a second interconnect opening in the initial first lower dielectric layer, the second interconnect opening also extending into the substrate of the logic area, and the second interconnect opening exposing the surface of the first logic interconnect structure; forming a second interconnect material layer in the second interconnect opening and on the surface of the initial first lower dielectric layer; and planarizing the second interconnect material layer while planarizing the initial first lower dielectric layer until the surface of the second electrode layer is exposed.

[0036] Optionally, the method for forming the third interconnect structure includes: after forming the second interconnect structure, forming a third interconnect opening in the first upper dielectric layer of the logic area, the third interconnect opening exposing the top surface of the second interconnect structure; and forming the third interconnect structure in the third interconnect opening.

[0037] Optionally, the material of the first electrode layer includes at least one of titanium, titanium nitride, tantalum and tantalum nitride; the material of the second electrode layer includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0038] Optionally, the material of the sidewall spacer includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride and silicon carbon boron nitride.

[0039] Optionally, in a direction perpendicular to the side wall surface of the magnetic tunnel junction, the thickness of the side wall is greater than 10 nanometers.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since the first electrode material layer exposed on the surface of the substrate is removed after the side wall is formed to form the first electrode layer, the side wall surface of the magnetic tunnel junction and the side wall surface of the second electrode layer can be protected by the side wall, and the etching by-products remaining on the side wall surfaces of the magnetic tunnel junction and the second electrode layer during the etching process of removing the first electrode material layer are reduced. Therefore, not only the short circuit problem between each magnetic tunnel junction and the short circuit problem between each magnetic tunnel junction and the substrate are reduced, but also the parasitic resistance of the second electrode layer can be reduced, so that the performance of the semiconductor structure is improved.

[0042] Furthermore, since the method for forming the sidewall includes: forming a sidewall material layer on the surface of the magnetic tunnel junction, the second electrode layer and the first electrode material layer; etching back the sidewall material layer until the top surface of the second electrode layer and the surface of the first electrode material layer are exposed, therefore, on the first hand, the first electrode material layer can be used as an etching stop layer in the process of etching back the sidewall material layer, thereby increasing the process window of the etching process and reducing the damage to the substrate surface caused by the etching back process, thereby improving the graphic accuracy of the semiconductor structure and thus improving the performance of the semiconductor structure; on the second hand, since there is a separate etching process for forming the sidewall, not only the pertinence of the etching process is improved, but also The accuracy of the etching process can be improved, and in the back etching process, the damage to other structures caused by the etching process can also be reduced, thereby improving the graphic accuracy of the sidewalls and other structures of the semiconductor structure at the same time; on the third aspect, when the first dielectric layer is subsequently formed, and an interconnection structure electrically interconnected with the second electrode layer is formed in the first dielectric layer, or an interconnection structure electrically interconnected with the substrate is formed, since a separate etching process is used to remove the second electrode layer and the sidewall material layer on the surface of the first electrode material layer during the formation of the sidewall, the loading effect caused by etching through the second electrode layer and the sidewall material layer on the surface of the substrate when etching the first dielectric layer can be reduced, thereby reducing the damage to the second electrode layer and the substrate caused by the etching process while reducing the first dielectric layer to be formed subsequently, thereby improving the performance of the semiconductor structure.

[0043] Furthermore, since the thickness of the side wall is more than 10 nanometers, the thicker side wall can not only reduce the outward diffusion of materials in the magnetic tunnel junction to improve the performance of the semiconductor structure, but also better protect the magnetic tunnel junction and the side wall of the second electrode layer, and further ensure that the etching process of the first electrode material layer has little or no effect on the magnetic tunnel junction and the side wall of the second electrode layer, thereby helping to better prevent short circuits between magnetic tunnel junctions and improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 to Figure 2 It is a structural schematic diagram of each step of the formation process of a semiconductor structure;

[0045] Figures 3 to 10 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] As described in the background art, the performance of the semiconductor structure is still relatively poor. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0047] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0048] Figure 1 to Figure 2 It is a structural schematic diagram of the various steps in the formation process of a semiconductor structure.

[0049] Please refer to Figure 1 , providing a substrate 10, wherein the substrate 10 has a logic circuit and an interconnection structure (not shown) electrically interconnected with the logic circuit; forming a lower electrode material layer 20 on the surface of the substrate 10; forming a magnetic tunnel junction material layer 30 on the surface of the lower electrode material layer 20; forming mutually discrete mask structures 50 on the surface of the magnetic tunnel junction material layer 30, and an upper electrode layer 40 located between the mask structure 50 and the magnetic tunnel junction material layer 30.

[0050] Please refer to Figure 2 , using the mask structure 50 and the upper electrode layer 40 as masks, the magnetic tunnel junction material layer 30 and the lower electrode material layer 20 are etched until the surface of the substrate 10 is exposed to form a lower electrode layer 21 and a magnetic tunnel junction 31 between the lower electrode layer 21 and the upper electrode layer 40. The upper electrode layer 40, the magnetic tunnel junction 31 and the lower electrode layer 21 constitute a storage device, and the lower electrode layer 21 is electrically interconnected with the interconnect structure, thereby realizing the embedding of the storage device in the logic circuit.

[0051] However, in the above method, during the process of etching the lower electrode material layer 40, etching byproducts are likely to remain on the sidewalls of the magnetic tunnel junction 31 and the second electrode layer 40. The remaining etching byproducts are likely to cause short circuits between the magnetic tunnel junctions 31 and between the magnetic tunnel junction 31 and the substrate 10, thereby making the performance of the semiconductor structure poor. In addition, the remaining etching byproducts, especially the etching byproducts remaining on the sidewalls of the second electrode layer 40, will also increase the parasitic capacitance of the memory device, further deteriorating the performance of the semiconductor structure.

[0052] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure. Since side walls are formed on the side walls of the magnetic tunnel junction and the second electrode layer, and after the side walls are formed, the first electrode material layer exposed on the surface of the substrate is removed to form a first electrode layer, thereby improving the performance of the semiconductor structure.

[0053] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Figures 3 to 10It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0055] Please refer to Figure 3 , providing a substrate 100.

[0056] The substrate 100 is made of semiconductor material.

[0057] In this embodiment, the substrate 100 is made of silicon.

[0058] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0059] In this embodiment, the substrate 100 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0060] In this embodiment, the substrate 100 includes a storage area A and a logic area B.

[0061] In other embodiments, the substrate does not include a memory region or a logic region.

[0062] In this embodiment, the substrate 100 of the logic area B has a logic circuit (not shown), a first logic interconnection structure 110 electrically interconnected with the logic circuit, and a substrate dielectric structure (not shown) surrounding the logic circuit and the first logic interconnection structure 110.

[0063] Please refer to Figure 4 , a first electrode material layer 200 is formed on the surface of the substrate 100 ; a plurality of mutually discrete magnetic tunnel junctions 210 are formed on the surface of the first electrode material layer 200 , and a second electrode layer 220 is formed on the top surface of each magnetic tunnel junction 210 .

[0064] The first electrode material layer 200 provides material for subsequently forming a first electrode layer between the magnetic tunnel junction 210 and the substrate 100 .

[0065] In this embodiment, the material of the first electrode material layer 200 includes at least one of titanium, titanium nitride, tantalum and tantalum nitride. Accordingly, the material of the first electrode layer includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0066] In this embodiment, the magnetic tunnel junction 210 includes: a first electromagnetic layer 211 located on the surface of the first electrode material layer 200 , a tunneling layer 212 located on the surface of the first electromagnetic layer 211 , and a second electromagnetic layer 213 located on the surface of the tunneling layer 212 .

[0067] In this embodiment, the first electromagnetic layer 211 serves as a fixed layer of the magnetic tunnel junction 210 , and the second electromagnetic layer 213 serves as a free layer of the magnetic tunnel junction 210 .

[0068] In other embodiments, the first electromagnetic layer serves as a free layer of a magnetic tunnel junction, and the second electromagnetic layer serves as a fixed layer of the magnetic tunnel junction.

[0069] In this embodiment, the thickness D1 of the second electrode layer 220 is in a range of 45 nanometers to 70 nanometers.

[0070] If the thickness D1 of the second electrode layer 220 is too small, the risk of the second electrode layer 220 being etched through due to loss will increase during the subsequent etching of the first electrode material layer 200 to form the first electrode layer, which is not conducive to improving the reliability of the semiconductor structure. If the thickness D1 of the second electrode layer 220 is too large, on the one hand, the second electrode layer 220 will have a higher parasitic resistance, which is not conducive to improving the performance of the semiconductor structure. On the other hand, it will not only increase the time for forming the material layer of the second electrode layer 220, but also cause waste of the material of the second electrode layer 220, resulting in increased manufacturing costs. Therefore, when a suitable thickness D1 of the second electrode layer 220 is selected, that is, when the thickness D1 of the second electrode layer 220 ranges from 45 nanometers to 70 nanometers, on the one hand, the risk of subsequent etching through due to loss is reduced, and the reliability of the semiconductor structure is improved. On the other hand, it can not only reduce the parasitic resistance of the second electrode layer 220 to improve the performance of the semiconductor structure, but also reduce the manufacturing time and cost of the semiconductor structure.

[0071] In this embodiment, the method for forming the magnetic tunnel junction 210 includes: forming a magnetic tunnel junction material layer (not shown) on the surface of the first electrode material layer 200; forming a plurality of mutually separate first mask structures 230 on the magnetic tunnel junction material layer; and etching the magnetic tunnel junction material layer using the first mask structure 230 as a mask until the surface of the first electrode material layer 200 is exposed.

[0072] In this embodiment, the method for forming the second electrode layer 220 includes: after forming the magnetic tunnel junction material layer and before forming the first mask structure 230, forming a second electrode material layer (not shown) on the surface of the magnetic tunnel junction material layer; using the first mask structure 230 as a mask, etching the second electrode material layer until the surface of the magnetic tunnel junction material layer is exposed.

[0073] Since the second electrode material layer is etched separately to form the second electrode layer 220 before etching the magnetic tunnel junction material layer, the by-products remaining on the side wall of the magnetic tunnel junction 210 during the etching of the second electrode material layer are reduced, thereby reducing the short circuit defects caused by the by-products and improving the performance of the semiconductor structure.

[0074] In this embodiment, the process of etching the second electrode material layer includes a reactive ion etching process (RIE, Reactive Ion Etching) or an ion beam etching process (IBE, Ion Beam Etching).

[0075] In this embodiment, the material of the second electrode material layer includes at least one of titanium, titanium nitride, tantalum and tantalum nitride. Correspondingly, the material of the second electrode layer 220 includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0076] In this embodiment, the magnetic tunnel junction material layer includes: a first electromagnetic material layer (not shown) located on the surface of the first electrode material layer 200, a tunneling material layer (not shown) located on the surface of the first electromagnetic material layer, and a second electromagnetic material layer (not shown) located on the surface of the tunneling material layer.

[0077] In this embodiment, the process of forming the first electromagnetic material layer, the tunneling material layer, the second electromagnetic layer and the reference material layer includes: a chemical vapor deposition process or an atomic layer deposition process.

[0078] In other embodiments, the method for forming the tunneling material layer includes: forming an initial tunneling material layer (not shown) on the surface of the first material layer using a deposition process; and performing an oxidation process on the initial tunneling material layer to form a tunneling material layer.

[0079] In this embodiment, the process of etching the magnetic tunnel junction material layer includes an ion beam etching process.

[0080] Since the ion beam etching process is adopted, physical etching is mainly used when etching the magnetic tunnel junction material layer, which reduces the chemical reaction in the etching process. Therefore, the by-products produced by the chemical reaction in the etching process are reduced, so that the by-products remaining on the surface of the first electrode material layer 200, the second electrode layer 220 and the magnetic tunnel junction 210 can be reduced, thereby reducing the short-circuit defects caused by the by-products and improving the performance of the semiconductor structure.

[0081] In this embodiment, the process parameters of the ion beam etching process include: the gas used includes at least one of argon, krypton and xenon; the ion energy range is 100eV to 800eV; the ion incident angle range is 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

[0082] Since the gas used includes at least one of argon, krypton and xenon, and argon, krypton and xenon are inert gases, during the ion beam etching process, the etching gas is not easy to chemically react with the magnetic tunnel junction material layer, thereby reducing the by-products produced during the ion beam etching process.

[0083] Since the ion energy range is from 100eV to 800eV, and the ion incident angle range is from 20 degrees to 45 degrees, that is, higher energy and smaller ion incident angle are used, it is beneficial to improve the verticality of the side wall of the magnetic tunnel junction 210, thereby improving the graphic accuracy of the magnetic tunnel junction 210 to improve the performance of the semiconductor structure.

[0084] In this embodiment, after forming the magnetic tunnel junction 210, an ion beam etching process is continued to be used to remove the second electrode layer 220 and the byproducts remaining on the sidewall of the magnetic tunnel junction 210 to further reduce the short circuit risk of the semiconductor structure. The process parameters of the ion beam etching process include: the gas used includes at least one of argon, krypton and xenon; the ion energy range is 10eV to 200eV; and the ion incident angle range is 50 degrees to 80 degrees.

[0085] Since the ion energy range is 10eV to 200eV, that is, a relatively small ion energy is used, the byproducts remaining on the sidewalls of the second electrode layer 220 and the magnetic tunnel junction 210 can be removed while the damage to the surface of the second electrode layer 220 and the magnetic tunnel junction 210 caused by the etching process can be reduced. Since the ion incident angle range is 50 degrees to 80 degrees, that is, a relatively large ion incident angle is used, the byproducts remaining on the sidewalls of the second electrode layer 220 and the magnetic tunnel junction 210 can be removed more easily, thereby better reducing the risk of short circuit of the semiconductor structure.

[0086] In this embodiment, the thickness of the first mask structure 230 is in the range of 50 nanometers to 80 nanometers.

[0087] In this embodiment, the material of the first mask structure 230 includes silicon oxide or silicon nitride.

[0088] In this embodiment, after the magnetic tunnel junction 210 is formed, the first mask structure 230 is removed.

[0089] Subsequently, sidewalls are formed on the sidewalls of the magnetic tunnel junction 210 and the second electrode layer 220. For details on the process of forming the sidewalls, please refer to Figure 5 to Figure 6 .

[0090] Please refer to Figure 5 A spacer material layer 300 is formed on the surface of the magnetic tunnel junction 210 , the second electrode layer 220 and the first electrode material layer 200 .

[0091] The spacer material layer 300 provides material for the subsequent formation of spacers.

[0092] In this embodiment, the process of forming the spacer material layer 300 includes a chemical vapor deposition process or an atomic layer deposition process.

[0093] In this embodiment, the material of the spacer material layer 300 includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride and silicon carbon nitride boron nitride. Correspondingly, the material of the spacer includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride and silicon carbon nitride boron nitride.

[0094] Please refer to Figure 6 , the sidewall material layer 300 is etched back until the top surface of the second electrode layer 220 and the surface of the first electrode material layer 200 are exposed, so as to form a sidewall 310 on the magnetic tunnel junction 210 and the sidewall surface of the second electrode layer 220 .

[0095] Since the method for forming the sidewall 310 includes: forming a sidewall material layer 300 on the surface of the magnetic tunnel junction 210, the second electrode layer 220 and the first electrode material layer 200; etching back the sidewall material layer 300 until the top surface of the second electrode layer 220 and the surface of the first electrode material layer 200 are exposed, therefore, on the first hand, the first electrode material layer 200 can be used as an etching stop layer in the process of etching back the sidewall material layer, thereby increasing the process window of the etching process, and reducing the damage to the surface of the substrate 100 caused by the etching back process, thereby improving the graphic accuracy of the semiconductor structure, and thus improving the performance of the semiconductor structure. On the second hand, since there is a separate etching process for forming the sidewall 310, not only the pertinence of the etching process is improved, so that the accuracy of the etching process can be improved, but also in the etching back process, the damage to other structures caused by the etching process can be reduced, thereby improving the graphic accuracy of the sidewall 310 and other structures of the semiconductor structure at the same time. On the third aspect, when the first dielectric layer is subsequently formed and an interconnection structure (first interconnection structure or third interconnection structure) electrically interconnected with the second electrode layer 220 is formed in the first dielectric layer, or an interconnection structure (second interconnection structure) electrically interconnected with the substrate 100 is formed, since a separate etching process is used to remove the second electrode layer 220 and the sidewall material layer 300 on the surface of the first electrode material layer 200 during the formation of the sidewall 310, the loading effect caused by etching through the second electrode layer 220 and the sidewall material layer 300 on the surface of the substrate 100 when etching the first dielectric layer can be reduced. Therefore, while reducing the first dielectric layer to be formed subsequently, the damage to the second electrode layer 220 and the substrate 100 caused by the etching process can be reduced, thereby improving the performance of the semiconductor structure.

[0096] In this embodiment, the process of etching back the spacer material layer 300 includes: a reactive ion etching process or an ion beam etching process.

[0097] In this embodiment, process parameters of the reactive ion etching process or ion beam etching process for etching the spacer material layer 300 include: an ion incident angle range of 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

[0098] Since the ion incident angle ranges from 20 degrees to 45 degrees, that is, a smaller ion incident angle is adopted, it is beneficial to improve the verticality of the side wall surface of the side wall 310, thereby improving the graphic accuracy of the side wall 310 to improve the performance of the semiconductor structure.

[0099] In this embodiment, in a direction perpendicular to the sidewall surface of the magnetic tunnel junction 210 , a thickness D2 of the sidewall spacer 310 is greater than 10 nanometers.

[0100] Since the thickness D2 of the side wall 310 is above 10 nanometers, the thicker side wall 310 can not only reduce the outward diffusion of the material in the magnetic tunnel junction 210 to improve the performance of the semiconductor structure, but also better protect the magnetic tunnel junction 210 and the side wall of the second electrode layer 220, and further ensure that the subsequent etching process of the first electrode material layer 200 has little or no effect on the side wall of the magnetic tunnel junction 210 and the second electrode layer 220, thereby helping to better prevent short circuits between the magnetic tunnel junctions 210, thereby improving the performance of the semiconductor structure.

[0101] Please refer to Figure 7 After forming the sidewall spacer 310 , the first electrode material layer 200 exposed on the surface of the substrate 100 is removed to form a first electrode layer 201 .

[0102] Since the first electrode material layer 200 exposed on the surface of the substrate 100 is removed to form the first electrode layer 201 after the sidewall 310 is formed, the sidewall surface of the magnetic tunnel junction 210 and the sidewall surface of the second electrode layer 220 can be protected by the sidewall 310, and the etching byproducts remaining on the sidewall surface of the magnetic tunnel junction 210 and the second electrode layer 220 during the etching process of removing the first electrode material layer 200 are reduced, thereby reducing the short circuit problem between each magnetic tunnel junction 210 and the short circuit problem between each magnetic tunnel junction 210 and the substrate 100. In addition, during the etching process of the first electrode material layer 200, the thickness of the second electrode layer 220 can be thinned by the etching process, thereby reducing the parasitic resistance of the second electrode layer 220. In summary, the performance of the semiconductor structure is improved.

[0103] In this embodiment, the method for forming the first electrode layer 201 includes: after forming the sidewall 310 , etching the first electrode material layer 200 using the second electrode layer 220 and the sidewall 310 as masks until the surface of the substrate 100 is exposed.

[0104] In this embodiment, the thickness D3 of the first electrode layer 201 ranges from 15 nanometers to 25 nanometers.

[0105] If the thickness D3 of the first electrode layer 201 is too small, the risk of the material of the magnetic tunnel junction 210 diffusing in the substrate 100 will be increased, which is not conducive to improving the performance of the semiconductor structure. If the thickness D3 of the first electrode layer 201 is too large, on the one hand, the first electrode layer 201 will have a higher parasitic resistance, which is not conducive to improving the performance of the semiconductor structure. On the other hand, it will not only increase the time for forming the material layer of the first electrode layer 201, but also cause waste of the material of the first electrode layer 201, resulting in increased manufacturing costs. Therefore, when a suitable thickness D3 of the first electrode layer 201 is selected, that is, when the thickness D3 of the first electrode layer 201 ranges from 15 nanometers to 25 nanometers, on the one hand, the risk of the material of the magnetic tunnel junction 210 diffusing in the substrate 100 is reduced, and on the other hand, the parasitic resistance of the second electrode layer 220 can be reduced, thereby improving the performance of the semiconductor structure. At the same time, it can also reduce the manufacturing time and cost of the semiconductor structure.

[0106] In this embodiment, the process of etching the first electrode material layer 200 includes an ion beam etching process.

[0107] The process parameters of the ion beam etching process include: an ion energy range of 100 eV to 800 eV; an ion incident angle range of 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

[0108] Since the ion energy range is 100eV to 800eV, and the ion incident angle range is 20 degrees to 45 degrees, that is, higher energy and smaller ion incident angle are used, it is beneficial to improve the verticality of the side wall of the first electrode layer 201, thereby improving the graphic accuracy of the first electrode layer 201 to improve the performance of the semiconductor structure.

[0109] The gases used in the ion beam etching process include argon, krypton and xenon.

[0110] In other embodiments, the process of etching the first electrode material layer includes a reactive ion etching process.

[0111] Subsequently, after forming the first electrode layer 201, a first dielectric layer is formed on the surface of the substrate 100, the second electrode layer 220 and the sidewall 310, wherein the first dielectric layer includes a first lower dielectric layer and a first upper dielectric layer located on the surface of the first lower dielectric layer, wherein the surface of the first lower dielectric layer is higher than or flush with the surface of the second electrode layer 220. For details on the process of forming the first dielectric layer, please refer to Figures 8 to 9 .

[0112] Please refer to Figure 8After forming the first electrode layer 201, an initial first lower dielectric layer (not shown) is formed on the surfaces of the substrate 100, the second electrode layer 220 and the sidewall 310; the initial first lower dielectric layer is planarized until the surface of the second electrode layer 220 is exposed to form a first lower dielectric layer 410.

[0113] By planarizing the initial first lower dielectric layer, the surface flatness of the semiconductor structure can be improved, thereby facilitating the improvement of the graphic accuracy of the semiconductor structure and increasing the size of the process window for subsequently forming the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0114] The material of the first lower dielectric layer 410 includes a low dielectric constant material (dielectric constant is less than 3.9), or a combination of a low dielectric constant material and a low temperature oxide.

[0115] In this embodiment, the material of the first lower dielectric layer 410 includes a combination of a low dielectric constant material and a low temperature oxide.

[0116] Since the material of the first lower dielectric layer 410 includes a combination of a low dielectric constant material and a low-temperature oxide, the material of the first lower dielectric layer 410 has good fluidity, so that the first lower dielectric layer 410 can better fill the gaps between the adjacent first electrode layer 201, the magnetic tunnel junction 210 and the second electrode layer 220.

[0117] In this embodiment, the process of forming the initial first lower dielectric layer includes: a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0118] In this embodiment, the process of planarizing the initial first lower dielectric layer includes a chemical mechanical polishing process.

[0119] In this embodiment, the thickness of the initial first lower dielectric layer ranges from 2000 angstroms to 3000 angstroms.

[0120] If the thickness of the initial first lower dielectric layer is too small, it may result in that the initial first lower dielectric layer cannot fill the gaps between the adjacent first electrode layer 201, the magnetic tunnel junction 210, and the second electrode layer 220, which is not conducive to improving the reliability and performance of the semiconductor structure; if the thickness of the initial first lower dielectric layer is too large, it will increase the time and cost of forming the initial first lower dielectric layer. Therefore, when a suitable thickness of the initial first lower dielectric layer is selected, that is, when the thickness of the initial first lower dielectric layer ranges from 2000 angstroms to 3000 angstroms, on the one hand, the time and cost of forming the initial first lower dielectric layer can be more appropriate, and on the other hand, it is also conducive to filling the gaps between the adjacent first electrode layer 201, the magnetic tunnel junction 210, and the second electrode layer 220, so as to improve the performance and reliability of the semiconductor structure.

[0121] In this embodiment, before subsequently forming the first upper dielectric layer, a second interconnect structure 510 is formed in the first lower dielectric layer 410 of the logic region B and the substrate 100 , and the second interconnect structure 510 is electrically interconnected with the first logic interconnect structure 110 .

[0122] In this embodiment, the material of the second interconnect structure 510 is a conductive material, such as copper, tungsten, aluminum, titanium nitride, tantalum nitride, cobalt, etc.

[0123] In this embodiment, the method for forming the second interconnect structure 510 includes: forming a second interconnect opening (not shown) in the initial first lower dielectric layer, the second interconnect opening also extending into the substrate 100 of the logic area B, and the second interconnect opening exposing the surface of the first logic interconnect structure 110; forming a second interconnect material layer (not shown) in the second interconnect opening and on the surface of the initial first lower dielectric layer; and planarizing the second interconnect material layer while planarizing the initial first lower dielectric layer until the surface of the second electrode layer 220 is exposed.

[0124] In this embodiment, the method for forming the second interconnect opening includes: forming a second interconnect opening mask layer (not shown) on the surface of the initial first lower dielectric layer, the second interconnect opening mask layer exposing the surface of the initial first lower dielectric layer on a portion of the logic area B; using the second interconnect opening mask layer as a mask, etching the initial first lower dielectric layer and the substrate 100 until the surface of the first logic interconnect structure 110 is exposed.

[0125] In this embodiment, the process of etching the initial first lower dielectric layer and the substrate 100 includes a reactive ion etching process.

[0126] In this embodiment, after the second interconnect opening is formed, the second interconnect opening mask layer is removed.

[0127] In this embodiment, the process of forming the second interconnect material layer includes: a metal electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0128] Please refer to Fig. 9 After forming the first lower dielectric layer 410 , a first upper dielectric layer 420 is formed on the surface of the first lower dielectric layer 410 to form a first dielectric layer 400 on the surfaces of the substrate 100 , the second electrode layer 220 and the sidewall 310 .

[0129] The first dielectric layer 400 includes: a first lower dielectric layer 410 and a first upper dielectric layer 420 located on the surface of the first lower dielectric layer 410 . The surface of the first lower dielectric layer 410 is higher than or flush with the surface of the second electrode layer 220 .

[0130] In this embodiment, the process of forming the first upper dielectric layer 420 includes: a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0131] In this embodiment, the material of the first upper dielectric layer 420 includes a low dielectric constant material.

[0132] In this embodiment, at least one of the magnetic tunnel junctions 210, the second electrode layer 220 located on the top surface of the magnetic tunnel junction 210, the first electrode layer 201 located between the magnetic tunnel junction 210 and the substrate 100, the side wall 310 located on the side wall of the magnetic tunnel junction 220, and at least a portion of the first dielectric layer 400 are located on the storage area A.

[0133] In this embodiment, at least one of the magnetic tunnel junctions 210, the second electrode layer 220 located on the top surface of the magnetic tunnel junction 210, the first electrode layer 201 located between the magnetic tunnel junction 210 and the substrate 100, the sidewall 310 located on the side wall of the magnetic tunnel junction 220, and at least a portion of the first dielectric layer 400 are located on the logic area B.

[0134] Please refer to Fig.10 , a first interconnect structure 520 is formed in the first upper dielectric layer 420 of the storage area A, and the first interconnect structure 520 is electrically interconnected with the second electrode layer 220 of the storage area A.

[0135] In this embodiment, the material of the first interconnect structure 520 is a conductive material, such as copper, tungsten, aluminum, titanium nitride, tantalum nitride, and cobalt.

[0136] In this embodiment, the method for forming the first interconnect structure 520 includes: after forming the first upper dielectric layer 420, forming a first interconnect opening (not shown) in the first upper dielectric layer 420 of the storage area A, the first interconnect opening exposing the surface of the second electrode layer 220 of the storage area A; and forming the first interconnect structure 520 in the first interconnect opening.

[0137] In this embodiment, the method for forming the first interconnect opening includes: forming a first interconnect opening mask layer (not shown) on the surface of the first upper dielectric layer 420, the first interconnect opening mask layer exposing the surface of the first upper dielectric layer 420 on a portion of the storage area A; using the first interconnect opening mask layer as a mask, etching the first upper dielectric layer 420 until the surface of the second electrode layer 220 on the storage area A is exposed.

[0138] In this embodiment, the process of etching the first upper dielectric layer 420 includes a reactive ion etching process.

[0139] In this embodiment, after the first interconnection opening is formed, the first interconnection opening mask layer is removed.

[0140] In this embodiment, the method for forming the first interconnect structure 520 in the first interconnect opening includes: forming a first interconnect material layer (not shown) in the first interconnect opening and on the surface of the first upper dielectric layer 420; and planarizing the first interconnect material layer until the surface of the first upper dielectric layer 420 is exposed.

[0141] In this embodiment, the process of forming the first interconnect material layer includes: a metal electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0142] In this embodiment, the process of planarizing the first interconnect material layer includes a chemical mechanical polishing process.

[0143] In this embodiment, after forming the first upper dielectric layer 420 , a third interconnect structure 530 is further formed in the first upper dielectric layer 420 of the logic region B, and the third interconnect structure 530 is electrically interconnected with the second interconnect structure 510 .

[0144] In this embodiment, the material of the third interconnect structure 530 is a conductive material, such as copper, tungsten, aluminum, titanium nitride, tantalum nitride, and cobalt.

[0145] The method for forming the third interconnect structure 530 includes: after forming the second interconnect structure 510, forming a third interconnect opening (not shown) in the first upper dielectric layer 420 of the logic area B, wherein the third interconnect opening exposes the top surface of the second interconnect structure 510; and forming the third interconnect structure 530 in the third interconnect opening.

[0146] In this embodiment, the first interconnect opening mask layer also exposes a portion of the surface of the first upper dielectric layer 420 of the logic region B.

[0147] In this embodiment, the method for forming the third interconnect opening includes: while forming the first interconnect opening, etching the first upper dielectric layer 420 using the first interconnect opening mask layer as a mask until the top surface of the second interconnect structure 510 is exposed to form the third interconnect opening.

[0148] In other embodiments, the third interconnection opening is formed separately.

[0149] In this embodiment, the method for forming the third interconnect structure 530 in the third interconnect opening includes: while forming the first interconnect material layer in the first interconnect opening and on the surface of the first upper dielectric layer 420, the first interconnect material layer is also formed in the third interconnect opening; and planarizing the first interconnect material layer until the surface of the first upper dielectric layer 420 is exposed. That is, while forming the first interconnect structure 520, the third interconnect structure 530 is formed.

[0150] In other embodiments, the third interconnect structure is formed separately.

[0151] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.10 , including: a substrate 100; a plurality of mutually discrete magnetic tunnel junctions 210 located on the substrate 100; a second electrode layer 220 located on the top surface of the magnetic tunnel junction 210; a sidewall 310 located on the sidewalls of the magnetic tunnel junction 210 and the second electrode layer 220; a first electrode layer 201 located between the bottom surface of the magnetic tunnel junction 210 and the surface of the substrate 100, and between the bottom surface of the sidewall 310 and the surface of the substrate 100.

[0152] The substrate 100 is made of semiconductor material.

[0153] In this embodiment, the substrate 100 is made of silicon.

[0154] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0155] In this embodiment, the substrate 100 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0156] In this embodiment, the substrate 100 includes a storage area A and a logic area B.

[0157] In other embodiments, the substrate does not include a memory region or a logic region.

[0158] In this embodiment, the substrate 100 of the logic area B has a logic circuit (not shown), a first logic interconnection structure 110 electrically interconnected with the logic circuit, and a substrate dielectric structure (not shown) surrounding the logic circuit and the first logic interconnection structure 110.

[0159] In this embodiment, the material of the first electrode layer 201 includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0160] In this embodiment, the thickness D3 of the first electrode layer 201 ranges from 15 nanometers to 25 nanometers.

[0161] In this embodiment, the material of the second electrode layer 220 includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0162] In this embodiment, the magnetic tunnel junction 210 includes: a first electromagnetic layer 211 located on the surface of the first electrode layer 201 , a tunneling layer 212 located on the surface of the first electromagnetic layer 211 , and a second electromagnetic layer 213 located on the surface of the tunneling layer 212 .

[0163] In this embodiment, the first electromagnetic layer 211 serves as a fixed layer of the magnetic tunnel junction 210 , and the second electromagnetic layer 213 serves as a free layer of the magnetic tunnel junction 210 .

[0164] In other embodiments, the first electromagnetic layer serves as a free layer of a magnetic tunnel junction, and the second electromagnetic layer serves as a fixed layer of the magnetic tunnel junction.

[0165] In this embodiment, the material of the spacer 310 includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride and silicon carbon boron nitride.

[0166] In this embodiment, in a direction perpendicular to the sidewall surface of the magnetic tunnel junction 210 , a thickness D2 of the sidewall spacer 310 is greater than 10 nanometers.

[0167] In this embodiment, the semiconductor structure also includes: a first dielectric layer 400 located on the surface of the substrate 100, the second electrode layer 220 and the sidewall 310, the first dielectric layer 400 includes a first lower dielectric layer 410, and a first upper dielectric layer 420 located on the surface of the first lower dielectric layer 410.

[0168] The material of the first lower dielectric layer 410 includes a low dielectric constant material (dielectric constant is less than 3.9), or a combination of a low dielectric constant material and a low temperature oxide.

[0169] In this embodiment, the material of the first lower dielectric layer 410 includes a combination of a low dielectric constant material and a low temperature oxide.

[0170] In this embodiment, the material of the first upper dielectric layer 420 includes a low dielectric constant material.

[0171] In this embodiment, at least one of the magnetic tunnel junctions 210, the second electrode layer 220 located on the top surface of the magnetic tunnel junction 210, the first electrode layer 201 located between the magnetic tunnel junction 210 and the substrate 100, the side wall 310 located on the side wall of the magnetic tunnel junction 220, and at least a portion of the first dielectric layer 400 are located on the storage area A.

[0172] In this embodiment, at least one of the magnetic tunnel junctions 210, the second electrode layer 220 located on the top surface of the magnetic tunnel junction 210, the first electrode layer 201 located between the magnetic tunnel junction 210 and the substrate 100, the sidewall 310 located on the side wall of the magnetic tunnel junction 220, and at least a portion of the first dielectric layer 400 are located on the logic area B.

[0173] In this embodiment, the semiconductor structure further includes: a first interconnect structure 520 located in the first upper dielectric layer 420 of the storage area A, and the first interconnect structure 520 is electrically interconnected with the second electrode layer 220 of the storage area A.

[0174] In this embodiment, the material of the first interconnect structure 520 is a conductive material, such as copper, tungsten, aluminum, titanium nitride, tantalum nitride, and cobalt.

[0175] In this embodiment, the semiconductor structure also includes: a first lower dielectric layer 410 located in the logic area B and a second interconnection structure 510 in the substrate 100, the second interconnection structure 510 being electrically interconnected with the first logic interconnection structure 110; and a third interconnection structure 530 located in the first upper dielectric layer 420, the third interconnection structure 530 being electrically interconnected with the second interconnection structure 510.

[0176] In this embodiment, the material of the second interconnect structure 510 is a conductive material, such as copper, tungsten, aluminum, titanium nitride, tantalum nitride, cobalt, etc.

[0177] In this embodiment, the material of the third interconnect structure 530 is a conductive material, such as copper, tungsten, aluminum, titanium nitride, tantalum nitride, and cobalt.

[0178] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; The substrate comprises a storage area and a logic area; the substrate of the logic area has a logic circuit and a first logic interconnection structure electrically interconnected with the logic circuit; forming a first electrode material layer on the surface of the substrate; Forming a plurality of mutually discrete magnetic tunnel junctions on the surface of the first electrode material layer, and forming a second electrode layer on the top surface of each magnetic tunnel junction; forming sidewalls on the magnetic tunnel junction and the sidewalls of the second electrode layer; After forming the sidewalls, etching the first electrode material layer using the second electrode layer and the sidewalls as masks until the substrate surface is exposed to form a first electrode layer; After forming the first electrode layer, forming a first dielectric layer on the substrate, the second electrode layer and the surface of the sidewall, the first dielectric layer comprising a first lower dielectric layer and a first upper dielectric layer located on the surface of the first lower dielectric layer, the surface of the first lower dielectric layer being higher than or flush with the surface of the second electrode layer; Before forming the first upper dielectric layer, a second interconnect structure is formed in the first lower dielectric layer of the logic region and in the substrate, the second interconnect structure being electrically interconnected with the first logic interconnect structure; after forming the first upper dielectric layer, a third interconnect structure is formed in the first upper dielectric layer, the third interconnect structure being electrically interconnected with the second interconnect structure; The method for forming the first dielectric layer comprises: forming an initial first lower dielectric layer on the surfaces of the substrate, the second electrode layer and the sidewalls; planarizing the initial first lower dielectric layer until the surface of the second electrode layer is exposed; after forming the first lower dielectric layer, forming a first upper dielectric layer on the surface of the first lower dielectric layer; The method for forming the second interconnect structure includes: forming a second interconnect opening in the initial first lower dielectric layer, the second interconnect opening also extending into the substrate of the logic area, and the second interconnect opening exposing the surface of the first logic interconnect structure; forming a second interconnect material layer in the second interconnect opening and on the surface of the initial first lower dielectric layer; and planarizing the second interconnect material layer while planarizing the initial first lower dielectric layer until the surface of the second electrode layer is exposed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the magnetic tunnel junction includes: forming a magnetic tunnel junction material layer on the surface of the first electrode material layer; forming a plurality of mutually independent first mask structures on the magnetic tunnel junction material layer; and etching the magnetic tunnel junction material layer using the first mask structure as a mask until the surface of the first electrode material layer is exposed.

3. The method for forming a semiconductor structure according to claim 2, wherein: The process of etching the magnetic tunnel junction material layer includes an ion beam etching process.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process parameters of the ion beam etching process include: the gas used includes at least one of argon, krypton and xenon; the ion energy range is 100eV to 800eV; the ion incident angle range is 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the first electrode material layer includes a reactive ion etching process or an ion beam etching process.

6. The method for forming a semiconductor structure according to claim 5, wherein: When the first electrode material layer is etched using an ion beam etching process, the process parameters of the ion beam etching process include: an ion energy range of 100eV to 800eV; an ion incident angle range of 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the sidewall includes: forming a sidewall material layer on the surface of the magnetic tunnel junction, the second electrode layer and the first electrode material layer; etching back the sidewall material layer until the top surface of the second electrode layer and the surface of the first electrode material layer are exposed.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process of etching back the spacer material layer includes a reactive ion etching process or an ion beam etching process.

9. The method for forming a semiconductor structure according to claim 7, wherein: The process parameters of the reactive ion etching process or the ion beam etching process for etching the sidewall material layer include: an ion incident angle range of 20 degrees to 45 degrees, and the ion incident angle is the angle between the ion incident direction and the substrate normal direction.

10. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the second electrode layer includes: after forming the magnetic tunnel junction material layer and before forming the first mask structure, forming the second electrode material layer on the surface of the magnetic tunnel junction material layer; using the first mask structure as a mask, etching the second electrode material layer until the surface of the magnetic tunnel junction material layer is exposed.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first lower dielectric layer includes a low dielectric constant material or a combination of a low dielectric constant material and a low temperature oxide.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first upper dielectric layer includes a low dielectric constant material.

13. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the initial first lower dielectric layer ranges from 2000 angstroms to 3000 angstroms.

14. The method for forming a semiconductor structure according to claim 1, wherein: The storage area includes at least one magnetic tunnel junction, a second electrode layer located on the top surface of the magnetic tunnel junction, a first electrode layer located between the magnetic tunnel junction and the substrate, a side wall located on the side wall of the magnetic tunnel junction, and at least a portion of the first dielectric layer located on the storage area.

15. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: A first interconnect structure is formed in the first upper dielectric layer of the storage region, the first interconnect structure being electrically interconnected with the second electrode layer of the storage region.

16. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the first interconnect structure includes: after forming the first upper dielectric layer, forming a first interconnect opening in the first upper dielectric layer of the storage area, wherein the first interconnect opening exposes the surface of the second electrode layer of the storage area; and forming the first interconnect structure in the first interconnect opening.

17. The method for forming a semiconductor structure according to claim 14, wherein: The logic area includes at least one magnetic tunnel junction, a second electrode layer located on the top surface of the magnetic tunnel junction, a first electrode layer located between the magnetic tunnel junction and the substrate, a side wall located on the side wall of the magnetic tunnel junction, and at least a portion of the first dielectric layer located on the logic area.

18. The method for forming a semiconductor structure according to claim 17, wherein: The substrate of the logic area also has a substrate dielectric structure surrounding the logic circuit and the first logic interconnection structure.

19. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first electrode layer includes at least one of titanium, titanium nitride, tantalum and tantalum nitride; the material of the second electrode layer includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

20. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sidewall spacer includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride and silicon carbon boron nitride.

21. The method for forming a semiconductor structure according to claim 1, wherein: In a direction perpendicular to the side wall surface of the magnetic tunnel junction, the thickness of the side wall is greater than 10 nanometers.

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