A balun structure

By using one ground plane and two interlaced inductors in the Barron structure, the existing low-frequency band Barron size is solved, and a smaller volume, wider bandwidth and better insertion loss is achieved.

CN113745786BActive Publication Date: 2025-06-13SHENZHEN ZHENHUA FU ELECTRONICS
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Patent Information

Application Number
CN202111094237.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-09-17
Publication Date
2025-06-13
Estimated Expiration
2041-09-17

AI Technical Summary

Technical Problem

The existing low-frequency barrons are large in size and are difficult to meet the needs of electronic systems for miniaturization and integration.

Method used

Using a Barron structure including one ground plane and two interlaced inductors, the structure is simplified by coupled inductor lines and reduced production complexity, which is smaller in size when suitable for low frequency bands.

Benefits of technology

It realizes the size reduction of Barron in the low frequency band, wider bandwidth, better insertion loss, and simplifies the structure and manufacturing process.

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Abstract

The present application provides a balun structure, comprising: a substrate, an input port, an output port and a ground port are arranged on the outer side of the substrate; a circuit layer, the circuit layer is arranged in the substrate; the circuit layer comprises a ground layer and an interleaved inductor layer, the interleaved inductor layer is composed of a first inductor line and a second inductor line which are mutually coupled and arranged in an interleaved manner from bottom to top, the first inductor line is connected in series through a vertical through hole to form a first inductor, and the second inductor line is connected in series through a vertical through hole to form a second inductor; one end of the first inductor is connected to the ground port, and the other end is connected to the output port; one end of the second inductor is connected to the input port, and the other end is connected to the output port. The present application solves the problem that the existing balun in the low frequency band has a large volume.
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Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a balun structure. Background Art

[0002] With the rapid development of electronic circuit technologies and electronic component packaging technologies, people have put forward increasingly higher requirements for the miniaturization of electronic products. A balun is a balanced-unbalanced converter. In addition to completing the mutual conversion of signals from an unbalanced port to a balanced port, it generally also has an impedance transformation function. It is widely used in the feeding networks of antennas, differential amplifiers, balanced mixers and other systems that require differential circuits. With the continuous development of electronic systems towards miniaturization, light weight and high performance, higher requirements have also been put forward for the size of baluns.

[0003] For existing broadband baluns, such as the invention patent with the published patent number CN106684516A and the patent name of a broadband three-wire balun, this balun adopts a three-wire balun structure. When its center frequency is 2.1 GHz, the size has reached 4.6 mm * 4.7 mm. If this balun is to achieve a lower frequency, the length of the coupling line needs to be increased, and in this case, the size of the balun will be greater than or equal to 4.6 mm * 4.7 mm, which does not conform to the development trend of balun miniaturization and is also not conducive to the integration of the balun with other circuit components. Summary of the Invention

[0004] The embodiments of this application provide a balun structure, which solves the problem of the large volume of existing baluns in the low-frequency band.

[0005] The present invention is implemented as follows. A balun structure includes:

[0006] A substrate, on the outer side of which there are provided an input port, an output port and a ground port;

[0007] A circuit layer, which is arranged inside the substrate;

[0008] The circuit layer includes a ground layer and an interleaved inductor layer. The interleaved inductor layer is composed of a first inductor line and a second inductor line that are mutually coupled and arranged in an interleaved manner from bottom to top. The first inductor line is connected in series through vertical vias to form a first inductor, and the second inductor line is connected in series through vertical vias to form a second inductor;

[0009] One end of the first inductor is connected to the ground port, and the other end is connected to the output port;

[0010] One end of the second inductor is connected to the input port, and the other end is connected to the output port.

[0011] According to the balun structure provided by the embodiments of the present application, the first inductor line and the second inductor line are arranged in a staggered manner from bottom to top to form a staggered inductor layer. The first inductor line and the second inductor line can be coupled to each other for energy transfer. Compared with the existing balun, the balun of the embodiments of the present application only needs to adopt one ground layer and two inductors, the structure is simplified, the manufacturing complexity is reduced, and the volume is smaller when applied in the low frequency band.

[0012] In one embodiment, there is one input port, and the input port is provided with an input electrode;

[0013] There are two output ports, namely a first output port and a second output port. The first output port is provided with a first output electrode, and the second output port is provided with a second output electrode;

[0014] There are two ground ports, and the ground ports are provided with ground electrodes;

[0015] One end of the first inductor is connected to the ground electrode, and the other end is connected to the first output electrode;

[0016] One end of the second inductor is connected to the input electrode, and the other end is connected to the second output electrode.

[0017] In one embodiment, the ground layer is located above the staggered inductor layer, and the ground layer is used to connect the ground electrode to form a shielding cover.

[0018] In one embodiment, the ground layer is in a grid structure.

[0019] In one embodiment, the first inductor line has eight segments, and the first inductor line is a planar spiral inductor;

[0020] The second inductor line has eight segments, and the second inductor line is a planar spiral inductor.

[0021] In one embodiment, in the direction of the staggered arrangement of the first inductor line and the second inductor line, two adjacent first inductor lines and second inductor lines face each other.

[0022] In one embodiment, in the direction from bottom to top, the first layer, the fourth layer, the fifth layer, the eighth layer, the ninth layer, the twelfth layer, the thirteenth layer and the sixteenth layer of the staggered inductor layer are all the first inductor lines;

[0023] The second layer, the third layer, the sixth layer, the seventh layer, the tenth layer, the eleventh layer, the fourteenth layer and the fifteenth layer of the staggered inductor layer are all the second inductor lines.

[0024] In one embodiment, the second inductive line patterns of the third layer and the eleventh layer of the interleaved inductance layer are the same, the first inductive line patterns of the fourth layer and the twelfth layer are the same, the first inductive line patterns of the fifth layer and the thirteenth layer are the same, the second inductive line patterns of the sixth layer and the fourteenth layer are the same, the second inductive line patterns of the seventh layer and the fifteenth layer are the same, and the first inductive line patterns of the eighth layer and the sixteenth layer are the same.

[0025] In one embodiment, the input electrode, the first output electrode, the second output electrode, and the ground electrode are all three-layer metal structures;

[0026] The three-layer metal structure includes a silver layer, a nickel layer, and a tin layer. The nickel layer is located between the silver layer and the tin layer, and the tin layer is away from the substrate.

[0027] In one embodiment, the substrate is a ceramic substrate in the shape of a cuboid, and the length of the ceramic substrate is 2.0 mm, the width of the ceramic substrate is 1.25 mm, and the height of the ceramic substrate is 0.95 mm.

[0028] In one embodiment, the passband of the balun structure is 240 MHz - 1150 MHz, and the insertion loss within the passband is ≤ 1.40 dB;

[0029] The amplitude imbalance of the balun structure is ≤ 1.10 dB, and the phase imbalance of the balun structure is ≤ 6.0°.

[0030] The beneficial effects of the balun structure provided by this application are as follows: This application uses two inductors and a ground layer. Compared with the existing balun, the number of inductors and the ground layer is reduced, the balun structure is simplified, the complexity of balun production is reduced, the volume is smaller when applied in the low-frequency band, the bandwidth is wider, and the insertion loss is also better. Description of the Drawings

[0031] Figure 1 is a schematic structural diagram of the balun structure provided by the embodiment of this application.

[0032] Figure 2 is a schematic diagram of the circuit layer arrangement of the balun structure provided by the embodiment of this application.

[0033] Figure 3 is the circuit schematic diagram of the balun structure provided by the embodiment of this application.

[0034] Figure 4 is Figure 2 the pattern schematic diagram of L22 and L26 in

[0035] Figure 5 is Figure 2 the pattern schematic diagram of L12 and L16 in

[0036] Figure 6 Is Figure 2 Schematic diagram of the patterns of L13 and L17 in

[0037] Figure 7 Is Figure 2 Schematic diagram of the patterns of L23 and L27 in

[0038] Figure 8 Is Figure 2 Schematic diagram of the patterns of L24 and L28 in

[0039] Figure 9 Is Figure 2 Schematic diagram of the patterns of L14 and L18 in

[0040] Figure 10 Is Figure 2 Schematic diagram of the pattern of L11 in

[0041] Figure 11 Is Figure 2 Schematic diagram of the pattern of L15 in

[0042] Figure 12 Is Figure 2 Schematic diagram of the pattern of L21 in

[0043] Figure 13 Is Figure 2 Schematic diagram of the pattern of L25 in

[0044] Figure 14 Is Figure 2 Schematic diagram of the patterns of P1 and P2 in

[0045] Figure 15 Is Figure 2 Schematic diagram of the pattern of the ground layer in

[0046] Reference numerals: 10, substrate; 11, input port; 12, output port; 13, ground port; 121, first output port; 122, second output port;

[0047] 20, circuit layer; 21, ground layer; 22, first inductor; 23, second inductor. Detailed implementation manners

[0048] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0050] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically defined.

[0051] The embodiment of the present application provides a balun structure, which solves the problem of large volume of the existing balun in the low-frequency band.

[0052] Referring to Figure 1 , the balun structure provided by the embodiment of the present application includes a substrate 10, an input port 11, an output port 12, and a ground port 13 are arranged on the outer side of the substrate 10; a circuit layer 20, the circuit layer 20 is arranged inside the substrate 10; the circuit layer 20 includes a ground layer 21 and an interleaved inductor layer, the interleaved inductor layer is composed of a first inductor line and a second inductor line that are mutually coupled and arranged in an interleaved manner from bottom to top, the first inductor line is connected in series through a vertical via to form a first inductor 22, and the second inductor line is connected in series through a vertical via to form a second inductor 23; one end of the first inductor 22 is connected to the ground port 13, and the other end is connected to the output port 12; one end of the second inductor 23 is connected to the input port 11, and the other end is connected to the output port 12.

[0053] According to the balun structure provided by the embodiment of the present application, the first inductor line and the second inductor line are arranged in an interleaved manner from bottom to top to form an interleaved inductor layer. The mutual coupling of the first inductor line and the second inductor line can be used for energy transmission. Compared with the existing balun, the balun of the embodiment of the present application only needs to adopt one ground layer 21 and two inductors, the structure is simplified, the manufacturing complexity is reduced, and the volume is smaller when applied in the low-frequency band.

[0054] It should be noted that the balun of the embodiment of the present application is fabricated using the LTCC process. The above-mentioned substrate 10 is a ceramic substrate, which is made of low-temperature co-fired ceramic powder. The sintering temperature is 860°C to 900°C. The dielectric constant of the ceramic powder is 8 ± 2, and the dielectric loss factor is tanα ≤ 0.005. Further, the ceramic substrate is in the shape of a cuboid. The length of the ceramic substrate in the embodiment of the present application is 2.0 mm, the width is 1.25 mm, and the height is 0.95 mm. The first inductor 22, the second inductor 23, and the ground layer 21 are encapsulated within the ceramic substrate.

[0055] In one embodiment, referring to Figure 1 , there is one input port 11, and the input port 11 is provided with an input electrode; there are two output ports 12, namely the first output port 121 and the second output port 122. The first output port 121 is provided with a first output electrode, and the second output port 122 is provided with a second output electrode; there are two ground ports 13, and the ground ports 13 are provided with ground electrodes; one end of the first inductor 22 is connected to the ground electrode, and the other end is connected to the first output electrode; one end of the second inductor 23 is connected to the input electrode, and the other end is connected to the second output electrode.

[0056] It should be noted that by setting the electrodes to connect the inductor to the external circuit, the connection is more convenient. It only needs to connect the external circuit to the ports provided on the outer side of the substrate 10. Specifically, the input electrode, the first output electrode, the second output electrode, and the ground electrode are all three-layer metal structures; the three-layer metal structure includes a silver layer, a nickel layer, and a tin layer. The nickel layer is located between the silver layer and the tin layer, and the tin layer is away from the substrate 10. The electrodes with a three-layer metal structure can ensure the welding reliability of the product.

[0057] Optionally, inner electrodes are provided on the first inductor 22, the second inductor 23, and the ground layer 21, which can facilitate the connection of the first inductor 22, the second inductor 23, and the ground layer 21 to the ports respectively. The inner electrodes are made of silver paste. The sintering temperature of the silver paste is 860°C to 900°C, the silver content of the silver paste is 85 ± 5%, and the thickness of the silver layer is 10 μm ± 3 μm.

[0058] In one embodiment, referring to Figure 2 , the ground layer 21 is located above the interleaved inductor layer, and the ground layer 21 is used to connect the ground electrode to form a shielding cover.

[0059] It should be noted that the above-mentioned ground layer 21 can be placed above the interleaved inductor layer or below the interleaved inductor layer. When the ground layer 21 is placed above the interleaved inductor layer, a shielding cover can be formed by connecting to the external electrode for grounding.

[0060] Referring to Figure 15, the grounding layer 21 is in a tic-tac-toe grid structure. This is beneficial for reducing the parasitic capacitance of the inductor to the ground, facilitating the reduction of the product height, and reducing the amount of metallic silver paste used for the grounding layer 21, thereby saving material costs.

[0061] In one embodiment, optionally, the first inductor line has eight segments, and the first inductor line is a planar spiral inductor; the second inductor line has eight segments, and the second inductor line is a planar spiral inductor.

[0062] In the above arrangement, the eight segments of the first inductor line are respectively distributed on different planes, and the eight segments of the first inductor line can have the same length or different lengths, which is not limited in the embodiments of the present application. The first inductor lines on different planes are connected in series through vias to form the first inductor 22; the eight segments of the second inductor line are respectively distributed on different planes, and the eight segments of the second inductor line can have the same length or different lengths, which is not limited in the embodiments of the present application. The second inductor lines on different planes are connected in series through vias to form the second inductor 23; both the first inductor line and the second inductor line are arranged in the form of planar spiral inductors, which can achieve the maximum utilization of space, thereby reducing the volume of the substrate 10 and the volume of the balun.

[0063] Reference Figure 2 , the eight segments of the first inductor line are respectively L11, L12, L13, L14, L15, L16, L17, and L18, and L11, L12, L13, L14, L15, L16, L17, and L18 are connected in series to form the first inductor 22; the eight segments of the second inductor line are respectively L21, L22, L23, L24, L25, L26, L27, and L28, and L21, L22, L23, L24, L25, L26, L27, and L28 are connected in series to form the second inductor 23.

[0064] In one embodiment, optionally, in the direction where the first inductor line and the second inductor line are arranged in an interleaved manner, two adjacent first inductor lines and second inductor lines face each other. This is beneficial for enhancing the coupling degree between the first inductor line and the second inductor line, thereby better transmitting energy from the input end to the output end.

[0065] In one embodiment, reference Figure 2 , in the direction from bottom to top, the first layer L11, the fourth layer L12, the fifth layer L13, the eighth layer L14, the ninth layer L15, the twelfth layer L16, the thirteenth layer L17, and the sixteenth layer L18 of the interleaved inductor layer are all first inductor lines; the second layer L21, the third layer L22, the sixth layer L23, the seventh layer L24, the tenth layer L25, the eleventh layer L26, the fourteenth layer L27, and the fifteenth layer L28 of the interleaved inductor layer are all second inductor lines.

[0066] With the above arrangement, reference Figure 2, L11, L21, L22, L12, L13, L23, L24, L14, L15, L25, L26, L16, L17, L27, L28, and L18 are arranged in sequence from bottom to top in the direction along the Z-axis. The input energy is transmitted to the output end through the coupling between L11 and L21, L22 and L12, L13 and L23, L24 and L14, L15 and L25, L26 and L16, L17 and L27, and L28 and L18 in pairs.

[0067] In one embodiment, optionally, the second inductive wire patterns of the third layer L22 and the eleventh layer L26 of the interleaved inductance layer are the same, the first inductive wire patterns of the fourth layer L12 and the twelfth layer L16 are the same, the first inductive wire patterns of the fifth layer L13 and the thirteenth layer L17 are the same, the second inductive wire patterns of the sixth layer L23 and the fourteenth layer L27 are the same, the second inductive wire patterns of the seventh layer L24 and the fifteenth layer L28 are the same, and the first inductive wire patterns of the eighth layer L14 and the sixteenth layer L18 are the same. With the above settings, the patterns of some inductive wires are consistent, which can effectively reduce the number of stencils required in the balun forming process and simplify the forming process.

[0068] Optionally, the passband of the balun structure is 240 MHz - 1150 MHz, and the insertion loss within the passband is ≤ 1.40 dB; the amplitude imbalance of the balun structure is ≤ 1.10 dB, and the phase imbalance of the balun structure is ≤ 6.0°.

[0069] Both the first inductor 22 and the second inductor 23 in the embodiments of the present application are 1 / 4 wavelength coupled lines. Most common baluns are composed of four 1 / 4 wavelength coupled lines plus three ground layers, while the balun in the embodiments of the present application only needs to adopt two 1 / 4 wavelength coupled lines plus one ground layer 21, with a simplified structure and reduced manufacturing complexity. It can be effectively applied to low frequency bands, that is, frequencies as low as 150 MHz, with a relative bandwidth of more than 130%, and the size is only 2.0 mm * 1.25 mm * 0.95 mm. In this way, the size of the balun is smaller, and the insertion loss is also better, which is beneficial to the miniaturization of the balun.

[0070] Exemplarily, when the cut-off frequency of the balun is 240 MHz - 1150 MHz, the two inductors and one ground layer 21 of the balun are encapsulated in a ceramic substrate with a size of 2.0 mm * 1.25 mm * 0.95 mm (length * width * height); the ceramic substrate is made of low-temperature co-fired ceramic powder, the sintering temperature is 875 °C, the dielectric constant of the ceramic powder is 7.8, and the dielectric loss factor tanα is 0.005; the inner electrode is made of silver paste, the sintering temperature of the silver paste is 875 °C, the silver content of the silver paste is 85%, and the silver layer thickness is 10 microns.

[0071] Reference Figure 2, the balun is fabricated using the LTCC process. The specific fabrication process is as follows: during the forming process, first stack some blank dielectric layers with a blank dielectric film, print the coupling line L11 on the A surface, stack a perforated dielectric film, print the coupling line L21 on the B surface, stack a perforated dielectric film, fill and print metal vias, print the coupling line L22 on the C surface, stack a perforated dielectric film, fill and print metal vias, print the coupling line L12 on the D surface, stack a perforated dielectric film, print the coupling line L13 on the E surface, stack a perforated dielectric film, fill and print metal vias, print the coupling line L23 on the F surface, stack a perforated dielectric film, print the coupling line L24 on the G surface, stack a perforated dielectric film, print the coupling line L14 on the H surface, stack a perforated dielectric film, print the coupling line L15 on the I surface, stack a perforated dielectric film, fill and print metal vias, print the coupling line L25 on the J surface, stack a perforated dielectric film, print the coupling line L26 on the K surface, stack a perforated dielectric film, print the coupling line L16 on the L surface, stack a perforated dielectric film, fill and print metal vias, print the coupling line L17 on the M surface, stack a perforated dielectric film, print the coupling line L27 on the N surface, stack a perforated dielectric film, print the coupling line L28 on the O surface, stack a perforated dielectric film, print the coupling line L18 on the P surface, stack a perforated dielectric film, print the output electrodes P1 and P2 on the Q surface, stack a non-perforated dielectric film, print the ground layer 21 on the R surface, stack the upper blank dielectric film, and print the identification pattern. Specifically, the patterns of L11, L21, L22, L12, L13, L23, L24, L14, L15, L25, L26, L16, L17, L27, L28, L18, P1, P2, and the ground layer 21 are as Figures 4 - 15 shown.

[0072] Refer to Figure 3 , the circuit principle of the balun in the embodiment of this application is as Figure 3 shown. In the figure, L1 is the first inductor and L2 is the second inductor.

[0073] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claimed rights.

Claims

1. A balun structure, characterized in that, it includes: a substrate (10), an input port (11), an output port (12) and a ground port (13) are arranged on the outer side of the substrate (10); a circuit layer (20), the circuit layer (20) is arranged inside the substrate (10); the circuit layer (20) includes a ground layer (21) and an interleaved inductor layer, the interleaved inductor layer is composed of a first inductor line and a second inductor line which are mutually coupled and arranged in an interleaved manner from bottom to top, both the first inductor line and the second inductor line have eight segments, and both the first inductor line and the second inductor line are planar spiral inductors; the first inductor line is connected in series through vertical vias to form a first inductor (22), and the second inductor line is connected in series through vertical vias to form a second inductor (23); one end of the first inductor (22) is connected to the ground port (13), and the other end is connected to the output port (12); one end of the second inductor (23) is connected to the input port (11), and the other end is connected to the output port (12); there is one input port (11), and an input electrode is arranged on the input port (11); there are two output ports (12), namely a first output port (121) and a second output port (122), a first output electrode is arranged on the first output port (121), and a second output electrode is arranged on the second output port (122); there are two ground ports (13), and ground electrodes are arranged on the ground ports (13); one end of the first inductor (22) is connected to the ground electrode, and the other end is connected to the first output electrode; one end of the second inductor (23) is connected to the input electrode, and the other end is connected to the second output electrode.

2. The balun structure according to claim 1, characterized in that, the ground layer (21) is located above the interleaved inductor layer, and the ground layer (21) is used to connect the ground electrodes to form a shielding cover.

3. The balun structure according to claim 2, characterized in that, the ground layer (21) is in a grid structure.

4. The balun structure according to claim 1, characterized in that, in the direction of the interleaved arrangement of the first inductor line and the second inductor line, two adjacent first inductor lines and second inductor lines face each other.

5. The balun structure according to claim 4, characterized in that, in the direction from bottom to top, the first layer, the fourth layer, the fifth layer, the eighth layer, the ninth layer, the twelfth layer, the thirteenth layer and the sixteenth layer of the interleaved inductor layer are all the first inductor lines; the second layer, the third layer, the sixth layer, the seventh layer, the tenth layer, the eleventh layer, the fourteenth layer and the fifteenth layer of the interleaved inductor layer are all the second inductor lines.

6. The balun structure according to claim 5, characterized in that, The second inductive line patterns of the third and eleventh layers of the interleaved inductance layer are the same, the first inductive line patterns of the fourth and twelfth layers are the same, the first inductive line patterns of the fifth and thirteenth layers are the same, the second inductive line patterns of the sixth and fourteenth layers are the same, the second inductive line patterns of the seventh and fifteenth layers are the same, and the first inductive line patterns of the eighth and sixteenth layers are the same.

7. The balun structure according to claim 1, wherein, the input electrode, the first output electrode, the second output electrode, and the ground electrode are all three-layer metal structures; The three-layer metal structure includes a silver layer, a nickel layer, and a tin layer. The nickel layer is located between the silver layer and the tin layer, and the tin layer is away from the substrate.

8. The balun structure according to any one of claims 1-7, wherein, the substrate (10) is a ceramic substrate in the shape of a cuboid, and the length of the ceramic substrate is 2.0 mm, the width of the ceramic substrate is 1.25 mm, and the height of the ceramic substrate is 0.95 mm.

9. The balun structure according to claim 8, wherein, the passband of the balun structure is 240 MHz - 1150 MHz, and the insertion loss within the passband is ≤ 1.40 dB; the amplitude unbalance of the balun structure is ≤ 1.10 dB, and the phase unbalance of the balun structure is ≤ 6.0°.

Citation Information

Patent Citations

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    CN106684516A

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