Control integrated circuit and step-down power converter

Abstract

The application provides a control integrated circuit and a step-down power converter, wherein the semiconductor switch module is turned on according to a high-level driving signal and generates a first low level, or is turned off according to a low-level driving signal and generates a first high level; the field effect tube switch module is turned on according to the first low level and an auxiliary power module and generates a second high level, or is turned off according to the first high level and generates a second low level; the triode driving module increases an output voltage according to the second high level and the auxiliary power module until a switch transistor is turned on, or reduces the output voltage according to the second low level until the switch transistor is turned off. The application comprises a semiconductor driving assembly composed of the semiconductor switch module, the field effect tube switch module, the diode module and the triode driving module, so that there is no low-impedance connection relationship between the control module and the direct-current input voltage, and the application can be directly applied to a high direct-current input voltage and a large-duty-cycle application scenario.

Description

Technical Field

[0001] This application belongs to the field of power supply technology, and in particular relates to a control integrated circuit and a buck power converter. Background Technology

[0002] Buck converters typically contain a control integrated circuit that directly drives the switching transistors to turn on and off. However, the voltage withstand value of the control integrated circuit is generally low, and when the input voltage is high, the voltage withstand value of the existing control integrated circuit cannot meet the requirements.

[0003] In order to enable the control integrated circuit to be used in applications with high input voltage, a drive transformer is usually used to control the switching transistor to turn on and off. However, this method is not suitable for scenarios with large duty cycles. In addition, the magnetizing inductance of the drive transformer has a delay effect on the drive signal, and the transformer itself is relatively large. Summary of the Invention

[0004] The purpose of this application is to provide a control integrated circuit and a buck power converter, which aims to solve the problem of low withstand voltage of traditional control integrated circuits.

[0005] To achieve the above objectives, in a first aspect, embodiments of this application provide a control integrated circuit, comprising:

[0006] The semiconductor switch module is configured to turn on and generate a first low level according to a high-level drive signal, or turn off and generate a first high level according to a low-level drive signal;

[0007] A diode module, electrically connected to the field-effect transistor switching module, is configured to clamp the field-effect transistor switching module;

[0008] A field-effect transistor switching module, electrically connected to the semiconductor switching module and the auxiliary power supply module, is configured to turn on and generate a second high level according to the first low level and the auxiliary power supply module, or to turn off and generate a second low level according to the first high level;

[0009] The transistor driver module, electrically connected to the MOSFET switching module and the auxiliary power supply module, is configured to increase the output voltage until the switching transistor is turned on according to the second high level and the auxiliary power supply module; or to decrease the output voltage until the switching transistor is turned off according to the second low level.

[0010] In one possible implementation of the first aspect, the semiconductor switching module includes a first resistor, a sixth resistor, and a second NPN transistor;

[0011] One end of the first resistor is electrically connected to the drive signal, the other end of the first resistor is electrically connected to the base of the second NPN transistor, and the collector of the second NPN transistor is electrically connected to one end of the sixth resistor.

[0012] Alternatively, the semiconductor switching module includes a first resistor, a sixth resistor, and a second NMOS transistor;

[0013] One end of the first resistor is electrically connected to the drive signal, the other end of the first resistor is electrically connected to the gate of the second NMOS transistor, and the drain of the second NMOS transistor is electrically connected to one end of the sixth resistor.

[0014] In another possible implementation of the first aspect, the field-effect transistor switching module includes a second resistor, a seventh resistor, and a third PMOS transistor;

[0015] One end of the second resistor is electrically connected to the other end of the sixth resistor, the other end of the second resistor is electrically connected to one end of the seventh resistor and the gate of the third PMOS transistor, and the source of the third PMOS transistor and the other end of the seventh resistor are electrically connected to the auxiliary power supply module.

[0016] In another possible implementation of the first aspect, the transistor driving module includes a third resistor, a fourth resistor, a fourth NPN transistor, a fifth PNP transistor, and a fifth resistor;

[0017] One end of the third resistor is electrically connected to the drain of the third PMOS transistor, and the other end of the third resistor is electrically connected to the base of the fourth NPN transistor, the base of the fifth PNP transistor, and one end of the fourth resistor. The collector of the fourth NPN transistor is electrically connected to the auxiliary power supply module. The emitters of the fourth NPN transistor and the fifth PNP transistor are electrically connected to one end of the fifth resistor. The other end of the fourth resistor and the collector of the fifth PNP transistor are grounded.

[0018] In another possible implementation of the first aspect, the semiconductor switching module further includes a tenth resistor;

[0019] One end of the tenth resistor is electrically connected to the base of the second NPN transistor, and the other end of the tenth resistor is electrically connected to the emitter of the second NPN transistor.

[0020] Alternatively, one end of the tenth resistor is electrically connected to the gate of the second NMOS transistor, and the other end of the tenth resistor is electrically connected to the source of the second NMOS transistor.

[0021] In another possible implementation of the first aspect, the field-effect transistor switching module further includes a third diode, a fourteenth resistor, and an eighth NPN transistor;

[0022] The negative terminal of the third diode is electrically connected to one end of the second resistor, one end of the fourteenth resistor, and the base of the eighth NPN transistor. The positive terminal of the third diode is electrically connected to the emitter of the eighth NPN transistor, one end of the seventh resistor, and the gate of the third PMOS transistor. The other end of the fourteenth resistor and the collector of the eighth NPN transistor are electrically connected to the auxiliary power supply module.

[0023] In another possible implementation of the first aspect, the transistor driving module further includes an eighth resistor, a ninth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a sixth NPN transistor, a seventh PNP transistor, a first Zener diode, and a fourth capacitor.

[0024] One end of the eighth resistor is electrically connected to the emitter of the fourth NPN transistor and the emitter of the fifth PNP transistor. The other end of the eighth resistor is electrically connected to the base of the sixth NPN transistor, the base of the seventh PNP transistor, and one end of the ninth resistor. The collector of the fourth NPN transistor is electrically connected to one end of the twelfth resistor. The collector of the sixth NPN transistor is electrically connected to one end of the thirteenth resistor. The other ends of the twelfth and thirteenth resistors are electrically connected to the auxiliary power supply module. The emitters of the sixth NPN transistor and the seventh PNP transistor, and the cathode of the first Zener diode are electrically connected to one end of the fourth capacitor. The anode of the first Zener diode and the other end of the fourth capacitor are electrically connected to one end of the fifth resistor. The other end of the fifth resistor is electrically connected to one end of the eleventh resistor. The other end of the ninth resistor, the collector of the seventh PNP transistor, and the other end of the eleventh resistor are grounded.

[0025] In another possible implementation of the first aspect, the control integrated circuit further includes a control module, a first capacitor, a first sampling resistor, a first NMOS transistor, a first diode, a first inductor, and a second capacitor;

[0026] The control module is electrically connected to the semiconductor switch module, one end of the first capacitor, and one end of the first sampling resistor. The other end of the first capacitor and the drain of the first NMOS transistor are electrically connected to the positive terminal of the input voltage terminal. The other end of the first sampling resistor is grounded. The gate of the first NMOS transistor is electrically connected to the transistor driving module. The source of the first NMOS transistor is electrically connected to one end of the first inductor and the negative terminal of the first diode. The other end of the first inductor and one end of the second capacitor are electrically connected to the output voltage terminal. The positive terminal of the first diode and the other end of the second capacitor are grounded.

[0027] In another possible implementation of the first aspect, the control integrated circuit further includes a control module, a first capacitor, a first sampling resistor, a first NMOS transistor, a ninth NMOS transistor, a first inductor, and a second capacitor;

[0028] The control module is electrically connected to the semiconductor switch module, one end of the first capacitor, and one end of the first sampling resistor. The other end of the first capacitor and the drain of the first NMOS transistor are electrically connected to the positive terminal of the input voltage terminal. The other end of the first sampling resistor is grounded. The gate of the first NMOS transistor is electrically connected to the transistor driving module. The source of the first NMOS transistor is electrically connected to one end of the first inductor and the drain of the ninth NMOS transistor. The other end of the first inductor and one end of the second capacitor are electrically connected to the output voltage terminal. The source of the ninth NMOS transistor and the other end of the second capacitor are grounded.

[0029] Secondly, embodiments of this application provide a buck power converter, including the aforementioned control integrated circuit.

[0030] The beneficial effects of this invention compared to the prior art are as follows: The aforementioned control integrated circuit, through a semiconductor switching module, turns on and generates a first low level based on a high-level drive signal, or turns off and generates a first high level based on a low-level drive signal; through a field-effect transistor switching module, turns on and generates a second high level based on the first low level and an auxiliary power supply module, or turns off and generates a second low level based on the first high level; through a diode module, clamps the field-effect transistor switching module; through a transistor driving module, increases the output voltage until the switching transistor turns on based on the second high level and the auxiliary power supply module; or decreases the output voltage until the switching transistor turns off based on the second low level. This application uses a semiconductor switching module, a field-effect transistor switching module, a diode module, and a transistor driving module to form a semiconductor driving component, eliminating the low-impedance connection between the control module and the DC input voltage. This allows for direct application in scenarios with high DC input voltage and large duty cycles, and is also small in size, low in cost, and widely applicable. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a first structure of a conventional control integrated circuit provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of a second structure of a conventional control integrated circuit provided in an embodiment of this application;

[0034] Figure 3 A driving voltage waveform diagram for a first structure of a conventional control integrated circuit provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of a third structure of a conventional control integrated circuit provided in an embodiment of this application;

[0036] Figure 5 A driving voltage waveform diagram for a third structure of a conventional control integrated circuit provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the overall structure of the control integrated circuit provided in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram of a first structure of a control integrated circuit provided in an embodiment of this application;

[0039] Figure 8 This is a schematic diagram of a second structure of the control integrated circuit provided in an embodiment of this application;

[0040] Figure 9 This is a schematic diagram of a first specific structure of the control integrated circuit provided in an embodiment of this application;

[0041] Figure 10 This is a schematic diagram of a second specific structure of the control integrated circuit provided in the embodiments of this application;

[0042] Figure 11 The output voltage waveform of the control integrated circuit provided in the embodiment of this application is shown.

[0043] The following are the labeling elements in the figure:

[0044] 1-Semiconductor switch module, 2-Field-effect transistor switch module, 3-Transistor driver module, 4-Auxiliary power supply module, 5-Diode module, 10-Control module. Detailed Implementation

[0045] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0046] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on the other component. When a component is referred to as being "electrically connected to" another component, it can be directly electrically connected to or indirectly electrically connected to the other component.

[0047] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0049] Currently, buck converters generally include a control integrated circuit that directly drives the switching transistors to turn on and off. However, the voltage withstand value of the control integrated circuit is generally low, and when the input voltage is high, the voltage withstand value of the existing control integrated circuit cannot meet the requirements.

[0050] Figure 1 This is a schematic diagram of a first structure of a conventional control integrated circuit provided in an embodiment of this application. Figure 2 This is a schematic diagram of a second structure of a conventional control integrated circuit provided in the embodiments of this application. For a conventional buck power converter with DC input and DC output, such as... Figure 1 As shown, it generally includes an input filter capacitor, a current sampling resistor, a high-voltage side switching transistor, a freewheeling diode, a filter inductor, an output filter capacitor, and a control circuit; or as shown in the diagram. Figure 2 As shown, it includes an input filter capacitor, a current sampling resistor, a high-voltage side switching transistor, a low-voltage side switching transistor, a filter inductor, an output filter capacitor, and a control circuit.

[0051] like Figure 1 As shown, the first transistor Q1 is typically a field-effect transistor, and the maximum voltage range that its gate and source can withstand is fixed (its absolute value is generally less than 30V, for example, ±30V). Based on the working principle of the buck converter, the drive voltage U(GS) applied between the gate and source of the first transistor Q1 will have the following states:

[0052] When U(G,S) is a high voltage (e.g., 10V), the first transistor Q1 is turned on; when U(G,S) is a low voltage (e.g., 0V), the first transistor Q1 is turned off. Therefore, the voltage U(S, GND) between the source of the first transistor Q1 and the negative terminal of the first auxiliary power supply (VCC1-GND) (or the negative terminal of the input voltage VI-GND) has the following equation:

[0053] When the first transistor Q1 is turned on, U(S,GND) = U(VI,GND);

[0054] When the first transistor Q1 is turned off, U(S,GND) = -VD1 = -0.7V.

[0055] The source voltage U(S, GND) of the first transistor Q1 is approximately the input voltage VI during the turn-on period of the first transistor Q1. During the turn-off period of the first transistor Q1, due to the freewheeling effect of the first inductor L1, the voltage is approximately the negative forward voltage drop VD1 (-0.7V) of the first diode D1.

[0056] It can be seen that the voltage U(G,GND) between the gate of the first transistor Q1 and the negative terminal of the first auxiliary power supply (VCC1-GND) (or the negative terminal of the input voltage VI-GND) has the following equation:

[0057] When the first transistor Q1 is turned on, U(G,GND) = U(VI,GND) + U(G,S);

[0058] When the first transistor Q1 is turned off, U(G,GND)=-VD1=-0.7V.

[0059] It can be seen that the voltage value U(G,GND) between the gate of the first transistor Q1 and the negative terminal of the first auxiliary power supply (VCC1-GND) (or the negative terminal of the input voltage VI-GND) varies in the range of -0.7V to U(VI,GND)+U(G,S).

[0060] Because the drive signal output pin of control module 10 is connected to the gate of the first transistor Q1 through a small drive resistor (generally less than 100Ω), the voltage value U(G,GND) of its gate is basically equal to the output voltage of the drive pin of control module 10. Therefore, the output voltage variation range of the drive pin of control module 10 is -0.7V to U(VI,GND)+U(G,S).

[0061] Figure 3 The output voltage waveform diagram of the first structure of the conventional control integrated circuit provided in the embodiments of this application is as follows: Figure 3 As shown, Ton is the turn-on time of the first transistor Q1 in one switching cycle, Toff is the turn-off time of the first transistor Q1 in one switching cycle, T is the switching cycle time of the first transistor Q1, U(G,S) is the voltage between the gate (G) and source (S) of the first transistor Q1, U(S,GND) is the voltage between the source (S) of the first transistor Q1 and the negative terminal of the first auxiliary power supply (VCC1-GND), and U(G,GND) is the voltage between the gate (G) of the first transistor Q1 and the negative terminal of the first auxiliary power supply (VCC1-GND). Because the maximum value of the voltage U(G,GND) at the drive pin of the control module 10 is U(VI,GND)+U(G,S), and the drive circuit of the control module 10 is a high-current, low-impedance circuit, the internal integrated circuit connected to the drive pin of the control module 10 must also be able to withstand a voltage with a maximum value of U(VI,GND)+U(G,S).

[0062] When the input voltage U(VI, GND) in buck converter applications is high (e.g., greater than 100V), existing commercially available control integrated circuits do not meet this voltage withstand requirement. Developing dedicated high-voltage control integrated circuits would be far more expensive than the market price range, making it economically unfeasible.

[0063] Figure 4 Figure 4 shows a third structural schematic diagram of a conventional control integrated circuit provided in the embodiments of this application. In the prior art, in order to apply the buck power converter to application scenarios with high input voltage, a driving method of controlling the conduction and turn-off of the switching transistor by driving the transformer is adopted. However, this method is not suitable for scenarios with a large duty cycle. At the same time, the magnetizing inductance of the driving transformer has a delay effect on the driving signal, and the transformer itself is large in size.

[0064] like Figure 4 As shown, T1 is the first drive transformer, D is the positive terminal of the drive output voltage of control module 10, and other circuit symbols are the same as those in the diagram. Figure 1The same applies. The low-impedance drive output signal VD of the control module 10 is connected to the primary side of the first drive transformer T1 through the second transistor Q2 and the third transistor Q3, and its maximum withstand voltage value is the first auxiliary power supply voltage value U(VCC1,GND). The control module 10 is not connected to the input voltage VI by a low-impedance circuit, so the internal integrated circuit of the control module 10 does not need to withstand the input voltage U(VI,GND), but only the first auxiliary power supply voltage U(VCC1,GND).

[0065] Figure 5 The output voltage waveform diagram of the third structure of the conventional control integrated circuit provided in the embodiments of this application is as follows: Figure 5 As shown, based on the working principle of the step-down power converter, the duty cycle D can be obtained as follows:

[0066] D = Ton / (Ton + Toff)

[0067] D = VO / VI

[0068] Since the first drive transformer T1 needs to satisfy the volt-second balance magnetic reset principle (U1*T1=U2*T2), the absolute value of the positive gate voltage VG1 and the absolute value of the negative gate voltage VG2 of the first transistor Q1 need to satisfy:

[0069] VG1*Ton=VG2*Toff

[0070] Therefore, the duty cycle D of the drive signal voltage U(D,GND) of the control module 10 needs to satisfy the following conditions:

[0071] VG2 = D * VG1 / (1 - D)

[0072] Therefore, the larger the duty cycle D, the larger the ratio of VG2 to VG1. When the duty cycle D = 80%, VG2 = 4 * VG1. According to general specifications, the positive drive voltage U(G,S) of the gate of the first field-effect transistor Q1 is 10V, then VG2 = 4 * VG1 = 40V. At this time, the absolute value of the negative gate voltage VG2 (40V) of the first transistor Q1 is already greater than its maximum tolerable voltage (generally less than 30V). Therefore, the method of using a drive transformer to control the switching transistor is not suitable for applications with a large duty cycle. At the same time, because the magnetizing inductance of the drive transformer has a delay effect on the drive signal, and the transformer itself is relatively large, it is also not suitable for applications with high switching frequency, small size, and high power density. Its applicability is limited, and its practical application value is low.

[0073] To address the aforementioned issues, this application provides a control integrated circuit that comprises a semiconductor drive assembly consisting of a semiconductor switch module, a field-effect transistor switch module, a diode module, and a transistor drive module. This eliminates the need for a low-impedance connection between the control module and the DC input voltage, allowing direct application in scenarios with high DC input voltage and large duty cycles. Furthermore, it is small in size, low in cost, and has a wide range of applications.

[0074] Figure 6 This is a schematic diagram of the overall structure of a control integrated circuit provided in an embodiment of this application, as shown below. Figure 6 As shown, for ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The control integrated circuit may include:

[0075] Semiconductor switch module 1 is configured to turn on and generate a first low level according to a high-level drive signal, or turn off and generate a first high level according to a low-level drive signal;

[0076] The field-effect transistor switching module 2 is electrically connected to the semiconductor switching module 1 and the auxiliary power supply module 4, and is configured to turn on the auxiliary power supply module 4 according to a first low level and generate a second high level, or turn off the auxiliary power supply module 4 according to a first high level and generate a second low level.

[0077] Diode module 5 is electrically connected to field-effect transistor switch module 2 and is configured to clamp field-effect transistor switch module 2;

[0078] The transistor driver module 3, which is electrically connected to the field-effect transistor switching module 2 and the auxiliary power supply module 4, is configured to increase the output voltage until the switching transistor is turned on according to the second high level and the auxiliary power supply module 4; or decrease the output voltage until the switching transistor is turned off according to the second low level.

[0079] In this embodiment, a semiconductor switch module is turned on and generates a first low level based on a high-level drive signal, or turned off and generates a first high level based on a low-level drive signal; a field-effect transistor switch module is turned on and generates a second high level based on the first low level and the auxiliary power supply module, or turned off and generates a second low level based on the first high level; a diode module clamps the field-effect transistor switch module; a transistor drive module increases the output voltage until the switching transistor is turned on based on the second high level and the auxiliary power supply module, or decreases the output voltage until the switching transistor is turned off based on the second low level. This eliminates the low-impedance connection between the control module 10 and the DC input voltage, and all circuits except the semiconductor switch Q2 do not need to withstand high input voltages. This results in lower cost and higher reliability when applied to applications with high input voltages. The auxiliary power supply module 4 includes an auxiliary power supply VCC2, and the diode module includes a second diode D2.

[0080] Figure 7 This is a schematic diagram of a first structure of the control integrated circuit provided in an embodiment of this application. Figure 8 This is a schematic diagram of a second structure of the control integrated circuit provided in the embodiments of this application, as shown below. Figure 7 and Figure 8 As shown, exemplarily, the semiconductor switch module 1 includes a first resistor R1, a sixth resistor R6, and a second NPN transistor Q2;

[0081] One end of the first resistor R1 is electrically connected to the drive signal V1, the other end of the first resistor R1 is electrically connected to the base of the second NPN transistor Q2, and the collector of the second NPN transistor Q2 is electrically connected to one end of the sixth resistor R6.

[0082] Alternatively, the semiconductor switch module 1 includes a first resistor R1, a sixth resistor R6, and a second NMOS transistor Q2;

[0083] One end of the first resistor R1 is electrically connected to the drive signal V1, the other end of the first resistor R1 is electrically connected to the gate of the second NMOS transistor Q2, and the drain of the second NMOS transistor Q2 is electrically connected to one end of the sixth resistor R6.

[0084] In this embodiment, when the drive output signal U1(V1,VCC1-GND) of the control module 10 is high, the current flows from the circuit network node V1 through the first resistor R1, the base (or the gate) of the second NPN transistor Q2, the emitter (or the source) of the second NPN transistor Q2, to the negative terminal of the first auxiliary power supply VCC1-GND. At this time, the second NPN transistor Q2 (or the second NMOS transistor Q2) is turned on, and the voltage value of the circuit network node V2 decreases through the sixth resistor R6. The lowest value of the voltage of the circuit network node V2 is clamped to the negative terminal of the auxiliary power supply VCC2-GND by the second diode D2.

[0085] When the drive output signal U1 (V1, VCC1-GND) of the control module 10 is low, no current flows into the base of the second NPN transistor Q2 (or the gate of the second NMOS transistor Q2), and the second NPN transistor Q2 (or the second NMOS transistor Q2) is cut off.

[0086] like Figure 7 and Figure 8 As shown, exemplarily, the field-effect transistor switching module 2 includes a second resistor R2, a seventh resistor R7, and a third PMOS transistor Q3;

[0087] One end of the second resistor R2 is electrically connected to the other end of the sixth resistor R6. The other end of the second resistor R2 is electrically connected to one end of the seventh resistor R7 and the gate of the third PMOS transistor Q3. The source of the third PMOS transistor Q3 and the other end of the seventh resistor R7 are electrically connected to the auxiliary power supply module 4.

[0088] In this embodiment, when the voltage of circuit network node V2 decreases, current flows from the auxiliary power supply VCC2 through the source of the third PMOS transistor Q3, the gate of the third PMOS transistor Q3, and the second resistor R2 to circuit network node V2. At this time, the voltage between the gate and source of the third PMOS transistor Q3 (which is negative) gradually decreases. When the gate voltage is lower than the turn-on threshold voltage of the third PMOS transistor Q3 (the absolute value of the gate voltage is higher than the absolute value of the threshold voltage), the third PMOS transistor Q3 turns on, and the voltage of circuit network node V3 approaches the voltage of the positive terminal VCC2 of the auxiliary power supply. Simultaneously, due to the clamping effect of the second diode D2, the absolute value of the gate voltage of the third PMOS transistor Q3 is less than the absolute value of the voltage of the auxiliary power supply VCC2, preventing the insulating gate of the third PMOS transistor Q3 from being broken down.

[0089] When the second NPN transistor Q2 (or the second NMOS transistor Q2) is turned off, no current flows through the second resistor R2, the sixth resistor R6, and the base of the third PMOS transistor Q3. Therefore, no current charges the parasitic capacitance between the source and gate of the third PMOS transistor Q3. The charge on the parasitic capacitance between the source and gate of the third PMOS transistor Q3 is discharged through the seventh resistor R7. At this time, the voltage between the gate and source of the third PMOS transistor Q3 (which is negative) gradually increases (the absolute value decreases). When the gate voltage is higher than the turn-on threshold voltage of the third PMOS transistor Q3 (the absolute value of the gate voltage is lower than the absolute value of the threshold voltage), the third PMOS transistor Q3 is turned off.

[0090] like Figure 7 and Figure 8 As shown, exemplarily, the transistor driver module 3 includes a third resistor R3, a fourth resistor R4, a fourth NPN transistor Q4, a fifth PNP transistor Q5, and a fifth resistor R5;

[0091] One end of the third resistor R3 is electrically connected to the drain of the third PMOS transistor Q3. The other end of the third resistor R3 is electrically connected to the base of the fourth NPN transistor Q4, the base of the fifth PNP transistor Q5, and one end of the fourth resistor R4. The collector of the fourth NPN transistor Q4 is electrically connected to the auxiliary power supply module 4. The emitters of the fourth NPN transistor Q4 and the fifth PNP transistor Q5 are electrically connected to one end of the fifth resistor R5. The other end of the fourth resistor R4 and the collector of the fifth PNP transistor Q5 are grounded.

[0092] In this embodiment, when the third PMOS transistor Q3 is turned on, the voltage of the circuit network node V3 is close to the voltage of the positive terminal VCC2 of the auxiliary power supply. Current flows from the auxiliary power supply VCC2 through the source and drain of the third PMOS transistor Q3, the circuit network node V3, the third resistor R3, the base and emitter of the fourth NPN transistor Q4, the fifth resistor R5, the gate of the first NMOS transistor Q1, and the source of the first NMOS transistor Q1 back to the negative terminal VCC2-GND of the auxiliary power supply. When current flows into the base of the fourth NPN transistor Q4, in the amplified state, the maximum current at the collector of the fourth NPN transistor Q4 will be several tens of times the base current. Current flows from the collector into the emitter of the fourth NPN transistor Q4 and the fifth resistor R5 to increase the driving capability and improve the charging speed of the parasitic capacitance between the gate and source of the first NMOS transistor Q1 on the high-voltage side. At this time, the voltage U(G,S) between the gate and source of the first NMOS transistor Q1 gradually increases. When U(G,S) is greater than the turn-on threshold voltage of the first NMOS transistor Q1, the first NMOS transistor Q1 is turned on. At this time, the source voltage of the first NMOS transistor Q1 is close to the positive value of the input DC voltage VI, the current flowing through the first inductor L1 gradually increases, and the DC output voltage U(VO,VO-GND) rises.

[0093] When the third PMOS transistor Q3 is turned off, the circuit network node V3 is at a low level. The charge stored in the parasitic capacitance between the gate and source of the first NMOS transistor Q1 on the high-voltage side splits into two paths after passing through the gate of the first NMOS transistor Q1, the fifth resistor R5, and the emitter of the fifth PNP transistor Q5. Most of the current flows through the collector of the fifth PNP transistor Q5 to the negative terminal of the auxiliary power supply VCC2-GND, and a small portion of the current flows through the base of the fifth PNP transistor Q5 and the fourth resistor R4 to the negative terminal of the auxiliary power supply VCC2-GND. When the charge between the gate and source of the first NMOS transistor Q1 is released, the voltage U(G,S) between the gate and source of the first NMOS transistor Q1 gradually decreases. When the voltage U(G,S) is lower than the turn-on threshold voltage of the first NMOS transistor Q1, the first NMOS transistor Q1 is turned off, and the freewheeling current of the first inductor L1 turns on the first diode D1. At this time, the current flowing through the first inductor L1 gradually decreases, and the DC output voltage U(VO,VO-GND) decreases. The first-stage totem-pole drive circuit is composed of the fourth NPN transistor Q4 and the fifth PNP transistor Q5.

[0094] Figure 9 This is a schematic diagram of a first specific structure of the control integrated circuit provided in an embodiment of this application. Figure 10 This is a schematic diagram of a second specific structure of the control integrated circuit provided in an embodiment of this application. Figure 11The output voltage waveform diagram of the control integrated circuit provided in the embodiments of this application is as follows: Figure 9 and Figure 10 As shown, by way of example, the semiconductor switch module 1 also includes a tenth resistor R10;

[0095] One end of the tenth resistor R10 is electrically connected to the base of the second NPN transistor Q2, and the other end of the tenth resistor R10 is electrically connected to the emitter of the second NPN transistor Q2.

[0096] Alternatively, one end of the tenth resistor R10 is electrically connected to the gate of the second NMOS transistor Q2, and the other end of the tenth resistor R10 is electrically connected to the source of the second NMOS transistor Q2.

[0097] In this embodiment, the tenth resistor R10 is used as a bias resistor to prevent input signal distortion.

[0098] like Figure 9 and Figure 10 As shown, by way of example, the field-effect transistor switching module 2 also includes a third diode D3, a fourteenth resistor R14 and an eighth NPN transistor Q8;

[0099] The negative terminal of the third diode D3 is electrically connected to one end of the second resistor R2, one end of the fourteenth resistor R14, and the base of the eighth NPN transistor Q8. The positive terminal of the third diode D3 is electrically connected to the emitter of the eighth NPN transistor Q8, one end of the seventh resistor R7, and the gate of the third PMOS transistor Q3. The other end of the fourteenth resistor R14 and the collector of the eighth NPN transistor Q8 are electrically connected to the auxiliary power supply module 4.

[0100] In this embodiment, the voltage of the base-emitter PN junction of the eighth NPN transistor Q8 under reverse bias is clamped by the third diode D3, preventing it from being broken down by the reverse high voltage. The fourteenth resistor R14 and the eighth NPN transistor Q8 quickly discharge the residual charge at the gate and source capacitances of the third PMOS transistor Q3 when it is off, reducing the voltage waveform fall time at node V3 and improving the turn-off speed. The seventh resistor R7 discharges the residual charge at the gate and source parasitic capacitances of the second NMOS transistor. The seventh resistor R7 also prevents the second NPN transistor from falsely turning on due to increased base leakage current at high temperatures, increasing reliability.

[0101] like Figure 9 and Figure 10 As shown, exemplarily, the transistor drive module 3 also includes an eighth resistor R8, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a sixth NPN transistor Q6, a seventh PNP transistor Q7, a first Zener diode ZD1, and a fourth capacitor C4.

[0102] One end of the eighth resistor R8 is electrically connected to the emitter of the fourth NPN transistor Q4 and the emitter of the fifth PNP transistor Q5. The other end of the eighth resistor R8 is electrically connected to the base of the sixth NPN transistor Q6, the base of the seventh PNP transistor Q7, and one end of the ninth resistor R9. The collector of the fourth NPN transistor Q4 is electrically connected to one end of the twelfth resistor R12. The collector of the sixth NPN transistor Q6 is electrically connected to one end of the thirteenth resistor R13. The other ends of the twelfth and thirteenth resistors R12 and R13 are electrically connected to the auxiliary power supply module 4. The emitters of the sixth NPN transistor Q6 and the seventh PNP transistor Q7, and the cathode of the first Zener diode ZD1 are electrically connected to one end of the fourth capacitor C4. The anode of the first Zener diode ZD1 and the other end of the fourth capacitor C4 are electrically connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is electrically connected to one end of the eleventh resistor R11. The ninth resistor R9... The other end, the collector of the seventh PNP transistor Q7, and the other end of the eleventh resistor R11 are grounded.

[0103] In this embodiment, a second-stage totem-pole drive current amplifier circuit is formed by the eighth resistor R8, the ninth resistor R9, the thirteenth resistor R13, the sixth NPN transistor Q6, and the seventh PNP transistor Q7. This further reduces the rise time of the drive voltage between the gate and source of the first NMOS transistor Q1, thereby reducing switching losses and improving efficiency. The twelfth resistor R12 is used for the collector current limiting of the fourth NPN transistor Q4, and this resistor can adjust the rise time of the drive voltage between the gate and source of the first NMOS transistor Q1. A negative drive voltage generation circuit is formed by the first Zener diode ZD1 and the fourth capacitor C4. When the drive voltage between the gate and source of the first NMOS transistor Q1 drops and is cut off, this negative voltage can offset the disadvantage that the minimum output voltage (1.4V) of the two-stage totem-pole drive circuit cannot drop to 0V. This ensures that the lowest point of the drive voltage waveform of the first NMOS transistor Q1 is slightly lower than 0V, achieving the purpose of fast and reliable turn-off and anti-interference for the first NMOS transistor Q1.

[0104] For example, the control integrated circuit also includes a control module 10, a first capacitor C1, a first sampling resistor RS1, a first NMOS transistor Q1, a first diode D1, a first inductor L1, and a second capacitor C2;

[0105] The control module 10 is electrically connected to the semiconductor switch module 1, one end of the first capacitor C1 and one end of the first sampling resistor RS1. The other end of the first capacitor C1 and the drain of the first NMOS transistor Q1 are electrically connected to the positive terminal of the input voltage terminal. The other end of the first sampling resistor RS1 is grounded. The gate of the first NMOS transistor Q1 is electrically connected to the transistor drive module 3. The source of the first NMOS transistor Q1 is electrically connected to one end of the first inductor L1 and the negative terminal of the first diode D1. The other end of the first inductor L1 and one end of the second capacitor C2 are electrically connected to the output voltage terminal. The positive terminal of the first diode D1 and the other end of the second capacitor C2 are grounded.

[0106] In this embodiment, the control module 10 outputs a high-level drive signal or a low-level drive signal to control the entire circuit. The circuit is filtered by the first capacitor C1 and the second capacitor C2, the input current signal is sampled by the first sampling resistor RS1, the drive voltage is generated by the first NMOS transistor Q1, the current is freewheeled by the first diode D1, and the circuit is filtered by the first inductor L1.

[0107] For example, the control integrated circuit also includes a control module 10, a first capacitor C1, a first sampling resistor RS1, a first NMOS transistor Q1, a ninth NMOS transistor Q9, a first inductor L1, and a second capacitor C2;

[0108] The control module 10 is electrically connected to the semiconductor switch module 1, one end of the first capacitor C1 and one end of the first sampling resistor RS1. The other end of the first capacitor C1 and the drain of the first NMOS transistor Q1 are electrically connected to the positive terminal of the input voltage terminal. The other end of the first sampling resistor RS1 is grounded. The gate of the first NMOS transistor Q1 is electrically connected to the transistor drive module 3. The source of the first NMOS transistor Q1 is electrically connected to one end of the first inductor and the drain of the ninth NMOS transistor Q9. The other end of the first inductor L1 and one end of the second capacitor C2 are electrically connected to the output voltage terminal. The source of the ninth NMOS transistor Q9 and the other end of the second capacitor C2 are grounded.

[0109] In this embodiment, the entire circuit is controlled by the control module 10 outputting a high-level drive signal or a low-level drive signal. The circuit is filtered by the first capacitor C1 and the second capacitor C2, the input current signal is sampled by the first sampling resistor RS1, the drive voltage is generated by the first NMOS transistor Q1, the current is freewheeled by the ninth NMOS transistor Q9, and the circuit is filtered by the first inductor L1.

[0110] This application discloses a buck power converter, which, by way of example, may include a control integrated circuit.

[0111] In this embodiment, a semiconductor driving component is formed by a semiconductor switching module, a field-effect transistor switching module, and a transistor driving module. This eliminates the need for a low-impedance connection between the control module and the DC input voltage, allowing direct application in scenarios with high DC input voltage and large duty cycles. Furthermore, the overall circuit conforms to the industry's technological development trend of miniaturization and increased power density, offering a wider range of applications than existing technologies. It also boasts lower costs and better economic and social benefits, thus showing promise for large-scale application.

[0112] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0113] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0115] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0116] In the embodiments provided in this application, it should be understood that the disclosed control integrated circuit can be implemented in other ways. For example, the control integrated circuit embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or electrical communication connections shown or discussed may be indirect couplings or electrical communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0118] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0119] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A control integrated circuit, characterized in that, include: The semiconductor switch module is configured to turn on and generate a first low level according to a high-level drive signal, or turn off and generate a first high level according to a low-level drive signal; A field-effect transistor switching module, electrically connected to the semiconductor switching module and the auxiliary power supply module, is configured to turn on and generate a second high level according to the first low level and the auxiliary power supply module, or to turn off and generate a second low level according to the first high level; A diode module, electrically connected to the field-effect transistor switching module, is configured to clamp the field-effect transistor switching module; The transistor driver module, electrically connected to the MOSFET switching module and the auxiliary power supply module, is configured to increase the output voltage until the switching transistor is turned on according to the second high level and the auxiliary power supply module; or to decrease the output voltage until the switching transistor is turned off according to the second low level. The field-effect transistor switching module includes a third diode, a fourteenth resistor, and an eighth NPN transistor; the negative terminal of the third diode is electrically connected to one end of the fourteenth resistor and the base of the eighth NPN transistor, the positive terminal of the third diode is electrically connected to the emitter of the eighth NPN transistor, and the other end of the fourteenth resistor and the collector of the eighth NPN transistor are electrically connected to the auxiliary power supply module.

2. The control integrated circuit as described in claim 1, characterized in that, The semiconductor switching module includes a first resistor, a sixth resistor, and a second NPN transistor; One end of the first resistor is electrically connected to the drive signal, the other end of the first resistor is electrically connected to the base of the second NPN transistor, and the collector of the second NPN transistor is electrically connected to one end of the sixth resistor. Alternatively, the semiconductor switching module includes a first resistor, a sixth resistor, and a second NMOS transistor; One end of the first resistor is electrically connected to the drive signal, the other end of the first resistor is electrically connected to the gate of the second NMOS transistor, and the drain of the second NMOS transistor is electrically connected to one end of the sixth resistor.

3. The control integrated circuit as described in claim 2, characterized in that, The field-effect transistor switching module includes a second resistor, a seventh resistor, and a third PMOS transistor; One end of the second resistor is electrically connected to the other end of the sixth resistor, the other end of the second resistor is electrically connected to one end of the seventh resistor and the gate of the third PMOS transistor, and the source of the third PMOS transistor and the other end of the seventh resistor are electrically connected to the auxiliary power supply module.

4. The control integrated circuit as described in claim 3, characterized in that, The transistor driving module includes a third resistor, a fourth resistor, a fourth NPN transistor, a fifth PNP transistor, and a fifth resistor; One end of the third resistor is electrically connected to the drain of the third PMOS transistor, and the other end of the third resistor is electrically connected to the base of the fourth NPN transistor, the base of the fifth PNP transistor, and one end of the fourth resistor. The collector of the fourth NPN transistor is electrically connected to the auxiliary power supply module. The emitters of the fourth NPN transistor and the fifth PNP transistor are electrically connected to one end of the fifth resistor. The other end of the fourth resistor and the collector of the fifth PNP transistor are grounded.

5. The control integrated circuit as described in claim 2, characterized in that, The semiconductor switching module also includes a tenth resistor; One end of the tenth resistor is electrically connected to the base of the second NPN transistor, and the other end of the tenth resistor is electrically connected to the emitter of the second NPN transistor. Alternatively, one end of the tenth resistor is electrically connected to the gate of the second NMOS transistor, and the other end of the tenth resistor is electrically connected to the source of the second NMOS transistor.

6. The control integrated circuit as described in claim 4, characterized in that, The transistor driving module also includes an eighth resistor, a ninth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a sixth NPN transistor, a seventh PNP transistor, a first Zener diode, and a fourth capacitor; One end of the eighth resistor is electrically connected to the emitter of the fourth NPN transistor and the emitter of the fifth PNP transistor. The other end of the eighth resistor is electrically connected to the base of the sixth NPN transistor, the base of the seventh PNP transistor, and one end of the ninth resistor. The collector of the fourth NPN transistor is electrically connected to one end of the twelfth resistor. The collector of the sixth NPN transistor is electrically connected to one end of the thirteenth resistor. The other ends of the twelfth and thirteenth resistors are electrically connected to the auxiliary power supply module. The emitters of the sixth NPN transistor, the seventh PNP transistor, and the cathode of the first Zener diode are electrically connected to one end of the fourth capacitor. The anode of the first Zener diode and the other end of the fourth capacitor are electrically connected to one end of the fifth resistor. The other end of the fifth resistor is electrically connected to one end of the eleventh resistor. The other end of the ninth resistor, the collector of the seventh PNP transistor, and the other end of the eleventh resistor are grounded.

7. The control integrated circuit according to any one of claims 1-6, characterized in that, The control integrated circuit also includes a control module, a first capacitor, a first sampling resistor, a first NMOS transistor, a first diode, a first inductor, and a second capacitor; The control module is electrically connected to the semiconductor switch module, one end of the first capacitor, and one end of the first sampling resistor. The other end of the first capacitor and the drain of the first NMOS transistor are electrically connected to the positive terminal of the input voltage terminal. The other end of the first sampling resistor is grounded. The gate of the first NMOS transistor is electrically connected to the transistor driving module. The source of the first NMOS transistor is electrically connected to one end of the first inductor and the negative terminal of the first diode. The other end of the first inductor and one end of the second capacitor are electrically connected to the output voltage terminal. The positive terminal of the first diode and the other end of the second capacitor are grounded.

8. The control integrated circuit according to any one of claims 1-6, characterized in that, The control integrated circuit also includes a control module, a first capacitor, a first sampling resistor, a first NMOS transistor, a ninth NMOS transistor, a first inductor, and a second capacitor; The control module is electrically connected to the semiconductor switch module, one end of the first capacitor, and one end of the first sampling resistor. The other end of the first capacitor and the drain of the first NMOS transistor are electrically connected to the positive terminal of the input voltage terminal. The other end of the first sampling resistor is grounded. The gate of the first NMOS transistor is electrically connected to the transistor driving module. The source of the first NMOS transistor is electrically connected to one end of the first inductor and the drain of the ninth NMOS transistor. The other end of the first inductor and one end of the second capacitor are electrically connected to the output voltage terminal. The source of the ninth NMOS transistor and the other end of the second capacitor are grounded.

9. A step-down power converter, characterized in that, Includes the control integrated circuit as described in any one of claims 1 to 8.

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