Precise timing method, device and signal slot reservation method and device

Abstract

The present application relates to a precise timing method, device and signal slot reservation method and device, and relates to the field of signal processing technology. The precise timing method includes the following steps: based on a first preset clock signal, generating a first valid signal; superimposing the first preset clock signal with the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency division signal; based on the first preset value, performing a frequency multiplication operation on the first frequency division signal, and removing jitter to obtain a first target clock signal. The present application performs signal superposition, frequency division and frequency multiplication, and jitter removal operations based on the first preset clock signal, thereby obtaining a first target clock signal with a target frequency ratio whose value is a non-positive integer, and providing technical support for subsequent signal slot reservation and coding insertion work.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a precise timing method and device, and a signal slot reservation method and device. Background Art

[0002] At present, users have higher and higher requirements for the resolution and refresh rate of display devices. For example, e-sports game players generally require display devices to support at least 4K resolution and a refresh rate of 144hz or above, which places great demands on the transmission bandwidth of the interface. Currently, the common interfaces DP1.4 and HDMI 2.0 on the market cannot meet the transmission bandwidth requirements of 4k 144hz. Therefore, the Video Electronics Standards Association VESA has released a display stream compression standard, abbreviated as DSC, which can losslessly compress the graphics to be displayed with a compression ratio of 3 to 1, thereby greatly reducing the transmission bandwidth requirements. This allows users to use the existing DP1.4 and HDMI 2.0 interfaces to enjoy the shocking experience brought by high resolution and high refresh rate.

[0003] Since the DSC algorithm is based on prediction and difference processing, if a bit error occurs during transmission, the entire image may not be restored, so it places higher requirements on the reliability of the interface. FEC, or forward error correction code, is a code that increases the reliability of data communication. The DP interface specification clearly requires that if the interface supports the transmission of DSC compressed data streams, it must also support the calculation and insertion of FEC.

[0004] When performing FEC insertion, it is necessary to reserve spaces in the signal. To reserve spaces, the signal needs to be adjusted based on a specific frequency. Therefore, an accurate determination technology is needed to adjust the signal for space reservation according to a specific frequency ratio to meet the needs of FEC insertion. Summary of the invention

[0005] The present application provides a precise timing method and device as well as a signal slot reservation method and device, which perform signal superposition, frequency division and multiplication, and jitter removal operations based on a first preset clock signal, thereby obtaining a first target clock signal having a ratio to a target frequency whose value is a non-positive integer, and providing technical support for subsequent signal slot reservation and coding insertion work.

[0006] In a first aspect, the present application provides a precise timing method for generating a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, the method comprising the following steps:

[0007] Based on the first preset clock signal, generating a first valid signal;

[0008] Superimposing the first preset clock signal with the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0009] Based on the first preset value, the first frequency-divided signal is multiplied and jitter is removed to obtain the first target clock signal; wherein,

[0010] The frequency ratio of the first preset clock signal to the first valid signal is the same as the target frequency ratio;

[0011] The target frequency ratio is a non-integer;

[0012] The first preset value is an integer;

[0013] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0014] Specifically, the step of generating a first valid signal based on the first preset clock signal includes the following steps:

[0015] Creating a first counter, a first calculated value, and a second calculated value;

[0016] When the current value of the first counter is less than the first calculated value, adding the current value of the first counter to the second calculated value is used as the update value of the first counter, and setting the value of the first valid signal to 0;

[0017] When the current value of the first counter is not less than the first calculated value, adding the second calculated value to the current value of the first counter and subtracting the first calculated value as the updated value of the first counter, and setting the value of the first valid signal to 1;

[0018] Obtaining the first valid signal; wherein,

[0019] A ratio of the first calculated value to the second calculated value is equal to a target frequency ratio.

[0020] Specifically, performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal includes the following steps:

[0021] Create a second counter;

[0022] When the value of the second counter is less than half of the first preset value, the value of the second counter is incremented by one, and the value of the first frequency-divided signal is maintained unchanged;

[0023] When the value of the second counter is not less than half of the first preset value, the current value of the second counter is subtracted from half of the first preset value, then an addition operation is performed, and the value of the first frequency-divided signal is inverted; wherein,

[0024] An initial value of the first frequency-divided signal is 1.

[0025] Specifically, a clock phase-locked loop chip is used to perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain the first target clock signal.

[0026] In a second aspect, the present application provides a precise timing device for generating a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, the device comprising:

[0027] A valid signal generating module, configured to generate a first valid signal based on the first preset clock signal;

[0028] a signal frequency division module, configured to superimpose the first preset clock signal and the first valid signal to obtain a first superimposed signal, and perform a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0029] A target signal generating module is used to perform a frequency multiplication operation on the first frequency-divided signal based on the first preset value, and remove jitter to obtain the first target clock signal; wherein,

[0030] The frequency ratio of the first preset clock signal to the first valid signal is the same as the target frequency ratio;

[0031] The target frequency ratio is a non-integer;

[0032] The first preset value is an integer;

[0033] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0034] Furthermore, the effective signal generating module is also used to create a first counter, a first calculated value and a second calculated value;

[0035] The valid signal generating module is further configured to add the current value of the first counter to the second calculated value as an updated value of the first counter and set the value of the first valid signal to 0 when the current value of the first counter is less than the first calculated value;

[0036] The valid signal generating module is further used for adding the second calculated value to the current value of the first counter and subtracting the first calculated value as the updated value of the first counter when the current value of the first counter is not less than the first calculated value, and setting the value of the first valid signal to 1; wherein,

[0037] A ratio of the first calculated value to the second calculated value is equal to a target frequency ratio.

[0038] Furthermore, the signal frequency division module is also used to create a second counter;

[0039] The signal frequency division module is further used for, when the value of the second counter is less than half of the first preset value, adding one to the value of the second counter and maintaining the value of the first frequency division signal unchanged;

[0040] The signal frequency division module is also used for, when the value of the second counter is not less than half of the first preset value, subtracting half of the first preset value from the current value of the second counter, performing an addition operation, and inverting the value of the first frequency division signal; wherein,

[0041] An initial value of the first frequency-divided signal is 1.

[0042] Specifically, the target signal generating module uses a clock phase-locked loop chip to perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain the first target clock signal.

[0043] In a third aspect, the present application provides a signal slot reservation method, the method comprising the following steps:

[0044] Determine the target frequency ratio of the initial clock signal to the target clock signal according to the signal slot reservation requirement;

[0045] Based on the initial clock signal, generate a first valid signal;

[0046] Superimposing the initial clock signal with the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0047] Based on the first preset value, the first frequency-divided signal is multiplied and jitter is removed to obtain the target clock signal; wherein,

[0048] The frequency ratio of the initial clock signal to the first valid signal is the same as the target frequency ratio;

[0049] The target frequency ratio is a non-integer;

[0050] The first preset value is an integer;

[0051] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0052] In a fourth aspect, the present application provides a signal space reservation device, the device comprising:

[0053] A frequency ratio determination module, which is used to determine a target frequency ratio between an initial clock signal and a target clock signal according to a signal slot reservation requirement;

[0054] A valid signal generating module, configured to generate a first valid signal based on the initial clock signal;

[0055] a signal frequency division module, configured to superimpose the initial clock signal and the first valid signal to obtain a first superimposed signal, and perform a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0056] A target signal generating module is used to perform a frequency multiplication operation on the first frequency-divided signal based on the first preset value, and remove jitter to obtain the target clock signal; wherein,

[0057] The frequency ratio of the initial clock signal to the first valid signal is the same as the target frequency ratio;

[0058] The target frequency ratio is a non-integer;

[0059] The first preset value is an integer;

[0060] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0061] The beneficial effects of the technical solution provided by this application include:

[0062] (1) The present application performs signal superposition, frequency division and multiplication, and jitter removal operations based on a first preset clock signal, thereby obtaining a first target clock signal having a target frequency ratio whose value is a non-positive integer, and providing technical support for subsequent signal space reservation and coding insertion.

[0063] (2) The signal slot reservation requirement of the present application is to determine the target frequency ratio between the initial clock signal and the target clock signal, perform signal superposition, frequency division and multiplication, and jitter removal operations on the first preset clock signal, so as to obtain a satisfactory first target clock signal, thereby meeting the signal slot reservation requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Terminology explanation:

[0065] DP: Display Port, display interface;

[0066] DSC: Display Stream Compression, display stream compression;

[0067] FEC: Forward Error Correction, forward error correction coding.

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0069] Figure 1 A flowchart of the steps of the precise timing method provided in an embodiment of the present application;

[0070] Figure 2 A schematic diagram of the generation principle of the first valid signal in step S1 of the precise timing method provided in an embodiment of the present application;

[0071] Figure 3 A schematic diagram of the generation principle of the first frequency-divided signal in step S2 of the precise timing method provided in an embodiment of the present application;

[0072] Figure 4 A schematic diagram of the generation principle of the first target clock signal in step S3 of the precise timing method provided in an embodiment of the present application;

[0073] Figure 5 It is a flow chart of FEC insertion in the DP specification in the precise timing method provided in the embodiment of the present application;

[0074] Figure 6 This is a schematic diagram of the principle of inserting a vacancy in the precise timing method provided in the embodiment of the present application;

[0075] Figure 7 This is a flowchart of steps A1 to A4 in the precise timing method provided in an embodiment of the present application;

[0076] Figure 8 This is a flowchart of steps B1 to B4 in the precise timing method provided in an embodiment of the present application;

[0077] Fig. 9 This is a structural block diagram of a precise timing device provided in an embodiment of the present application;

[0078] Fig.10 A flowchart of the signal space reservation method provided in an embodiment of the present application;

[0079] Fig.11 This is a structural block diagram of the precise timing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0081] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0082] The embodiments of the present application provide a precise timing method and device, as well as a signal slot reservation method and device, which perform signal superposition, frequency division and multiplication, and jitter removal operations based on a first preset clock signal, thereby obtaining a first target clock signal having a ratio to a target frequency whose value is a non-positive integer, and providing technical support for subsequent signal slot reservation and coding insertion work.

[0083] In order to achieve the above technical effects, the overall idea of ​​this application is as follows:

[0084] A precise timing method is used to generate a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, the method comprising the following steps:

[0085] S1. Generate a first valid signal based on a first preset clock signal;

[0086] S2, superimposing the first preset clock signal and the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0087] S3, based on the first preset value, performing a frequency multiplication operation on the first frequency-divided signal and removing jitter to obtain a first target clock signal; wherein,

[0088] The frequency ratio of the first preset clock signal to the first effective signal is the same as the target frequency ratio;

[0089] The target frequency ratio is a non-integer;

[0090] The first preset value is an integer;

[0091] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0092] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0093] First, see Figures 1 to 8 As shown, an embodiment of the present application provides a precise timing method, which is used to generate a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, and the method includes the following steps:

[0094] S1. Generate a first valid signal based on a first preset clock signal;

[0095] S2, superimposing the first preset clock signal and the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0096] S3, based on the first preset value, performing a frequency multiplication operation on the first frequency-divided signal and removing jitter to obtain a first target clock signal; wherein,

[0097] The frequency ratio of the first preset clock signal to the first effective signal is the same as the target frequency ratio;

[0098] The target frequency ratio is a non-integer;

[0099] The first preset value is an integer;

[0100] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0101] In the embodiment of the present application, step S1 is first performed to generate a first valid signal based on a first preset clock signal. In actual implementation, the specific operation may be in the following form:

[0102] Based on the generated clock signal Link_clkb, a valid signal is generated, the first preset clock signal is the clock signal Link_clkb, and the first valid signal is the valid signal;

[0103] The clock signal Link_clkb is a clock used to indicate the working rate of the DP interface. When the working rate of the DP interface is set during specific operation, the clock signal Link_clkb also has a specific value of its frequency.

[0104] Inside the chip, the clock signal Link_clkb can be a parallel user clock generated by a high-speed serial transmitter.

[0105] As shown in the attached figure of the specification Figure 2 As shown, Figure 2 This is a schematic diagram of generating the first valid signal in step S1, and the specific operations are as follows:

[0106] Create the first counter, denoted as Cnt1;

[0107] Create a first calculated value and a second calculated value, the first calculated value is recorded as M, and the second calculated value is recorded as N;

[0108] Define M = 65537, N = 64000;

[0109] When the value of the first counter Cnt1 is less than M, Cnt1=Cnt1+N is executed, and the value of the first valid signal, namely the valid signal, is set to 0; when the value of the first counter Cnt1 is greater than or equal to M, Cnt1=Cnt1-M+N is executed, and the value of the first valid signal, namely the valid signal, is set to 1;

[0110] Now the clock signal Link_clkb is superimposed with the valid signal, which is mathematically equivalent to the first target clock signal, which is denoted as Link_clka. That is, in the symbol insertion work, if a new LL symbol is transmitted when the value of the valid signal is 1 under the clock signal Link_clkb, it is equivalent to transmitting a new LL symbol in each beat of Link_clka.

[0111] In addition, for step S1, another target frequency ratio is used as an example for explanation. Assuming that the target frequency ratio is 3 / 5, the first preset clock signal is recorded as clock signal A, and the first valid signal corresponding to signal A is recorded as signal A. valid , the first target clock signal is recorded as clock signal B,

[0112] The frequency ratio of clock signal A to clock signal B is 3 / 5. Using traditional technical means, it is impossible to directly obtain clock signal B.

[0113] First, a signal A is generated under the clock signal A and valid The condition that needs to be met is: make the clock signal A every 5 beats, signal A valid There are 3 beats.

[0114] Then any signal under the clock signal A and under the signal A valid The signal A is processed only when its value is 1. valid If the value of is 0, no processing is performed, which is equivalent to only 3 processings in every 5 cycles of clock signal A. In this way, due to clock signal A, it is equivalent to processing every beat under clock signal B.

[0115] Then, step S2 is performed, that is, the first preset clock signal is superimposed with the first valid signal to obtain a first superimposed signal, and the first superimposed signal is frequency-divided according to the first preset value to obtain a first frequency-divided signal. In actual implementation, the specific operation form may be as follows:

[0116] Perform X-frequency division on the clock signal Link_clkb under the corresponding valid signal to obtain a square wave signal clk_div, which is a first frequency-divided signal;

[0117] In addition, X is an even number greater than or equal to 2.

[0118] Similarly, for step S2, the target frequency ratio is equal to 3 / 5 as an example for explanation.

[0119] After step S1, the signal A corresponding to the clock signal A is obtained. valid , every 5 cycles of clock signal A, signal A valid There are 3 beats.

[0120] Clock signal A and signal A valid Superposition, theoretically the superimposed signal can be regarded as clock signal B,

[0121] Then divide the frequency by 2, that is, X=2, and the final clock frequency is A*(3 / 5)*(1 / 2), that is, A*3 / 10, which is B*1 / 2.

[0122] Therefore, it can be seen that without considering the signal jitter, the clock signal A and signal A valid The clock signal B can be obtained by superposition, but in order to eliminate jitter, frequency division, frequency multiplication and jitter elimination are required.

[0123] As shown in the attached figure of the specification Figure 3 As shown, Figure 3 This is a schematic diagram of generating the first frequency-divided signal in step S2, and the specific operations are as follows:

[0124] Create a second counter, denoted as Cnt2;

[0125] The second counter Cnt and the first frequency division signal clk_div perform operations only when the value of the valid signal is 1, otherwise they remain unchanged. The specific operations are as follows:

[0126] When the value of Cnt2 is less than X / 2, Cnt2=Cnt2+1 is executed, and the first frequency division signal clk_div is maintained unchanged.

[0127] When the value of Cnt2 is greater than or equal to X / 2, Cnt2=Cnt2-X / 2+1 is executed, and the value of the first frequency-divided signal clk_div is inverted, that is, clk_div=~clk_div;

[0128] Through the above operation, the first frequency division signal clk_div is obtained. The frequency of the first frequency division signal clk_div can be mathematically regarded as the X-frequency division of Link_clka.

[0129] However, the duty cycle of the first frequency division signal clk_div is not a fixed 50%, and its period is not constant, that is, there is jitter. The essential reason for the jitter is that 65537 / 64000 is not an integer.

[0130] In the face of jitter, as long as the value of X is large enough, the frequency of the first frequency-divided signal clk_div is low enough, and the ratio of its period change to its period itself is small enough, so that the signal jitter is small enough, and the signal jitter small enough is easy to be filtered out. Generally, an appropriate value of X is taken to make the frequency of the first frequency-divided signal clk_div close to 8khz.

[0131] Finally, step S3 is performed to perform a frequency multiplication operation on the first frequency-divided signal based on the first preset value, and remove jitter to obtain a first target clock signal. In actual implementation, the specific operation may be in the following form:

[0132] As shown in the attached figure of the specification Figure 4 As shown, Figure 4 This is a schematic diagram of generating the first target clock signal in step S3, and the specific operations are as follows:

[0133] The first frequency-divided signal clk_div is multiplied by X and the jitter is removed to obtain the required first target clock signal Link_clka;

[0134] In step S3, since the value of X is an integer, most clock phase-locked loop chips on the market can implement it, and the final required first target clock signal Link_clka is obtained, and the ratio between its frequency and the frequency of the clock signal Link_clkb is equal to 64000 / 65537; wherein,

[0135] The value of X needs to be large enough, and X is selected so that the first frequency division signal clk_div is close to 8khz.

[0136] If necessary, the value of X can be adaptively adjusted according to the recommended input frequency of the clock phase-locked loop chip.

[0137] It should be noted that the technical solution of the embodiment of the present application can be specifically used in an application scenario, the specific situation is as follows:

[0138] At present, users have higher and higher requirements for the resolution and refresh rate of display devices. For example, e-sports game players generally require display devices to support at least 4K resolution and a refresh rate of 144hz or above, which puts great demands on the transmission bandwidth of the interface. The common interfaces DP1.4 and HDMI 2.0 on the market cannot meet the transmission bandwidth requirements of 4k 144hz. Therefore, the Video Electronics Standards Association VESA has released a display stream compression standard, abbreviated as DSC, which can losslessly compress the graphics to be displayed with a compression ratio of 3 to 1, thereby greatly reducing the transmission bandwidth requirements. This allows users to use the existing DP1.4 and HDMI 2.0 interfaces to enjoy the shocking experience brought by high resolution and high refresh rate.

[0139] Since the DSC algorithm is based on prediction and difference, if a bit error occurs during transmission, the entire image may not be restored, so it places higher requirements on the reliability of the interface. FEC, or forward error correction code, is a code that increases the reliability of data communication. The DP interface specification clearly requires that if the interface supports the transmission of DSC compressed data streams, it must also support the calculation and insertion of FEC. Therefore, how to implement FEC insertion in the DP interface becomes a technical key.

[0140] As shown in the attached figure of the specification Figure 5 and Figure 6 As shown, when the DP interface performs FEC insertion, the original DP link layer data stream symbol is called LL symbol. In order to insert the FEC check code and related control code, it is necessary to reserve space on the continuously transmitted LL symbol.

[0141] The rule for reserving empty spaces is that every 250 LL symbols are considered as a group, and 6 empty spaces need to be reserved. However, when reaching the 256th group, 7 empty spaces need to be reserved. Then the calculation is as follows:

[0142] The number of original symbols is: 250*256=64000,

[0143] The total number of symbols after the position reservation is: (250+6)*255+(250+7)=65537,

[0144] That is, every 64,000 LL symbols will become 65,537 symbols after the reserved positions, which contain 1,537 empty positions;

[0145] Insert the FEC check code and control code into the reserved space to form the final data stream with FEC check, and finally complete the FEC insertion work;

[0146] In summary, how to reserve a location is the key to this application scenario.

[0147] Since the symbols are transmitted continuously under the clock inside the digital chip, it is assumed that the LL data stream is transmitted under the clock domain Link_clka, and the LL data is written into the FIFO cache.

[0148] A new clock Link_clkb needs to be generated. The frequencies of Link_clkb and Link_clka have the following mathematical proportional relationship, that is, F Link_clkb / F Link_clka =65537 / 64000,

[0149] The read control logic operates in the clock domain Link_clkb, which controls when to take out LL data from the FIFO and when to transmit the empty symbol, thus realizing the empty insertion function.

[0150] However, it is difficult to implement two clocks with a frequency ratio of 65537 / 64000 in hardware circuits, because this ratio is irreducible and the absolute value of the ratio is equal to 1.024015625. Existing clock generation chips cannot produce such accuracy. If the clock cannot strictly meet this ratio, the FIFO in the figure will be empty and full, resulting in data loss.

[0151] Therefore, it is necessary to apply the precise timing method in the embodiment of the present application. Based on the precise timing method in the embodiment of the present application, two signals with irreducible frequency ratio relationship can be obtained, thereby meeting the requirements of position reservation work and finally meeting the requirements of FEC insertion work.

[0152] In the embodiment of the present application, based on the first preset clock signal, signal superposition, frequency division and multiplication, and jitter removal operations are performed to obtain a first target clock signal having a ratio to a target frequency whose value is a non-positive integer, thereby providing technical support for subsequent signal space reservation and coding insertion work.

[0153] The embodiment of the present application mainly relies on the clock ratio relationship to provide a signal basis for vacancy insertion, which is simple to implement and saves the logic resources of the chip;

[0154] In addition, the clock signal generated by the method according to the embodiment of the present application has the advantage of high precision and can meet the precision requirements to a certain extent.

[0155] In summary, as shown in the accompanying drawings of the specification Figure 7 Specifically, based on the first preset clock signal, generating the first valid signal includes the following steps:

[0156] A1. Create a first counter, a first calculated value, and a second calculated value;

[0157] A2. When the current value of the first counter is less than the first calculated value, the current value of the first counter plus the second calculated value is used as the updated value of the first counter, and the value of the first valid signal is set to 0;

[0158] A3. When the current value of the first counter is not less than the first calculated value, the current value of the first counter is added with the second calculated value, and the first calculated value is subtracted as the updated value of the first counter, and the value of the first valid signal is set to 1;

[0159] A4. Obtaining a first valid signal; wherein,

[0160] The ratio of the first calculated value to the second calculated value is equal to the target frequency ratio.

[0161] In addition, based on the frequency ratio mentioned in the embodiment of the present application, that is, 65537 / 64000, the first calculated value may be 65537, and the second calculated value may be 64000;

[0162] Of course, if other frequency ratios are required, they can be adjusted according to actual conditions.

[0163] In summary, as shown in the accompanying drawings of the specification Figure 8 As shown, specifically, performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal includes the following steps:

[0164] B1. Create a second counter;

[0165] B2. When the value of the second counter is less than half of the first preset value, the value of the second counter is incremented by one, and the value of the first frequency-divided signal is maintained unchanged;

[0166] B3. When the value of the second counter is not less than half of the first preset value, the current value of the second counter is subtracted from half of the first preset value, and then an addition operation is performed, and the value of the first frequency-divided signal is inverted;

[0167] B4, obtaining a first frequency division signal; wherein,

[0168] The initial value of the first frequency-divided signal is 1.

[0169] In summary, specifically, a clock phase-locked loop chip is used to perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain a first target clock signal.

[0170] Second, see Fig. 9 As shown, an embodiment of the present application provides a precise timing device, which is based on the precise timing method mentioned in the first aspect, and is used to generate a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, and the device includes:

[0171] An effective signal generating module, which is used to generate a first effective signal based on a first preset clock signal;

[0172] A signal frequency division module, which is used to superimpose a first preset clock signal and a first valid signal to obtain a first superimposed signal, and perform a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0173] A target signal generating module is used to perform a frequency multiplication operation on the first frequency-divided signal based on a first preset value, and remove jitter to obtain a first target clock signal; wherein,

[0174] The frequency ratio of the first preset clock signal to the first effective signal is the same as the target frequency ratio;

[0175] The target frequency ratio is a non-integer;

[0176] The first preset value is an integer;

[0177] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0178] In the embodiment of the present application, firstly, based on the first preset clock signal, a first valid signal is generated. In actual implementation, the operation may be in the following form:

[0179] Based on the generated clock signal Link_clkb, a valid signal is generated, the first preset clock signal is the clock signal Link_clkb, and the first valid signal is the valid signal;

[0180] The clock signal Link_clkb is a clock used to indicate the working rate of the DP interface. When the working rate of the DP interface is set during specific operation, the clock signal Link_clkb also has a specific value of its frequency.

[0181] Inside the chip, the clock signal Link_clkb can be a parallel user clock generated by a high-speed serial transmitter.

[0182] The specific operations for generating the first valid signal are as follows:

[0183] Create the first counter, denoted as Cnt1;

[0184] Create a first calculated value and a second calculated value, the first calculated value is recorded as M, and the second calculated value is recorded as N;

[0185] Define M = 65537, N = 64000;

[0186] When the value of the first counter Cnt1 is less than M, Cnt1=Cnt1+N is executed, and the value of the first valid signal, namely the valid signal, is set to 0; when the value of the first counter Cnt1 is greater than or equal to M, Cnt1=Cnt1-M+N is executed, and the value of the first valid signal, namely the valid signal, is set to 1;

[0187] Now the clock signal Link_clkb is superimposed with the valid signal, which is mathematically equivalent to the first target clock signal, which is denoted as Link_clka. That is, in the symbol insertion work, if a new LL symbol is transmitted when the value of the valid signal is 1 under the clock signal Link_clkb, it is equivalent to transmitting a new LL symbol in each beat of Link_clka.

[0188] Furthermore, the first preset clock signal is superimposed with the first valid signal to obtain a first superimposed signal, and the first superimposed signal is frequency-divided according to a first preset value to obtain a first frequency-divided signal. In actual implementation, the specific operation may be in the following form:

[0189] Perform X-frequency division on the clock signal Link_clkb under the corresponding valid signal to obtain a square wave signal clk_div, which is a first frequency-divided signal;

[0190] In addition, X is an even number greater than or equal to 2.

[0191] The specific operation of generating the first frequency division signal is as follows:

[0192] Create a second counter, denoted as Cnt2;

[0193] The second counter Cnt and the first frequency division signal clk_div perform operations only when the value of the valid signal is 1, otherwise they remain unchanged. The specific operations are as follows:

[0194] When the value of Cnt2 is less than X / 2, Cnt2=Cnt2+1 is executed, and the first frequency division signal clk_div is maintained unchanged.

[0195] When the value of Cnt2 is greater than or equal to X / 2, Cnt2=Cnt2-X / 2+1 is executed, and the value of the first frequency-divided signal clk_div is inverted, that is, clk_div=~clk_div;

[0196] Through the above operation, the first frequency division signal clk_div is obtained. The frequency of the first frequency division signal clk_div can be mathematically regarded as the X-frequency division of Link_clka.

[0197] However, the duty cycle of the first frequency division signal clk_div is not a fixed 50%, and its period is not constant, that is, there is jitter. The essential reason for the jitter is that 65537 / 64000 is not an integer.

[0198] In the face of jitter, as long as the value of X is large enough, the frequency of the first frequency-divided signal clk_div is low enough, and the ratio of its period change to its period itself is small enough, so that the signal jitter is small enough, and the signal jitter small enough is easy to be filtered out. Generally, an appropriate value of X is taken to make the frequency of the first frequency-divided signal clk_div close to 8khz.

[0199] Finally, based on the first preset value, the first frequency-divided signal is multiplied and jitter is removed to obtain a first target clock signal. In actual implementation, the operation may be as follows:

[0200] The specific operations of generating the first target clock signal are as follows:

[0201] The first frequency-divided signal clk_div is multiplied by X and the jitter is removed to obtain the required first target clock signal Link_clka;

[0202] In step S3, since the value of X is an integer, most clock phase-locked loop chips on the market can implement it, and the final required first target clock signal Link_clka is obtained, and the ratio between its frequency and the frequency of the clock signal Link_clkb is equal to 64000 / 65537; wherein,

[0203] The value of X needs to be large enough, and X is selected so that the first frequency division signal clk_div is close to 8khz.

[0204] If necessary, the value of X can be adaptively adjusted according to the recommended input frequency of the clock phase-locked loop chip.

[0205] In the embodiment of the present application, based on the first preset clock signal, signal superposition, frequency division and multiplication, and jitter removal operations are performed to obtain a first target clock signal having a ratio to a target frequency whose value is a non-positive integer, thereby providing technical support for subsequent signal space reservation and coding insertion work.

[0206] Furthermore, the valid signal generation module is also used to create a first counter, a first calculated value, and a second calculated value;

[0207] The valid signal generating module is further used for adding the current value of the first counter to the second calculated value as the updated value of the first counter when the current value of the first counter is less than the first calculated value, and setting the value of the first valid signal to 0;

[0208] The valid signal generating module is also used for adding the second calculated value to the current value of the first counter and subtracting the first calculated value as the updated value of the first counter when the current value of the first counter is not less than the first calculated value, and setting the value of the first valid signal to 1; wherein,

[0209] The ratio of the first calculated value to the second calculated value is equal to the target frequency ratio.

[0210] Furthermore, the signal frequency division module is also used to create a second counter;

[0211] The signal frequency division module is also used for adding one to the value of the second counter when the value of the second counter is less than half of the first preset value, and maintaining the value of the first frequency division signal unchanged;

[0212] The signal frequency division module is also used to, when the value of the second counter is not less than half of the first preset value, subtract half of the first preset value from the current value of the second counter, then add one, and invert the value of the first frequency division signal; wherein,

[0213] The initial value of the first frequency-divided signal is 1.

[0214] Specifically, the target signal generation module uses a clock phase-locked loop chip to perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain a first target clock signal.

[0215] Thirdly, see Fig.10 As shown, an embodiment of the present application provides a signal slot reservation method, which is based on the precise timing method mentioned in the first aspect, and the signal slot reservation method includes the following steps:

[0216] Q1. Determine the target frequency ratio between the initial clock signal and the target clock signal according to the signal slot reservation requirement;

[0217] Q2. Generate a first valid signal based on the initial clock signal;

[0218] Q3, superimposing the initial clock signal with the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0219] Q4. Based on the first preset value, perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain a target clock signal; wherein,

[0220] The frequency ratio of the initial clock signal to the first effective signal is the same as the target frequency ratio;

[0221] The target frequency ratio is a non-integer;

[0222] The first preset value is an integer;

[0223] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0224] Furthermore, signal insertion may be performed according to the target clock signal.

[0225] It should be noted that the specific operations of Q2 to Q4 in this method can be based on the precise timing method mentioned in the first aspect.

[0226] In an embodiment of the present application, the signal slot reservation requirement is met, the target frequency ratio of the initial clock signal to the target clock signal is determined, and the first preset clock signal is subjected to signal superposition, frequency division, frequency multiplication and jitter removal operations to obtain a satisfactory first target clock signal, thereby meeting the signal slot reservation requirement.

[0227] Similarly, based on the precise timing method mentioned in the first aspect, generating a first valid signal based on a first preset clock signal includes the following steps:

[0228] Creating a first counter, a first calculated value, and a second calculated value;

[0229] When the current value of the first counter is less than the first calculated value, the current value of the first counter plus the second calculated value is used as the update value of the first counter, and the value of the first valid signal is set to 0;

[0230] When the current value of the first counter is not less than the first calculated value, the current value of the first counter is added with the second calculated value, and the first calculated value is subtracted as the updated value of the first counter, and the value of the first valid signal is set to 1;

[0231] Obtain a first valid signal; wherein,

[0232] The ratio of the first calculated value to the second calculated value is equal to the target frequency ratio.

[0233] In addition, based on the frequency ratio mentioned in the embodiment of the present application, that is, 65537 / 64000, the first calculated value may be 65537, and the second calculated value may be 64000;

[0234] Of course, if other frequency ratios are required, they can be adjusted according to actual conditions.

[0235] Specifically, performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal includes the following steps:

[0236] Create a second counter;

[0237] When the value of the second counter is less than half of the first preset value, the value of the second counter is incremented by one, and the value of the first frequency-divided signal is maintained unchanged;

[0238] When the value of the second counter is not less than half of the first preset value, the current value of the second counter is subtracted from half of the first preset value, and then an addition operation is performed, and the value of the first frequency-divided signal is inverted;

[0239] A first frequency-divided signal is obtained; wherein,

[0240] The initial value of the first frequency-divided signal is 1.

[0241] Specifically, a clock phase-locked loop chip is used to perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain a first target clock signal.

[0242] Fourthly, see Fig.11 As shown, an embodiment of the present application provides a signal slot reservation device, which is based on the precise timing method mentioned in the first aspect and the signal slot reservation method mentioned in the third aspect, and the signal slot reservation device includes:

[0243] A frequency ratio determination module, which is used to determine a target frequency ratio between an initial clock signal and a target clock signal according to a signal slot reservation requirement;

[0244] A valid signal generating module, which is used to generate a first valid signal based on an initial clock signal;

[0245] A signal frequency division module, which is used to superimpose the initial clock signal and the first valid signal to obtain a first superimposed signal, and perform a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal;

[0246] A target signal generating module is used to perform a frequency multiplication operation on the first frequency-divided signal based on a first preset value, and remove jitter to obtain a target clock signal; wherein,

[0247] The frequency ratio of the initial clock signal to the first effective signal is the same as the target frequency ratio;

[0248] The target frequency ratio is a non-integer;

[0249] The first preset value is an integer;

[0250] The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

[0251] It should be noted that, in a specific implementation, the working method of the device is based on the precise timing method mentioned in the first aspect and the signal slot reservation method mentioned in the third aspect.

[0252] In an embodiment of the present application, the signal slot reservation requirement is met, the target frequency ratio of the initial clock signal to the target clock signal is determined, and the first preset clock signal is subjected to signal superposition, frequency division, frequency multiplication and jitter removal operations to obtain a satisfactory first target clock signal, thereby meeting the signal slot reservation requirement.

[0253] It should be noted that, in this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0254] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A precise timing method, characterized in that: The method is used to generate a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, and the method comprises the following steps: Based on the first preset clock signal, generating a first valid signal; Superimposing the first preset clock signal with the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal; Based on the first preset value, the first frequency-divided signal is multiplied and jitter is removed to obtain the first target clock signal; wherein, The frequency ratio of the first preset clock signal to the first valid signal is the same as the target frequency ratio; The target frequency ratio is a non-integer; The first preset value is an integer; The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold; The step of generating a first valid signal based on the first preset clock signal comprises the following steps: Creating a first counter, a first calculated value, and a second calculated value; When the current value of the first counter is less than the first calculated value, adding the current value of the first counter to the second calculated value is used as the update value of the first counter, and setting the value of the first valid signal to 0; When the current value of the first counter is not less than the first calculated value, adding the second calculated value to the current value of the first counter and subtracting the first calculated value as the updated value of the first counter, and setting the value of the first valid signal to 1; Obtaining the first valid signal; wherein, A ratio of the first calculated value to the second calculated value is equal to a target frequency ratio.

2. The precise timing method according to claim 1, characterized in that: Performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal includes the following steps: Create a second counter; When the value of the second counter is less than half of the first preset value, the value of the second counter is incremented by one, and the value of the first frequency-divided signal is maintained unchanged; When the value of the second counter is not less than half of the first preset value, the current value of the second counter is subtracted from half of the first preset value, then an addition operation is performed, and the value of the first frequency-divided signal is inverted; wherein, An initial value of the first frequency-divided signal is 1.

3. The precise timing method according to claim 1, characterized in that: The first frequency-divided signal is frequency-multiplied by using a clock phase-locked loop chip, and jitter is eliminated to obtain the first target clock signal.

4. A precise timing device, characterized in that: The device is used to generate a first target clock signal corresponding to a target frequency ratio based on a first preset clock signal, and the device includes: A valid signal generating module, configured to generate a first valid signal based on the first preset clock signal; a signal frequency division module, configured to superimpose the first preset clock signal and the first valid signal to obtain a first superimposed signal, and perform a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal; A target signal generating module is used to perform a frequency multiplication operation on the first frequency-divided signal based on the first preset value, and remove jitter to obtain the first target clock signal; wherein, The frequency ratio of the first preset clock signal to the first valid signal is the same as the target frequency ratio; The target frequency ratio is a non-integer; The first preset value is an integer; The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold; The effective signal generating module is further used to create a first counter, a first calculated value and a second calculated value; The valid signal generating module is further configured to add the current value of the first counter to the second calculated value as an updated value of the first counter and set the value of the first valid signal to 0 when the current value of the first counter is less than the first calculated value; The valid signal generating module is further used for adding the second calculated value to the current value of the first counter and subtracting the first calculated value as the updated value of the first counter when the current value of the first counter is not less than the first calculated value, and setting the value of the first valid signal to 1; wherein, A ratio of the first calculated value to the second calculated value is equal to a target frequency ratio.

5. The precise timing device according to claim 4, characterized in that: The signal frequency division module is also used to create a second counter; The signal frequency division module is further used for, when the value of the second counter is less than half of the first preset value, adding one to the value of the second counter and maintaining the value of the first frequency division signal unchanged; The signal frequency division module is also used for, when the value of the second counter is not less than half of the first preset value, subtracting half of the first preset value from the current value of the second counter, performing an addition operation, and inverting the value of the first frequency division signal; wherein, An initial value of the first frequency-divided signal is 1.

6. The precise timing device according to claim 4, characterized in that: The target signal generation module uses a clock phase-locked loop chip to perform a frequency multiplication operation on the first frequency-divided signal and remove jitter to obtain the first target clock signal.

7. A signal slot reservation method, based on the precise timing method according to any one of claims 1 to 3, characterized in that: The signal slot reservation method comprises the following steps: Determine the target frequency ratio of the initial clock signal to the target clock signal according to the signal slot reservation requirement; Based on the initial clock signal, generate a first valid signal; Superimposing the initial clock signal with the first valid signal to obtain a first superimposed signal, and performing a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal; Based on the first preset value, the first frequency-divided signal is multiplied and jitter is removed to obtain the target clock signal; wherein, The frequency ratio of the initial clock signal to the first valid signal is the same as the target frequency ratio; The target frequency ratio is a non-integer; The first preset value is an integer; The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

8. A signal slot reservation device, based on the signal slot reservation method according to claim 7, characterized in that: The device comprises: A frequency ratio determination module, which is used to determine a target frequency ratio between an initial clock signal and a target clock signal according to a signal slot reservation requirement; A valid signal generating module, configured to generate a first valid signal based on the initial clock signal; a signal frequency division module, configured to superimpose the initial clock signal and the first valid signal to obtain a first superimposed signal, and perform a frequency division operation on the first superimposed signal according to a first preset value to obtain a first frequency-divided signal; A target signal generating module is used to perform a frequency multiplication operation on the first frequency-divided signal based on the first preset value, and remove jitter to obtain the target clock signal; wherein, The frequency ratio of the initial clock signal to the first valid signal is the same as the target frequency ratio; The target frequency ratio is a non-integer; The first preset value is an integer; The first preset value is configured to make the frequency of the first frequency-divided signal lower than a first frequency threshold.

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