Packaging interface with improved impedance continuity

Abstract

Disclosed herein are package interfaces with improved impedance continuity. An illustrative embodiment of a packaged integrated circuit includes an integrated circuit chip having a SerDes signal pad, and a package substrate having a core via and an arrangement of micro vias connecting the SerDes signal pad to an external contact for a solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro vias provides a pi-network inductance that improves the connection impedance match. An illustrative method embodiment includes obtaining a desired impedance of a PCB trace, determining parasitic capacitances of a core via and a solder ball connection to the PCB trace, minimizing the core via capacitance, calculating a pi-network inductance that improves the impedance match to the PCB trace, and adjusting the micro via arrangement between the core via and the solder ball connection to provide the pi-network inductance.

Description

BACKGROUND

[0001] Digital communication occurs between a transmitting device and a receiving device over an intermediate communication medium or "channel" (e.g., optical fiber, insulated wire, printed circuit board ("PCB") trace). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects a (possibly corrupted) sequence of symbols from which it reconstructs the transmitted data. Many digital communication links use only one bit per symbol, but higher order signal constellations are known and often used. In 4-level pulse amplitude modulation ("PAM4"), each symbol interval can carry any one of four symbols labeled -3, -1, +1, and +3.

[0002] Channel dispersion creates intersymbol interference, which can cause each symbol to interfere with its neighboring symbols, a result known as intersymbol interference ("ISI"). ISI can make it difficult for a receiving device to determine which symbols were transmitted in each interval, especially when such ISI is combined with additive noise. As symbol rates continue to increase, the effects of channel dispersion and ISI become more and more severe. To combat noise and ISI, transmitting and receiving devices can employ various equalization techniques, including linear equalizers and decision feedback equalizers.

[0003] A serializer / deserializer ("SerDes") block is a functional module that converts between a (low-rate) parallel stream of symbols and a (high-rate) serial stream of symbols. Integrated circuits often contain SerDes blocks to reduce the number of physical input / output ("I / O") pins and / or external signal lines required for communication. SerDes blocks are typically designed to operate at as high a symbol rate as possible to maximize their benefit, so they are modules that benefit the most from the use of efficient design techniques.

[0004] As single-lane data rates move toward 56 Gbps and beyond, any impedance mismatch exacerbates signal attenuation and ISI. Connections between packaged integrated circuit chips and printed circuit board traces are a common cause of impedance mismatch, so efficient design solutions are sought. SUMMARY

[0005] Accordingly, disclosed herein are packaged integrated circuit interface designs and associated methods for efficiently improving impedance continuity of high bandwidth signal connections. An illustrative embodiment of a packaged integrated circuit includes an integrated circuit chip having a SerDes signal pad, and a package substrate having a core via and an arrangement of micro vias connecting the SerDes signal pad to an external contact for a solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro vias provides a pi network inductance that, together with the first and second parasitic capacitances, yields a connection impedance that matches a desired impedance of the PCB trace.

[0006] An illustrative embodiment of a method for providing a connection from an integrated circuit signal pad to a printed circuit board trace is disclosed. The method includes obtaining a desired impedance of the PCB trace, determining a first parasitic capacitance of a core via, estimating a second parasitic capacitance of a solder ball connection between a package substrate pad and the PCB trace, minimizing the first parasitic capacitance under one or more design constraints, calculating a pi network inductance that, together with the first and second parasitic capacitances, matches the desired impedance of the PCB trace, and adjusting an arrangement of micro vias between the core via and the solder ball connection to provide the pi network inductance.

[0007] An illustrative software embodiment includes a non-transitory information storage medium that configures one or more processors to implement the above-described method.

[0008] Each of the above-described embodiments can be employed individually or in combination, and can be further implemented using any one or more of the following optional features in any suitable combination. 1. The IC pad is a SerDes transmitter output, the SerDes transmitter providing a signal having a symbol rate greater than 10 GHz. 2. The desired impedance is a function of frequency. 3. The impedance matching occurs at half the symbol rate. 4. The micro via arrangement includes at least two micro vias, and the adjusting includes increasing an offset between the at least two micro vias. 5. The adjusting includes making a trace length of a connection offset micro via greater than an offset distance. 6. The adjusting includes offsetting a first micro via from a second micro via in a first direction, and offsetting a third micro via from the second micro via in a direction perpendicular to the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a cross-section of an illustrative IC package interface.

[0010] Figure 2 is a schematic diagram of an illustrative interface model.

[0011] Figures 3A-3Dis an isometric view of an alternative package substrate connection geometry.

[0012] Figure 4 is a flowchart of an illustrative interface design method.

[0013] Figure 5A is a plot comparing time domain reflectometry (TDR) impedance before and after optimization.

[0014] Figure 5B is a plot comparing injection loss spectra before and after optimization.

[0015] The term

[0016] An integrated circuit ("IC") die is a singulated unit of an IC wafer. (Herein, "dices" will be used as the plural form of "die.") A single IC die in a package form ready for soldering or other electrical connection bonding to a larger circuit or system having nodes, pins, posts, pads, terminals, leads, bumps, solder balls, or other electrical contacts (collectively referred to herein as "contacts") can be referred to as an IC chip. When multiple IC dies are packaged together (e.g., as a multi-chip module or a system-in-package), the packaged unit is referred to herein as a "microelectronic assembly." Multiple IC dies can be attached directly to a package substrate (which can take the form of a laminated circuit board or a ceramic, glass, or semiconductor substrate) and typically have printed or etched traces that are much larger (by orders of magnitude) than the traces on the IC dies. Because such size differences adversely affect communication performance between the IC dies, at least some microelectronic assemblies employ so-called 2.5D or 3D technology. In 3D technology, IC dies are stacked on top of one another to provide direct electrical connections between adjacent dies. However, such stacking can make it difficult for the package to provide adequate heat dissipation. In 2.5D technology, at least some of the IC dies are attached to an "interposer," which in turn can be attached to the package substrate. The interposer can be a silicon substrate that employs through-silicon via (TSV) technology to provide contacts on both its upper surface (for the IC dies) and its lower surface (for the package substrate). The traces on the interposer can more closely match the size of the traces on the IC dies to improve communication performance between the dies, and can incorporate intentional inductive and capacitive elements to provide better impedance matching to the contacts and traces on the package substrate. A limited number of active devices (e.g., transistors) can be incorporated into the interposer so long as their density and power dissipation are constrained, without facing the heat dissipation difficulties of 3D technology.

[0017] When not qualified, the term "substrate" can refer to a package substrate, an interposer, an IC die, or any other form of platform that provides electrical connections for the integrated circuit elements of a die to other elements of a microelectronic assembly or to external contacts. DETAILED DESCRIPTION

[0018] While specific embodiments are given in the drawings and following description, it is understood that they are not limiting of the present disclosure. On the contrary, they are provided as examples of alternatives, equivalents, and modifications to the

[0019] Manufacturing processes for electronic devices vary widely, but they typically involve the use of a printed circuit board ("PCB") for interconnecting packaged integrated circuit chips with each other and with various mechanisms for interacting with users and the environment of the electronic device. The chips have contacts that are soldered to corresponding contacts on the PCB. These connections can cause impedance mismatches for signals that are carried to or from the chips through the PCB traces. In the frequency ranges used by most electronic devices, these impedance mismatches are typically insignificant, but serializer-deserializer (SerDes) communication links are pushing symbol rates up to 10 GHz or higher, where such impedance mismatches can cause significant reflections and attenuation.

[0020] Figure 1 is a partial cross-section of an integrated circuit chip showing a die 102 mounted on a package substrate 104 that is soldered to printed circuit board contacts 106. An array of solder connections 108 electrically connects pads of the die 102 to corresponding internal contacts of the package substrate 104, and an array of solder balls 110 connects external contacts of the package substrate 104 to the PCB contacts 106. The package substrate includes an arrangement of traces and vias 112 for providing electrical connections between the internal and external contacts, and typically includes one or more ground planes 114 to reduce inter-layer crosstalk. At locations where connections are needed between an overlying layer and an underlying layer, the ground plane includes an "anti-pad" or opening.

[0021] Connection 116 is an example of an electrical path from an internal contact of the package substrate to a PCB trace, including a core via, a microvia, and a solder ball. Details of the connection geometry are discussed further below.

[0022] Connection impedance is conventionally calculated by simulating electromagnetic properties of the proposed geometry of the substrate conductors. However, Figure 2 A simplified model that has been found useful is shown.

[0023] In Figure 2In the illustrative interface model, a SerDes (serializer / deserializer) transmitter 202 has an output impedance Z0, and a printed circuit board trace 204 (typically implemented as a stripline in the frequency range of interest) has a characteristic impedance (also referred to herein as an input impedance) Z1. The impedance of the connection 116 is dominated by the parasitic capacitance Co of the core via and the parasitic capacitance Ci of the solder ball 110. In this model, a series inductance L is introduced between the two parasitic capacitances to form a "pi network" 206 (so named due to the shape of the Greek letter pi that this schematic takes). Pi networks are often used for impedance matching, so this approach helps to reduce the impedance discontinuity on the package substrate. Using this model, when the output impedance Z0 is matched to the characteristic impedance Z1, and

[0024]

[0025] or equivalently, when the pi network inductance is set to

[0026] the discontinuity is minimized.

[0027] While Figure 2 the model is for a signal output (transmitted) from an integrated circuit die, the model for a signal input to (received by) a SerDes receiver is equivalent, and the same inductance calculation can be performed.

[0028] Figure 3A is a perspective view of the geometry of the connection 116. It includes: a first microvia arrangement 300, including short interconnect traces or pads at various layers on the inside of the package substrate; a core via 302, connecting between the inside and outside of the package substrate; a second microvia arrangement 304, coupling the signal through the layers on the outside of the package substrate; a solder ball 306, connecting the external contact of the package substrate to a corresponding pad on the printed circuit board; and a PCB via arrangement 308, coupling the solder pad to the target PCB trace.

[0029] Because the core via 302 is typically formed by drilling a hole in the substrate and plating the sides of the hole with a conductive material (i.e., a "plated via"), while the microvias and interconnect traces are made using photolithography techniques to pattern additional layers, the core via is much larger in size, resulting in a significant parasitic capacitance Co. The solder ball 306 is similarly large, resulting in a second parasitic capacitance Ci.

[0030] Typically, parasitic capacitance can be slightly reduced. If conductor sizes have already been minimized, one common technique is to increase the size of the anti-pad of any ground plane(s) proximate to the core via or external contact. While effective, certain design constraints can limit the benefit that this technique can provide. The increase in anti-pad size (and the associated decrease in ground plane coverage) can weaken return current continuity, increase crosstalk between conductors, and consume signal routing area. In cases where such techniques are insufficient, traces can be lengthened between the core via and the solder ball to introduce compensatory inductance. The required inductance value can be easily determined using the pi-network model discussed earlier.

[0031] Figure 3B Connection geometries associated with the first impedance matching technique are shown. In the illustrated embodiment, the microvia arrangement 304 is modified by introducing an offset between two of the microvias and increasing the length of the interconnect trace 314 beyond the offset distance. The desired inductive impedance can be achieved with a relatively modest increase in trace length over the frequency range of interest. Figure 3B

[0032] Figure 3C Connection geometries associated with the alternative impedance matching technique are shown. In the illustrated embodiment, the microvia arrangement 304 is modified by introducing an offset between three or more of the microvias and systematically varying the offset direction to simulate at least a portion of a spiral winding 324. In the illustrated embodiment, each offset direction is perpendicular to the preceding offset direction, but the change in direction can be a function of the number of layers on the outer side of the substrate. Figure 3C

[0033] For additional inductive enhancement, these techniques can be repeated and / or combined (e.g., in additional layers), as shown by the microvia arrangement 334 in Figure 3D Figure 3D In the illustrated embodiment, multiple offsets are provided and one of the traces is arcuate such that the length of that trace is greater than the offset distance.

[0034] Figure 4 is a flowchart of an illustrative method for designing a SerDes connection in a package substrate. The process can be implemented by, for example, one or more processors executing software for forming a package substrate in which an integrated circuit die will be mounted. In block 402, the design system determines a target impedance value (Z1) associated with the PCB trace. In block 404, the system calculates the parasitic capacitance (C1) of the solder ball. Both Z1 and C1 can be standardized or expected values, or they can be values determined through simulation or measurement if the PCB geometry is known.

[0035] ​​​At block 406, the system obtains an initial layout design of the package substrate and determines the parasitic capacitance (Co) associated with the core via. While a measurement via simulation is also possible, there are models for estimating the parasitic capacitance based on the via size in each layer and separation from the nearest current return path.

[0036] At block 408, the system compares the connection impedance (approximated ) to the target impedance and, subject to design constraints, adjusts the size of the core via and nearby ground plane to reduce any mismatch as much as possible.

[0037] At block 410, the system determines whether sufficient impedance matching is achieved, and if not, the system determines the required pi-network inductance L at block 412 and modifies the microvia arrangement 304 between the core via and the solder ball to introduce the desired inductance. Various modifications can be tried and evaluated to verify whether the desired impedance matching is achieved. Once sufficient impedance matching is achieved, the system outputs the optimized design, e.g., by displaying the optimized design to a user, storing the optimized design on a non-transitory information storage medium, and / or providing the optimized design to equipment that manufactures the package substrate and mounts the integrated circuit die.

[0038] Figure 5A is a time-domain reflectometry (TDR) plot showing impedance (in ohms) as a function of distance (or equivalently, as a function of propagation time). The package substrate without the pi-network inductance presents a sharp drop in impedance from 96 ohms to about 85 ohms, where the PCB trace is connected to the package substrate. With the pi-network inductance, the impedance discontinuity is reduced by more than 50%.

[0039] Figure 5B shows signal injection loss (in dB) as a function of frequency (in GHz) on the package substrate and the PCB trace. Without the pi-network inductance, the magnitude of the loss presents a gradual transition from zero to about 46 GHz, where the loss starts to grow faster. With the pi-network inductance, the loss returns to the previous slope (mainly attributable to the PCB trace). Although the difference is already very significant at 56 GHz (0.2 dB), the difference quickly reaches 1.6 dB above 60 GHz.

[0040] Numerous alternative forms, equivalents, and modifications will become apparent to those skilled in the art once fully understood the above disclosure. It is intended that the claims be interpreted to embrace all such alternatives, equivalents, and modifications.

Claims

1. A method for providing a connection from signal pads of an integrated circuit die to traces on a printed circuit board (PCB), the integrated circuit including a package substrate, the package substrate including vias and arrangements of microvias connecting the signal pads to external contacts for solder ball connections to the PCB traces, characterized in that, The method includes the following: Obtain the desired impedance of the PCB trace; Determine the first parasitic capacitance of the core via; Estimate the second parasitic capacitance associated with the solder ball connection; Calculate the pi network inductance, which, together with the first parasitic capacitance and the second parasitic capacitance, provides an impedance that matches the desired impedance of the PCB trace; and Adjusting the via arrangement between the core via and the solder ball connection to provide the pi network inductance, the via arrangement including at least a first via, a second via, and a third via; wherein the adjustment includes: The second micro-via is offset from the first micro-via in a first direction, and The third micro-via is offset from the second micro-via in a direction perpendicular to the first direction.

2. The method as described in claim 1, characterized in that, The signal pads are output from a SerDes transmitter, which provides a signal with a symbol rate greater than 10 GHz.

3. The method as described in claim 1, characterized in that, The desired impedance is a function of frequency, wherein the PCB trace is used to transmit a signal with a symbol rate, and wherein the impedance matching occurs at half the symbol rate.

4. The method as described in claim 1, characterized in that, The adjustment includes increasing the offset between at least three micro-vias.

5. The method as described in claim 4, characterized in that, The adjustment further includes making the trace length of the connected offset microvia greater than the offset distance.

6. A packaged integrated circuit, characterized in that: Integrated circuit die, with SerDes signal pads; and The package substrate has vias and microvias arranged to connect the SerDes signal pads to external contacts for solder ball connections to PCB traces. The vias have a first parasitic capacitance, the solder ball connections are associated with a second parasitic capacitance, and the arrangement of the microvias provides a pi network inductance. The arrangement of the microvias is adjusted such that the pi network inductance, together with the first and second parasitic capacitances, produces a connection impedance that matches the desired impedance of the PCB traces. The microvia arrangement includes at least a first microvia, a second microvia, and a third microvia, wherein the second microvia is offset from the first microvia in a first direction, and the third microvia is offset from the second microvia in a direction perpendicular to the first direction.

7. The integrated circuit as claimed in claim 6, characterized in that, The SerDes signal pad is the transmitter output, which provides a signal with a symbol rate greater than 10 GHz.

8. The integrated circuit as described in claim 7, characterized in that, The desired impedance is a function of frequency, and impedance matching occurs at half the symbol rate.

9. The integrated circuit as described in claim 6, characterized in that, At least three microvias are offset to increase the inductance of the pi network.

10. The integrated circuit as claimed in claim 9, characterized in that, The traces connecting the at least three microvias have a length greater than the offset distance.

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