Host controller interface using multi-cycle queue and method of operation thereof

Abstract

A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store head and tail pointers for one or more first queues; and an entry buffer configured to store a first command from a first queue of the one or more first queues, wherein the processing circuitry is configured to determine an order in which commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in a second queue of one or more second queues.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0066076 filed with the Korean Intellectual Property Office on June 1, 2020 and Korean Patent Application No. 10-2021-0008898 filed on January 21, 2021, the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0003] At least some exemplary embodiments of the present invention relate to a host controller interface configured to transmit commands to a storage device, and more specifically to a host controller interface having a bitmap-based doorbell structure and capable of using multiple circular queues.

[0004] Serial ATA (SATA), PCIe (PCIe), Serial Attached SCSI (SAS), embedded MMC (eMMC), and Universal Flash Storage (UFS) are used as interfaces in storage systems based on storage devices such as solid-state drives (SSDs). Various storage devices are being developed, and the amount of data they handle simultaneously is increasing. However, interfaces such as SATA are not specifically designed for storage devices (e.g., SSDs) and therefore have fundamental limitations.

[0005] Recently, as part of efforts to create standardized interfaces for data storage devices, high-speed non-volatile memory (NVMe) interfaces and UFS interfaces have been developed. The NVMe interface provides direct memory access to storage devices (or non-volatile memory) connected via the PCIe bus, while UFS adopts the architecture of M-PHY and Mobile Industrial Processor Interface (MIPI) and UniPro.

[0006] When a bitmap doorbell is shared by multiple cores, the overall system performance may be degraded due to resource overhead. For example, in the UFS protocol, when any one of the multiple cores begins to process the bitmap doorbell, other cores cannot access it. Summary of the Invention

[0007] The present invention provides a host controller with a bitmap-based doorbell structure and a method for operating it that can use multiple circular queues.

[0008] According to at least some example embodiments of the inventive concepts, a host controller interface configured to provide interfacing between a host device and a storage device includes a processing circuitry, a doorbell register configured to store head and tail pointers of one or more first queues, and an entry buffer configured to store a first command from one of the one or more first queues into the entry buffer, wherein the processing circuitry is configured to determine an order in which commands of the one or more first queues are to be processed, route the first command to be stored into the entry buffer according to the determined order, and route a first response to be stored into one of one or more second queues.

[0009] According to at least some example embodiments of the inventive concepts, a storage system includes a host device and a storage device, wherein the host device is configured to transmit a first command to the storage device, wherein the host device includes a host memory configured to store at least one queue, at least one core configured to process the at least one queue, a first processing circuitry configured to provide interfacing with the host memory, and a doorbell register configured to store head and tail pointers with respect to the at least one queue, and wherein the storage device includes a second processing circuitry configured to provide a first response to the host device as a result of performing a storage operation based on the first command.

[0010] According to at least some example embodiments of the inventive concepts, there is provided a method of operating a host controller interface configured to provide interfacing between a host device and a storage device using at least one queue including at least one command, the method including arbitrating an order of a plurality of commands including a first command, the first command being included in a first queue, storing the first command into an entry buffer, updating a first head pointer of the first queue, storing a second command into the entry buffer, updating a second head pointer of a second queue including the second command, and providing the first command and the second command to the storage device in sequence. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other features and advantages of the example embodiments of the inventive concepts will become more apparent by reference to the following detailed description taken in conjunction with the accompanying drawings. The drawings are intended to depict example embodiments of the inventive concepts and should not be interpreted in a limiting sense. The drawings are not to scale and are intended for use only in conceptual understanding.

[0012] Figure 1 is a block diagram of a storage system according to at least some example embodiments of the inventive concepts;

[0013] Figure 2 is Figure 1 is a block diagram of an embodiment of a host device shown in

[0014] Figure 3 is a block diagram of an embodiment of a storage controller as shown in Figure 1

[0015] Figure 4 is a block diagram of an embodiment of a storage system applying a Universal Flash Storage (UFS) interface;

[0016] Figure 5 is an illustration of the operation of a storage system according to at least some example embodiments of the inventive concept;

[0017] Figure 6 is a flowchart of a method of operation of a host device according to at least some example embodiments of the inventive concept;

[0018] Figure 7 is a block diagram of a storage system to which a write command is written according to at least some example embodiments of the inventive concept;

[0019] Figure 8 is a block diagram of a storage system to which a write response is written according to at least some example embodiments of the inventive concept;

[0020] Figure 9 is an illustration of a process in which a command is written to a circular queue according to at least some example embodiments of the inventive concept;

[0021] Figure 10 is a flowchart of a method of operation of a storage system according to at least some example embodiments of the inventive concept;

[0022] Figure 11 and Figure 12 is a block diagram of examples of various information stored in a host memory and registers of a host controller;

[0023] Figure 13 is an illustration of an embodiment of a data read process and packet according to a UFS interface;

[0024] Figure 14A and Figure 14B is an illustration of the structure of a packet according to at least some example embodiments of the inventive concept;

[0025] Figure 15 is a block diagram of a system to which a storage device according to at least some example embodiments of the inventive concept is applied;

[0026] Figure 16 is an illustration for describing a UFS system according to at least some example embodiments of the inventive concept;

[0027] Figures 17A to 17C ​is an illustration of the size form factor of a UFS card according to exemplary embodiments of the inventive concept;

[0028] Figure 18A is a block diagram of a host-storage system according to at least some exemplary embodiments of the inventive concept, and Figures 18B to 18E is Figure 18A a detailed block diagram of the configuration shown in

[0029] Figure 19 is a block diagram of a memory system according to at least some exemplary embodiments of the inventive concept;

[0030] Figure 20 is a block diagram of a memory system according to at least some exemplary embodiments of the inventive concept;

[0031] Figure 21 is a block diagram of a memory device according to at least some exemplary embodiments of the inventive concept;

[0032] Figure 22 is an illustration of a three-dimensional (3D) vertical NAND (V-NAND) structure that can be applied to a UFS device according to at least some exemplary embodiments of the inventive concept;

[0033] Figure 23 is a cross-sectional view of a memory device according to at least some exemplary embodiments of the inventive concept; and

[0034] Figure 24 is an illustration of a data center to which a storage system according to at least some exemplary embodiments of the inventive concept is applied. DETAILED DESCRIPTION

[0035] As is conventional in the art to which the present inventive concepts pertain, embodiments will be described with reference to functional blocks, units, and / or modules and illustrated in the attached drawings by these functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules can be implemented by circuitry (or optical circuitry), such as logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wires, and / or the like, which can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. Where a block, unit, and / or module is implemented by a microprocessor or similar option, it can be programmed using software (e.g., microcode) to perform various functions discussed herein and can be driven, optionally, by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by special purpose hardware, or can be implemented as a combination of special purpose hardware and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs certain functions. Also, each block, unit, and / or module of an embodiment can be physically separated into two or more distinct blocks, units, and / or modules interacting with one another, without departing from the scope of the present inventive concepts. Moreover, various blocks, units, and / or modules of an embodiment can be physically combined into more complex blocks, units, and / or modules, without departing from the scope of the present inventive concepts.

[0036] Figure 1 is a block diagram of a storage system 10 according to at least some example embodiments of the present inventive concepts.

[0037] The storage system 10 can also be referred to as a host storage system 10, which can include a host device 100 and a storage device 200. The host 100 can also be referred to as a host device 100.

[0038] For smooth data transfer between the host device 100 and the storage device 200, various standard protocols have been developed or are currently under development. As one of the standard protocols, the Joint Electron Device Engineering Council (JEDEC) has developed Universal Flash Storage (UFS) for flash memory devices such as smartphones and tablets. The UFS takes a command protocol that supports multiple commands with command queue progression and a Small Computer System Interface (SCSI) architectural model, thereby implementing a multi-threaded programming paradigm.

[0039] Another standard protocol developed by the JEDEC is the Embedded Multimedia Card (eMMC) standard protocol. The eMMC can provide a simplified application interface design, a small package size, and low power consumption. Storage devices based on eMMC flash memory are one major form of memory in current mobile devices.

[0040] The storage system 10 according to at least one exemplary embodiment of the inventive concept can include a flash memory-based storage device standard protocol, such as UFS and eMMC. However, the present embodiment is not limited thereto.

[0041] The storage system 10 can be embodied as, for example, a personal computer (PC) including a desktop computer and a laptop computer, a data server, a network attached storage (NAS), an Internet of Things (IoT) device, a workstation, a server, an electric vehicle, or a handheld electronic device. The handheld electronic device can include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an electronic book (e-book), and / or a wearable device.

[0042] The storage system 10 can store data into or retrieve data from the storage device 200 according to a command CMD of the host device 100. In an exemplary embodiment, the host device 100 can provide data to be written into the storage device 200, and can read the data by receiving a response RESP from the storage device 200. According to an exemplary embodiment, the host device 100 can issue a command CMD and transmit the command CMD to the storage device 200, and the storage device 200 can read, clear, or write data in response to the command and can generate a response RESP as a result, and provide the response RESP to the host device 100.

[0043] The command CMD can be contained in and managed in a command packet PACKET_C, and the response RESP can be contained in and managed in a response packet PACKET_R. Reference will be made to Figure 14A and Figure 14B The configuration of the packets is described in detail.

[0044] The host device 100 can include a host controller 110 and a host memory 130.

[0045] The host device 100 can provide various services to a user of the host device according to operation of one or more electronic circuits, chips, or devices. According to an exemplary embodiment, the host device 100 can perform various operations to process a command received from a user of the host device 100, and can provide a result of the operation to the user of the host device 100. The host device 100 according to an exemplary embodiment can include an operating system, an application, etc. The host device 100 according to at least some exemplary embodiments of the present inventive concept can include a universal flash storage (UFS) host control driver to support a UFS protocol. However, the present inventive concept is not limited thereto, and the host device 100 can include a driver to support an eMMC protocol or a high-speed non-volatile memory (NVMe) protocol.

[0046] The host controller 110 can control all operations of the host device 100, and more particularly, can control operations of other components included in the host device 100. In an exemplary embodiment, the host controller 110 can be embodied as a processor or an application processor, etc. Further, the host controller 110 can be embodied as an operating processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), etc.) including a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), but is not limited thereto. According to at least some exemplary embodiments of the present inventive concept, the host controller 110 can be or can include a processing circuit, e.g., hardware including a logic circuit; a hardware / software combination executing software; or a combination thereof. For example, the processing circuit can more particularly include, but is not limited to, one or more of a central processing unit (CPU), a processor core, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. According to at least some exemplary embodiments of the present inventive concept, the processing circuit of the host controller 110 can be specially structured and / or programmed (e.g., via computer executable program code) to implement and / or control some or all of the operations described in this specification as being performed by a host (e.g., the host 100), a host controller (e.g., the host controller 110), or an element of a host or host controller (e.g., a host controller interface (HCI) 190, discussed in greater detail below) in accordance with the present inventive concept. Figure 5 Some or all of the operations described in greater detail below are performed by the host controller 110.

[0047] The host controller 110 can execute various software loaded into the host memory 130. For example, the host controller 110 can execute an operating system (OS) and an application program.

[0048] The host controller 110 can generate a command CMD in response to a request of a user, and determine whether to transfer the command CMD to the storage device 200. In addition, the host controller 110 can receive a response RESP. In an exemplary embodiment, the host controller 110 can write the command CMD and / or the response RESP to a queue as a processing wait line, or remove the command CMD and / or the response RESP from the queue.

[0049] The host controller 110 can include one or more cores, and can further include another intellectual property (IP) configured to control a memory and / or the storage device 200. According to an exemplary embodiment, the core can execute a queue which is a processing wait line constituted by the command CMD and the response RESP processed by the host device 100. According to an exemplary embodiment, the host controller 110 can further include an accelerator which is a dedicated circuit for high-speed data operation (e.g., artificial intelligence (AI) data operation), and the accelerator can include a graphic processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and can also be embodied as a separate chip physically independent of other components of the host controller 110.

[0050] The host controller 110 can include a host controller interface (hereinafter, HCI), which can manage an operation of storing data (e.g., write data) of the host memory 130 into the non-volatile memory 230 or storing data (e.g., read data) of the non-volatile memory 230 into the host memory 130. In addition, the storage controller 210 can include a device controller interface (not shown) for interfacing with the host controller 110.

[0051] A submission queue (SQ) can refer to a line waiting for processing of various events such as a request or a command CMD from the host device 100. The command CMD stored in the SQ can be transferred to the storage device 200 by being fetched by the host controller 110. A completion queue (CQ) can denote a line for processing various events including a request or a response RESP from the storage device 200. The response RESP stored in the CQ fetched by the host controller 110 can indicate an update of metadata to be processed by the host after the end of a memory operation (e.g., write, read, or clear data). The SQ and the CQ can be generated in the host memory 130 of the host device 100. Although the implementation of the SQ and the CQ is shown as a circular queue according to at least one exemplary embodiment of the present inventive concept, the implementation is not limited thereto.

[0052] According to at least some exemplary embodiments of the inventive concept, the host controller 110 can include a doorbell register. The doorbell register is a register allocated to manage the SQ and the CQ. For example, the host controller 110 can perform interface operations with respect to the SQ and the CQ by accessing the SQ and the CQ via the doorbell register with the aid of the host memory 130. According to exemplary embodiments, the doorbell register can be included within the host controller interface.

[0053] The doorbell register according to exemplary embodiments can manage or control a queue pair generated by the host device 100. The doorbell register can correspond to a queue pair. For example, the doorbell register can store a head pointer (HP) and a tail pointer (TP) of a queue. For example, the doorbell register can store a tail pointer pointing to a tail of the SQ and a head pointer pointing to a head of the CQ.

[0054] According to at least one exemplary embodiment of the inventive concept, a doorbell register related to the SQ is referred to as an SQ doorbell register, and a doorbell register related to the CQ is referred to as a CQ doorbell register. Further, a structure in which a doorbell corresponding to one queue pair is expressed as a bitmap is referred to as a bitmap doorbell, and a bitmap is a group of 1-bit data spaces. According to at least some exemplary embodiments of the inventive concept, the SQ doorbell register, the CQ doorbell register, and the bitmap doorbell, etc. can be managed by the HCI 190. Reference will be made to FIG. 2. Figure 5 The HCI 190 is described in more detail.

[0055] The host memory 130 can be used as a main memory or a cache memory. Alternatively, the host memory 130 can be used as a drive memory configured to drive software, applications, or firmware. Programs or data to be processed by the host controller 110 can be loaded into the host memory 130. For example, a file system, applications, and device drivers, etc. can be loaded into the host memory 130. The file system can provide a logical address according to a command (e.g., a write command or a read command) to the storage device 200. The file system can be used according to a specific operating system executed by the host device 100. The file system can be embodied by software, applications, or firmware. For example, the host device 100 can execute Windows, Linux, and Unix, etc.

[0056] The host memory 130 can load the SQ and the CQ for a docking operation between the host device 100 and the storage device 200. The SQ can store a command CMD to be provided to the storage device 200, and the CQ can store a response RESP as completion information about an operation completed in the storage device 200.

[0057] According to an exemplary embodiment, the SQ and the CQ loaded by the host controller 130 can be referred to by the host controller 110. For example, the host controller 110 can write a command CMD or a response RESP to the SQ by referring to the tail pointer TP, and can read a command CMD or a response RESP from the CQ by referring to the head pointer HP. For example, the host controller 110 can increase the value of the tail pointer TP to indicate that the next empty space after the command CMD or the response RESP is to be written to the SQ or the CQ. Reference will be made to Figure 9 The operation of writing a command CMD or a response RESP to a queue or reading a command CMD or a response RESP from a queue will be described in more detail.

[0058] According to an exemplary embodiment, the host controller 110 and the host memory 130 can be embodied as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 130 can be integrated into the same semiconductor chip. For example, the host controller 110 can be included in any one of a plurality of modules provided within an AP, and the AP can be embodied as a system on chip (SoC). Further, the host memory 130 can be an embedded memory provided within the AP, or can be a memory device or a memory module external to the AP.

[0059] The host device 100 can further include various devices related to the driving of the storage device 200. For example, a software module (not shown), such as a host application and a device driver, can be further provided, and the software module can be loaded into the host memory 130 and executed by a processor (not shown).

[0060] The storage device 200 can include a storage controller 210 and a non-volatile memory device (NVM) 230. The NVM 230 can include an NVM core.

[0061] The storage device 200 can include a storage device configured to store data in response to a request from the host device 100. For example, the storage device 200 can include one or more solid state drives (SSDs). When the storage device 200 includes an SSD, the storage device 200 can include a plurality of flash memory chips (e.g., NAND memory chips) configured to store data in a non-volatile manner.

[0062] According to example embodiments, the storage device 200 can correspond to a flash memory device including one or more flash memory chips. The flash memory device can be a non-volatile data storage medium to / from which data can be electrically written / erased. In example embodiments, the storage device 200 can be an embedded memory embedded in a storage system. For example, the storage device 200 can be an embedded Multi-Media Card (eMMC) or an embedded UFS memory device. In example embodiments, the storage device 200 can be an external memory that can be attached to or detached from the storage system 10. For example, the storage device 200 can include various flash memory-based storage devices including a UFS memory card, a CompactFlash (CF) card, a Secure Digital (SD) card, a Micro Secure Digital (Micro-SD) card, a Mini Secure Digital (Mini-SD) card, an extreme Digital (xD) card or a memory stick, a Solid State Drive (SSD), a Universal Serial Bus (USB), and a flash drive.

[0063] When the storage device 200 includes a flash memory, the flash memory can include a two-dimensional NAND memory array or a three-dimensional (or vertical) NAND memory array. A 3D memory array is circuitry related to an array of memory cells having active regions on a silicon substrate or related to the operation of memory cells that are formed in a monolithic fashion on the substrate or are at least one physical level of circuitry formed within the substrate. The term "monolithic" means that the layers of each level that make up the array are directly stacked on the layers of a lower level of the array.

[0064] In example embodiments, the 3D memory array includes VNAND strings arranged in a vertical direction such that at least one memory cell is on top of another memory cell. The at least one memory cell can include a charge-trapping layer.

[0065] Each of U.S. Patent Publication Nos. 7,679,133, 8,533,456, 8,654,587, and 8,559,235 discloses appropriate configurations related to 3D memory configured in multiple levels in which word lines and / or bit lines are shared between the multiple levels, the disclosures of which are incorporated by reference herein in their entireties.

[0066] As another example, the storage device 200 can also include other various non-volatile memories. For example, magnetic RAM (MRAM), spin-transfer torque MRAM, conductive-bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM, and other various memories can be applied to the storage device 200.

[0067] The storage controller 210 can control all operations of the storage device 200. For example, the storage controller 210 can schedule operations of the NVM 230, or can encode and decode signals / data processed by the storage device 200. In an exemplary embodiment, the storage controller 210 can control the NVM to write, read, or erase data. According to at least some exemplary embodiments of the inventive concepts, the storage controller 210 can be or can include processing circuitry, e.g., hardware including logic circuitry; a hardware / software combination executing software; or a combination thereof. For example, the processing circuitry can include, but is not limited to, one or more of a central processing unit (CPU), a processor core, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc., more specifically. According to at least some exemplary embodiments of the inventive concepts, the processing circuitry of the storage controller 210 can be specially structured and / or programmed (e.g., via computer executable program code) to perform and / or control some or all of the operations described in this specification as being performed by a storage device (e.g., the storage device 200), a storage controller (e.g., the storage controller 210), or an element of a storage device or storage controller.

[0068] The NVM 230 can include a storage medium for storing data in response to a request from the host device 100. In an exemplary embodiment, as described above, the NVM 230 can include at least one flash memory chip configured to store data in a non-volatile manner, and can include a NAND or VNAND memory array.

[0069] The host device 100 and the storage device 200 can communicate with each other through various interfaces. For example, the host device 100 and the storage device 200 can be connected to each other through a standard interface, e.g., a Universal Flash Storage (UFS), a Serial ATA (SATA), a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), and an eMMC. The host device 100 and the storage device 200 can generate packets according to a protocol of the adopted interface, respectively, and transmit the packets. Figure 1 An example in FIG. 1 illustrates a command packet PACKET_C generated in the host device 100 and transmitted to the storage device 200, and a response packet PACKET_R generated in the storage device 200 and transmitted to the host device 100.

[0070] According to at least one exemplary embodiment of the inventive concept, the host device 100 can directly control SQ doorbell registers, CQ doorbell registers, bitmap doorbells, and arbitration and routing of SQs and CQs, thereby resolving the occupancy problem of the computing resources of the host device 100 and significantly improving its performance.

[0071] Figure 2 is Figure 1 a block diagram of an embodiment of the host device 100 shown in Figure 2 The example in illustrates an AP including the host controller 110. Hereinafter, the host device 100 will be described using this AP. However, it should be understood that the inventive concept is not limited to being embodied as an AP, and can be applied to various host devices that can provide master-slave functions.

[0072] In conjunction with Figure 1 Referring to Figure 2 , the host device 100 can include the AP and the host memory 130, and the AP can include one or more modules as the IP. In an exemplary embodiment, the AP can include the host controller 110, the at least one core 120, the host memory controller 140, the modem 150, the embedded memory 160, the camera interface 170, and the display interface 180. The host controller 110, the at least one core 120, the host memory controller 140, the modem 150, the embedded memory 160, the camera interface 170, and the display interface 180 can transmit and receive signals to and from each other through an internal bus. The host controller 110 can include the register 111 and the HCI 190.

[0073] Although the host memory 130 is shown in Figure 2 as corresponding to a memory outside the AP, embodiments of the inventive concept are not necessarily limited thereto. For example, in the above-described embodiment, the embedded memory 160 within the AP can also be used as the host memory 130. Since Figure 2 the configuration shown in Figure 2 is only one embodiment, the AP can further include other configurations in addition to the configuration shown in Figure 2 , or alternatively can not provide some of the configurations shown in

[0074] The at least one core 120 can control overall operations of the AP. For example, software configured to manage data write / read operations with respect to the storage system 10 (e.g., a driver of the AP and the device) can be loaded into the host memory 130 or the embedded memory 160, and the at least one core 120 can manage the data write / read operations by executing the software. The host memory 130 can be embodied as a volatile memory or a non-volatile memory, and according to an embodiment, the host memory 130 can include a non-volatile memory such as a Dynamic Random Access Memory (DRAM) and / or a Static Random Access Memory (SRAM).

[0075] The at least one core 120 can be a homogeneous multi-core processor or a heterogeneous multi-core processor.

[0076] According to at least some exemplary embodiments of the inventive concept, when the at least one core 120 includes a plurality of cores, different cores can each perform a task of a processing unit as an operation by executing different software. For example, a first core can perform a first task, and a second core which is homogeneous or heterogeneous with the first core can perform a second task. Each of the plurality of cores can include a dedicated queue. For example, the first core can use a first SQ and a second SQ, and the second core can use a second SQ and a second CQ, by which different tasks can be performed in parallel.

[0077] According to exemplary embodiments, the AP can perform a camera control operation, a display control operation, a modem operation, etc. Since the modem 150 is included in the AP, the AP can be referred to as a ModAP.

[0078] According to the above-described embodiments, the host controller 110 can transmit / receive a packet PACKET including a command CMD or a response RESP to / from the storage device 200. The host controller 110 can include a register configured to store one or more transmission requests.

[0079] According to exemplary embodiments, a transmission request with respect to a write / read to the storage device 200 can be stored into the register 111 based on control of the at least one core 120. Further, various information for generating a packet corresponding to the transmission request on the basis of control of the at least one core 120 can be stored into the host memory 130, and for example, information with respect to a type of the packet and table information including an address can be stored into the host memory 130. Further, in the case of a data write request, write data can be stored into a plurality of data buffers of the host memory 130 based on control of the at least one core 120. The host controller 110 can acknowledge the transmission request stored in the register 111 of the host controller 110, and can perform interfacing with the storage device 200 based on the transmission request.

[0080] As in the above-described embodiment, the host controller 110 can receive a response packet PACKET_R including a response RESP from the storage device 200 (see Figure 1 ), parse the response RESP from the received packet PACKET, and confirm whether the memory operation is processed according to the parsed response RESP.

[0081] The HCI 190 can connect the host device 100 to the storage device 200 by converting the format of commands (e.g., read commands, write commands, etc.), logical addresses, and data corresponding to various access requests issued by the host device 100 or by converting the format of exchanged instructions. In addition to the above-described UFS and eMMC, protocols applied to the host controller interface 190 can include Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), and Serial Attached SCSI (SAS). However, the protocol is not limited thereto, and various standard protocols supporting interfacing between different devices can be applied.

[0082] According to at least some example embodiments of the inventive concept, the HCI 190 can include an SQ doorbell register, an SQ arbiter, a bit map doorbell router, a bit map doorbell entry, a CQ router, and a CQ doorbell register. Reference will be made to Figure 5 Detailed configurations included in the HCI 190 will be described in more detail.

[0083] Figure 3 is Figure 1 a block diagram of an embodiment of the storage controller 210 shown in

[0084] Referring to Figure 1 and Figure 3 , the storage controller 210 can include a host interface 211, a CPU 212 as a processor, and a memory interface 216. In addition, the storage controller 210 can further include a flash translation layer (FTL) 213, a packet manager 214, and a buffer manager 215. The storage controller 210 can further include a working memory (not shown) in which the FTL 213 is loaded. According to execution of the FTL 213 by the CPU 212, data write and read operations to the memory core can be controlled.

[0085] The host interface 211 can transmit / receive the packet PACKET to / from the host device 100, and the packet PACKET transmitted from / received by the host interface 211 can include the buffer address indicating the position of the data buffer among the buffer areas in the host device 100 according to the embodiments described above. In addition, the memory interface 216 can perform an operation of writing or reading data by interfacing with the memory core.

[0086] The packet manager 214 can generate the packet PACKET according to the protocol of the interface negotiated with the host device 100, or parse various information from the received packet PACKET. In addition, the buffer manager 215 can manage an operation for storing various information parsed from the packet PACKET into the buffer; for example, the buffer manager 215 can manage a storage operation of the command CMD or the response RESP parsed from the packet PACKET.

[0087] The buffer manager 215 can manage an operation of storing the write data parsed from the packet PACKET into the buffer, and can manage an operation of storing the data read from the memory core into the buffer. According to an embodiment, the buffer manager 215 can be a buffer manager 215 provided within the storage controller 210. According to an embodiment, the buffer manager 215 can manage a buffer provided outside the storage controller 210.

[0088] For example, in a data write operation, the write command CMD and the first buffer address corresponding thereto can be parsed from the packet PACKET received from the host device 100, and the first buffer address can be stored in the buffer of the storage device 200. As a response to the write command, the storage device 200 can generate the packet PACKET including the response RESP requesting transmission of the write data having a certain size unit. In this case, the first buffer address corresponding to the first write command can be included into the packet PACKET, and the host device 100 can transmit the data stored in the data buffer at the position indicated by the first buffer address to the storage device 200 with reference to the response RESP and the first buffer address included in the packet PACKET.

[0089] Similarly, according to an example of a data read operation, a read command and a second buffer address corresponding thereto are parsed from a packet PACKET received from the host device 100, and the second buffer address can be stored within a buffer of the storage device 200. The storage device 200 generates a packet including data read in response to the read command CMD, and the second buffer address corresponding to the read command CMD can be included within the packet PACKET along with the response RESP. Further, the host device 100 can store the read data into a data buffer at a location indicated by the second buffer address with reference to the response RESP and the second buffer address included within the packet PACKET.

[0090] Reference will again be made to Figure 18A Description Figure 3 the host interface 211, the CPU 212, the FTL 213, the packet manager 214, the buffer manager 215, and the memory interface 216 shown in the storage system 10.

[0091] Figure 4 is a block diagram of an embodiment of the storage system 20 to which a UFS interface is applied. Figure 1 The storage system 10 in Figure 4 may be applied to the storage system 20.

[0092] Figure 1 In connection with Figure 4 , the UFS host and the UFS storage system of the storage system 20 can perform communication according to the UFS interface, and the UFS host can include the host memory 21, the software module 23, and the UFS host controller 25 corresponding to the hardware module as components. Since the host memory 21 can provide functions similar to those of the host memory 130 described with reference to Figure 1 and Figure 2 Description, a repeated description will be omitted. In Figure 4 , a host device interfaced by taking the UFS protocol (see Figure 1 ) is simply referred to as a UFS host, and a storage device 200 interfaced by taking the UFS protocol (see Figure 1 ) is simply referred to as a UFS device.

[0093] The software module 23 can include software (e.g., an application) and a UFS host controller driver. The software can include various applications executed by a UFS host, and the UFS host controller driver can be configured to manage driving of a peripheral device connected to the UFS host to enable use thereof, and data management operations such as data writing and reading for the storage device 200 can be performed through execution of the UFS host controller driver. The application software and the UFS host controller driver can be loaded into the host memory 21 or another operation memory of the UFS host, and can be executed by the processor.

[0094] The UFS host controller 25 can be an embodiment of the host controller 110 shown in Figure 2 FIG. 1. The UFS host controller 25 can include a UFS host controller interface (UFS HCI), a UTP protocol engine, and a UFS interconnect layer (UIC).

[0095] The UFS HCI can receive a generated request through the UFS host controller driver, and provide the request to the UTP protocol engine, or can provide a data access result provided by the UTP protocol engine to the UFS host controller driver.

[0096] The UTP protocol engine can provide services for an upper layer (or an application layer); for example, the UTP protocol engine can generate a packet or release a packet and parse information therein.

[0097] The UFS interconnect layer can communicate with the UFS storage device 27, and for example, the UFS interconnect layer can include a link layer and a physical layer (PHY layer). The link layer can include a Mobile Industry Processor Interface (MIPI) UniPro, and the PHY layer can include an MIPI M-PHY. Further, according to the UFS interface, the UFS host can provide a reference clock signal and a reset signal to the UFS storage device 27.

[0098] The UFS storage device 27 can include a storage controller and a memory core. According to an embodiment, in Figure 4 the storage controller can include a UFS interconnect layer, a UTP protocol engine, and a UFS storage device interface. Further, the memory core can be a core including a non-volatile memory (NVM) core.

[0099] In a structure in which the UFS host controller 25 and the UFS storage device 27 communicate with each other, data transmission and reception in response to a request from the UFS host controller driver can be performed through the UFS host controller interface. For example, in a data write operation, write data can be stored into a data buffer of the host memory 21 by the software module 23, the UFS host controller interface can access the data buffer of the host memory 21 and the accessed write data can be provided to the UFS storage device 27. A command CMD for a data transmission and reception operation can be stored into a queue. In an exemplary embodiment, when a circular queue is used, a head pointer HP and a tail pointer TP in which a command CMD is stored can be stored into the host memory 21. For example, the head pointer HP and the tail pointer TP can be stored into a doorbell register of the host memory 21.

[0100] According to at least some exemplary embodiments of the inventive concept, a command packet PACKET_C and / or a response packet PACKET_R transmitted by the storage device 200 to the host device 100 can include a buffer address indicating a location of a data buffer in the host memory 21. The buffer address can correspond to a physical address indicating a location of the data buffer. For example, table information (e.g., a physical region description table (PRDT)) including the buffer address can be stored into a region of the host memory 21, a UTP protocol engine of the UFS host can confirm the buffer address through the PRDT, and can generate a command packet PACKET_C including the confirmed buffer address. Further, a UTP protocol engine of the storage device 200 can generate a response packet PACKET_R including a buffer address stored in the storage device 200 and managed.

[0101] Further, the UFS host controller 25 and the UFS storage device 27 are connected in a port-mapped input / output type, and write and read operations can be processed in a multi-tasking method. Accordingly, the UFS storage device 27 can store and manage a plurality of commands derived from a plurality of packets and buffer addresses corresponding to the plurality of commands.

[0102] According to application of the UFS interface, various packets can be defined, and at least some exemplary embodiments of the inventive concept can be applied to at least some of the various packets.

[0103] In an exemplary embodiment, a packet according to the UFS interface can be defined as a UFS protocol information unit (UPIU), and as a kind thereof, packets such as a command UPIU for a write and read request, a response UPIU, a Data_In UPIU including read data, a Data_Out UPIU including write data, a task management (TM) request UPIU, and a ready to transfer (RTT) UPIU can be defined.

[0104] Further, according to at least some example embodiments of the present inventive concept, at least some kinds of packets among packets defined in the UFS interface can include the buffer address described above. For example, a packet requesting access to a data buffer of the host memory 21 can include the buffer address described above. According to at least one example embodiment of the present inventive concept, packets are exchanged between the host device 100 and the storage device 200, among the packets, a command packet PACKET C can include a command CMD, an SQ identification SQ ID, and a CQ identification CQ ID, and a response packet PACKET R can include a response RESP, an SQ identification SQ ID, and a CQ identification CQ ID. Reference will be made to Figure 14A and Figure 14B The configuration of the packet will be described.

[0105] Hereinafter, a detailed operation example of an interface between a host and a storage device according to at least some example embodiments of the present inventive concept will be described. In the embodiments hereinafter, a host and a storage device taking a UFS interface will be described. However, as described above, in addition to the UFS interface, at least some example embodiments of the present inventive concept can be applied to other various interfaces.

[0106] Figure 5 is an illustration of the operation of the storage system 10 according to at least some example embodiments of the present inventive concept. In conjunction with Figure 1 and Figure 2 Reference will be made to Figure 5 .

[0107] The host device 100 can include a plurality of processors or can include a plurality of cores 120 within one processor. For convenience of explanation, it is assumed that one or more processors include a plurality of cores 120. Further, it is further assumed that a UFS protocol is applied for interfacing between the host device 100 and the storage device 200.

[0108] The at least one core 120 can perform an interfacing operation with the storage device 200 based on at least one SQ and at least one CQ. The interfacing operation can be performed in units of a queue pair including an SQ to input a requested command and a CQ to write a processing unit of the command CMD.

[0109] According to at least some example embodiments of the present inventive concept, the at least one core 120 can process a memory operation by using the SQ and the CQ. Further, the SQ can store a processing address of the command CMD or the response RESP into an SQ head pointer SHP and an SQ tail pointer STP, and the CQ can store a processing address of the command CMD or the response RESP into a CQ head pointer CHP and a CQ tail pointer CTP.

[0110] The HCI 190 can include an SQ doorbell register 191, an SQ arbiter 192, a bitmap doorbell router 193, a bitmap doorbell register 194, an entry buffer 195, a CQ router 196, and a CQ doorbell register 197.

[0111] The SQ doorbell register 191 can be a pointer storage space to store an order or a location of the SQ. The SQ doorbell register 191 can store a pointer indicating a tail or a head. According to an exemplary embodiment, the SQ doorbell register 191 can include a register indicating a base address of an SQ entry space and a register indicating a size of the SQ entry. According to an exemplary embodiment, the SQ doorbell register 191 can store an SQ head pointer SHP and an SQ tail pointer STP.

[0112] An address in which an entry of the SQ is stored in the HCI 190, referred to as an SQ entry address SQ ENTRY ADDR, can be calculated as in Equation 1.

[0113] [Equation 1]

[0114] (SQ ENTRY ADDR) = (SQ ENTRY BASE ADDR) + (SHP) x (SQ ENTRY SIZE)

[0115] That is, the SQ entry address SQ ENTRY ADDR can be a location obtained by adding a size of a product of the size of the SQ entry and the SQ head pointer SHP to the SQ entry base address SQ ENTRY BASE ADDR.

[0116] The pointer stored in the SQ doorbell register 191 can be updated at every doorbell notification of an input of a command CMD or an input / output of data. According to at least some exemplary embodiments of the inventive concept, the core 120 can write the command CMD to the SQ. After the command CMD is written to the SQ, the SQ tail pointer STP can be changed. The command CMD can be sequentially or simultaneously transferred to the storage device 200 by being fetched by the core 120. For example, the core 120 can fetch the SQ and transfer the command CMD stored in the SQ to the storage device 200. After the command CMD written to the SQ is transferred to the HCI 190, the SQ head pointer SHP can be changed.

[0117] Based on the SQ head pointer SHP and the SQ tail pointer STP stored in the SQ doorbell register 191, the command CMD written to the SQ can be transferred to the SQ arbiter 192. Since the SQ can be in the host memory 130 (see FIG. 1), the SQ arbiter 192 can be in the host memory 130. The SQ arbiter 192 can be a circuit for arbitrating the order of the command CMD written to the SQ. Figure 1) are stored, so it can be understood that commands or signals are provided from the SQ doorbell registers to which the SQ head pointer SHP or the SQ tail pointer STP are stored. According to at least some exemplary embodiments of the inventive concept, since there can be a plurality of cores 120, there can be a plurality of SQs, and the SQ arbiter 192 can receive a plurality of SQs.

[0118] The SQ arbiter 192 can arbitrate the order of processing of the SQs by selecting any one of the plurality of SQs according to the reference, determining the order of processing the SQs among the plurality of SQs. For example, the SQ arbiter 192 can determine the order of the commands CMD among the plurality of SQs, and each of the plurality of SQs can execute the commands stored in the circular queue according to the determined order in a first-in first-out method. In addition, as a method of selecting any one of the SQs by the SQ arbiter 192, there are various algorithms for non-preemptive scheduling or preemptive scheduling according to a time point at which an application is scheduled, and static scheduling and dynamic scheduling according to whether a scheduling priority is changed. For example, the SQ arbiter 192 can apply a round robin method in which, because the SQs are sequentially (or in a circular manner) selected, the processing time period between the SQs is uniform, a weighted round robin method in which the processing time period between the SQs is not uniformly allocated by starting to process the queue (e.g., SQ) from the SQ having a greater weight, in which a higher weight is given to a relatively important SQ among the SQs, and a fixed priority method in which a fixed priority is given to the SQs as part of static scheduling, but is not limited thereto.

[0119] The SQ arbiter 192 can arbitrate the order of the plurality of SQs by comparing the difference between the plurality of SQs. According to at least some exemplary embodiments of the inventive concept, the SQ arbiter 192 can compare the tail of the SQ with the head thereof. To acquire information about the SQ, the SQ arbiter 192 can refer to the SQ head pointer SHP and the SQ tail pointer STP stored in the SQ doorbell register 191.

[0120] The SQ arbiter 192 according to at least some exemplary embodiments of the inventive concept can access the SQ doorbell register 191 within the HCI 190, and by doing so the SQ arbiter 192 can refer to the head and the tail of the SQs processed by the at least one core 120, and can arbitrate so that the SQ having insufficient free space is preferentially processed.

[0121] According to at least some exemplary embodiments of the inventive concept, the SQ arbiter 192 can arbitrate the order of the SQs, thereby preferentially processing the SQ having a priority processing flag that needs priority processing.

[0122] According to at least some example embodiments of the inventive concept, the SQ arbiter 192 can determine a selected SQ among the plurality of SQs or a SQ having priority as a result of the comparison. The SQ arbiter 192 can transfer the command CMD written into the determined SQ to the bitmap doorbell router 193.

[0123] The bitmap doorbell router 193 can designate (i.e., route) a space of the entry buffer 195 in which the command CMD is to be stored. According to at least some example embodiments of the inventive concept, the bitmap doorbell router 193 can search the bitmap doorbell register 194 including information about occupied spaces and free spaces of the entry buffer 195, and can designate a path or provide address information so that the command CMD can be written into the free space. According to an example embodiment, the bitmap doorbell router 193 can designate a space in the entry buffer 195 in which the command CMD selected by the SQ arbiter 192 is to be stored.

[0124] The bitmap doorbell register 194 can be a bit storage space that can indicate a state of a storage space in the entry buffer 195. The bitmap doorbell is a data structure expressed as a bitmap of a set of 1-bit data spaces. The bitmap doorbell register 194 expresses whether a data space is occupied using a bit "0" and a bit "1", so the bitmap doorbell router 193 can write the selected command CMD (or operation) into a free space in which data is not stored by searching for a bit "0".

[0125] In an example embodiment, when the command CMD or the response RESP is written into a free space of the entry buffer 195, a bitmap for the space can be changed to a bit "1". In an example embodiment, when the command CMD or the response RESP written into an occupied space of the entry buffer 195 is processed, a bitmap for the space can be changed to a bit "0".

[0126] The entry buffer 195 can include SQ entries and CQ entries to be exchanged with the storage device 200 (see Figure 1 ) and can further include buffers configured to store a UTP transfer request descriptor (UTRD), a PRDT, a SQ identification SQ_ID, and a CQ identification CQ_ID in addition to data storage spaces indicating whether occupied by data.

[0127] According to an example embodiment, the entry buffer 195 can transfer the command CMD to the storage controller 210 (see Figure 1SQ identification SQ ID and a CQ identification CQ ID, the former indicating a SQ to which the transmitted command CMD is written, and the latter indicating a CQ involved by the transmitted command CMD. Similarly, the entry buffer 195 can receive a SQ identification SQ ID and a CQ identification CQ ID from the storage controller 210, the former indicating a SQ involved by the provided response RESP, and the latter indicating a CQ involved by the transmitted response RESP.

[0128] The host device 100 can provide a command CMD to the storage device 200 with reference to an entry buffer 195 in which data is stored (i.e., "1" is stored into the bitmap doorbell register 194). The storage device 200 can perform some operation for the command CMD, and can provide a response RESP to the host device 100 as a result of the operation. The response RESP can be stored into the entry buffer 195 again. The host device 100 and the storage device 200 can perform data communication in units of a packet PACKET, and the command CMD and the response RESP can be contained into a command packet PACKET C and a response packet PACKET R, respectively.

[0129] According to at least some example embodiments of the inventive concepts, the entry buffer 195 can buffer a plurality of SQ entries and / or CQ entries. For example, the entry buffer 195 can buffer UTRD, PRDT, command CMD, response RESP, SQ identification SQ ID, CQ identification CQ ID, etc.

[0130] The CQ router 196 can specify (i.e., route) a CQ in which a response RESP stored in the entry buffer 195 is to be processed. The response RESP can be provided by the storage device 200, and then buffered by the entry buffer 195 before being processed.

[0131] According to at least some example embodiments of the inventive concepts, the CQ router 196 can search for a core in which a response RESP can be processed, and can perform routing such that the response RESP is written into a CQ processed by the searched core. According to example embodiments, a head pointer (e.g., CHP) or a tail pointer (e.g., CTP) of a CQ in a CQ doorbell register can be updated as a result of the CQ router 196 assigning a response RESP to a CQ.

[0132] In an exemplary embodiment, the CQ router 196 can refer to a CQ identifier CQ ID provided by the storage device 200 to determine a core of the plurality of cores that loads a CQ to which the response RESP will be written. For example, the CQ router 196 can write the response RESP into a first CQ by receiving a first CQ identifier CQ ID loaded into a first core. Similar to the SQ selection method described above, various selection algorithms can be applied to the method of searching for a CQ by the CQ router 196.

[0133] Further, according to at least some exemplary embodiments of the inventive concept, the CQ router 196 can control data input / output between the CQ and the entry buffer 195, thereby preventing the CQ from overflowing. For example, the CQ router 196 can control data flow between the CQ and the entry buffer 195 to prevent an overflow state in which the CQ is full and cannot store the response RESP.

[0134] The CQ doorbell register 197 can include a pointer storage space configured to store an order or a location of the CQ. The CQ doorbell register 197 can store a pointer indicating a tail or a head. According to an exemplary embodiment, the CQ doorbell register 197 can include a register indicating a base address of an entry space of the CQ and a size of a CQ entry. According to an exemplary embodiment, the CQ doorbell register 197 can store a CQ head pointer CHP and a CQ tail pointer CTP.

[0135] An address CQ ENTRY ADDR at which the CQ entry is stored in the HCI 190 can be calculated as in Equation 2.

[0136] [Equation 2]

[0137] (CQ ENTRY ADDR) = (CQ ENTRY BASE ADDR) + (CHP) x (CQ ENTRY SIZE)

[0138] That is, the CQ entry address CQ ENTRY ADDR can be a location obtained by adding a size of a product of the size of the CQ entry and the CQ head pointer CHP to the CQ entry base address CQ ENTRY BASE ADDR.

[0139] The pointer stored in the CQ doorbell register 197 can be updated at every doorbell notification that occurs according to the input of the command CMD or the input / output of data. According to at least some exemplary embodiments of the present inventive concept, the core 120 can write the response RESP received from the HCI 190 to the CQ. After the response RESP is written to the CQ, the CQ tail pointer CTP can be changed. The responses RESP can be processed sequentially or simultaneously by being fetched by the core 120. For example, the core 120 can fetch the CQ and perform a processing operation corresponding to the responses RESP stored in the CQ. After the responses RESP written to the CQ are processed, the CQ head pointer CHP can be changed.

[0140] The SQ arbiter 192, the bitmap doorbell router 193, and the CQ router 196 can be embodied as processing circuitry, for example, hardware including a logic circuit, or can be embodied as a combination of hardware and software, for example, a processor running software that performs the arbitration operation and / or the routing operation. Specifically, the processing circuitry can be embodied as a CPU, an arithmetic logic unit (ALU) configured to perform arithmetic and logical operations, a digital signal processor (DSP), a microprocessor, and an application specific integrated circuit (ASIC), but is not limited thereto.

[0141] When one bitmap doorbell is shared by a plurality of cores, resource occupation overhead will occur, and the performance of the entire system can be degraded accordingly. For example, in the UFS protocol, when any one of the plurality of cores sets out to process the bitmap doorbell, the other cores cannot access the bitmap doorbell.

[0142] The storage system 10 according to at least one exemplary embodiment of the present inventive concept includes the SQ arbiter 192 and the CQ router 196 to prevent resource occupation of a plurality of queues, and by doing so, the interfacing between the host device and the storage device taking the UFS protocol can be smoothly performed even in a multi-queue environment.

[0143] According to at least one exemplary embodiment of the present inventive concept, in the HCI 190, a dedicated SQ and a dedicated CQ suitable for a plurality of cores and a queue doorbell for a plurality of cores (i.e., for the SQ doorbell and the CQ doorbell) can be used directly. That is, according to at least one exemplary embodiment of the present inventive concept, the bitmap doorbell structure applied to the UFS is maintained, and by doing so, changes in the structure of the storage system 10 can be minimized as much as possible, while the SQ arbiter 192, the bitmap doorbell router 193, and the CQ router 196 can maintain compatibility with other devices taking the UFS protocol.

[0144] Accordingly, the storage system 10 according to at least one exemplary embodiment of the inventive concept can use a multi-cyclic queue (e.g., SQ and CQ) in transferring a command CMD directly from the HCI 190 to the storage device 200, and thus can significantly improve an overhead due to an occupation of a shared resource between a plurality of cores and a performance of the storage system 10.

[0145] Figure 6 is a flowchart of an operation method of the host device 100 (see Figure 1 ) according to at least some exemplary embodiments of the inventive concept. In conjunction with Figure 6 reference is made to Figure 1 and Figure 5 .

[0146] In operation S110, the host device 100 can arbitrate a plurality of commands CMD written to a plurality of SQs. According to an exemplary embodiment, there can be a plurality of cores, and one core can process a command CMD and / or a response RESP by using at least one SQ and at least one CQ. For example, the SQ arbiter 192 can arbitrate a priority between the commands CMD with reference to an SQ head pointer SHP and an SQ tail pointer STP of an SQ entry stored in the SQ doorbell register 191.

[0147] In operation S120, the host device 100 can write an SQ entry to the entry buffer 195. In an exemplary embodiment, the host device 100 can store only a command CMD contained in the SQ into the entry buffer 195, not the entire SQ entry.

[0148] In operation S130, the host device 100 can set a bitmap doorbell. In an exemplary embodiment, a command CMD can be stored into the entry buffer 195, and a specific value of the bitmap doorbell can be set.

[0149] For example, the SQ arbiter 192 can transfer any one selected command CMD to the bitmap doorbell router 193, and the bitmap doorbell router 193 can store the command CMD into the entry buffer 195 by designating a free space of the bitmap doorbell register 194 in which the command CMD will be stored. When the command CMD is written to the entry buffer 195, a data area of the bitmap doorbell register 194 corresponding to the entry buffer 195 can be changed from a bit "0" to a bit "1".

[0150] In operation S140, the host device 100 can update an SQ doorbell. According to an exemplary embodiment, when a command CMD is written to the entry buffer 195, the host device 100 can update an SQ head pointer SHP in the SQ doorbell register 191.

[0151] According to at least some example embodiments of the inventive concept, once a command CMD to be processed is written to the entry buffer 195, the command CMD will be transferred to the storage device 200 (see Figure 1 ), and will not be processed in the host device 100. Accordingly, the host device 100 can improve the efficiency of the space of the SQ by updating the SQ head pointer SHP.

[0152] In operation S150, the host device 100 can transfer the command CMD and receive the response RESP. According to an example embodiment, the host device 100 can transfer the command CMD to the storage device 200. The storage device 200 can perform a specific memory operation based on the command CMD, and can provide the response RESP, which is metadata about the result of the execution, back to the host device 100. In operation S160, the host device 100 can store the received response RESP into the entry buffer 195. According to at least some example embodiments of the inventive concept, the entry buffer 195 can buffer the command CMD and the response RESP.

[0153] In operation S170, the host device 100 can designate (route) the response RESP to be stored into any one of the plurality of CQs. For example, referring to the bitmap doorbell register 194, the CQ router 196 can refer to the plurality of responses RESP written, select any one of the plurality of responses RESP according to a certain criterion (e.g., priority), and can store the response RESP into the CQ doorbell register 197.

[0154] In operation S180, the host device 100 can update the CQ doorbell. According to an example embodiment, as a result of the CQ router 196 designating the response RESP for the CQ, the tail pointer (e.g., CTP) of the CQ in the CQ doorbell register 197 can be updated.

[0155] According to at least some example embodiments of the inventive concept, the HCI 190 can arbitrate the order of the plurality of SQs. The HCI 190 can determine the priority, and can store the command contained in the selected SQ entry into the entry buffer 195. For example, a first command stored in a first SQ can be stored into the entry buffer 195. When the first command is stored into the entry buffer 195, the HCI 190 can update the head pointer of the first SQ.

[0156] The HCI 190 can select a next order among the plurality of SQs. The HCI 190 can store a second command stored in a second SQ into the entry buffer 195. When the second command is stored into the entry buffer 195, the HCI 190 can update a head pointer of the second SQ. The process is repeated in order. The first and second commands stored in the entry buffer 195 can be transferred to the storage device 200 according to the input order.

[0157] Figure 7 is a block diagram of a storage system 10 to which a command CMD is written according to at least some example embodiments of inventive concepts. In conjunction with Figure 7 Referring to Figure 5 and Figure 6 .

[0158] The storage system 10 can include a host device 100 and a storage device 200. Since Figure 1 the host device 100 and the storage device 200 in the above-described

[0159] The host device 100 can include a first core 121 and a second core 123.

[0160] The first core 121 can write a command CMD to a first SQ SQ1, and can refer to a first SQ head pointer SHPl and a first SQ tail pointer STPl. The first SQ head pointer SHPl and the first SQ tail pointer STPl can be included into a first SQ doorbell. Further, the first core 121 can process a response RESP written to a first CQ CQl by referring to a first CQ head pointer CHP1 and a first CQ tail pointer CTP1.

[0161] The second core 123 can write a command CMD to a second SQ SQ2, and can refer to a second SQ head pointer SHP2 and a second SQ tail pointer STP2. Further, the second core 123 can include a second CQ head pointer CHP2 and a second CQ tail pointer CTP2 of a second CQ CQ2.

[0162] According to at least some example embodiments of inventive concepts, the host device 100 can provide a first command CMD1 to the entry buffer 195 as a result of taking out a first SQ SQ1 executed in the first core 112. For example, the bitmap doorbell router 193 can search for a blank space by referring to bits stored in the bitmap doorbell register 135. The entry buffer 195 can write the first command CMD1 to a data space for buffering, and a value of a bitmap of the space corresponding to the first command CMD1 in the bitmap doorbell register 194 can be changed from a bit "0" to a bit "1".

[0163] According to exemplary embodiments, when the first command CMD is transferred, an SQ identifier SQ_ID indicating which SQ the command CMD is written into between the first SQ and the second SQ can be stored into the entry buffer 195. In addition, a CQ identifier CQ_ID indicating a CQ having enough computational resources or a blank data space of a queue between the first CQ CQ1 and the second CQ CQ2 can be transferred to the entry buffer 195. The first command CMD1, the SQ identifier SQ_ID, and the CQ identifier CQ_ID can be transferred in the form of a packet PACKET.

[0164] According to at least some exemplary embodiments of the inventive concept, the first SQ head pointer SHP1 of the first SQ SQ1 can be updated after the first command CMD1 is transferred. For example, when the head of the first SQ head pointer SHP1 is increased by one (++HEAD), the write space indicated by the head of the first SQ1 can be changed. When the first SQ head pointer SHP1 is increased by one, the command CMD1 written to the first SQ SQ1 can be erased. That is, the first command CMD can be removed from the queue.

[0165] According to at least some exemplary embodiments of the inventive concept, once a command CMD to be processed is written into the entry buffer 195, the command will not be processed in the host device 100. For example, when the storage space of the first command CMD1 is moved from the first SQ SQ1 to the entry buffer 195, the first SQ SQ1 does not have to store the first command CMD1 any more. Due to the characteristics of a circular queue having a limited write space, a new command can be written only after unnecessary commands are removed. Therefore, after the first command CMD1 is stored into the entry buffer 195, the first command CMD1 written to the first SQ SQ1 when the SQ head pointer SHP1 of the write space is updated (i.e., when the head value is increased by one) can be removed from the queue. Accordingly, the host device 100 can improve the efficiency of input / output by removing the first command CMD1 from the first SQ SQ1.

[0166] The host device 100 can provide the first command CMD1 to the storage device 200 through the entry buffer 195. After the first command CMD1 is transferred, the bitmap doorbell register 194 can change the value of the bitmap corresponding to the space where the first command CMD1 is written from a bit "1" to a bit "0".

[0167] Figure 8 is a block diagram of a storage system 10 to which a response RESP is written according to at least some exemplary embodiments of the inventive concept. Figure 8 Operation after the first command CMD1 is written according to Figure 7 will be omitted.Figure 7 those same descriptions. In conjunction Figure 8 Referring to Figures 5 to 7 .

[0168] According to at least some example embodiments of the inventive concept, the storage device 200 can generate a second response RESP2 as a result of executing the first command CMD1, and transmit the second response RESP2 back to the host device 100.

[0169] According to an example embodiment, the entry buffer 195 can store the response RESP. For example, the entry buffer 195 can write the second response RESP2 into a data space for buffering, and a value of a bitmap corresponding to a space into which the second response RESP2 is written can be changed from a bit "0" to a bit "1".

[0170] In addition to the transmission of the second response RESP2, an SQ identification SQ_ID indicating which SQ between the first SQ SQ1 and the second SQ SQ2 the command (e.g., the first command CMD1) processed and a CQ identification CQ_ID indicating which CQ between the first CQ CQ1 and the second CQ CQ2 the command processed can be transmitted to the host device 100. The second response RESP2, the SQ identification SQ_ID, and the CQ identification CQ_ID can be transmitted in the form of a packet PACKET.

[0171] According to an example embodiment, based on the CQ identification CQ_ID provided by the storage device 200, the response RESP can be written to a CQ between the first core 121 and the second core 123 corresponding to the referenced CQ identification CQ_ID. For example, according to the CQ identification CQ_ID indicating the second CQ CQ2 loaded into the second core 113, the response RESP can be written to the second CQ CQ2.

[0172] According to an example embodiment, the CQ router 196 can designate (route) the response RESP to the CQ. According to an example embodiment, the second response RESP2 can be temporarily stored in the entry buffer 195 until it is determined whether the host device 100 can access the second CQ CQ2.

[0173] In an example embodiment, after the second response RESP2 is written, a second CQ tail pointer CTP2 of the second CQ CQ2 can be updated. For example, when a value of a tail of the second CQ tail pointer CTP2 is increased by 1 (++TAIL), a write space indicated by the tail of the second CQ2 can be changed. That is, when the tail pointer is incremented by 1, the second response RESP2 can be queued to the second SQ SQ2.

[0174] After the second response RESP2 is written to the second CQ CQ2, the bitmap doorbell register 194 can change the state of the space to which the second response RESP2 is written from a bit "1" to a bit "0".

[0175] Figure 9 is a diagram of a process in which a command CMD is written to a circular queue according to at least some example embodiments of the inventive concepts. Figure 9 The circular queue shown in Figures 1 to 8 SQ and / or CQ shown in Figure 9 Referring to Figure 1 and Figure 2 .

[0176] A circular queue has an array in which a first address and a last address are connected, and is a data structure that allows insertion and deletion of data. The initial value of the head and the tail of the circular queue is 0, and when the value of the head is equal to the value of the tail, it is understood that the circular queue is empty. In the initial state in which the values of the head and the tail are 0, respectively, new data (e.g., a command) can be written. The new data (e.g., a command) can be written to a space indicated by the tail.

[0177] Referring to Figure 9 , it is assumed that there are eight writable spaces in the circular queue, and a first command CMD1, a second command CMD2, and a third command CMD3 are written therein.

[0178] A command CMD can be written to a space indicated by the tail, and the value of the pointer can increase by 1 each time a command is written. For example, the initial value of the head can be 0, and after the first command CMD1 to the third command CMD3 are written, the value of the tail can be 3. That is, the tail indicates a space to which a command is to be written, and after the command is written, the value of the tail can increase to indicate the next space just after the space to which the data is written. According to an example embodiment, when the first command CMD1, the second command CMD2, and the third command CMD3 are sequentially written, the tail can increase by 1, and when the third command CMD3 is written, the tail can indicate the next space just after the space to which the third command CMD3 is written.

[0179] In an example embodiment, a fourth command CMD4 can be queued to the circular queue. The head can maintain the initial value of 0, and the value of the tail can increase (++TAIL) as a new command is written. Accordingly, the tail can indicate the next space just after the fourth command CMD4.

[0180] When the commands are sequentially written to the circular queue as described above, the value of the head remains the same while the value of the tail is increased by 1 (++TAIL). When the value of the tail + 1 is equal to the value of the head, it is understood that the circular queue is full. In an exemplary embodiment, since the queue depth, which is the data capacity of the circular queue, is finite, the value of the tail can be allocated in a wrap-around method that reuses the existing address. For example, when the queue depth of the circular queue is N, when the increased value of the tail is N, the tail can have 0 again as the value corresponding to the address. As described above, the next address of the last address is the first address of the circular queue, which is advantageous for a finite data space allocation environment and can be easily embodied.

[0181] According to at least some exemplary embodiments of the inventive concept, Figures 1 to 8 SQ and / or CQ in FIG. 10 can be implemented as a circular queue. In using the circular queue structure, the command (or response) can be easily written to the SQ and / or CQ by simply adding 1 (++TAIL) to the tail pointer of the address of the write space indicated as the tail. Similarly, the command (or response) written to the SQ and / or CQ can be easily cleared by adding 1 (++HEAD) to the head pointer.

[0182] Figure 10 is a flowchart of an operation method of the storage system 10 according to at least some exemplary embodiments of the inventive concept. In conjunction with Figure 1 and Figure 5 Referring to Figure 10 .

[0183] In operation S205, the core 120 can issue a command CMD. The command CMD can be written into an SQ entry.

[0184] In operation S210, the core 120 can write the issued command into the SQ and update the SQ doorbell. For example, the core 120 can perform a process according to the write of data by updating the SQ tail pointer STP of the SQ doorbell.

[0185] In operation S215, the core 120 can transfer the SQ entry to the HCI 190. The SQ itself is basically stored in the host memory 130 (see Figure 1 ) and can be managed by the core 120. Accordingly, the core 120 can transfer the entry information of the SQ to the HCI 190.

[0186] In operation S220, the HCI 190 can store the SQ entry into the entry buffer 195. According to an exemplary embodiment, the HCI 190 can arbitrate a plurality of commands CDM written to a plurality of SQs, and the SQ arbiter 192 can arbitrate a priority between the commands CDM with reference to the SQ head pointer SHP and the SQ tail pointer STP of the SQ entry stored in the SQ doorbell register 191. As a result of the arbitration, the HCI 190 can store the command CDM contained in the SQ into the entry buffer 195.

[0187] In operation S225, the HCI 190 can set a bitmap doorbell. For example, the entry buffer 195 can write the command CDM into a data space for buffering, and a value of a bitmap of the bitmap doorbell register 194 corresponding to a space in which the command CDM is written can be changed from a bit "0" to a bit "1".

[0188] In operation S230, the HCI 190 can update the SQ doorbell. According to an exemplary embodiment, when the command CDM is written to the entry buffer 195, the HCI 190 can update the SQ head pointer SHP in the SQ doorbell register 191.

[0189] According to an exemplary embodiment, when the command CDM to be processed is written to the entry buffer 195, the HCI 190 can improve efficiency of a space of the SQ by updating the SQ head pointer SHP.

[0190] In operation S235, the HCI 190 can transmit the command CDM and receive a response RESP. According to an exemplary embodiment, the HCI 190 can transmit the command CDM to the storage device 200. The storage device 200 can perform a specific memory operation based on the command CDM, and can provide the response RESP of metadata as a result of the performance back to the host controller interface 190.

[0191] In operation S240, the HCI 190 can store the received response RESP into the entry buffer 195. According to an exemplary embodiment, the entry buffer 195 can buffer the response RESP before a path of the response RESP is set.

[0192] In operation S245, the HCI 190 can transfer the response RESP to the CQ entry. According to at least some example embodiments of the present inventive concepts, the CQ router 196 can designate (route) the response RESP to be stored into any one of the plurality of CQs. For example, by reference to the bitmap doorbell register 194, the CQ router 196 can select any one of the plurality of responses RESP according to some criteria (e.g., priority) and can store a pointer to the response RESP within the CQ doorbell register 197. Thereafter, the response RESP can be written to the CQ. The CQ itself is substantially stored within the host memory 130, and the HCI 190 can transfer the entry information of the CQ to the core 120.

[0193] In operation S250, the HCI 190 can update the CQ doorbell. According to example embodiments, when the response RESP is written to the CQ, the HCI 190 can update the CQ tail pointer CTP of the CQ doorbell register 197.

[0194] In operation S255, the HCI 190 can clear the bitmap doorbell. According to example embodiments, the HCI 190 can store the response RESP according to the command CMD within the CQ doorbell register 197 to be assigned to a specific completion queue, and thereafter can secure free space of the bitmap doorbell by removing the bitmap involved by the SQ with respect to the command CMD and the bitmap involved by the CQ with respect to the response RESP.

[0195] For example, with reference to the processes in Figure 7 and Figure 8 , the first command CMD1, the SQ identification SQ ID, and the CQ identification CQ ID written to the first SQ SQ1 can be stored within the entry buffer 195, and can change the memory area state (bit "0" -> bit "1") of the bitmap doorbell register 194. The first command CMD1 can be provided to the storage device 200, and the second response RESP2 according to the first command CMD1 can be stored back to the entry buffer 195 along with the SQ identification SQ ID and the CQ identification CQ ID. The second response RESP2 can be assigned to the second CQ CQ2, and stored within the CQ doorbell register 197. When the second response RESP2 is processed, the data (the first command CMD1, the second response RESP2, and the SQ identification SQ ID and the CQ identification CQ ID stored within the entry buffer 195) generated or stored in the processing of the first command CMD1 and the second response RESP2 can be cleared. As a result, the bitmap doorbell register 194 and the entry buffer 195 can be initialized.

[0196] In operation S260, the CQ entry can be consumed. According to an exemplary embodiment, the CQ can access a location where the response RESP is stored by referring to a pointer within the CQ doorbell register 197. For example, the second core 123 (see Figure 8 ) can write the second response RESP2 to the second completion queue CQ2 by referring to the second CQ tail pointer CTP2, and the second response RESP2 can be processed by the second core 123.

[0197] In operation S265, the CQ doorbell can be updated. According to an exemplary embodiment, after the second response RESP2 is processed by the second core 123, a free space is generated again within the second CQ CQ2. The CQ doorbell register 197 can improve input / output efficiency of the second CQ CQ2 by updating the CQ head pointer CHP2.

[0198] Figure 11 and Figure 12 Each is an example of various information stored within the host memory 130 (see Figure 1 ) and the register 111 of the host controller 110 (see Figure 1 ). In connection with Figure 11 and Figure 12 , reference is made to Figure 1 and Figure 2 .

[0199] Reference is made to Figure 11 , the host device 100 includes the host memory 130 and the register 111 as a component provided within the host controller 110, and the host memory 130 can be external to the host controller 110. For data management of the storage system 10, various commands and parameters defined according to the JEDEC UFS standard can be stored within the host memory 130 and the register 111.

[0200] The UTF transfer request descriptor is stored within the descriptor area of the host memory 130, and the UPIU information and the PRDT information corresponding thereto can be stored within another area of the host memory 130. Further, the UTF transfer request descriptor can be stored into or acknowledged within the host memory 130 by the UTF transfer request stored within the register 111.

[0201] Further, the write data and the read data are stored into a plurality of data buffers included within the buffer area of the host memory 130, and the PRDT information can include a buffer address which is a physical address of the data buffer. Further, the PRDT information can not be stored for some of the command UPIU, for example, for the command UPIU not related to access of the data buffer, the PRDT information can not be stored.

[0202] Further, Figure 11 Further shown are various information defined by the JEDEC UFS standard. For example, a UTF task management request list can be further stored into a region of the host memory 130, and (for example) a task management UPIU and a task management response UPIU can be stored into a region of the host memory 130. Further, the task management request list can be stored into the host memory 130 by a UPT task management request stored in the register 111. Further, other components defined by the JEDEC UFS standard are further shown in the register 111, for example, host controller capabilities, interrupts and host status, UFS interconnect (UIC) commands (UIC commands) and vendor details can be stored into the register 111.

[0203] In the operating system, for storing data stored in the data buffer of the host memory 130 into the storage device 200 (see Figure 1 ), the HCI 190 can be initiated by creating a UTP transfer request descriptor and creating a UTP transfer request (see Figure 2 ).

[0204] The HCI 190 can access the space of the host memory 130 corresponding to the UTP transfer request, and can read the UTP transfer request descriptor, and can send the corresponding command UPIU to the storage device 200.

[0205] The storage device 200 receiving the command UPIU can send a prepare transfer UPIU to the HCI 190 along with the size and offset information to be received, and the HCI 190 can access the corresponding location of the UTP transfer request descriptor with reference to the logical unit number (LUN) and the tag (identifier) in the header (transfer information) of the RTT UPIU, and finally find the address of the data buffer and initiate data transfer.

[0206] Figure 12 is a block diagram showing the results of comparing the frequency of access to the host memory 130 according to at least some example embodiments of the inventive concept. Figure 12 An example is shown in which the host performs operations according to the packets received from the storage device.

[0207] Figure 12 An example is shown in which a packet is processed according to a general format. Referring to Figure 12 , one or more UTP transfer requests are stored in the register 111 (see Figure 2Among them, for example, the first transfer request UTP Transfer Request 0 can correspond to a data write request, and the third transfer request UTP Transfer Request 2 can correspond to a data read request. The host controller 110 can receive the RTT UPIU from the storage device 200 (see Figure 1 ) in response to the first transfer request Transfer Request 0. In addition, the host controller 110 can receive the DATA_IN UPIU from the storage device 200 in response to the third transfer request Transfer Request 2.

[0208] The packet PACKET transferred from the storage device 200 can include a header region in which header information is stored, and the header information of the RTT UPIU can include size and offset information of data to be received for the data write operation. The host controller 110 can perform a processing operation by using at least some data values in the header information of the RTT UPIU. For example, the host controller 110 accesses the host memory 130 by referring to the LUN and tag information in the header information of the RTT UPIU to identify a corresponding UTP transfer request descriptor. In addition, the host controller 110 accesses the host memory 130 at a location determined by the UTP transfer request descriptor, thereby identifying PRDT information. In addition, the host controller 110 can access a data buffer by the identified PRDT information (e.g., buffer address), and transfer data stored in the data buffer to the storage device 200.

[0209] Upon receipt of the DATA_IN UPIU, the host controller 110 can access the host controller 130 to identify a corresponding UTP transfer request descriptor from the header information of the DATA_IN UPIU, and can access the host memory 130 to identify PRDT information corresponding thereto. In addition, read data contained in the DATA_IN UPIU can be stored into a data buffer corresponding to the identified PRDT information.

[0210] Figure 13 is a diagram of an embodiment example of a data read operation and a packet according to the UFS interface.

[0211] Referring to Figure 13, the command UPIU for the data read request CMD UPIU can be transmitted from the host device 100 to the storage device 200, and a buffer address (or a physical address (PA) of a data buffer) can be included in the command UPIU for the data read request CMD UPIU. The storage device 200 can read data from the memory core in response to the command UPIU for the data read request, and can transmit a DATA_IN UPIU including the read data along with a physical address (PA) resolved from the command UPIU to the host. Further, the storage device 200 can transmit a response UPIU indicating that the operation corresponding to the command UPIU is completed to the host device 100. According to the above-described embodiment, the host device 100 can store the read data into the data buffer having a location indicated by the physical address PA resolved from the DATA_IN UPIU. The packet structure of the above-stated command UPIU and DATA_IN UPIU can be embodied as shown in Figure 14A and Figure 14B

[0212] Figure 14A and Figure 14B are illustrations of the structure of packets according to at least some exemplary embodiments of the inventive concept.

[0213] Figure 14A Figure 14B shows an example in which a buffer address is included into an existing header area; Figure 14A shows the structure of a command UPIU, and Figure 14B shows the structure of a DATA_IN UPIU.

[0214] Referring to Figure 14A , the header area of the command UPIU includes a reserved area, and a buffer address and its information according to at least some exemplary embodiments of the inventive concept can be included into some of the reserved area. For example, in addition to a host memory buffer address included in the reserved area, an information CWA indicating a buffer address is included into the CMD UPIU, and an information indicating the size of the area into which the buffer address is stored (or the size of the area into which the buffer address and its information are stored) can be further included into the reserved area.

[0215] The configuration of the command packet PACKET_C transmitted from the host device 100 adopting the UFS protocol to the storage device 200 can include an SQ identification SQ_ID, a CQ identification CQ_ID, and a response credit CR_RESP.

[0216] ​​The SQ identification SQ_ID indicating which SQ the command is related to among the plurality of SQs and the CQ identification CQ_ID indicating which CQ the command is related to among the plurality of CQs are transmitted from the host device 100 to the storage device 200.

[0217] In an exemplary embodiment, the initialization of the host device 100 can be performed by using a reservation command.

[0218] Referring to FIG. 14, the DATA_IN UPIU can include a payload area including a header area and a data area, and the header area can include a reserved area. In addition, the buffer address of the host memory 130 and information thereof can be contained into at least some of the reserved area.

[0219] The response packet PACKET_R transmitted from the storage device 200 adopting the UFS protocol to the host device 100 can include the SQ identification SQ_ID, the CQ identification CQ_ID, and the command credit CR_CMD.

[0220] The information contained in the reserved area shown in Figure 14B is the same as or similar to the example in Figure 14A , and thus a detailed description thereof will be omitted.

[0221] Figure 15 is a diagram of a system 1000 to which a storage device according to at least one exemplary embodiment of the present inventive concept is applied. Figure 15 The system 1000 of Figure 15 may be basically a mobile system such as a portable communication terminal (for example, a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a care device, or an Internet of Things (IOT) device. However,

[0222] Referring to Figure 15 , the system 1000 can include a main processor 1100, a memory (for example, 1200a and 1200b), and a storage device (for example, 1300a and 1300b). In addition, the system 1000 can include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0223] The main processor 1100 can control all operations of the system 1000, and more particularly, can control operations of other components contained in the system 1000. The main processor 1100 can be embodied as a general-purpose processor, a special-purpose processor, or an application processor.

[0224] The main processor 1100 can include at least one CPU core 1110 and further include a controller 1120 configured to control the memories 1200a and 1200b and / or the storage devices 1300a and 1300b. In some embodiments, the main processor 1100 can further include an accelerator 1130, which is a special-purpose circuit for high-speed data operations (e.g., artificial intelligence (AI) data operations). The accelerator 1130 can include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and can be embodied as a chip physically separated from other components of the main processor 1100.

[0225] The memories 1200a and 1200b can be used as main memory devices in the system 1000. Although each of the memories 1200a and 1200b can include a volatile memory such as a static random access memory (SRAM) and / or a dynamic RAM (DRAM), each of the memories 1200a and 1200b can include a non-volatile memory such as a flash memory, a phase change RAM (PRAM), and / or a resistive RAM (RRAM). The memories 1200a and 1200b can be embodied within the same package as the main processor 1100.

[0226] The storage devices 1300a and 1300b can function as non-volatile storage devices configured to store data regardless of whether power is supplied thereto and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b can include storage controllers (STRG CTRL) 1310a and 1310b and NVMs (non-volatile memories) 1320a and 1320b configured to store data under the control of the storage controllers 1310a and 1310b, respectively. Although the NVMs 1320a and 1320b can include a flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 1320a and 1320b can include other types of NVMs such as PRAM and / or RRAM.

[0227] The storage 1300a and 1300b can be physically separated from the main processor 1100 and included in the system 1000, or embodied in the same package as the main processor 1100. Also, the storage 1300a and 1300b can have a type of a solid state device (SSD) or a memory card, and combined with other components of the system 1000 in a removable manner through an interface, which can be a connection interface 1480 as described below. The storage 1300a and 1300b can be devices that apply a standard protocol such as Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC), or Non-Volatile Memory Express (NVMe), but are not limited thereto.

[0228] The image capture device 1410 can capture still images or moving images. The image capture device 1410 can include a camera, a camcorder, and / or a webcam.

[0229] The user input device 1420 can receive various types of data of a user input of the system 1000, and can include a touchpad, a keypad, a keyboard, a mouse, and / or a microphone.

[0230] The sensor 1430 can detect various types of physical quantities that can be obtained from the outside of the system 1000, and convert the detected physical quantities into electrical signals. The sensor 1430 can include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biological sensor, and / or a gyro sensor.

[0231] The communication device 1440 can transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 can include an antenna, a transceiver, and / or a modem.

[0232] The display 1450 and the speaker 1460 can function as output devices configured to output visual information and auditory information, respectively, to a user of the system 1000.

[0233] The power supply device 1470 can appropriately convert power from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each of the components of the system 1000.

[0234] The connection interface 1480 can provide a connection between the system 1000 and an external device connected to the system 1000 and capable of transmitting data to and receiving data from the system 1000. The connection interface 1480 can be embodied by using various interface schemes such as an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer small interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), a high-speed PCI (PCIe), an NVMe, an IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multimedia card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

[0235] Figure 16 is a diagram of a UFS system 2000 according to an embodiment. The UFS system 2000 can be a system conforming to a UFS standard published by the Joint Electron Device Engineering Council (JEDEC), and include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. The above description of the system 1000 of Figure 1 may also apply to the UFS system 2000 of Figure 16 without conflicting with the description below of the UFS system 2000 of Figure 16 .

[0236] Referring to Figure 16 , the UFS host 2100 can be connected to the UFS device 2200 through the UFS interface 2300. When the main processor 1100 of the system 1000 of Figure 1 is an AP, the UFS host 2100 can be embodied as a part of the AP. The UFS host controller 2110 and the host memory 2140 can correspond to the controller 1120 and the memories 1200a and 1200b of the main processor 1100 of Figure 1 , respectively. The UFS device 2200 can correspond to the storage devices 1300a and 1300b of Figure 1 , and the UFS device controller 2210 and the NVM 2220 can correspond to the storage controllers 1310a and 1310b and the NVMs 1320a and 1320b of Figure 1 , respectively.

[0237] The UFS host 2100 can include a UFS host controller 2110, an application 2120, a UFS driver 2130, a host memory 2140, and a UFS interconnect (UIC) layer 2150. The UFS device 2200 can include a UFS device controller 2210, an NVM 2220, a storage interface 2230, a device memory 2240, a UIC layer 2250, and a voltage regulator 2260. The NVM 2220 can include a plurality of memory units 2221. Although each of the memory units 2221 can include a V-NAND flash memory having a 2D structure or a 3D structure, each of the memory units 2221 can include other kinds of NVM such as PRAM and / or RRAM. The UFS device controller 2210 can be connected to the NVM 2220 through the storage interface 2230. The storage interface 2230 can be configured to comply with a standard protocol such as Toggle or ONFI.

[0238] The application 2120 can refer to a program that wants to communicate with the UFS device 2200 to use a function of the UFS device 2200. The application 2120 can transfer an input-output request (IOR) to the UFS driver 2130 to implement an input / output (I / O) operation on the UFS device 2200. The IOR can refer to a data read request, a data store (or write) request, and / or a data erase (or discard) request, but is not limited thereto.

[0239] The UFS driver 2130 can manage the UFS host controller 2110 through a UFS host controller interface (UFS-HCI). The UFS driver 2130 can convert an IOR generated by the application 2120 into a UFS command defined by a UFS standard, and transfer the UFS command to the UFS host controller 2110. One IOR can be converted into a plurality of UFS commands. Although the UFS command can be basically defined by a SCSI standard, the UFS command can be a command dedicated to the UFS standard.

[0240] The UFS host controller 2110 can transfer the UFS command converted by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 through the UIC layer 2150 and the UFS interface 2300. The UFS host register 2111 of the UFS host controller 2110 can function as a command queue (CQ) during the transmission of the UFS command.

[0241] The UIC layer 2150 on the side of the UFS host 2100 can include a Mobile Industry Processor Interface (MIPI) M-PHY 2151 and a MIPI UniPro 2152, and the UIC layer 2250 on the side of the UFS device 2200 can also include a MIPI M-PHY 2251 and a MIPI UniPro 2252.

[0242] The UFS interface 2300 can include a line configured to transfer a reference clock signal REF_CLK, a line configured to transfer a hardware reset signal RESET_n for the UFS device 2200, a pair of lines configured to transfer a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transfer a pair of differential output signals DOUT_t and DOUT_c.

[0243] The frequency of the reference clock signal provided from the UFS host 2100 to the UFS device 2200 can be one of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 2100 can change the frequency of the reference clock signal REF_CLK during operation, that is, during a data transmission / reception operation between the UFS host 2100 and the UFS device 2200. The UFS device 2200 can generate clock signals having various frequencies from the reference clock signal REF_CLK provided from the UFS host 2100 by using a phase-locked loop (PLL). Also, the UFS host 2100 can set a data rate between the UFS host 2100 and the UFS device 2200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate can be determined in accordance with the frequency of the reference clock signal REF_CLK.

[0244] The UFS interface 2300 can support a plurality of lanes, each of which can be embodied as a pair of differential lines. For example, the UFS interface 2300 can include at least one reception lane and at least one transmission lane. In Figure 16 The pair of lines configured to transfer a pair of differential input signals DIN_T and DIN_C can constitute a reception lane, and the pair of lines configured to transfer a pair of differential output signals DOUT_T and DOUT_C can constitute a transmission lane. Although one transmission lane and one reception lane are illustrated in Figure 16 The number of transmission lanes and the number of reception lanes can be changed.

[0245] The receive channel and the transmit channel can transfer data based on a serial communication scheme. Due to the structure of the receive channel and the transmit channel being separate, full-duplex communication can be enabled between the UFS host 2100 and the UFS device 2200. That is, while data is being received from the UFS host 2100 through the receive channel, the UFS device 2200 can transfer data to the UFS host 2100 through the transmit channel. Also, control data (e.g., commands) from the UFS host 2100 to the UFS device 2200 and user data to be stored by the UFS host 2100 to or read from the NVM 2220 of the UFS device 2200 can be transferred through the same channel. Therefore, between the UFS host 2100 and the UFS device 2200, it can not be necessary to further provide separate channels for data transfer in addition to a pair of receive channels and a pair of transmit channels.

[0246] The UFS device controller 2210 of the UFS device 2200 can control all operations of the UFS device 2200. The UFS device controller 2210 can manage the NVM 2220 by using logical units (LUs) 2211 as logical data storage units. The number of the LUs 2211 can be 8, but is not limited thereto. The UFS device controller 2210 can include an FTL, and convert a logical data address (e.g., a logical block address (LBA)) received from the UFS host 2100 into a physical data address (e.g., a physical block address (PBA)) by using address mapping information of the FTL. A logical block configured to store user data into the UFS system 2000 can have a size within an expected or predetermined range. For example, according to at least some example embodiments of the present inventive concepts, the minimum size of the logical block can be set to 4 Kbytes. However, at least some example embodiments are not limited to this example. For example, the minimum size of the logical block can be set to a value other than 4 Kbytes, e.g., the setting can be according to the preference of a user or designer of the UFS system 2000 or elements thereof.

[0247] Upon a command from the UFS host 2100 being applied to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform an operation in response to the command, and transfer a completion response to the UFS host 2100 upon completion of the operation.

[0248] As an example, when the UFS host 2100 intends to store user data into the UFS device 2200, the UFS host 2100 can transmit a data store command to the UFS device 2200. Upon receiving a response from the UFS device 2200 indicating that the UFS host 2100 is ready to receive user data (transmit ready), the UFS host 2100 can transmit user data to the UFS device 2200. The UFS device controller 2210 can temporarily store the received user data in the device memory 2240 and store the user data temporarily stored in the device memory 2240 to selected locations of the NVM 2220 based on the FTL's address mapping information.

[0249] As another example, when the UFS host 2100 intends to read user data stored in the UFS device 2200, the UFS host 2100 can transmit a data read command to the UFS device 2200. The UFS device controller 2210 having received the command can read user data from the NVM 2220 based on the data read command and temporarily store the user data in the device memory 2240. During the read operation, the UFS device controller 2210 can detect and correct errors in the read user data by using an ECC engine (not shown) embedded therein. More specifically, the ECC engine can generate parity bits for write data to be written into the NVM 2220 and the generated parity bits can be stored into the NVM 2220 along with the write data. During the read of data from the NVM 2220, the ECC engine can correct errors in the read data by using the parity bits read from the NVM 2220 along with the read data and output the error-corrected read data.

[0250] Further, the UFS device controller 2210 can transmit the user data temporarily stored in the device memory 2240 to the UFS host 2100. Further, the UFS device controller 2210 can further include an AES engine (not shown). The AES engine can perform at least one of an encryption operation and a decryption operation on data transmitted to the UFS device controller 2210 by using a symmetric key algorithm.

[0251] The UFS host 2100 can store a command sequence to be transferred to the UFS device 2200 into a UFS host register 2111 which can function as a common queue, and transfer the command sequence to the UFS device 2200. In this case, the UFS host 2100 can transfer a next command pending in the CQ to the UFS device 2200 even while a previously transferred command is still being processed by the UFS device 2200, that is, even before receiving a notification that the previously transferred command has been processed by the UFS device 2200. Thus, the UFS device 2200 can also receive a next command from the UFS host 2100 during processing of a previously transferred command. According to at least some example embodiments of the present inventive concepts, the maximum number of commands (or queue depth) that can be stored into the CQ can be, for example, 32. However, at least some example embodiments are not limited to this example. For example, the maximum number of commands (or queue depth) that can be stored in the CQ can be other than 32, for example, it can be according to the preference of a user or designer of the UFS system 2000 or elements thereof. Also, the CQ can be embodied as a circular queue in which the beginning and end of a command line stored in the queue are represented by a head pointer and a tail pointer.

[0252] Each of the plurality of memory cells 2221 can include a memory cell array (not shown) and a control circuit (not shown) configured to control operations of the memory cell array. The memory cell array can include a 2D memory cell array or a 3D memory cell array. The memory cell array can include a plurality of memory cells. Although each of the memory cells is configured as a single-level cell (SLC) that stores 1-bit information, each of the memory cells can be a cell configured to store 2-bit or more information, such as a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC). The 3D memory cell array can include a vertical NAND string in which at least one memory cell has a vertical orientation and is located on another memory cell.

[0253] The voltages VCC, VCCQ, and VCCQ2 can be applied to the UFS device 2200 as power supply voltages. The voltage VCC can be a main power supply voltage for the UFS device 2200 and be in a range of 2.4V to 3.6V. The voltage VCCQ can be a power supply voltage for mainly supplying a low voltage to the UFS device controller 2210 and can be in a range of 1.14V to 1.26V. The voltage VCCQ2 can be a power supply voltage for mainly supplying a voltage lower than the voltage VCC and higher than the voltage VCCQ to the I / O interface (e.g., the MIPI M-PHY 2251) and can be in a range of 1.7V to 1.95V. These power supply voltages can be supplied to the respective components of the UFS device 2200 through a voltage regulator 2260. The voltage regulator 2260 can be embodied as a set of unit voltage regulators connected to different ones of the above-described power supply voltages, respectively.

[0254] Figures 17A to 17C is an illustration of the size and shape of a UFS automobile. When referring to Figure 16 the UFS device 2200 described above is embodied as a UFS card 4000, the appearance of the UFS card 4000 can be as shown in Figures 17A to 17C

[0255] Figure 17A is a top view of the UFS card 4000 according to an exemplary embodiment. Referring to Figure 17A , it can be seen that the UFS card 4000 completely follows a shark shape design. In Figure 17A , the UFS card 4000 can have the outer shape dimensions shown below in Table 1 as an example.

[0256] [Table 1]

[0257] Item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0258] Figure 17B is a side view of the UFS card 4000 according to an exemplary embodiment. In Figure 17B , the UFS card 4000 can have the outer shape dimensions shown below in Table 2 as an example.

[0259] [Table 2]

[0260] Item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

[0261] Figure 17C is a bottom view of the UFS card 4000 according to an exemplary embodiment. Referring to Figure 17C , a plurality of pins for electrical contact with a UFS slot can be formed on the bottom surface of the UFS card 4000. The function of each of the pins will be described below. Based on the symmetry between the top surface and the bottom surface of the UFS card 4000, the description of the pins will be made with reference to Figure 17A ​Some information on the outer dimensions described in Table 1 (e.g., T1 to T5 and T9) can also apply to Figure 17C a bottom view of the UFS card 4000 shown in FIG. 4B.

[0262] A plurality of pins for electrical connection with a UFS host can be formed on a bottom surface of the UFS card 4000. Referring to Figure 17C , the total number of pins can be 12. Each of the pins can have a rectangular shape, and signal names corresponding to the pins can be as shown in Figure 17C . Detailed information on each of the pins will be understood with reference to Table 3 below and the description provided above with reference to Figure 16 .

[0263] [Table 3]

[0264]

[0265] Figure 18A is a block diagram of a host storage system 10 according to an exemplary embodiment, and Figures 18B to 18E is a detailed block diagram of elements of Figure 18A .

[0266] The host storage system 10 can include a host 100 and a storage device 200. Further, the storage device 200 can include a storage controller 210 and an NVM 220. According to an exemplary embodiment, the host 100 can include a host controller 110 and a host memory 130. The host memory 130 can function as a buffer memory configured to temporarily store data to be transferred to the storage device 200 or data received from the storage device 200.

[0267] The storage device 200 can include a storage medium configured to store data in response to a request from the host 100. As an example, the storage device 200 can include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 can be a device conforming to the NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 can be a device conforming to the UFS standard or the eMMC standard. Each of the host 100 and the storage device 200 can generate and transfer packets according to a standard protocol adopted.

[0268] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory can include a 3D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 can include other various NVMs. For example, the storage device 200 can include a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive-bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and other various memories.

[0269] According to embodiments, the host controller 110 and the host memory 130 can be embodied as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 130 can be integrated within the same semiconductor chip. As an example, the host controller 110 can be any one of a plurality of modules included in an application processor (AP). The AP can be embodied as a system on chip (SoC). Further, the host memory 130 can be an embedded memory included within the AP, or can be an NVM or a memory module located outside the AP.

[0270] The host controller 110 can manage an operation of storing data (e.g., write data) of a buffer region of the host memory 130 into the NVM 220 or an operation of storing data (e.g., read data) of the NVM 220 into the buffer region.

[0271] The storage controller 210 can include a host interface 211, a memory interface 216, and a CPU 212. Further, the storage controller 210 can further include a flash translation layer (FTL) 213, a packet manager 214, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218. The storage controller 210 can further include a working memory (not shown) into which the FTL 213 is loaded. The CPU 212 can execute the FTL 213 to control data write and read operations to the NVM 220.

[0272] The host interface 211 can transmit and receive packets to and from the host 100. Packets transmitted from the host 100 to the host interface 211 can include commands or data to be written to the NVM 220. Packets transmitted from the host interface 211 to the host 100 can include responses to the commands or data read from the NVM 220. The memory interface 216 can transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 216 can be configured to comply with a standard protocol, such as Toggle or Open NAND Flash Interface (ONFI).

[0273] The FTL 213 can perform various functions such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation can be an operation of converting a logical address received from the host 100 into a physical address used to actually store data in the NVM 220. The wear leveling operation can be a technique of preventing a specific block from being excessively deteriorated by allowing the blocks of the NVM 220 to be uniformly used. As an example, the wear leveling operation can be embodied using a firmware technique of leveling the erase counts of the physical blocks. The garbage collection operation can be a technique of securing available capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0274] The packet manager 215 can generate a packet according to a protocol of the interface agreed upon by the interface 100, or parse various types of information from a packet received from the host 100. Further, the buffer memory 216 can temporarily store data to be written to the NVM 220 or data to be read from the NVM 220. Although the buffer memory 216 can be a component included in the storage controller 210, the buffer memory 216 can be external to the storage controller 210.

[0275] The ECC engine 217 can perform an error detection and correction operation on read data read from the NVM 220. More specifically, the ECC engine 217 can generate parity bits for write data to be written into the NVM 220, and the generated parity bits can be stored into the NVM 220 along with the write data. During reading of data from the NVM 220, the ECC engine 217 can correct errors in the read data by using the parity bits read from the NVM 220 along with the read data, and output the error-corrected read data.

[0276] The AES engine 218 can perform at least one of an encryption operation and a decryption operation on data input to the storage controller 210 by using a symmetric key algorithm.

[0277] Figure 18B is Figure 18A a detailed diagram of the ECC engine 217. Referring to Figure 18BECC engine 217 can include ECC encoding circuit 510 and ECC decoding circuit 520. In response to ECC control signal ECC CON, ECC encoding circuit 510 can generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells of memory cell array 221. Parity bits ECCP[0:7] can be stored within ECC cell array 223. According to an embodiment, in response to ECC control signal ECC CON, ECC encoding circuit 510 can generate parity bits ECCP[0:7] for write data WData[0:63] to be stored within memory cells of memory cell array 221 that include defective cells.

[0278] In response to ECC control signal ECC CON, ECC decoding circuit 520 can correct error bit data using read data RData[0:63] read from memory cells of memory cell array 221 and parity bits ECCP[0:7] read from ECC cell array 223, and output error corrected data Data[0:63]. According to an embodiment, in response to ECC control signal ECC CON, ECC decoding circuit 520 can correct error bit data using read data RData[0:63] read from memory cells of memory cell array 221 that include defective cells and parity bits ECCP[0:7] read from ECC cell array 223, and output error corrected data Data[0:63].

[0279] Figure 18C is a diagram of ECC encoding circuit 510 of Figure 18B

[0280] Referring to Figure 18C ECC encoding circuit 510 can include parity generator 511 that receives 64-bit write data WData[0:63] and base bits B[0:7] in response to ECC control signal ECC CON, and generates parity bits ECCP[0:7] using XOR array operations. Base bits B[0:7] can be bits used to generate parity bits ECCP[0:7] for 64-bit write data WData[0:63], e.g., b'00000000 bits. Base bits B[0:7] can use other specific bits instead of b'00000000 bits.

[0281] Figure 18D is a diagram of ECC decoding circuit 520 of Figure 18B

[0282] Referring to Figure 18D ​​The ECC decoding circuit 520 may include a corrector generator 521, a coefficient calculator 522, a 1-bit error location detector 523, and an error corrector 524. The corrector generator 521 can receive 64 bits of read data and 8 parity bits ECCP[0:7] in response to the ECC control signal ECC_CON, and generate corrector data S[0:7] using an XOR array operation. The coefficient calculator 522 can calculate the coefficients of the error location equation using the corrector data S[0:7]. The error location equation can be an equation rooted at the reciprocal of the error bit. The 1-bit error location detector 523 can calculate the location of a 1-bit error using the calculated error location equation. The error corrector 524 can determine the location of a 1-bit error based on the detection result of the 1-bit error location detector 523. Error corrector 524 can correct errors by inverting the logic values ​​of the erroneous bits in the 64-bit read data RData[0:63] based on the determined 1-bit error location information, and output the corrected 64-bit data Data[0:63].

[0283] Figure 18E yes Figure 18A Detailed illustration of the AES engine 218. The AES engine 218 can encrypt and decrypt data using the AES algorithm, and may include an encryption module 218a and a decryption module 218b. Although Figure 18E The illustration shows the case where encryption module 218a and decryption module 218b are implemented as separate modules. However, in another case, a module capable of performing both encryption and decryption operations can be implemented within the AES engine 218. The buffer memory 216 can be a volatile memory acting as a buffer, or it can be an NVM.

[0284] The AES engine 218 can receive first data transmitted from the buffer memory 216. The encryption module 218a can encrypt the first data transmitted from the buffer memory 216 using an encryption key and generate second data. The second data can be transmitted from the AES engine 218 to the buffer memory 216 and stored in the buffer memory 216.

[0285] Furthermore, the AES engine 218 can receive third data transmitted from the buffer memory 216. The third data can be data encrypted using the same encryption key used to encrypt the first data. The decryption module 218b can decrypt the third data transmitted from the buffer memory 216 using the same encryption key used to encrypt the first data, and generate fourth data. The fourth data can be transmitted from the AES engine 218 to the buffer memory 216 and stored therein.

[0286] Figure 19 is a block diagram of a memory system 15 according to an embodiment. Referring to Figure 19 , the memory system 15 can include a memory device 17 and a memory controller 16. The memory system 15 can support a plurality of channels CH1 to CHm, and the memory device 17 can be connected to the memory controller 16 through the plurality of channels CH1 to CHm. For example, the memory system 15 can be embodied as a storage device, e.g., an SSD.

[0287] The memory device 17 can include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm, the connection being implemented through a passway corresponding thereto. For example, the NVM devices NVM11 to NVM1n can be connected to the first channel CH1 through passways W11 to W1n, and the NVM devices NVM21 to NVM2n can be connected to the second channel CH2 through passways W21 to W2n. In an exemplary embodiment, each of the NVM devices NVM11 to NVMmn can be embodied as any memory unit that can operate according to a separate command from the memory controller 16. For example, each of the NVM devices NVM11 to NVMmn can be embodied as a chip or a die, although at least some exemplary embodiments of the inventive concept are not limited thereto.

[0288] The memory controller 16 can transmit and receive signals to and from the memory device 17 through the plurality of channels CH1 to CHm. For example, the memory controller 16 can transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17, or receive data DATAa to DATAm from the memory device 17 through the channels CH1 to CHm.

[0289] The memory controller 16 can select one of the NVM devices NVM11 to NVMmn connected to each of the channels CH1 to CHm by using a corresponding one of the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller 16 can select the NVM device NVM11 from the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 can transmit a command CMDa, an address ADDRa, and data DATAa to the selected NVM device NVM11, or receive data DATAa from the selected NVM device NVM11 through the first channel CH1.

[0290] The memory controller 16 can transmit and receive signals to and from the memory device 17 in parallel through different channels. For example, the memory controller 16 can transmit a command CMDb to the memory device 17 through the second channel CH2 while transmitting a command CMDa to the memory device 17 through the first channel CH1. For example, the memory controller 16 can receive data DATAb from the memory device 17 through the second channel CH2 while receiving data DATAa from the memory device 17 through the first channel CH1.

[0291] The memory controller 16 can control all operations of the memory device 17. The memory controller 16 can transmit signals to the channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 16 can transmit a command CMDa and an address ADDRa to the first channel CH1 and control a selected one of the NVM devices NVM11 to NVM1n based on the command CMDa and the address ADDRa.

[0292] Each of the NVM devices NVM11 to NVMmn can operate via control of the memory controller 16. For example, the NVM device NVM11 can program data DATAa based on the command CMDa, the address ADDRa, and the data DATAa to be provided to the first channel CH1. For example, the NVM device NVM21 can read data DATAb based on a second command CMDb and an address ADDRb provided to the second channel CH2 and transmit the read data DATAb to the memory controller 16.

[0293] Although Figure 19 An example is shown in which the memory device 17 communicates with the memory controller 16 through m channels and includes NVM devices corresponding to each of the channels, but there can be various variations in the number of channels and the number of NVM devices connected to each channel.

[0294] Figure 20 is a block diagram of a memory system according to an embodiment. Referring to Figure 20 , the memory system can include a memory device 300 and a memory controller 400. The above description of the storage device 200 Figure 1 may be applicable to the memory system of Figure 20 The memory device 300 can correspond to one of the NVM devices NVM11 to NVMmn, which communicates with the memory controller 400 based on one of the multiple channels CH1 to CHm of Figure 19 The memory controller 400 can correspond to the memory controller 16 of Figure 19

[0295] ​The memory device 300 can include first through eighth pins P11 through P18, a memory interface circuit 310, a control logic circuit 320, and a memory cell array 330.

[0296] The memory interface circuit 310 can receive a chip enable signal nCE from the memory controller 400 through the first pin P11. The memory interface circuit 310 can transmit and receive signals to and from the memory controller 400 through the second through eighth pins P12 through P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit 310 can transmit and receive signals to and from the memory controller 400 through the second through eighth pins P12 through P18.

[0297] The memory interface circuit 310 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 400 through the second through fourth pins P12 through P14. The memory interface circuit 310 can receive data signals DQ from or transmit the data signals DQ to the memory controller 400 through the seventh pin P17. Commands CMD, addresses ADDR, and data can be transmitted via the data signals DQ. For example, the data signals DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 can include a plurality of pins corresponding to the plurality of data signals DQ, respectively.

[0298] The memory interface circuit 310 can obtain a command CMD from the data signals DQ, which is received within an enabled section (e.g., a high level state) of the command latch enable signal CLE based on a toggle point of the write enable signal nWE. The memory interface circuit 310 can further obtain an address ADDR from the data signals DQ, which is received within an enabled section (e.g., a high level state) of the address latch enable signal CLE based on a toggle point of the write enable signal nWE.

[0299] In an exemplary embodiment, the write enable signal nWE can be held on a static state (e.g., a high level or a low level) and toggled between the high level and the low level. For example, the write enable signal nWE can be toggled within a section in which a command CMD or an address ADDR is transmitted. Thus, the memory interface circuit 310 can obtain the command CMD or the address ADDR based on a toggle point of the write enable signal nWE.

[0300] The memory interface circuit 310 can receive a read enable signal nRE from the memory controller 400 through the fifth pin P15. The memory interface circuit 310 can receive or transmit a data strobe signal DQS to / from the memory controller 400 through the sixth pin P16.

[0301] In a data (DATA) output operation of the memory device 300, the memory interface circuit 310 can receive a read enable signal nRE before outputting data DATA, the read enable signal nRE toggled through the fifth pin P15. The memory interface circuit 310 can generate a data strobe signal DQS toggled based on the toggling of the read enable signal nRE. For example, the memory interface circuit 310 can generate the data strobe signal DQS toggled starting after an intended or predetermined delay (e.g., tDQSRE) based on a toggling start time of the read enable signal nRE. The memory interface circuit 310 can transmit data signals DQ including the data DATA based on a toggling time point of the data strobe signal DQS. Thus, the data DATA can be aligned with the toggling time point of the data strobe signal DQS and transmitted to the memory controller 400.

[0302] In a data (DATA) input operation of the memory device 300, the memory interface circuit 310 can receive a toggled data strobe signal DQS along with the data DATA from the memory controller 400 when data signals DQ including the data DATA are received from the memory controller 400. The memory interface circuit 310 can obtain the data DATA from the data signals DQ based on a toggling time point of the data strobe signal DQS. For example, the memory interface circuit 310 can sample the data signals DQ on rising and falling edges of the data strobe signal DQS and obtain the data DATA.

[0303] The memory interface circuit 310 can transmit a ready / busy output signal nR / B to the memory controller 400 through the eighth pin P18. The memory interface circuit 310 can transmit the status information of the memory device 300 to the memory controller 400 through the ready / busy output signal nR / B. When the memory device 300 is in a busy state (i.e., when an operation is being performed in the memory device 300), the memory interface circuit 310 can transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when an operation is not being performed in the memory device 300 or has been completed), the memory interface circuit 310 can transmit the ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, while the memory device 300 is reading data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 can transmit the ready / busy output signal nR / B indicating the busy state (e.g., a low level) to the memory controller 400. For example, while the memory device 300 is programming data DATA to the memory cell array 330 in response to a program command, the memory interface circuit 310 can transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 400.

[0304] The control logic circuit 320 can control all operations of the memory device 300. The control logic circuit 320 can receive the command / address CMD / ADDR obtained from the memory interface circuit 310. The control logic circuit 320 can generate control signals for controlling other components of the memory device 300 in response to the received command / address CMD / ADDR. For example, the control logic circuit 320 can generate various control signals for programming data DATA to the memory cell array 330 or reading data DATA from the memory cell array 330.

[0305] The memory cell array 330 can store data DATA obtained from the memory interface circuit 310 via control of the control logic circuit 320. The memory cell array 330 can output the stored data to the memory interface circuit 310 via control of the control logic circuit 320.

[0306] The memory cell array 330 can include a plurality of memory cells. For example, the plurality of memory cells can be flash memory cells. However, at least some exemplary embodiments of the inventive concepts are not limited thereto, and the memory cells can be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Embodiments in which the memory cells are NAND flash memory cells will be described hereinafter.

[0307] The memory controller 400 can include first through eighth pins P21 through P28 and a controller interface circuit 410. The first through eighth pins P21 through P28 can correspond to the first through eighth pins P11 through P18 of the memory device 300, respectively.

[0308] The controller interface circuit 410 can transmit a chip enable signal nCE to the memory device 300 through the first pin P21. The controller interface circuit 410 can transmit and receive signals to and from the memory device 300 selected by the chip enable signal nCE through the second through eighth pins P22 through P28

[0309] The controller interface circuit 410 can transmit a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 300 through the second through fourth pins P22 through P24. The controller interface circuit 410 can transmit and receive a data signal DQ to and from the memory device 300 through the seventh pin P27.

[0310] The controller interface circuit 410 can transmit the data signal DQ including a command CMD or an address ADDR to the memory device 300 along with a toggled write enable signal nWE. The controller interface circuit 410 can transmit the data signal DQ including the command CMD to the memory device 300 by transmitting the command latch enable signal CLE having an enable state. Also, the controller interface circuit 410 can transmit the data signal DQ including the address ADDR to the memory device 300 by transmitting the address latch enable signal ALE having an enable state.

[0311] The controller interface circuit 410 can transmit a read enable signal nRE to the memory device 300 through the fifth pin P25. The controller interface circuit 410 can receive and transmit a data strobe signal DQS to and from the memory device 300 through the sixth pin P26.

[0312] In a data (DATA) output operation of the memory device 300, the controller interface circuit 410 can generate a toggled read enable signal nRE and transmit the read enable signal nRE to the memory device 300. For example, the controller interface circuit 410 can generate the read enable signal nRE changing from a static state (e.g., a high level or a low level) to a toggled state before outputting the data DATA. Accordingly, the memory device 300 can generate a toggled data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 410 can receive the data signal DQ including the data DATA along with the data strobe signal DQS from the memory device 300. The controller interface circuit 410 can obtain the data DATA from the data signal DQ based on a toggling point of the data strobe signal DQS.

[0313] In a data (DATA) input operation of the memory device 300, the controller interface circuit 410 can generate a toggled data strobe signal DQS. For example, before transferring data DATA, the controller interface circuit 410 can generate the data strobe signal DQS from a static state (e.g., a high level or a low level) to a toggled state. The controller interface circuit 410 can transfer a data signal DQ including the data DATA to the memory device 300 based on a toggling point of time of the data strobe signal DQS.

[0314] The controller interface circuit 410 can receive a ready / busy output signal nR / B from the memory device 300 through the eighth pin P28. The controller interface circuit 410 can determine a state of the memory device 300 based on the ready / busy output signal nR / B.

[0315] Figure 21 is a block diagram of a memory device 300 according to an exemplary embodiment. Referring to Figure 21 , the memory device 300 can include a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. Although Figure 21 is not shown in the memory device 300, the memory device 300 can further include Figure 21 the memory interface circuit 310 shown in the memory device 300. In addition, the memory device 300 can further include column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder.

[0316] The control logic circuit 320 can control various operations of the memory device 300. The control logic circuit 320 can output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit 310. For example, the control logic circuit 320 can output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0317] The memory cell array 330 can include a plurality of memory blocks BLK1 to BLKz (here, z is a positive integer), each of which can include a plurality of memory cells. The memory cell array 330 can be connected to the page buffer 340 through a bit line BL and to the row decoder 360 through a word line WL, a string selection line SSL, and a ground selection line GSL.

[0318] In an exemplary embodiment, the memory cell array 330 can include a 3D memory cell array including a plurality of NAND strings. Each of the NAND strings can include memory cells respectively connected to word lines disposed perpendicularly stacked on a substrate. The disclosures of U.S. Patent Nos. 7679133, 8553466, 8654587, 8559235, and U.S. Patent Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array 330 can include a 2D memory cell array including a plurality of NAND strings arranged in a row direction and a column direction.

[0319] The page buffer 340 can include a plurality of page buffers PB1 to PBn (here, n is a positive integer greater than or equal to 3) which can be respectively connected to the memory cells through a plurality of bit lines BL. The page buffer 340 can select at least one of the bit lines BL in response to a column address Y-ADDR. The page buffer 340 can operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer 340 can apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 340 can sense a current or a voltage of the selected bit line BL and sense data stored in the memory cells.

[0320] The voltage generator 350 can generate various voltages for program, read, and erase operations based on a voltage control signal CTRL_vol. For example, the voltage generator 350 can generate a program voltage, a read voltage, a program verify voltage, and an erase voltage as a word line voltage VWL.

[0321] The row decoder 360 can select one of a plurality of word lines WL and select one of a plurality of string selection lines SSL in response to a row address X-ADDR. For example, the row decoder 360 can apply a program voltage and a program verify voltage to a selected word line WL during a program operation and apply a read voltage to the selected word line WL during a read operation.

[0322] Figure 22 is a diagram of a 3D V-NAND structure suitable for a UFS device according to an embodiment. When a storage module of a UFS device is embodied as a 3D V-NAND flash memory, each of a plurality of memory blocks contained within the storage module can be represented by Figure 22 the equivalent circuit shown in

[0323] Figure 22 The memory block BLKi shown in can refer to a 3D memory block having a 3D structure formed on a substrate. For example, a plurality of memory NAND strings contained in the memory block BLKi can be formed in a vertical direction with respect to the substrate.

[0324] Referring to Figure 22 , the memory block BLKi can include a plurality of memory NAND strings (e.g., NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory NAND strings NS11 to NS33 can include a string selection transistor SST, a plurality of memory cells (e.g., MC1, MC2, …, MC8), and a ground selection transistor GST. Each of the memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, …, MC8 in Figure 22 , but is not limited thereto.

[0325] The string selection transistor SST can be connected to a string selection line SSL1, SSL2, and SSL3 corresponding thereto. Each of the memory cells MC1, MC2, …, MC8 can be connected to a corresponding one of gate lines GTL1, GTL2, …, GTL8. The gate lines GTL1, GTL2, …, GTL8 can correspond to word lines, respectively, and some of the gate lines GTL1, GTL2, …, GTL8 can correspond to dummy word lines. The ground selection transistor GST can be connected to a ground selection line GSL1, GSL2, and GSL3 corresponding thereto. The string selection transistor SST can be connected to a bit line BL1, BL2, and BL3 corresponding thereto, and the ground selection transistor GST can be connected to a common source line CSL.

[0326] Word lines (e.g., WL1) of the same level can be commonly connected, and the ground selection lines GSL1, GSL2, and GSL3 and the string selection lines SSL1, SSL2, and SSL3 can be separated from each other. Figure 22 A case in which the memory block BLK is connected to eight gate lines GTL1, GTL2, …, GTL8 and three bit lines BL1, BL2, and BL3 is shown, but is not limited thereto.

[0327] Figure 23 A diagram of a memory device 600 according to another exemplary embodiment is shown. The above description of the NVM 230 of Figure 1 may apply to the memory device 600 of Figure 23 .

[0328] Referring to Figure 23The memory device 600 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting bonding metal formed on the uppermost metal layer of the upper chip to bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal may include copper (Cu), Cu-to-Cu bonding is used. However, exemplary embodiments are not limited to this. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0329] Each of the peripheral circuit area PERI and cell area CELL of the memory device 600 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0330] The Peripheral Circuit Area (PERI) may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c respectively connected to the plurality of circuit elements 720a, 720b, and 720c, and second metal layers 740a, 740b, and 740c formed on the first metal layers 730a, 730b, and 730c. In an exemplary embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 740a, 740b, and 740c may be formed of copper, which has a relatively low resistivity.

[0331] exist Figure 23 In the exemplary embodiments shown, although only the first metal layers 730a, 730b, and 730c and the second metal layers 740a, 740b, and 740c are shown and described, the exemplary embodiments are not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 740a, 740b, and 740c. At least a portion of the one or more additional metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum or the like, having a lower resistivity than those of the second metal layers 740a, 740b, and 740c.

[0332] An interlayer insulating layer 715 may be disposed on a first substrate 710 and cover a plurality of circuit elements 720a, 720b and 720c, first metal layers 730a, 730b and 730c and second metal layers 740a, 740b and 740c. The interlayer insulating layer 715 may comprise an insulating material such as silicon oxide or silicon nitride.

[0333] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b within the word line bonding area WLBA. Within the word line bonding area WLBA, the lower bonding metals 771b and 772b in the peripheral circuit region PERI can be electrically bonded to the upper bonding metals 871b and 872b of the cell region CELL. The lower bonding metals 771b and 772b and the upper bonding metals 871b and 872b can be formed of aluminum, copper, or tungsten, etc. In addition, the upper bonding metals 871b and 872b within the cell region CELL can be referred to as first metal pads, and the lower bonding metals 771b and 772b within the peripheral circuit region PERI can be referred to as second metal pads.

[0334] The cell region CELL can include at least one memory block. The cell region CELL can include a second substrate 810 and a common source line 820. On the second substrate 810, a plurality of word lines 831 to 838 (i.e., 830) can be disposed in a direction (Z-axis direction) perpendicular to an upper surface of the second substrate 810. At least one string selection line and at least one ground selection line can be arranged above and below the plurality of word lines 830, respectively, and the plurality of word lines 830 can be disposed between the at least one string selection line and the at least one ground selection line.

[0335] Within the bit line bonding area BLBA, a channel structure CH can extend in a direction (Z-axis direction) perpendicular to an upper surface of the second substrate 810, and pass through the plurality of word lines 830, the at least one string selection line, and the at least one ground selection line. The channel structure CH can include a data storage layer, a channel layer, and a buried insulating layer, etc., and the channel layer can be electrically connected to a first metal layer 850c and a second metal layer 860c. For example, the first metal layer 850c can be a bit line contact, and the second metal layer 860c can be a bit line. In an exemplary embodiment, the bit line 860c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0336] Within the bit line bonding area BLBA, a channel structure CH can extend in a direction (Z-axis direction) perpendicular to an upper surface of the second substrate 810, and pass through the plurality of word lines 830, the at least one string selection line, and the at least one ground selection line. The channel structure CH can include a data storage layer, a channel layer, and a buried insulating layer, etc., and the channel layer can be electrically connected to a first metal layer 850c and a second metal layer 860c. For example, the first metal layer 850c can be a bit line contact, and the second metal layer 860c can be a bit line. In an exemplary embodiment, the bit line 860c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810. Figure 23In the exemplary embodiment shown in FIG. 8, the region where the channel structure CH, the bit line 860c, and the like are provided can be defined as a bit line bonding region BLBA. Within the bit line bonding region BLBA, the bit line 860c can be electrically connected to the circuit element 720c that provides the page buffer 893 within the peripheral circuit region PERI. The bit line 860c can be connected to the upper bonding metals 871c and 872c within the cell region CELL, and the upper bonding metals 871c and 872c can be connected to the lower bonding metals 771c and 772c that are connected to the circuit element 720c of the page buffer 893. In the exemplary embodiment, the program operation can be performed on a page unit basis, in which case the write data of the page unit is stored in the page buffer 893, and the read operation can be performed on a sub-page unit basis, in which case the read data of the sub-page unit is stored in the page buffer 893. Also, the units of data transferred through the bit line can be different between the program operation and the read operation.

[0337] Within the word line bonding region WLBA, a plurality of word lines 830 can extend in a second direction (X-axis direction) that is parallel to the upper surface of the second substrate 810 and perpendicular to the first direction, and can be connected to a plurality of cell contact plugs 841 to 847 (i.e., 840). The plurality of word lines 830 and the plurality of cell contact plugs 840 can be connected to each other within pads provided by at least portions of the plurality of word lines 830 that extend in the second direction at different lengths. The first metal layer 850b and the second metal layer 860b can be sequentially connected to the upper portions of the plurality of cell contact plugs 840 connected to the plurality of word lines 830. The plurality of cell contact plugs 840 can be connected to the peripheral circuit region PERI through the upper bonding metals 871b and 872b of the cell region CELL within the word line bonding region WLBA and the lower bonding metals 771b and 772b of the peripheral circuit region PERI.

[0338] The plurality of cell contact plugs 840 can be electrically connected to the circuit element 720b that forms the row decoder 894 within the peripheral circuit region PERI. In the exemplary embodiment, the operating voltage of the circuit element 720b of the row decoder 894 can be different from the operating voltage of the circuit element 720c that forms the page buffer 893. For example, the operating voltage of the circuit element 720c that forms the page buffer 893 can be greater than the operating voltage of the circuit element 720b that forms the row decoder 894.

[0339] The common source line contact plug 880 can be disposed within the external pad bonding area PA. The common source line contact plug 880 can be formed of an electrically conductive material such as a metal, a metal compound, or polysilicon, and can be electrically connected to the common source line 820. The first metal layer 850a and the second metal layer 860a can be sequentially stacked on an upper portion of the common source line contact plug 880. For example, an area in which the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed can be defined as the external pad bonding area PA.

[0340] The input-output pads 705 and 805 can be disposed within the external pad bonding area PA. Referring to Figure 23 , a lower insulating film 701 covering a lower surface of the first substrate 710 can be formed below the first substrate 710, and the first input-output pad 705 can be formed on the lower insulating film 701. The first input-output pad 705 can be connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed within the peripheral circuit area PERI through a first input-output contact plug 703, and can be spaced apart from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film can be disposed between the first input-output contact plug 703 and the first substrate 710, thereby electrically isolating the first input-output contact plug 703 from the first substrate 710.

[0341] Referring to Figure 23 , an upper insulating film 801 covering an upper surface of the second substrate 810 can be formed on the second substrate 810, and the second input-output pad 805 can be disposed on the upper insulating layer 801. The second input-output pad 805 can be connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed within the peripheral circuit area PERI through a second input-output contact plug 803. In an exemplary embodiment, the second input-output pad 805 is electrically connected to the circuit element 720a.

[0342] According to an exemplary embodiment, the second substrate 810 and the common source line 820 can not be disposed within an area in which the second input-output contact plug 803 is disposed. Also, the second input-output pad 805 can not overlap the word line 830 in the third direction (Z-axis direction). Referring to Figure 23 , the second input-output contact plug 303 can be spaced apart from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810, and can pass through the interlayer insulating layer 815 of the cell area CELL, thereby being connected to the second input-output pad 805.

[0343] According to exemplary embodiments, the first input-output pad 705 and the second input-output pad 805 can be selectively formed. For example, the memory device 600 can include only the first input-output pad 705 disposed on the first substrate 710 or the second input-output pad 805 disposed on the second substrate 810. Alternatively, the memory device 600 can include both the first input-output pad 705 and the second input-output pad 805.

[0344] In each of the external pad bonding area PA and the bit line bonding area BLBA, a metal pattern provided on the uppermost metal layer can be provided as a dummy pattern or the uppermost metal layer can not exist, which is included in the cell region CELL and the peripheral circuit region PERI, respectively.

[0345] In the external pad bonding area PA, the memory device 600 can include a lower metal pattern 773a in the uppermost metal layer of the peripheral circuit region PERI, which corresponds to the upper metal pattern 872a formed in the uppermost metal layer of the cell region CELL and has the same cross-sectional shape as the upper metal pattern 872a of the cell region CELL, thereby being interconnected therewith. In the peripheral circuit region PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI can not be connected to a contact. Similarly, in the external pad bonding area PA, the upper metal pattern 872a can be formed in the uppermost metal layer of the cell region CELL, which corresponds to the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern 773a of the peripheral circuit region PERI.

[0346] The lower bonding metals 771b and 772b can be formed on the second metal layer 740b within the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 871b and 872b of the cell region CELL by Cu-to-Cu bonding.

[0347] Further, in the bit line bonding area BLBA, an upper metal pattern 892 can be formed in the uppermost metal layer of the cell region CELL, which corresponds to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same cross-sectional shape as the lower metal pattern 752 of the peripheral circuit region PERI. A contact can not be formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL.

[0348] In an exemplary embodiment, a reinforcing metal pattern having the same shape as a metal pattern formed in the uppermost metal layer among one of the cell region CELL and the peripheral circuit region PERI can be formed in the uppermost metal layer among the other of the cell region CELL and the peripheral circuit region PERI. A contact can not be formed on the reinforcing metal pattern.

[0349] Figure 24 is an illustration of a data center 3000 to which a host storage system 10 according to an embodiment is applied.

[0350] Referring to Figure 24 , the data center 3000 can be a facility that collects pieces of various types of data and provides services, which can be referred to as a data storage center. The data center 3000 can be a system for operating a search engine and a database, and can be a computing system used by a company such as a bank or a government agency. The data center 3000 can include application servers 3100 through 3100n and storage servers 3200 through 3200m. The number of the application servers 3100 through 3100n and the number of the storage servers 3200 through 3200m can be variously selected according to an embodiment. The number of the application servers 3100 through 3100n can be different from the number of the storage servers 3200 through 3200m.

[0351] The application server 3100 or the storage server 3200 can include at least one of a processor 3110 and 3210 and a memory 3120 and 3220. The storage server 3200 will now be described as an example. The processor 3210 can control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 can be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, and / or a non-volatile DIMM (NVDIMM). In some embodiments, various choices can be made for the processor 3210 and the memory 3220 contained in the storage server 3200. In an embodiment, the processor 3210 and the memory 3220 can provide a processor-memory pair. In an embodiment, the number of processors 3210 can be different from the number of memories 3220. The processor 3210 can include a single core processor or a multi-core processor. The above description of the storage server 3200 can be similarly applied to the application server 3100. In some embodiments, the application server 3100 can not include the storage device 3150. The storage server 3200 can include at least one storage device 3250. The number of storage devices 3250 contained in the storage server 3200 can be variously chosen according to an embodiment.

[0352] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be embodied by using a fiber channel (FC) or Ethernet. In this case, the FC can be a medium for relatively high-speed data transmission and uses an optical switch having high performance and high availability. According to an access method of the network 3300, the storage servers 3200 to 3200m can be provided as file storage, block storage, or object storage.

[0353] In an embodiment, the network 3300 can be a storage dedicated network, for example, a storage area network (SAN). For example, the SAN can be an FC-SAN, which uses an FC network and is embodied according to an FC protocol (FCP). As another example, the SAN can be an Internet protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is embodied according to a TCP / IP-based SCSI protocol or an Internet SCSI (iSCSI) protocol. In another embodiment, the network 3300 can be a general network, for example, a TCP / IP network. For example, the network 3300 can be embodied according to protocols such as a fiber channel over Ethernet (FCoE), network attached storage (NAS), and fabric-based NVMe (NVMe-oF).

[0354] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 can be applied to another application server 3100n, and the description of the storage server 3200 can be applied to another storage server 3200m.

[0355] The application server 3100 can store data requested by a user or a client into one of the storage servers 3200 to 3200m through the network 3300. Also, the application server 3100 can obtain data requested to be read by a user or a client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 can be embodied as a web server or a database management system (DBMS).

[0356] The application server 3100 can access the memory 3120n or the storage device 3150n contained in another application server 3100n through the network 3300. Alternatively, the application server 3100 can access the memory 3220 to 3220m or the storage device 3250 to 3250m contained in the storage servers 3200 to 3200m through the network 3300. Thus, the application server 3100 can perform various operations on data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 can execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, the data can be moved from the storage device 3250 to 3250m of the storage servers 3200 to 3200m to the memory 3120 to 3120n of the application servers 3100 to 3100n, directly or through the memory 3220 to 3220m of the storage servers 3200 to 3200m. The data moved through the network 3300 can be data encrypted for security or privacy.

[0357] The storage server 3200 will now be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251, and can provide a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be embodied using a direct attached storage (DAS) scheme in which the storage device 3250 is connected directly with a dedicated cable. For example, the interface 3254 can be embodied by using various interface schemes such as an ATA, a SATA, an e-SATA, a SCSI, a SAS, a PCI, a PCIe, an NVMe, an IEEE 1394, a USB interface, an SD card interface, an MMC interface, an eMMC interface, a UFS interface, an eUFS interface, and / or a CF card interface.

[0358] The storage server 3200 can further include a switch 3230 and a NIC (network interconnection) 3240. The switch 3230 can selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 via control of the processor 3210.

[0359] In an embodiment, the NIC 3240 can include a network interface card and a network adapter. The NIC 3240 can be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 can include an internal memory, a digital signal processor (DSP), and a host bus interface, and be connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface can be embodied as one of the above-described examples of the interface 3254. In an embodiment, the NIC 3240 can be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0360] In the storage server 3200 to 3200m or the application server 3100 to 3100n, the processor can transmit a command to the storage device 3150 to 3150n and 3250 to 3250m or the memory 3120 to 3120n and 3220 to 3220m, and program or read data. In this case, the data can be data whose error is corrected by an ECC engine. The data can be data for which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and can include cyclic redundancy code (CRC) information. The data can be data that is encrypted for security or privacy.

[0361] The memory devices 3150 to 3150n and 3250 to 3250m can transfer control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to read commands received from the processor. Thus, when data is read from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal, and thus data can be output to the DQ bus. A data strobe signal DQS can be generated using the RE signal. The command and address signals can be latched into page buffers in accordance with a rising edge or a falling edge of a write enable (WE) signal.

[0362] The controller 3251 can control all operations of the memory device 3250. In an embodiment, the controller 3251 can include an SRAM. The controller 3251 can write data to the NAND flash memory devices 3252 in response to a write command or read data from the NAND flash memory devices 3252 in response to a read command. For example, the write command and / or the read command can be provided from the processor 3210 of the storage server 3200, the processor 3210m of another storage server 3200m, or the processors 3110 and 3110n of the application servers 3100 and 3100n. The DRAM 3253 can temporarily store data to be written to the NAND flash memory devices 3252 or data read from the NAND flash memory devices 3252. Also, the DRAM 3253 can store metadata. Here, the metadata can be user data or data generated by the controller 3251 to manage the NAND flash memory devices 3252. The memory device 3250 can include a secure element (SE) for security or privacy.

[0363] Thus, having described example embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that many changes can be made in the way the inventive concept is implemented. Such changes not being regarded as a departure from the essence and scope of the example embodiments of the inventive concept, and all such modifications as would be obvious to one skilled in the art in light of the foregoing are intended to be included within the scope of the claims below.

Claims

1. A host device including a host controller interface configured to provide interfacing between the host device and a storage device, the host controller interface comprising: Processing circuitry; The doorbell register is configured to store the head and tail pointers of one or more first queues; as well as An entry buffer is configured to store a first command from one of one or more first queues. The bitmap doorbell register is configured to indicate the free and occupied space of the entry buffer using a bitmap. The processing circuit is configured as follows: Determine the order in which commands from one or more first queues are processed. The first command to be stored in the entry buffer is routed according to the determined order, and The route should be stored in one of the one or more second queues as the first response. The host device includes a first core configured to process a first submit queue and a first complete queue, and a second core configured to process a second submit queue and a second complete queue. The processing circuit is configured as follows: Determine the first priority and the second priority for the first commit queue and the second commit queue, respectively. Process the queue that is determined to have the highest priority between the first and second priority queues, from the first and second submission queues.

2. The host device of claim 1, wherein, One or more first queues comprise multiple circular queues.

3. The host device according to claim 1, wherein One or more first queues include one or more submit queues, and one or more second queues include one or more complete queues. The doorbell register stores the first head pointer and the first tail pointer for at least one of the one or more submission queues, and The doorbell register stores a second head pointer and a second tail pointer for at least one of the one or more completion queues.

4. The host device of claim 3, wherein, The processing circuitry is configured to update the first head pointer in response to the first command being stored in the entry buffer.

5. The host device of claim 3, wherein, The processing circuitry is configured to update the second tail pointer in response to the first response being stored in at least one completion queue.

6. The host device of claim 1, wherein, The processing circuit is configured to change the bit information in the bitmap corresponding to the data area where the first command or first response is stored in the entry buffer from bit 0 to bit 1 in response to the first command or first response being stored in the entry buffer.

7. The host device of claim 1, wherein, The processing circuitry is configured to allocate the first command to the free space of the entry buffer via a reference bitmap doorbell register.

8. The host device of claim 1, wherein, The processing circuitry is configured to route the first response to be written to the entry buffer via the reference bitmap doorbell register to the completion queue in one or more of the second queues.

9. The host device of claim 1, wherein, The processing circuitry is configured to determine a first priority and a second priority based on at least one of the following: Whether the priority flag is appended to the first submission queue. Whether the priority flag is appended to the second submission queue. Which of the first and second submission queues is received first? Which of the first and second commit queues has insufficient blank space? Which of the first and second submission queues has a higher weight, or whether one of the first submission queue and the second submission queue is previously designated as having a higher priority.

10. The host device of claim 1, wherein, the first response is a result of processing of the first command by the storage device.

11. A storage system, comprising: a host device; and a storage device, wherein the host device is configured to transmit a first command to the storage device, wherein the host device comprises, a host memory configured to store at least one queue, at least one core configured to process the at least one queue, a first processing circuit configured to provide an interface to the host memory, and a doorbell register configured to store a head pointer and a tail pointer for the at least one queue, and wherein the storage device comprises a second processing circuit configured to provide a first response to the host device as a result of performing a memory operation based on the first command, wherein the at least one core comprises, a first core configured to process a first submission queue and a first completion queue, and a second core configured to process a second submission queue and a second completion queue, and wherein the first processing circuit is configured to, determine a first priority and a second priority for the first submission queue and the second submission queue, respectively, and process a queue among the first submission queue and the second submission queue determined to have a highest priority among the first priority and the second priority.

12. The storage system of claim 11, wherein the at least one queue comprises a submission queue and a completion queue, and wherein the doorbell register stores, a first head pointer and a first tail pointer for the submission queue, and a second head pointer and a second tail pointer for the completion queue.

13. The storage system of claim 12, wherein, the host device further comprises: an entry buffer, and wherein the first processing circuit is further configured to update the first head pointer based on the first command being stored into the entry buffer.

14. The storage system of claim 12, wherein, the first processing circuit is further configured to update the second tail pointer based on the first response being stored into the completion queue.

15. The storage system of claim 11, wherein the host device further comprises: an entry buffer, wherein the at least one queue comprises one or more first queues and one or more second queues, and wherein the first processing circuit is further configured to, store the first command or the first response into the entry buffer; determine an order in which commands of the one or more first queues are processed; route the first command to be stored into the entry buffer according to the determined order; and route the first response to be stored into the doorbell register.

16. The storage system of claim 15, wherein, the host device further comprises: a bitmap doorbell register configured to indicate free space and occupied space of the entry buffer by using a bitmap.

17. The storage system of claim 16, wherein, the first processing circuit is further configured to allocate the first command to the free space of the entry buffer by referring to the bitmap doorbell register.

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