Semiconductor device and method for forming the same

Abstract

The present disclosure relates to semiconductor devices and methods for forming the same. One method includes forming a first-type deep well having a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first-type deep well to form a second-type doped region, wherein a concentration of the first impurity in the first-type deep well is higher than a concentration of the second impurity in the second-type doped region and lower than ten times a concentration of the second impurity in the second-type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide extending laterally from a first side of the second-type doped region; and forming a second-type well of a second conductivity type in the first-type deep well and on a second side of the second-type doped region opposite to the first side of the second-type doped region.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increased integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density comes from shrinking semiconductor process nodes (e.g., shrinking process nodes to nodes below 20nm). As semiconductor devices shrink, new technologies are desired to maintain the performance of electronic components from one generation to the next. For example, for various high-power applications, low on-resistance and high breakdown voltage of transistors are desired.

[0003] With the development of semiconductor technology, metal oxide semiconductor field effect transistors (MOSFETs) have become widely used in today's integrated circuits. MOSFETs are voltage-controlled devices. When a control voltage is applied to the MOSFET's gate and the control voltage is greater than the MOSFET's threshold, a conductive channel is established between the MOSFET's drain and source. As a result, current flows between the MOSFET's drain and source. On the other hand, when the control voltage is less than the MOSFET's threshold, the MOSFET is turned off.

[0004] MOSFETs can be divided into two main categories based on their conductivity type: n-channel MOSFETs and p-channel MOSFETs. Based on their structure, MOSFETs can be further divided into three subcategories: planar MOSFETs, laterally diffused MOSFETs (LDMOS) FETs, and vertically diffused MOSFETs. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first type deep well having a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first type deep well to form a second type doped region, wherein a concentration of the first impurity in the first type deep well is higher than a concentration of the second impurity in the second type doped region, but lower than about ten times a concentration of the second impurity in the second type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide extending laterally from a first side of the second type doped region; forming a second type well of the second conductivity type in the first type deep well and on a second side of the second type doped region opposite to the first side of the second type doped region; forming a gate structure extending laterally beyond the first and second sides of the second type doped region; and forming a source region in the second type well and a drain region in the first type deep well, wherein the field oxide extends laterally between the second type doped region and the drain region.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a deep n-well in a semiconductor substrate; forming a patterned mask layer above the deep n-well; appropriately utilizing the patterned mask layer to dope p-type dopants into the deep n-well to form a p-type doped region; annealing the semiconductor substrate to deepen the deep n-well and the p-type doped region; after annealing the semiconductor substrate, oxidizing a portion of the deep n-well and a portion of the p-type doped region to form a field oxide; forming a p-well in the deep n-well, wherein the p-type doped region is laterally located between the p-well and the field oxide; forming a gate structure extending from the p-well to the field oxide across the p-type doped region; and forming a source region in the p-well and a drain region in the deep n-well.

[0007] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a deep n-well in a semiconductor substrate; a field oxide partially embedded in the deep n-well and having a sharp corner at a position substantially flush with a top surface of the semiconductor substrate; a gate structure on the field oxide and extending laterally beyond the sharp corner of the field oxide; a p-type doped region in the deep n-well and intersecting the sharp corner of the field oxide; and a source region and a drain region at least partially separated laterally by the p-type doped region and the field oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A block diagram illustrating a method of forming a semiconductor device according to some embodiments is shown.

[0010] Figures 2 to 10 A method for manufacturing a semiconductor device at different stages according to some embodiments is shown.

[0011] Figure 11 A method for manufacturing a semiconductor device according to some embodiments is shown.

[0012] Figure 12 A method for manufacturing a semiconductor device according to some embodiments is shown.

[0013] Figure 13 A method for manufacturing a semiconductor device according to some embodiments is shown.

[0014] Figure 14 A method for manufacturing a semiconductor device according to some embodiments is shown.

[0015] Figure 15 A block diagram illustrating a method of forming a semiconductor device according to some embodiments is shown.

[0016] Figure 16 A method for manufacturing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] As used herein, "approximately," "about," "approximately," or "substantially" shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. The numerical quantities given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "approximately," or "substantially" can be inferred.

[0020] Laterally diffused (LD) MOS transistors have advantages. For example, because the asymmetric structure of the LDMOS transistor provides a short channel between the drain and source of the LDMOS transistor, it is able to pass more current per unit area. However, it has been recognized that LDMOS transistors suffer from some problems as described below. The breakdown voltage of the LDMOS transistor formed by the field oxide (FOX) is limited by the electric field peak, which may occur near the bird's beak of the FOX, which may cause device breakdown failure. For example, when the deep n-well (DNW) has not been fully depleted by the p-type semiconductor substrate, device breakdown failure may occur because the concentration of n-type dopants is higher than the concentration of p-type dopants near the bird's beak of the FOX, which in turn has an adverse effect on the electric field. When the concentration of the DNW near the bird's beak is reduced to achieve charge balance, the peak electric field can be improved. However, this will lead to breakdown of the drift region and reduce the breakdown voltage of the LDMOS transistor.

[0021] The present disclosure will be described with respect to embodiments in a specific context, using an LDMOS transistor manufactured using an improved process flow to address the aforementioned issues caused by FOX. In some embodiments, the LDMOS transistor may be an ultra-high voltage LDMOS transistor. However, embodiments of the present disclosure may also be applied to various metal oxide semiconductor transistors. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0022] Now refer to Figure 1, shows an exemplary method M1 for manufacturing a semiconductor device according to some embodiments, wherein the manufacturing includes a process for a semiconductor device having an additional p-type doped region that interfaces with a bird's beak of a field oxide below its gate structure. Method M1 includes relevant portions of the overall manufacturing process. It should be understood that in Figure 1 Additional operations are provided before, during, and after the operations shown, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Method M1 includes fabrication of semiconductor device 100. However, fabrication of semiconductor device 100 is merely an example for describing a semiconductor device 100 having an additional p-type doped region that interfaces with a bird's beak of a field oxide beneath a gate structure according to some embodiments of the present disclosure.

[0023] Note that the disclosed embodiments have been simplified for a better understanding. Figure 1 . In addition, the semiconductor device 100 can be configured as a system-on-chip (SoC) device having various PMOS and NMOS transistors fabricated to operate at different voltage levels. The PMOS and NMOS transistors can provide low voltage functions including logic / memory devices and input / output devices, as well as high voltage functions including power management devices. For example, transistors providing low voltage functions can have an operating (or drain) voltage of approximately 1.1V under standard CMOS technology, or an operating (or drain) voltage of approximately 1.8 / 2.5 / 3.3V under standard CMOS technology (special (input / output) transistors). In addition, transistors providing medium / high voltage functions can have an operating (or drain) voltage of approximately 5V or higher (e.g., approximately 20-35V), as well as other voltages within the scope of the present disclosure. It will be understood that Figure 2-10 The semiconductor device 100 may also include resistors, capacitors, inductors, diodes, and other suitable microelectronic devices that may be implemented in an integrated circuit.

[0024] Figures 2 to 10 1 shows a method for manufacturing a semiconductor device 100 at different stages according to some embodiments. Method M1 begins at block S10 where a deep n-well is formed in a p-type semiconductor substrate, such as Figure 2As shown. The semiconductor substrate 151 may include a semiconductor wafer such as a silicon wafer. Alternatively, the semiconductor substrate 151 may include other elemental semiconductors such as germanium. The semiconductor substrate 151 may also include a compound semiconductor, for example, silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In addition, the semiconductor substrate 151 may include an alloy semiconductor, for example, silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and indium gallium phosphide. In some embodiments, the semiconductor substrate 151 includes an epitaxial layer (epi layer) covering the bulk semiconductor. In addition, the semiconductor substrate 151 may include a semiconductor on insulator (SOI) structure. For example, the semiconductor substrate 151 may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX). In various embodiments, the semiconductor substrate 151 may include a buried layer such as an n-type buried layer (NBL), a p-type buried layer (PBL), and / or a buried dielectric layer including a buried oxide (BOX) layer.

[0025] In some embodiments shown as n-type MOS, the semiconductor substrate 151 includes a p-type silicon substrate (p-substrate). For example, p-type impurities (e.g., boron) are doped into the semiconductor substrate 151 to form a p-substrate. In order to form a complementary MOS, an n-type buried layer, i.e., a deep n-well (DNW) 152 (also referred to as an n-drift region), may be implanted deep below the active region of the semiconductor substrate 151. In some embodiments, the DNW 152 is formed by an ion implantation process P1. During the implantation process, a patterned photoresist layer (not shown) may be formed over the semiconductor substrate 151 as a mask. As an example and not limitation, the DNW 152 may be formed by an implantation process having a dose of about 1.0×10 11 atoms / cm 3 to about 1.0×10 13 atoms / cm 3 In some embodiments, DNW 152 has a concentration greater than 1.0×10 13 atoms / cm 3 By way of example and not limitation, the dopant concentration of DNW 152 is about 1.0×10 13 atoms / cm 3 to about 1.0×10 16 atoms / cm 3 The dopant concentration range is within the range of , and other dopant concentration ranges are within the scope of the present disclosure. In some embodiments, arsenic or phosphorus ions may be implanted to form DNW 152. In some embodiments, DNW 152 is formed by selective diffusion. DNW 152 serves to electrically isolate semiconductor substrate 151.

[0026] return Figure 1 Method M1 then proceeds to block S11 where p-type impurities are doped into the deep n-well to form a p-type doped region. Figure 3 In some embodiments of block S11, a photoresist 161 is coated on the DNW 152. Photolithography techniques are used to pattern the photoresist 161 into a desired pattern for a p-type doped region 162 to be formed in the DNW 152. The photoresist 161 is developed to expose the DNW 152 above the semiconductor substrate 151. A high-energy p-type dopant implantation process P2 is then performed to form the p-type doped region 162 through the photoresist 161.

[0027] In some embodiments, the breakdown voltage of the semiconductor device 100 is limited by the peak value of the electric field, which may occur at a certain position. Figure 5 The electric field peak may cause device breakdown failure near the bird's beak of FOX 108 (also called the tip corner). For example, when DNW 152 has not been completely depleted through semiconductor substrate 151, device breakdown failure may occur because the n-type dopant concentration may be higher than the p-type dopant concentration near the bird's beak of FOX 108, which in turn has an adverse effect on the electric field. Figure 5 As shown, when the concentration of DNW 152 near bird's beak 108 c of FOX 108 is reduced to achieve charge balance, the peak electric field can be improved. However, this will cause DNW 152 to break down and reduce the breakdown voltage of semiconductor device 100.

[0028] Therefore, p-type dopants are implanted into the p-type doped region 162 (ie, Figure 5 The p-type dopant concentration near the source region is increased (as shown near the bird's beak 108c of FOX 108 near the source region), thereby achieving charge balance. Therefore, the electric field peak can be reduced, thereby achieving an improved breakdown voltage of the semiconductor device 100. For example, if the concentration of the p-type dopant region 162 is increased so that the concentration of the n-type dopant in the DNW 152 is less than about 10 times the concentration of the p-type dopant in the p-type doping region 162, the electric field near the source region of the semiconductor device 100 can be less than about 1.5×10 5 Vcm -1 , thereby achieving charge balance. Therefore, the breakdown voltage of the semiconductor device 100 can be increased by about 100 V. Note that other electric field strengths and / or breakdown voltages are within the scope of the present disclosure.

[0029] In some embodiments, the p-type dopant concentration in the p-type doping region 162 is lower than the n-type dopant concentration. In some embodiments, the p-type dopant concentration in the p-type doping region 162 is lower than the n-type dopant concentration in the DNW 152. By way of example and not limitation, the p-type dopant concentration in the p-type doping region 162 is lower than the n-type dopant concentration in the DNW 152. In some embodiments, the p-type dopant concentration in the p-type doping region 162 is of the same order of magnitude as the n-type dopant concentration in the DNW 152. That is, the n-type dopant concentration in the DNW 152 is higher than the p-type dopant concentration in the p-type doping region 162 and is less than approximately ten times the p-type dopant concentration in the p-type doping region 162. In other words, the difference between the p-type dopant concentration in the p-type doping region 162 and the n-type dopant concentration in the DNW 152 is less than approximately one order of magnitude.

[0030] By way of example and not limitation, the n-type dopant concentration in the DNW 152 may be approximately 8.58×10 15 atoms / cm 3 , and the p-type dopant concentration in the p-type doping region 162 may be approximately 1.4×10 15 atoms / cm 3 , which is of the same order of magnitude as the n-type dopant concentration in DNW 152 (i.e., 10 15 ), and other concentrations are within the scope of the present disclosure. In some embodiments, the difference between the p-type dopant concentration in the p-type doping region 162 and the n-type dopant concentration in the DNW 152 can be less than one order of magnitude to achieve charge balance near the source region, thereby achieving an improved breakdown voltage of the semiconductor device 100. If the difference between the p-type dopant concentration in the p-type doping region 162 and the n-type dopant concentration in the DNW 152 is greater than one order of magnitude, this may in turn adversely affect the breakdown voltage. In some embodiments, for the implantation process P2, at approximately 300 keV, the dopant may include boron (B) and may include 1.0×10 12 atoms / cm 3 to 1.0×10 15 atoms / cm 3 The dosage of the dopant concentration is of the order of 100, and other dosages are within the scope of the present disclosure. If the concentration is lower, the charge balance cannot be effectively achieved, which in turn may lead to a decrease in the breakdown voltage.

[0031] In some embodiments, the p-type doped region 162 extends from the top surface of the semiconductor substrate 151 into the semiconductor substrate 151 by a distance (D2). The depth D2 of the p-type doped region 162 includes the entire thickness (or depth) D1 of the DNW 152. In some embodiments, by way of example and not limitation, the depth D2 of the p-type doped region 162 may be in the range of about 0.1 μm to about 10 μm to achieve charge balance near the source region. If the depth D2 of the p-type doped region 162 is less than about 0.1 μm, it may not be possible to Figure 5 Charge balance is shown to be achieved near the bird's beak 108 c of the FOX 108. If the depth D2 of the p-type doped region 162 is greater than about 10 μm, this may in turn adversely affect the semiconductor device 100.

[0032] exist Figure 3 In the embodiment, the bottommost position B2 of the p-type doping region 162 is aligned with the bottommost position B1 of the DNW 152. In some embodiments, the p-type doping region 162 may extend beyond the bottommost position B1 of the DNW 152. In some embodiments, the p-type doping region 162 is formed by selective diffusion.

[0033] return Figure 1 The method M1 then proceeds to block S12 where the semiconductor substrate is annealed to deepen the DNW and the bottommost position of the p-type doped region. Figure 4 In some embodiments of block S12, the photoresist 161 is removed, and then an annealing process P3 (e.g., rapid thermal annealing or laser annealing) is performed to anneal the semiconductor substrate 151, which causes the impurities in the DNW 152 and the p-type doping region 162 to diffuse toward the semiconductor substrate 151, thereby deepening the bottommost position B1 of the DNW 152 and deepening the bottommost position B2 of the p-type doping region 162. In some embodiments, by way of example and not limitation, the dopants in the DNW 152 and the p-type doping region 162 are driven in by heating the semiconductor substrate 151 to a temperature in a range from about 1000° C. to about 1100° C., and other temperature ranges are within the scope of the present disclosure.

[0034] In more detail, the semiconductor device 100 includes doped regions R1, R2, and R3 that are delimited in the lateral direction and each extend in the vertical direction, and the delimitation of the doped regions R1, R2, and R3 that are delimited in the lateral direction is defined by the vertical boundary of the p-type doped region 162. After the annealing process P3 is completed, the depth D3 of the DNW 152 in the doped regions R1 and R3 is greater than that performed before the annealing process P3. Figure 3 The depth D1 of the DNW 152 is shown. The depth D4 of the DNW 152 in the doped region R2 is greater than that performed before the annealing process P3. Figure 2The depth D1 of the DNW 152 is shown. The depth D5 of the p-type doped region 162 after the annealing process P3 is greater than that performed before the annealing process P3. Figure 3 The p-type doped region 162 is shown to have a depth D2.

[0035] In some embodiments, during annealing process P3, n-type dopants have a higher diffusion rate than p-type dopants, causing bottommost location B1 of DNW 152 to be lower than bottommost location B2 of p-type doping region 162. Therefore, bottommost location B2 of p-type doping region 162 is spaced apart from bottommost location B1 of DNW 152 by distance S1. In some embodiments, during annealing process P3, n-type dopants in doping region R1 or R3 have a higher diffusion rate than n-type dopants in doping region R2, causing bottommost location B1 of DNW 152 in doping region R1 or R3 to be lower than bottommost location B1 of DNW 152 in doping region R2. In other words, depth D3 of DNW 152 in doping region R1 or R3 is deeper than depth D4 of DNW 152 in doping region R2.

[0036] return Figure 1 , the method M1 then proceeds to block S13 where a field oxide is formed on the semiconductor substrate. Figure 5 In some embodiments of block S13, a nitride layer (not shown) including a dielectric is deposited over the semiconductor substrate 151. By way of example and not limitation, the nitride layer may have a thickness of 1500 angstroms, but the nitride layer may have other thicknesses. A photoresist (not shown) is deposited over the nitride layer. The photoresist is patterned with a desired pattern of the active area of ​​the semiconductor device 100. The photoresist is used as a mask to pattern the nitride layer. For example, a dry etch may be used to etch the nitride layer. After patterning the nitride layer, the photoresist is stripped using, for example, H2SO4.

[0037] exist Figure 5 In the embodiment of the present invention, a field oxide (FOX) 108 and a field oxide (FOX) 110 are formed over portions of the DNW 152 and the p-type doped region 162 using the nitride layer as a mask and embedded in the semiconductor substrate 151. The FOX 108 overlaps a portion of the p-type doped region 162. The field oxides 108 and 110 may include a dielectric, such as silicon oxide, nitride, or other suitable insulating material, deposited by heating the semiconductor substrate 151 at a temperature of approximately 980° C. in the presence of oxygen, and other temperatures are within the scope of the present disclosure. In some embodiments, the field oxides 108 and 110 formed by the thermal oxidation process may result in a bird's beak 108 c.

[0038] By way of example and not limitation, field oxide 108 includes a lower inclined facet 108a and an upper inclined facet 108d, which forms a corner with lower inclined facet 108a as a bird's beak 108c. In more detail, upper inclined facet 108d extends upward from the top surface of semiconductor substrate 151 to top surface 108t of field oxide 108. Lower inclined facet 108d extends downward from the top surface of semiconductor substrate 151 to bottom surface 108b of field oxide 108. By way of example and not limitation, the acute angle between lower inclined facet 108a of FOX 108 and the top surface of semiconductor substrate 151 is in the range of approximately 30 degrees to approximately 60 degrees, and other angle ranges are within the scope of the present disclosure.

[0039] In some embodiments, the p-type doped region 162 interfaces with the bird's beak 108c of the FOX 108. Figure 5 In the embodiment shown in FIG. 1 , the p-type doped region 162 contacts the lower inclined facet 108 a and the bottom surface 108 b of the field oxide 108 . In some embodiments, the p-type dopant of the p-type doped region 162 may diffuse into the FOX 108 .

[0040] In some embodiments, the bottom-most position of the DNW 152 below the p-type doped region 162 is higher than the bottom-most position of the DNW 152 below the FOX 108 and the FOX 110 .

[0041] In some embodiments, by way of example and not limitation, field oxide 108 or 110 may comprise a thickness of approximately 6000 angstroms, although field oxides 108 and 110 may alternatively comprise other thicknesses and materials. After forming field oxides 108 and 110, the patterned nitride layer is then stripped or removed.

[0042] Return to Figure 1 , method M1 then proceeds to block S14 where a p-top region is formed in the DNW and directly below the FOX. Figure 6In some embodiments of block S14, a p-top region 155 (also referred to as a buried p-well region) is formed in the middle of the DNW 152 and below the FOX 108 but not connected to the FOX 108. The p-top region 155 is a floating layer and is not connected to the source or drain region of the semiconductor device 100 to be formed below. The bottommost position of the p-type doped region 162 is located between the bottommost position of the p-top region 155 and the bottommost position of the DNW 152 in the vertical direction. In some embodiments, the p-type dopant concentration in the p-top region 155 is higher than the p-type dopant concentration in the p-type dopant region 162. In more detail, the p-type dopant concentration in the p-top region 155 is higher than the p-type dopant concentration in the p-type dopant region 162. By way of example and not limitation, the p-type dopant (e.g., boron) concentration of the p-type top region 155 is approximately 1.0×10 13 atoms / cm 3 to about 1.0×10 16 atoms / cm 3 and other concentration ranges are within the scope of the present disclosure.

[0043] In some embodiments, the difference between the p-type dopant concentration in the p-top region 155 and the p-type dopant concentration in the p-type doping region 162 can be less than three orders of magnitude, so that the p-type dopant region 162 can have a sufficient p-type dopant concentration to achieve charge balance near the source region, thereby achieving an improved breakdown voltage of the semiconductor device 100. In other words, the p-type dopant concentration in the p-top region 155 can be higher than the p-type dopant concentration in the p-type doping region 162 and less than about one thousand times the p-type dopant concentration in the p-type doping region 162. If the difference between the p-type dopant concentration in the p-top region 155 and the p-type dopant concentration in the p-type doping region 162 is greater than three orders of magnitude, this, in turn, can adversely affect the breakdown voltage. By way of example and not limitation, the p-type dopant concentration in the p-top region 155 can be about 1.0×10 16 atoms / cm 3 , and the p-type dopant concentration in the p-type doping region 162 may be approximately 1.0×10 15 atoms / cm 3 , and other concentrations are within the scope of the present disclosure. In some embodiments, the difference between the p-type dopant concentration in the p-top region 155 and the p-type dopant concentration in the p-type doping region 162 can be less than two orders of magnitude. In other words, the p-type dopant concentration in the p-top region 155 can be higher than the p-type dopant concentration in the p-type doping region 162 and less than about one hundred times the p-type dopant concentration in the p-type doping region 162.

[0044] return Figure 1, method M1 then proceeds to block S15 where a p-well is formed in the DNW and adjacent to the p-type doped region. Figure 7 In some embodiments of block S15, the p-well 154 (also referred to as a p-body) is formed by implanting a p-type dopant such as boron into the semiconductor substrate 151 and performing an annealing process (e.g., rapid thermal annealing or laser annealing) on ​​the p-well 154. Alternatively, the p-well 154 may be formed by another suitable process such as a diffusion process.

[0045] exist Figure 7 In the embodiment, the p-well 154 extends downward from the top surface of the semiconductor substrate 151, is adjacent to the p-type doped region 162, and a portion of the p-well 154 is below the FOX 110. The bottommost position of the p-type doped region 162 is located between the bottommost position of the p-well 154 and the bottommost position of the DNW 152 in the vertical direction. In some embodiments, the p-type dopant concentration in the p-well 154 is higher than the p-type dopant concentration in the p-type dopant region 162. In more detail, the p-type dopant concentration in the p-well 154 is higher than the p-type dopant concentration in the p-type dopant region 162. By way of example and not limitation, the p-type dopant (e.g., boron) concentration of the p-well 154 is in the range of about 1.0×10 14 atoms / cm 3 to about 1.0×10 17 atoms / cm 3 and other concentration ranges are within the scope of the present disclosure.

[0046] In some embodiments, the difference between the p-type dopant concentration in the p-well 154 and the p-type dopant concentration in the p-type doping region 162 can be less than three orders of magnitude, so that the p-type dopant region 162 can have a sufficient p-type dopant concentration to achieve charge balance near the source region, thereby achieving an improved breakdown voltage of the semiconductor device 100. In other words, the p-type dopant concentration in the p-well 154 can be higher than the concentration of the p-type dopant in the p-type doping region 162 and less than about one thousand times the p-type dopant concentration in the p-type doping region 162. If the difference between the p-type dopant concentration in the p-well 154 and the p-type dopant concentration in the p-type doping region 162 is greater than three orders of magnitude, this, in turn, can adversely affect the breakdown voltage. By way of example and not limitation, the p-type dopant concentration in the p-top region 155 can be about 1.0×10 16 atoms / cm 3 , and the p-type dopant concentration in the p-type doping region 162 may be approximately 1.0×10 15 atoms / cm 3, and other concentrations are within the scope of the present disclosure. In some embodiments, the difference between the p-type dopant concentration in the p-well 154 and the p-type dopant concentration in the p-type doping region 162 can be less than two orders of magnitude. In other words, the p-type dopant concentration in the p-well 154 can be higher than the p-type dopant concentration in the p-type doping region 162 and less than about one hundred times the p-type dopant concentration in the p-type doping region 162.

[0047] return Figure 1 Then, the method M1 proceeds to block S16 where a gate structure is formed on the semiconductor substrate. Figure 8 In some embodiments of block S16, the gate structure 147 includes a gate dielectric 140 formed on a semiconductor substrate 151, and a gate electrode 145 formed on the gate dielectric 140. The gate dielectric 140 has a first portion covering the p-type doped region 162 and a second portion covering the p-well 154. In some embodiments, the p-type dopant of the p-type doped region 162 can diffuse into the gate dielectric 140.

[0048] The gate dielectric 140 may include a silicon dioxide (referred to as silicon oxide) layer suitable for high voltage applications. Alternatively, the gate dielectric 140 may optionally include a high-k dielectric material, silicon oxynitride, other suitable materials, or a combination thereof. The high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, HfO2, or a combination thereof. The gate dielectric 140 may have a multilayer structure, for example, a layer of silicon oxide and another layer of high-k material. The gate dielectric 240 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, other suitable processes, or a combination thereof.

[0049] The gate electrode 145 can be configured to be coupled to a metal interconnect and can be arranged to cover the gate dielectric 140. The gate electrode 145 may include doped or undoped polycrystalline silicon (or polysilicon). Alternatively, the gate electrode 145 may include a metal (e.g., Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi), other suitable conductive materials, or a combination thereof. The gate electrode 145 can be formed by CVD, PVD, ALD, electroplating, and other appropriate processes. The gate electrode layer may have a multi-layer structure and may be formed in a multi-step process.

[0050] return Figure 1 , method M1 then proceeds to block S17 where a drain and a source are formed in the DNW and the p-well, respectively. Figure 9In some embodiments of block S17, a drain 128 may be formed in the DNW 152 and a source may be formed in an upper portion of the p-well 154. The FOX 108 separates the gate structure 147 from the drain 128. Figure 9 , the source has two oppositely doped regions 124 and 126, both formed in the upper portion of the p-well 154. The first region 124 of the source and the drain 128 can have a first conductivity type, and the second region 126 of the source can have a second conductivity type. By way of example and not limitation, the first region 124 of the source and the drain 128 include n-type dopants, such as phosphorus (P) or arsenic (As), and the second region 126 of the source includes p-type dopants, such as boron (B). Alternatively, the source can have one conductivity type. The source and drain can be located on either side of the gate structure 147. The source and drain can be formed by methods such as ion implantation or diffusion. A rapid thermal annealing (RTA) process can be used to activate the implanted dopants.

[0051] In some embodiments, the n-type dopant concentration in the first region 124 of the source is higher than the p-type dopant concentration in the p-type dopant region 162. In some embodiments, the n-type dopant concentration in the drain 128 is higher than the p-type dopant concentration in the p-type dopant region 162. In some embodiments, the p-type dopant concentration in the second region 126 of the source is higher than the p-type dopant concentration in the p-type dopant region 162. By way of example and not limitation, the n-type dopant concentration in the first region 124 of the source may be between approximately 1.0×10 19 atoms / cm 3 to about 1.0×10 21 atom 3 In the range of about 1.0×10 19 atoms / cm 3 to about 1.0×10 21 atoms / cm 3 , and the p-type dopant concentration in the second region 126 of the source may be approximately 1.0×10 19 atoms / cm 3 to about 1.0×10 21 atoms / cm 3 and other concentration ranges are within the scope of the present disclosure.

[0052] In some embodiments, the difference between the n-type dopant concentration in the first region 124 of the source and the p-type dopant concentration in the p-type doping region 162 can be less than five orders of magnitude, so that the p-type dopant region 162 can have a sufficient p-type dopant concentration to achieve charge balance near the source region, thereby achieving an improved breakdown voltage of the semiconductor device 100. In other words, the n-type dopant in the first region 124 of the source can be higher than the p-type dopant concentration in the p-type doping region 162 and less than about one hundred thousand times the p-type dopant concentration in the p-type doping region 162. If the difference between the n-type dopant concentration in the first region 124 of the source and the p-type dopant concentration in the p-type doping region 162 is greater than five orders of magnitude, this may in turn have an adverse effect on the breakdown voltage. By way of example and not limitation, the n-type dopant concentration in the first region 124 can be about 1.0×10 19 atoms / cm 3 , and the p-type dopant concentration in the p-type doping region 162 may be approximately 1.0×10 15 atoms / cm 3 , and other concentrations are within the scope of the present disclosure.

[0053] In some embodiments, the difference between the p-type dopant concentration in the second region 126 of the source and the p-type dopant concentration in the p-type doping region 162 can be less than five orders of magnitude, so that the p-type dopant region 162 can have a sufficient p-type dopant concentration to achieve charge balance near the source region, thereby achieving an improved breakdown voltage of the semiconductor device 100. In other words, the p-type dopant concentration in the second region 126 of the source can be higher than the p-type dopant concentration in the p-type doping region 162 and less than about one hundred thousand times the p-type dopant concentration of the p-type dopant region 162. If the difference between the p-type dopant concentration in the second region 126 of the source and the p-type dopant concentration in the p-type doping region 162 is greater than five orders of magnitude, this may in turn have an adverse effect on the breakdown voltage. By way of example and not limitation, the p-type dopant concentration in the second region 126 can be about 1.0×10 19 atoms / cm 3 , and the p-type dopant concentration in the p-type doping region 162 may be approximately 1.0×10 15 atoms / cm 3 , and other concentrations are within the scope of the present disclosure.

[0054] In some embodiments, the difference between the n-type dopant concentration in the drain 128 and the p-type dopant concentration in the p-type doping region 162 can be less than five orders of magnitude, so that the p-type dopant region 162 can have a sufficient p-type dopant concentration to achieve charge balance near the source region, thereby achieving an improved breakdown voltage of the semiconductor device 100. In other words, the n-type concentration dopant in the drain 128 can be higher than the p-type dopant concentration in the p-type doping region 162 and less than about one hundred thousand times the p-type dopant concentration in the p-type doping region 162. If the difference between the n-type dopant concentration in the drain 128 and the p-type dopant concentration in the p-type doping region 162 is greater than five orders of magnitude, this may in turn have an adverse effect on the breakdown voltage. By way of example and not limitation, the n-type dopant concentration in the drain 128 can be about 1.0×10 19 atoms / cm 3 , and the p-type dopant concentration in the p-type doping region 162 may be approximately 1.0×10 15 atoms / cm 3 , and other concentrations are within the scope of the present disclosure.

[0055] In some embodiments, the difference between the n-type dopant concentration in the drain 128 and the p-type dopant concentration in the p-type doping region 162 can be less than four or three orders of magnitude. In some embodiments, the difference between the p-type dopant concentration in the second region 126 of the source and the p-type dopant concentration in the p-type doping region 162 can be less than four or three orders of magnitude. In some embodiments, the difference between the n-type dopant concentration in the drain 128 and the p-type dopant concentration in the p-type doping region 162 can be less than four or three orders of magnitude.

[0056] return Figure 1 , the method M1 then proceeds to block S18, wherein a plurality of contacts are formed in the interlayer dielectric layer to contact the gate structure, the drain, and the source, respectively. Figure 10 In some embodiments of block S18, Figure 9 An interlayer dielectric (ILD) layer 196 is formed over the structure in FIG. In some embodiments, the ILD layer 196 includes a material having a low dielectric constant, for example, a dielectric constant less than about 3.9. For example, the ILD layer 196 may include silicon oxide. In some embodiments, the dielectric layer includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluorine-doped silicate glass (FSG), carbon-doped silicon oxide, Black (Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (his-benzocyclobutenes), SiLK (Dow Chemical, Midland, Michigan), polyimide, and / or other suitable materials. The ILD 196 layer can be formed by techniques including spin coating, CVD, or other suitable processes.

[0057] Then, a plurality of contacts 116, 114, and 118 are formed in the ILD layer 196 to contact the gate structure 147, the drain 128, and the source regions 124 and 126. For example, a plurality of openings are formed in the ILD layer 196, and a conductive material is then deposited in the openings. Excess portions of the conductive material outside the openings are removed using a CMP process, while portions remain in the openings to serve as contacts 116, 114, and 118. Contacts 116, 114, and 118 can be made of tungsten, aluminum, copper, or other suitable materials. In some embodiments, contact 116 is electrically connected to the gate structure 147, contact 114 is connected to the drain 128, and contact 118 is connected to the source regions 124 and 126.

[0058] refer to Figure 11 . Figure 11 A method for fabricating a semiconductor device 200 at different stages according to some embodiments is shown. The operations for forming the semiconductor device 200 are substantially the same as those for forming the semiconductor device 100 described in the previous description and are therefore not repeated here for clarity. Figure 11 Another profile of an LDMOS in addition to the semiconductor device 100 manufactured using method M1 is shown. Figure 11 Some alternative embodiments according to the present disclosure are shown in FIG. Figure 10 The semiconductor device 200 at the corresponding stage. Figure 11 As shown, the p-type doped region 262 interfaces with the bird's beak 108 c of the FOX 108. More specifically, the bottom-most portion of the p-type doped region 262 is located above the bottom surface of the FOX 108. The p-type doped region 262 contacts the lower inclined facet 108 a of the FOX 108 and does not contact the bottom surface 108 b of the FOX 108.

[0059] refer to Figure 12 . Figure 12A method for fabricating a semiconductor device 300 at different stages according to some embodiments is shown. The operations for forming the semiconductor device 300 are substantially the same as the operations for forming the semiconductor device 100 described in the foregoing description and are therefore not repeated here for clarity. Figure 12 Another profile of an LDMOS in addition to the semiconductor device 100 manufactured using method M1 is shown. Figure 12 Some alternative embodiments according to the present disclosure are shown in FIG. Figure 10 The semiconductor device 300 at the corresponding stage. Figure 12 As shown, p-type doped region 362 interfaces with bird's beak 108 c of FOX 108 . More specifically, the bottommost portion of p-type doped region 362 is below the bottom surface of FOX 108 and above the bottommost portion of p-well 154 and the upper boundary of p-top region 155 .

[0060] refer to Figure 13 . Figure 13 A method for fabricating a semiconductor device 400 at different stages according to some embodiments is shown. The operations for forming the semiconductor device 400 are substantially the same as the operations for forming the semiconductor device 100 described in the foregoing description and are therefore not repeated here for clarity. Figure 13 Another profile of an LDMOS in addition to the semiconductor device 100 manufactured using method M1 is shown. Figure 13 Some alternative embodiments according to the present disclosure are shown in FIG. Figure 10 The semiconductor device 400 at the corresponding stage. Figure 13 As shown, the p-type doped region 462 borders the bird's beak 108c of the FOX 108. More specifically, the bottommost position of the p-type doped region 462 is located between the bottommost position of the p-well 154 and the bottommost position of the DNW 152 in the vertical direction. Figure 13 , the bottommost position of the DNW 152 below the p-type doping region 462 in the doping region R2 is at a position substantially flush with the bottommost position of the DNW 152 below the doping regions R1 and R3 .

[0061] refer to Figure 14 . Figure 14 A method for fabricating a semiconductor device 500 at different stages according to some embodiments is shown. The operations for forming the semiconductor device 500 are substantially the same as those for forming the semiconductor device 100 described in the previous description and are therefore not repeated here for clarity. Figure 14 Another profile of an LDMOS in addition to the semiconductor device 100 manufactured using method M1 is shown. Figure 14 Some alternative embodiments according to the present disclosure are shown in FIG. Figure 10The semiconductor device 500 at the corresponding stage. Figure 14 As shown, the p-type doped region 562 is in contact with the p-top region 155 .

[0062] Now refer to Figure 15 , illustrates an exemplary method M2 for fabricating a semiconductor device according to some embodiments, wherein the fabrication includes a semiconductor device having an additional p-type doped region that interfaces with a bird's beak of a field oxide beneath a gate structure. Figure 16 1 shows an LDMOS transistor manufactured using method M2. Method M2 includes relevant parts of the entire manufacturing process. It should be understood that Figure 15 Additional operations are provided before, during, and after the illustrated operations, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Method M2 includes fabrication of semiconductor device 600. However, fabrication of semiconductor device 600 is merely an example for describing a self-aligned process for semiconductor device 600 according to some embodiments of the present disclosure.

[0063] refer to Figure 16 At block S20, a deep p-well 652 is formed in an n-type semiconductor substrate 651. In some embodiments shown as p-type MOS, the semiconductor substrate 651 comprises an n-type silicon substrate (n-substrate). For example, n-type impurities (e.g., arsenic (As)) are doped into the semiconductor substrate 651 to form an n-substrate. To form a complementary MOS, a p-type buried layer (i.e., a deep p-well (DPW) 652 (also referred to as a p-drift region)) may be implanted deep below the active region of the semiconductor substrate 651. In some embodiments, boron ions may be implanted to form the DPW 652.

[0064] At block S21, n-type impurities are doped into the DPW 652 to form an n-type doped region 662. A high-energy n-type dopant implantation process is then performed to form the n-type doped region 662 through the photoresist. By way of example and not limitation, the n-type doped region 662 is formed by implanting an n-type dopant, such as phosphorus (P) or arsenic (As), into the DPW 652. In some embodiments, the breakdown voltage of the semiconductor device 600 is limited by an electric field peak that may occur near the bird's beak of the FOX 608 and may cause device breakdown failure. For example, when the DPW 652 has not yet been fully depleted through the semiconductor substrate 651, device breakdown failure may occur because the p-type dopant concentration may be higher than the n-type dopant concentration near the bird's beak of the FOX 608, which in turn adversely affects the electric field. Therefore, p-type dopants are implanted into n-type doped region 662 in DPW 652 (i.e., near bird's beak 608c of FOX 608 near the source region), increasing the n-type dopant concentration near the source region to achieve charge balance. Consequently, the electric field peak can be reduced, thereby achieving an improved breakdown voltage of semiconductor device 600.

[0065] In some embodiments, the n-type dopant concentration in the n-type doping region 662 is lower than the p-type dopant concentration. In some embodiments, the n-type dopant concentration in the n-type doping region 662 is lower than the p-type dopant concentration in the DPW 652. By way of example and not limitation, the n-type dopant concentration in the n-type doping region 662 is lower than the p-type dopant concentration in the DPW 652. In some embodiments, the n-type dopant concentration in the n-type doping region 662 is of the same order of magnitude as the p-type dopant concentration in the DPW 652. That is, the p-type dopant concentration in the DPW 652 is higher than the n-type dopant concentration in the n-type doping region 662 and is less than approximately ten times the n-type dopant concentration in the n-type doping region 662. In other words, the difference between the n-type dopant concentration in the n-type doping region 662 and the p-type dopant concentration in the DPW 652 can be less than one order of magnitude.

[0066] At block S22, the semiconductor substrate is annealed to deepen the bottommost locations of the DPW 652 and the n-type doped region 662. In some embodiments, by way of example and not limitation, the dopants of the DPW 652 and the n-type doped region 662 are driven in by heating the semiconductor substrate 651 to a temperature in the range of about 1000° C. to about 1100° C., with other temperature ranges being within the scope of the present disclosure. In some embodiments, during the annealing process, the n-type dopant has a lower diffusion rate than the p-type dopant, which causes the bottommost location of the n-type doped region 662 to be higher than the bottommost location of the DPW 652.

[0067] At block S23, field oxide (FOX) 608 and FOX 610 are formed over portions of the DPW 652 and the n-type doped region 662. The FOX 608 overlaps a portion of the n-type doped region 662. In some embodiments, the field oxides 608 and 610 formed by the thermal oxidation process may cause a bird's beak 608c. By way of example and not limitation, the field oxide 608 includes a lower inclined facet and an upper inclined facet that forms a corner with the lower inclined facet as a bird's beak. In some embodiments, the n-type doped region 662 interfaces with the bird's beak of the FOX 608. Figure 16 In the embodiment shown in FIG. 6A , the n-type doped region 662 contacts the lower inclined facet and the bottom surface of the field oxide 608 . In some embodiments, the n-type dopant of the n-type doped region 662 can diffuse into the FOX 608 .

[0068] At block S24, an n-top region 655 is formed in the DPW 652 and directly below the FOX 608. The n-top region 655 (also referred to as a buried n-well region) is formed in the middle of the DPW 652 and below the FOX 608, but not connected to the FOX 608. The n-top region 655 is a floating layer and is not connected to the source or drain regions of the semiconductor device 600. By way of example and not limitation, the n-top region 655 has an n-type dopant (e.g., phosphorus (P) or phosphorus (As)) concentration. In some embodiments, the n-type dopant concentration in the n-top region 655 is higher than the n-type dopant concentration in the n-type doping region 662. In some embodiments, the difference between the n-type dopant concentration in the n-top region 655 and the n-type dopant concentration in the n-type doping region 662 can be less than three orders of magnitude. In other words, the n-type dopant concentration in the n-top region 655 is higher than the n-type dopant concentration in the n-type doping region 662 and is less than about one thousand times the n-type dopant concentration in the n-type doping region 662. In some embodiments, the difference between the concentration of the n-type dopant in the n-top region 655 and the n-type dopant concentration in the n-type doping region 662 can be less than two orders of magnitude. In other words, the n-type dopant concentration in the n-top region 655 is higher than the n-type dopant concentration in the n-type doping region 662 and is less than about one hundred times the n-type dopant concentration in the n-type doping region 662.

[0069] At block S25, an n-well 654 is formed in the DPW 652 and adjacent to the n-type doped region 662. The n-well 654 (also referred to as an n-body) is formed by implanting an n-type dopant, such as phosphorus (P) or arsenic (As), into the semiconductor substrate 651 and performing an annealing process (e.g., rapid thermal annealing or laser annealing) on ​​the n-well 654. Alternatively, the n-well 654 may be formed by another suitable process, such as a diffusion process. The n-well 654 extends downward from the top surface of the semiconductor substrate 651, adjacent to the n-type doped region 662, with a portion of the n-well 654 below the FOX 610. In some embodiments, the difference between the p-type dopant concentration in the n-well 654 and the n-type dopant concentration in the n-type dopant region 662 can be less than three orders of magnitude. In other words, the p-type dopant concentration in the n-well 654 is higher than the n-type dopant concentration in the n-type dopant region 662 and lower than approximately one thousand times the n-type dopant concentration in the n-type dopant region 662. In some embodiments, the difference between the p-type dopant concentration in the n-well 654 and the p-type dopant concentration in the n-type doping region 662 can be less than two orders of magnitude. In other words, the p-type dopant concentration in the n-well 654 is higher than the n-type dopant concentration in the n-type doping region 662 and is less than about one hundred times the n-type dopant concentration in the n-type doping region 662.

[0070] At block S26, a gate structure 647 is formed on the semiconductor substrate 651. The gate structure 647 includes a gate dielectric 640 formed on the semiconductor substrate 651, and a gate electrode 645 formed on the gate dielectric 640. The gate dielectric 640 has a first portion covering the n-type doped region 662 and a second portion covering the n-well 654. In some embodiments, the n-type dopant of the n-type doped region 662 may diffuse into the gate dielectric 640.

[0071] In block S27, a drain 628 may be formed in the DPW 652, and a source may be formed in the upper portion of the n-well 654. The source may have two oppositely doped regions 624 and 626, both formed in the upper portion of the n-well 654. The first region 624 and the drain 628 of the source may have a first conductivity type, and the second region 626 of the source may have a second conductivity type. By way of example and not limitation, the first region 624 and the drain 628 of the source may include a p-type dopant, such as boron (B), and the second region 626 of the source may include an n-type dopant, such as phosphorus (P) or arsenic (As). Alternatively, the source may have one conductivity type. The source and drain may be located on either side of the gate structure 647. In some embodiments, the p-type dopant concentration in the first region 624 of the source is higher than the n-type dopant concentration in the n-type doped region 662. In more detail, the difference between the p-type dopant concentration in the first region 624 of the source and the n-type dopant concentration in the n-type dopant region 662 can be less than five, four, or three orders of magnitude. In some embodiments, the n-type dopant concentration in the second region 626 of the source is higher than the n-type dopant concentration in the n-type dopant region 662. In more detail, the difference between the n-type dopant concentration in the second region 626 of the source and the n-type dopant concentration in the n-type dopant region 662 can be less than five, four, or three orders of magnitude. In some embodiments, the p-type dopant concentration in the drain 628 is higher than the n-type dopant concentration in the n-type dopant region 662. In more detail, the difference between the p-type dopant concentration in the drain 628 and the n-type dopant concentration in the n-type dopant region 662 can be less than five, four, or three orders of magnitude.

[0072] At block S28, contacts 616, 614, and 618 are formed in the interlayer dielectric (ILD) layer 696 to contact the gate structure 647, the drain 628, and the source regions 624 and 626. For example, an opening is formed in the ILD layer 196, and then a conductive material is deposited in the opening. Excess portions of the conductive material outside the opening are removed by using a CMP process, while portions remain in the opening to serve as contacts 616, 614, and 618. In some embodiments, the contacts 616, 614, and 618 may be made of tungsten, aluminum, copper, or other suitable materials. Figure 16 In FIG. 6 , contact 616 is electrically connected to gate structure 647 , contact 614 is connected to drain 628 , and contact 618 is connected to source regions 624 and 626 .

[0073] Based on the foregoing embodiments, it can be seen that the present disclosure provides advantages in the manufacture of semiconductor devices. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein. The breakdown voltage of the LDMOS transistor is limited by the electric field peak, which may occur near the bird's beak of the FOX, and the electric field peak may cause device breakdown failure. For example, when the deep n-well (DNW) has not been fully depleted by the p-type semiconductor substrate, a device breakdown failure may occur because the n-type dopant concentration is higher than the p-type dopant concentration near the bird's beak of the FOX, which in turn has an adverse effect on the electric field. When the n-type dopant concentration in the DNW is reduced to achieve charge balance near the bird's beak, the peak electric field can be improved. However, this will lead to breakdown of the drift region and reduce the breakdown voltage of the LDMOS transistor.

[0074] Therefore, one advantage is that when a p-type dopant is implanted into the p-type doped region in the deep n-well (i.e. Figure 5 In the vicinity of the bird's beak of FOX near the source region shown in FIG, the p-type dopant concentration near the source region is increased, thereby achieving charge balance. As a result, the electric field peak can be reduced, thereby achieving an improved breakdown voltage of the LDMOS transistor.

[0075] In some embodiments, a method for manufacturing a semiconductor device includes: forming a first type deep well having a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first type deep well to form a second type doped region, wherein the concentration of the first impurity in the first type deep well is higher than the concentration of the second impurity in the second type doped region, but lower than about ten times the concentration of the second impurity in the second type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide extending laterally from a first side of the second type doped region; forming a second type well of the second conductivity type in the first type deep well and on a second side of the second type doped region opposite to the first side of the second type doped region; forming a gate structure extending laterally beyond the first side and the second side of the second type doped region; forming a source region in the second type well and forming a drain region in the first type deep well, wherein the field oxide extends laterally between the second type doped region and the drain region.

[0076] In some embodiments, a method for manufacturing a semiconductor device includes: forming a deep n-well in a semiconductor substrate; forming a patterned mask layer above the deep n-well; appropriately utilizing the patterned mask layer to dope a p-type dopant into the deep n-well to form a p-type doped region; annealing the semiconductor substrate to deepen the deep n-well and the p-type doped region; after annealing the semiconductor substrate, oxidizing a portion of the deep n-well and a portion of the p-type doped region to form a field oxide; forming a p-well in the deep n-well, wherein the p-type doped region is laterally located between the p-well and the field oxide; forming a gate structure extending from the p-well to the field oxide across the p-type doped region; forming a source region in the p-well, and forming a drain region in the deep n-well.

[0077] In some embodiments, a semiconductor device includes: a semiconductor substrate, a deep n-well, a field oxide, a gate structure, a p-type doped region, a source region, and a drain region. The deep n-well is in the semiconductor substrate. The field oxide is partially embedded in the deep n-well and has a sharp corner substantially flush with the top surface of the semiconductor substrate. The gate structure is on the field oxide and extends laterally beyond the sharp corner of the field oxide. The p-type doped region is in the deep n-well and intersects the sharp corner of the field oxide. The source region and the drain region are at least partially laterally separated by the p-type doped region and the field oxide.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0079] Example 1 is a method for manufacturing a semiconductor device, comprising: forming a first type deep well having a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first type deep well to form a second type doped region, wherein the concentration of the first impurity in the first type deep well is higher than the concentration of the second impurity in the second type doped region, but lower than about ten times the concentration of the second impurity in the second type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide extending laterally from a first side of the second type doped region; forming a second type well of the second conductivity type in the first type deep well and on a second side of the second type doped region opposite to the first side of the second type doped region; forming a gate structure extending laterally beyond the first side and the second side of the second type doped region; and forming a source region in the second type well and a drain region in the first type deep well, wherein the field oxide extends laterally between the second type doped region and the drain region.

[0080] Example 2 is the method of Example 1, wherein the first conductivity type is n-type, and the second impurity is p-type.

[0081] Example 3 is the method of Example 1, wherein the second impurity includes boron.

[0082] Example 4 is the method of Example 1, wherein the concentration of the second impurity is greater than about 1.0×10 12 atoms / cm 3 .

[0083] Example 5 is the method described in Example 1, wherein the concentration of the second conductive type dopant in the second type well is higher than the concentration of the second impurity in the second type doping region, but lower than about one hundred times the concentration of the second impurity in the second type doping region.

[0084] Example 6 is the method described in Example 1, wherein the concentration of the first conductive type dopant in the source region is higher than the concentration of the second impurity in the second type doping region, but lower than about one hundred thousand times the concentration of the second impurity in the second type doping region.

[0085] Example 7 is the method described in Example 1, wherein the concentration of the first conductive type dopant in the drain region is higher than the concentration of the second impurity in the second type doping region, but is lower than about one hundred thousand times the concentration of the second impurity in the second type doping region.

[0086] Example 8 is the method described in Example 1, further comprising: forming a p-top region below the field oxide, wherein the concentration of the second conductive type dopant in the p-top region is higher than the concentration of the second impurity in the second type doping region, but lower than approximately one hundred times the concentration of the second impurity in the second type doping region.

[0087] Example 9 is the method of Example 1, wherein forming the field oxide is performed such that the second impurity of the second type doping region diffuses into the field oxide.

[0088] Example 10 is the method of Example 1, further comprising: annealing the semiconductor substrate after doping the second impurity and before forming the field oxide.

[0089] Example 11 is a method for manufacturing a semiconductor device, comprising: forming a deep n-well in a semiconductor substrate; forming a patterned mask layer above the deep n-well; appropriately utilizing the patterned mask layer to dope p-type dopants into the deep n-well to form a p-type doped region; annealing the semiconductor substrate to deepen the deep n-well and the p-type doped region; after annealing the semiconductor substrate, oxidizing a portion of the deep n-well and a portion of the p-type doped region to form a field oxide; forming a p-well in the deep n-well, wherein the p-type doped region is laterally located between the p-well and the field oxide; forming a gate structure extending from the p-well to the field oxide across the p-type doped region; and forming a source region in the p-well and a drain region in the deep n-well.

[0090] Example 12 is the method of Example 11, wherein after annealing the semiconductor substrate is completed, the bottommost position of the p-type doped region is higher than the bottom surface of the field oxide.

[0091] Example 13 is the method of Example 11, wherein after annealing the semiconductor substrate is completed, a bottommost position of the p-type doped region is lower than a bottom surface of the field oxide but higher than a bottommost position of the p-well.

[0092] Example 14 is the method of Example 11, wherein after annealing the semiconductor substrate is completed, a bottommost position of the p-type doped region is lower than a bottommost position of the p-well but higher than a bottommost position of the deep n-well.

[0093] Example 15 is the method of Example 11, wherein after annealing the semiconductor substrate is completed, the bottommost position of the deep n-well directly under the field oxide is lower than the bottommost position of the deep n-well directly under the p-type doped region.

[0094] Example 16 is the method of Example 11, wherein forming the gate structure is performed such that the p-type dopant of the p-type doped region diffuses into a gate dielectric of the gate structure.

[0095] Example 17 is a semiconductor device comprising: a deep n-well in a semiconductor substrate; a field oxide partially embedded in the deep n-well and having a sharp corner at a position substantially flush with the top surface of the semiconductor substrate; a gate structure on the field oxide and extending laterally beyond the sharp corner of the field oxide; a p-type doped region in the deep n-well and intersecting the sharp corner of the field oxide; and a source region and a drain region at least partially separated laterally by the p-type doped region and the field oxide.

[0096] Example 18 is the semiconductor device of Example 17, wherein the concentration of the n-type dopant in the deep n-well is higher than the concentration of the p-type dopant in the p-type doping region, but less than about ten times the concentration of the p-type dopant in the p-type doping region.

[0097] Example 19 is the semiconductor device of Example 17, wherein a bottommost position of the deep n-well directly below the source region is lower than a bottommost position of the deep n-well directly below the p-type doping region.

[0098] Example 20 is the semiconductor device of Example 17, wherein a bottommost position of the deep n-well directly below the field oxide is lower than a bottommost position of the deep n-well directly below the p-type doping region.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first type deep well having first impurities of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first type deep well to form a second type doped region, wherein a concentration of the first impurity in the first type deep well is higher than a concentration of the second impurity in the second type doped region, but lower than ten times a concentration of the second impurity in the second type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide extending laterally from a first side of the second type doped region; forming a second type well of the second conductivity type in the first type deep well and on a second side of the second type doped region opposite the first side of the second type doped region; forming a gate structure that laterally extends beyond the first side and the second side of the second type doped region; and forming a source region in the second type well and forming a drain region in the first type deep well, wherein the field oxide extends laterally between the second type doped region and the drain region, The method further comprises: annealing the semiconductor substrate after doping the second impurity and before forming the field oxide. After the semiconductor substrate is annealed, the bottommost position of the first type deep well directly below the field oxide is lower than the bottommost position of the first type deep well directly below the second type doped region.

2. The method according to claim 1, wherein The first conductivity type is n-type, and the second impurity is p-type.

3. The method according to claim 1, wherein The second impurity includes boron.

4. The method according to claim 1, wherein The concentration of the second impurity is greater than 1.0×10 12 atoms / cm 3 .

5. The method according to claim 1, wherein The concentration of the second conductivity type dopant in the second type well is higher than the concentration of the second impurity in the second type doping region, but lower than one hundred times the concentration of the second impurity in the second type doping region.

6. The method according to claim 1, wherein The concentration of the first conductivity type dopant in the source region is higher than the concentration of the second impurity in the second type doping region, but lower than one hundred thousand times the concentration of the second impurity in the second type doping region.

7. The method according to claim 1, wherein The concentration of the first conductivity type dopant in the drain region is higher than the concentration of the second impurity in the second type doping region, but lower than one hundred thousand times the concentration of the second impurity in the second type doping region.

8. The method according to claim 1, further comprising: A p-top region is formed below the field oxide, wherein a concentration of dopants of the second conductivity type in the p-top region is higher than a concentration of the second impurity in the second type doping region but less than one hundred times a concentration of the second impurity in the second type doping region.

9. The method according to claim 1, wherein Forming the field oxide is performed such that the second impurities of the second type doping region diffuse into the field oxide.

10. A method for manufacturing a semiconductor device, comprising: forming a deep n-well in a semiconductor substrate; forming a patterned mask layer over the deep n-well; appropriately utilizing the patterned mask layer to dope a p-type dopant into the deep n-well to form a p-type doped region; annealing the semiconductor substrate to deepen the deep n-well and the p-type doped region; After annealing the semiconductor substrate, oxidizing a portion of the deep n-well and a portion of the p-type doped region to form a field oxide; forming a p-well in the deep n-well, wherein the p-type doped region is laterally located between the p-well and the field oxide; forming a gate structure extending from the p-well to the field oxide across the p-type doped region; and forming a source region in the p-well and a drain region in the deep n-well, wherein the concentration of the n-type dopant in the deep n-well is higher than the concentration of the p-type dopant in the p-type doping region, but lower than ten times the concentration of the p-type dopant in the p-type doping region; After the semiconductor substrate is annealed, the bottom of the deep n-well directly below the field oxide is lower than the bottom of the deep n-well directly below the p-type doping region.

11. The method according to claim 10, wherein: After the semiconductor substrate is annealed, the bottommost position of the p-type doping region is higher than the bottom surface of the field oxide.

12. The method according to claim 10, wherein: After annealing the semiconductor substrate is completed, the bottommost position of the p-type doping region is lower than the bottom surface of the field oxide but higher than the bottommost position of the p-well.

13. The method according to claim 10, wherein: After the semiconductor substrate is annealed, the bottommost position of the p-type doping region is lower than the bottommost position of the p-well but higher than the bottommost position of the deep n-well.

14. The method according to claim 10, wherein: Forming the gate structure is performed such that the p-type dopant of the p-type doped region diffuses into a gate dielectric of the gate structure.

15. A semiconductor device comprising: deep n-well, in the semiconductor substrate; a field oxide partially embedded in the deep n-well and having sharp corners substantially flush with a top surface of the semiconductor substrate; a gate structure on the field oxide and extending laterally beyond the tip corner of the field oxide; a p-type doped region in the deep n-well and bordering the tip corner of the field oxide; as well as a source region and a drain region, at least partially laterally separated by the p-type doped region and the field oxide, wherein the concentration of the n-type dopant in the deep n-well is higher than the concentration of the p-type dopant in the p-type doping region, but lower than ten times the concentration of the p-type dopant in the p-type doping region; The bottommost position of the deep n-well directly below the field oxide is lower than the bottommost position of the deep n-well directly below the p-type doping region.

16. The semiconductor device according to claim 15, wherein The bottommost position of the deep n-well directly below the source region is lower than the bottommost position of the deep n-well directly below the p-type doping region.

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